1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_AGPDEFS_H 28 #define _SYS_AGPDEFS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * This AGP memory type is required by some hardware like i810 video 38 * card, which need physical contiguous pages to setup hardware cursor. 39 * Usually, several tens of kilo bytes are needed in this case. 40 * We use DDI DMA interfaces to allocate such memory in agpgart driver, 41 * and it can not be exported to user applications directly by calling mmap 42 * on agpgart driver. The typical usage scenario is as the following: 43 * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE 44 * on agpgart driver. Secondly, Xserver use the physical address to mmap 45 * the memory to Xserver space area by xsvc driver. 46 * 47 */ 48 #define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */ 49 50 #ifdef _KERNEL 51 52 /* AGP space units */ 53 #define AGP_PAGE_SHIFT 12 54 #define AGP_PAGE_SIZE (1 << AGP_PAGE_SHIFT) 55 #define AGP_PAGE_OFFSET (AGP_PAGE_SIZE - 1) 56 #define AGP_MB2PAGES(x) ((x) << 8) 57 #define AGP_PAGES2BYTES(x) ((x) << AGP_PAGE_SHIFT) 58 #define AGP_BYTES2PAGES(x) ((x) >> AGP_PAGE_SHIFT) 59 #define AGP_PAGES2KB(x) ((x) << 2) 60 #define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0) 61 62 /* stand pci register offset */ 63 #define PCI_CONF_CAP_MASK 0x10 64 #define PCI_CONF_CAPID_MASK 0xff 65 #define PCI_CONF_NCAPID_MASK 0xff00 66 67 #define INTEL_VENDOR_ID 0x8086 68 #define AMD_VENDOR_ID 0x1022 69 #define VENDOR_ID_MASK 0xffff 70 71 /* macros for device types */ 72 #define DEVICE_IS_I810 11 /* intel i810 series video card */ 73 #define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */ 74 #define DEVICE_IS_AGP 21 /* external AGP video card */ 75 #define CHIP_IS_INTEL 10 /* intel agp bridge */ 76 #define CHIP_IS_AMD 20 /* amd agp bridge */ 77 78 /* AGP bridge device id */ 79 #define AMD_BR_8151 0x74541022 80 #define INTEL_BR_810 0x71208086 81 #define INTEL_BR_810DC 0x71228086 82 #define INTEL_BR_810E 0x71248086 83 #define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */ 84 #define INTEL_BR_830M 0x35758086 85 #define INTEL_BR_845 0x25608086 /* include 845G/P */ 86 #define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */ 87 #define INTEL_BR_855PM 0x33408086 88 #define INTEL_BR_865 0x25708086 89 #define INTEL_BR_915 0x25808086 90 #define INTEL_BR_915GM 0x25908086 91 #define INTEL_BR_945 0x27708086 92 #define INTEL_BR_945GM 0x27a08086 93 #define INTEL_BR_946GZ 0x29708086 94 #define INTEL_BR_965G1 0x29808086 95 #define INTEL_BR_965Q 0x29908086 96 #define INTEL_BR_965G2 0x29a08086 97 #define INTEL_BR_965GM 0x2a008086 98 #define INTEL_BR_965GME 0x2a108086 99 100 /* AGP common register offset in pci configuration space */ 101 #define AGP_CONF_MISC 0x51 /* one byte */ 102 #define AGP_CONF_CAPPTR 0x34 103 #define AGP_CONF_APERBASE 0x10 104 #define AGP_CONF_STATUS 0x04 /* CAP + 0x4 */ 105 #define AGP_CONF_COMMAND 0x08 /* CAP + 0x8 */ 106 107 /* AGP target register and mask defines */ 108 #define AGP_CONF_CONTROL 0x10 /* CAP + 0x10 */ 109 #define AGP_TARGET_BAR1 1 110 #define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */ 111 #define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */ 112 #define AGP_CONF_APERSIZE 0x14 /* CAP + 0x14 */ 113 #define AGP_CONF_ATTBASE 0x18 /* CAP + 0x18 */ 114 #define AGP_ATTBASE_MASK 0xfffff000 115 #define AGPCTRL_GTLBEN (0x1 << 7) 116 #define AGP_APER_TYPE_MASK 0x4 117 #define AGP_APER_SIZE_MASK 0xf00 118 #define AGP_APER_128M_MASK 0x3f 119 #define AGP_APER_4G_MASK 0xf00 120 #define AGP_APER_4M 0x3f 121 #define AGP_APER_8M 0x3e 122 #define AGP_APER_16M 0x3c 123 #define AGP_APER_32M 0x38 124 #define AGP_APER_64M 0x30 125 #define AGP_APER_128M 0x20 126 #define AGP_APER_256M 0xf00 127 #define AGP_APER_512M 0xe00 128 #define AGP_APER_1024M 0xc00 129 #define AGP_APER_2048M 0x800 130 #define AGP_APER_4G 0x000 131 #define AGP_MISC_APEN 0x2 132 133 /* AGP gart table definition */ 134 #define AGP_ENTRY_VALID 0x1 135 136 /* AGP term definitions */ 137 #define AGP_CAP_ID 0x2 138 #define AGP_CAP_OFF_DEF 0xa0 139 140 /* Intel integrated video card, chipset id */ 141 #define INTEL_IGD_810 0x71218086 142 #define INTEL_IGD_810DC 0x71238086 143 #define INTEL_IGD_810E 0x71258086 144 #define INTEL_IGD_815 0x11328086 145 #define INTEL_IGD_830M 0x35778086 146 #define INTEL_IGD_845G 0x25628086 147 #define INTEL_IGD_855GM 0x35828086 148 #define INTEL_IGD_865G 0x25728086 149 #define INTEL_IGD_915 0x25828086 150 #define INTEL_IGD_915GM 0x25928086 151 #define INTEL_IGD_945 0x27728086 152 #define INTEL_IGD_945GM 0x27a28086 153 #define INTEL_IGD_946GZ 0x29728086 154 #define INTEL_IGD_965G1 0x29828086 155 #define INTEL_IGD_965Q 0x29928086 156 #define INTEL_IGD_965G2 0x29a28086 157 #define INTEL_IGD_965GM 0x2a028086 158 #define INTEL_IGD_965GME 0x2a128086 159 #define I8XX_CONF_GMADR 0x10 /* offset in PCI config space */ 160 #define I915_CONF_GMADR 0x18 /* offset in PCI config space */ 161 #define I8XX_CONF_GC 0x52 /* offset in PCI config space */ 162 163 /* Intel integrated video card graphics mode mask */ 164 #define I8XX_GC_MODE_MASK 0x70 165 #define I8XX_GC_MODE0 0x00 166 #define I8XX_GC_MODE1 0x10 167 #define I8XX_GC_MODE2 0x20 168 #define I8XX_GC_MODE3 0x30 169 #define I8XX_GC_MODE4 0x40 170 #define I8XX_GC_MODE5 0x50 171 172 /* Intel integrated video card GTT definition */ 173 #define GTT_PAGE_SHIFT 12 174 #define GTT_PAGE_SIZE (1 << GTT_PAGE_SHIFT) 175 #define GTT_PAGE_OFFSET (GTT_PAGE_SIZE - 1) 176 #define GTT_PTE_MASK (~GTT_PAGE_OFFSET) 177 #define GTT_PTE_VALID 0x1 178 #define GTT_TABLE_VALID 0x1 179 #define GTT_BASE_MASK 0xfffff000 180 #define GTT_MB_TO_PAGES(m) ((m) << 8) 181 #define GTT_POINTER_MASK 0xffffffff 182 183 /* Intel i810 register offset */ 184 #define I810_POINTER_MASK 0x3fffffff 185 #define I810_CONF_SMRAM 0x70 /* offset in PCI config space */ 186 #define I810_GMS_MASK 0xc0 /* smram register mask */ 187 /* 188 * GART and GTT entry format table 189 * 190 * AMD64 GART entry 191 * from bios and kernel develop guide for amd64 192 * ----------------------------- 193 * Bits Description | 194 * 0 valid | 195 * 1 coherent | 196 * 3:2 reserved | 197 * 11:4 physaddr[39:32] | 198 * 31:12 physaddr[31:12] | 199 * ----------------------------- 200 * Intel GTT entry 201 * Intel video programming manual 202 * ----------------------------- 203 * Bits descrition | 204 * 0 valid | 205 * 2:1 memory type | 206 * 29:12 PhysAddr[29:12] | 207 * 31:30 reserved | 208 * ----------------------------- 209 * AGP entry 210 * from AGP protocol 3.0 211 * ----------------------------- 212 * Bits descrition | 213 * 0 valid | 214 * 1 coherent | 215 * 3:2 reserved | 216 * 11:4 PhysAddr[39:32] | 217 * 31:12 PhysAddr[31:12] | 218 * 63:32 PhysAddr[71:40] | 219 * ----------------------------- 220 */ 221 222 /* 223 * gart and gtt table base register format 224 * 225 * AMD64 register format 226 * from bios and kernel develop guide for AMD64 227 * --------------------------------------------- 228 * Bits Description | 229 * 3:0 reserved | 230 * 31:4 physical addr 39:12 | 231 * ---------------------------------------------- 232 * INTEL AGPGART table base register format 233 * from AGP protocol 3.0 p142, only support 32 bits 234 * --------------------------------------------- 235 * Bits Description | 236 * 11:0 reserved | 237 * 31:12 physical addr 31:12 | 238 * 63:32 physical addr 63:32 | 239 * --------------------------------------------- 240 * INTEL i810 GTT table base register format 241 * _____________________________________________ 242 * Bits Description | 243 * 0 GTT table enable bit | 244 * 11:1 reserved | 245 * 31:12 physical addr 31:12 | 246 * --------------------------------------------- 247 */ 248 249 /* Intel agp bridge specific */ 250 #define AGP_INTEL_POINTER_MASK 0xffffffff 251 252 /* Amd64 cpu gart device reigster offset */ 253 #define AMD64_APERTURE_CONTROL 0x90 254 #define AMD64_APERTURE_BASE 0x94 255 #define AMD64_GART_CACHE_CTL 0x9c 256 #define AMD64_GART_BASE 0x98 257 258 /* Amd64 cpu gart bits */ 259 #define AMD64_APERBASE_SHIFT 25 260 #define AMD64_APERBASE_MASK 0x00007fff 261 #define AMD64_GARTBASE_SHIFT 8 262 #define AMD64_GARTBASE_MASK 0xfffffff0 263 #define AMD64_POINTER_MASK 0xffffffffff 264 #define AMD64_INVALID_CACHE 0x1 265 #define AMD64_GART_SHIFT 12 266 #define AMD64_RESERVE_SHIFT 4 267 #define AMD64_APERSIZE_MASK 0xe 268 #define AMD64_GARTEN 0x1 269 #define AMD64_DISGARTCPU 0x10 270 #define AMD64_DISGARTIO 0x20 271 #define AMD64_ENTRY_VALID 0x1 272 273 /* Other common routines */ 274 #define MB2BYTES(m) ((m) << 20) 275 #define BYTES2MB(m) ((m) >> 20) 276 #define GIGA_MASK 0xC0000000 277 #define UI32_MASK 0xffffffffU 278 #define MAXAPERMEGAS 0x1000 /* Aper size no more than 4G */ 279 280 #endif /* _KERNEL */ 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif /* _SYS_AGPDEFS_H */ 287