1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 #include <sys/types.h> 43 #include <sys/errno.h> 44 #include <sys/param.h> 45 #include <sys/stropts.h> 46 #include <sys/stream.h> 47 #include <sys/strsubr.h> 48 #include <sys/kmem.h> 49 #include <sys/conf.h> 50 #include <sys/devops.h> 51 #include <sys/ksynch.h> 52 #include <sys/stat.h> 53 #include <sys/modctl.h> 54 #include <sys/debug.h> 55 #include <sys/pci.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/dlpi.h> 59 #include <sys/taskq.h> 60 #include <sys/cyclic.h> 61 62 #include <sys/pattr.h> 63 #include <sys/strsun.h> 64 65 #include <sys/mac.h> 66 67 #ifdef __cplusplus 68 extern "C" { 69 #endif 70 71 #define XGELL_DESC "Xframe I/II 10Gb Ethernet %I%" 72 #define XGELL_IFNAME "xge" 73 #define XGELL_TX_LEVEL_LOW 8 74 #define XGELL_TX_LEVEL_HIGH 32 75 76 #include <xgehal.h> 77 78 #if defined(__sparc) || defined(__amd64) 79 #define XGELL_L3_ALIGNED 1 80 #endif 81 82 /* Control driver to copy or DMA received packets */ 83 #define XGELL_DMA_BUFFER_SIZE_LOWAT 256 84 85 /* There default values can be overrided by vaules in xge.conf */ 86 #define XGELL_RX_BUFFER_TOTAL (1024 * 6) /* 6K */ 87 #define XGELL_RX_BUFFER_POST_HIWAT (1024 * 3) /* 3K */ 88 #define XGELL_RX_BUFFER_RECYCLE_HIWAT 64 89 90 #define XGELL_RING_MAIN_QID 0 91 92 /* About 1s */ 93 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 94 95 /* 96 * If HAL could provide defualt values to all tunables, we'll remove following 97 * macros. 98 * Before removing, please refer to xgehal-config.h for more details. 99 */ 100 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 101 102 /* 103 * The reason to define different values for Link Utilization interrupts is 104 * different performance numbers between SPARC and x86 platforms. 105 */ 106 #if defined(__sparc) 107 #define XGE_HAL_DEFAULT_TX_URANGE_A 2 108 #define XGE_HAL_DEFAULT_TX_UFC_A 1 109 #define XGE_HAL_DEFAULT_TX_URANGE_B 5 110 #define XGE_HAL_DEFAULT_TX_UFC_B 10 111 #define XGE_HAL_DEFAULT_TX_URANGE_C 10 112 #define XGE_HAL_DEFAULT_TX_UFC_C 40 113 #define XGE_HAL_DEFAULT_TX_UFC_D 80 114 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 115 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 116 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 4000 117 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS 128 118 #define XGE_HAL_DEFAULT_RX_URANGE_A 2 119 #define XGE_HAL_DEFAULT_RX_UFC_A 1 120 #define XGE_HAL_DEFAULT_RX_URANGE_B 5 121 #define XGE_HAL_DEFAULT_RX_UFC_B 10 122 #define XGE_HAL_DEFAULT_RX_URANGE_C 10 123 #define XGE_HAL_DEFAULT_RX_UFC_C 40 124 #define XGE_HAL_DEFAULT_RX_UFC_D 80 125 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 126 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 24 127 #else 128 #define XGE_HAL_DEFAULT_TX_URANGE_A 10 129 #define XGE_HAL_DEFAULT_TX_UFC_A 1 130 #define XGE_HAL_DEFAULT_TX_URANGE_B 20 131 #define XGE_HAL_DEFAULT_TX_UFC_B 10 132 #define XGE_HAL_DEFAULT_TX_URANGE_C 50 133 #define XGE_HAL_DEFAULT_TX_UFC_C 40 134 #define XGE_HAL_DEFAULT_TX_UFC_D 80 135 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 136 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 137 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 4000 138 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS 128 139 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 140 #define XGE_HAL_DEFAULT_RX_UFC_A 1 141 #define XGE_HAL_DEFAULT_RX_URANGE_B 20 142 #define XGE_HAL_DEFAULT_RX_UFC_B 10 143 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 144 #define XGE_HAL_DEFAULT_RX_UFC_C 40 145 #define XGE_HAL_DEFAULT_RX_UFC_D 80 146 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 147 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 24 148 #endif 149 150 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 151 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 152 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 153 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 154 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 155 156 #ifdef XGELL_TX_NOMAP_COPY 157 158 #define XGE_HAL_DEFAULT_FIFO_FRAGS 1 159 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 0 160 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE (XGE_HAL_MAC_HEADER_MAX_SIZE + \ 161 XGE_HAL_DEFAULT_MTU) 162 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 163 #else 164 165 #if defined(__x86) 166 #define XGE_HAL_DEFAULT_FIFO_FRAGS 32 167 #else 168 #define XGE_HAL_DEFAULT_FIFO_FRAGS 16 169 #endif 170 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 4 171 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE sizeof (uint64_t) 172 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 6 173 174 #endif /* XGELL_TX_NOMAP_COPY */ 175 176 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 16 177 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 32 178 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 179 #define XGE_HAL_DEFAULT_RING_QUEUE_SIZE 64 180 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 35 181 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 182 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 183 184 #define XGE_HAL_DEFAULT_RING_NUM 8 185 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 186 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 187 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 188 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 189 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 190 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 191 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 4 192 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 193 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION 1 /* 2 splits */ 194 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 195 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 196 #define XGE_HAL_DEFAULT_SHARED_SPLITS 0 197 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 198 #define XGE_HAL_PCI_FREQ_MHERZ_DEFAULT 133 199 200 /* 201 * default the size of buffers allocated for ndd interface functions 202 */ 203 #define XGELL_STATS_BUFSIZE 4096 204 #define XGELL_PCICONF_BUFSIZE 2048 205 #define XGELL_ABOUT_BUFSIZE 512 206 #define XGELL_IOCTL_BUFSIZE 64 207 #define XGELL_DEVCONF_BUFSIZE 4096 208 209 /* 210 * xgell_event_e 211 * 212 * This enumeration derived from xgehal_event_e. It extends it 213 * for the reason to get serialized context. 214 */ 215 /* Renamb the macro from HAL */ 216 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 217 typedef enum xgell_event_e { 218 /* LL events */ 219 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 220 } xgell_event_e; 221 222 typedef struct { 223 int rx_buffer_total; 224 int rx_buffer_post_hiwat; 225 int rx_buffer_recycle_hiwat; 226 } xgell_config_t; 227 228 typedef struct xgell_rx_buffer_t { 229 struct xgell_rx_buffer_t *next; 230 void *vaddr; 231 dma_addr_t dma_addr; 232 ddi_dma_handle_t dma_handle; 233 ddi_acc_handle_t dma_acch; 234 void *lldev; 235 frtn_t frtn; 236 #ifdef XGELL_L3_ALIGNED 237 unsigned char header[XGE_HAL_TCPIP_HEADER_MAX_SIZE * 2 238 + 8]; 239 #endif 240 } xgell_rx_buffer_t; 241 242 /* Buffer pool for all rings */ 243 typedef struct xgell_rx_buffer_pool_t { 244 uint_t total; /* total buffers */ 245 uint_t size; /* buffer size */ 246 xgell_rx_buffer_t *head; /* header pointer */ 247 uint_t recycle_hiwat; /* hiwat to recycle */ 248 uint_t free; /* free buffers */ 249 uint_t post; /* posted buffers */ 250 uint_t post_hiwat; /* hiwat to stop post */ 251 spinlock_t pool_lock; /* buffer pool lock */ 252 } xgell_rx_buffer_pool_t; 253 254 typedef struct xgell_ring_t { 255 xge_hal_channel_h channelh; 256 mac_t *macp; 257 mac_resource_handle_t handle; /* per ring cookie */ 258 } xgell_ring_t; 259 260 typedef struct { 261 caddr_t ndp; 262 mac_t *macp; 263 int instance; 264 dev_info_t *dev_info; 265 xge_hal_device_h devh; 266 xgell_ring_t ring_main; 267 xgell_rx_buffer_pool_t bf_pool; 268 int resched_avail; 269 int resched_send; 270 int resched_retry; 271 xge_hal_channel_h fifo_channel; 272 volatile int is_initialized; 273 xgell_config_t config; 274 volatile int in_reset; 275 timeout_id_t timeout_id; 276 kmutex_t genlock; 277 } xgelldev_t; 278 279 typedef struct { 280 mblk_t *mblk; 281 #if !defined(XGELL_TX_NOMAP_COPY) 282 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 283 int handle_cnt; 284 #endif 285 } xgell_txd_priv_t; 286 287 typedef struct { 288 xgell_rx_buffer_t *rx_buffer; 289 } xgell_rxd_priv_t; 290 291 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 292 xgelldev_t **lldev_out); 293 294 void xgell_device_free(xgelldev_t *lldev); 295 296 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 297 298 int xgell_device_unregister(xgelldev_t *lldev); 299 300 void xgell_callback_link_up(void *userdata); 301 302 void xgell_callback_link_down(void *userdata); 303 304 int xgell_onerr_reset(xgelldev_t *lldev); 305 306 void xge_device_poll_now(void *data); 307 308 #ifdef __cplusplus 309 } 310 #endif 311 312 #endif /* _SYS_XGELL_H */ 313