1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 #ifndef _TPM_TIS_H 27 #define _TPM_TIS_H 28 29 /* 30 * TPM Interface Specification Defaults 31 * ICH7 spec (pg 253) says this is the base 32 * TPM on LPC: FED40000-FED40FFF But this is only locality 0 33 * It has to include 4 localities so the real range is FED40000-FED44FFF 34 * (TIS 1.2 pg 27) 35 */ 36 #define TIS_MEM_BASE 0xFED40000 37 #define TIS_MEM_LEN 0x5000 38 39 #define TPM_LOCALITY_OFFSET(x) ((x) << 12) 40 41 /* Used to gain ownership */ 42 #define TPM_ACCESS 0x0000 43 /* Enable Interrupts */ 44 #define TPM_INT_ENABLE 0x0008 45 /* Interrupt vector (SIRQ values) */ 46 #define TPM_INT_VECTOR 0x000C 47 /* What caused interrupt */ 48 #define TPM_INT_STATUS 0x0010 49 /* Supported Interrupts */ 50 #define TPM_INTF_CAP 0x0014 51 /* Status Register */ 52 #define TPM_STS 0x0018 53 /* I/O FIFO */ 54 #define TPM_DATA_FIFO 0x0024 55 /* Vendor and Device ID */ 56 #define TPM_DID_VID 0x0F00 57 /* Revision ID */ 58 #define TPM_RID 0x0F04 59 60 /* The number of all ordinals */ 61 #define TSC_ORDINAL_MAX 12 62 #define TPM_ORDINAL_MAX 243 63 #define TSC_ORDINAL_MASK 0x40000000 64 65 /* Timeouts (in milliseconds) (TIS v1.2 pg 43) */ 66 #define TPM_REQUEST_TIMEOUT 9000000 /* 9 seconds...too long? */ 67 #define TPM_POLLING_TIMEOUT 10000 /* 10 ms for polling */ 68 69 enum tis_timeouts { 70 TIS_TIMEOUT_A = 750000, 71 TIS_TIMEOUT_B = 2000000, 72 TIS_TIMEOUT_C = 750000, 73 TIS_TIMEOUT_D = 750000 74 }; 75 76 #define TPM_DEFAULT_DURATION 750000 77 78 /* Possible TPM_ACCESS register bit values (TIS 1.2 pg.47-49) */ 79 enum tis_access { 80 TPM_ACCESS_VALID = 0x80, 81 TPM_ACCESS_ACTIVE_LOCALITY = 0x20, 82 TPM_ACCESS_REQUEST_PENDING = 0x04, 83 TPM_ACCESS_REQUEST_USE = 0x02 84 }; 85 86 /* Possible TPM_STS register values (TIS 1.2 pg.52-54) */ 87 enum tis_status { 88 /* bit 0 and bit 2 are reserved */ 89 TPM_STS_RESPONSE_RETRY = 0x02, /* bit 1 */ 90 TPM_STS_DATA_EXPECT = 0x08, /* bit 3 */ 91 TPM_STS_DATA_AVAIL = 0x10, /* bit 4 */ 92 TPM_STS_GO = 0x20, /* bit 5 */ 93 TPM_STS_CMD_READY = 0x40, /* bit 6 */ 94 TPM_STS_VALID = 0x80 /* bit 7 */ 95 }; 96 97 /* Possible TPM_INTF_CAPABILITY register values (TIS 1.2 pg.55) */ 98 enum tis_intf_cap { 99 TPM_INTF_BURST_COUNT_STATIC = 0x100, 100 TPM_INTF_CMD_READY_INT = 0x080, 101 TPM_INTF_INT_EDGE_FALLING = 0x040, 102 TPM_INTF_INT_EDGE_RISING = 0x020, 103 TPM_INTF_INT_LEVEL_LOW = 0x010, 104 TPM_INTF_INT_LEVEL_HIGH = 0x008, 105 TPM_INTF_INT_LOCALITY_CHANGE_INT = 0x004, 106 TPM_INTF_INT_STS_VALID_INT = 0x002, 107 TPM_INTF_INT_DATA_AVAIL_INT = 0x001 108 }; 109 110 /* Possible TPM_INT_ENABLE register values (TIS 1.2 pg.62-63) */ 111 /* Interrupt enable bit for TPM_INT_ENABLE_x register */ 112 /* Too big to fit in enum... */ 113 #define TPM_INT_GLOBAL_EN 0x80000000 114 enum tis_int_enable { 115 TPM_INT_CMD_RDY_EN = 0x80, 116 TPM_INT_LOCAL_CHANGE_INT_EN = 0x04, 117 TPM_INT_STS_VALID_EN = 0x02, 118 TPM_INT_STS_DATA_AVAIL_EN = 0x01 119 }; 120 121 #endif /* _TPM_TIS_H */ 122