1 /* 2 * sfe_util.h: header to support the gem layer used by Masa Murayama 3 * 4 * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" /* sfe device driver */ 35 36 #ifndef _SFE_UTIL_H_ 37 #define _SFE_UTIL_H_ 38 #include <sys/mac.h> 39 #include <sys/mac_ether.h> 40 41 /* 42 * Useful macros and typedefs 43 */ 44 45 #define GEM_NAME_LEN 32 46 47 #define GEM_TX_TIMEOUT (drv_usectohz(5*1000000)) 48 #define GEM_TX_TIMEOUT_INTERVAL (drv_usectohz(1*1000000)) 49 #define GEM_LINK_WATCH_INTERVAL (drv_usectohz(1*1000000)) /* 1 sec */ 50 51 /* general return code */ 52 #define GEM_SUCCESS 0 53 #define GEM_FAILURE (-1) 54 55 /* return code of gem_tx_done */ 56 #define INTR_RESTART_TX 0x80000000 57 58 typedef int32_t seqnum_t; 59 60 /* 61 * I/O instructions 62 */ 63 #define OUTB(dp, p, v) \ 64 ddi_put8((dp)->regs_handle, \ 65 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 66 #define OUTW(dp, p, v) \ 67 ddi_put16((dp)->regs_handle, \ 68 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 69 #define OUTL(dp, p, v) \ 70 ddi_put32((dp)->regs_handle, \ 71 (void *)((caddr_t)((dp)->base_addr) + (p)), v) 72 #define INB(dp, p) \ 73 ddi_get8((dp)->regs_handle, \ 74 (void *)(((caddr_t)(dp)->base_addr) + (p))) 75 #define INW(dp, p) \ 76 ddi_get16((dp)->regs_handle, \ 77 (void *)(((caddr_t)(dp)->base_addr) + (p))) 78 #define INL(dp, p) \ 79 ddi_get32((dp)->regs_handle, \ 80 (void *)(((caddr_t)(dp)->base_addr) + (p))) 81 82 struct gem_stats { 83 uint32_t intr; 84 85 uint32_t crc; 86 uint32_t errrcv; 87 uint32_t overflow; 88 uint32_t frame; 89 uint32_t missed; 90 uint32_t runt; 91 uint32_t frame_too_long; 92 uint32_t norcvbuf; 93 uint32_t sqe; 94 95 uint32_t collisions; 96 uint32_t first_coll; 97 uint32_t multi_coll; 98 uint32_t excoll; 99 uint32_t xmit_internal_err; 100 uint32_t nocarrier; 101 uint32_t defer; 102 uint32_t errxmt; 103 uint32_t underflow; 104 uint32_t xmtlatecoll; 105 uint32_t noxmtbuf; 106 uint32_t jabber; 107 108 uint64_t rbytes; 109 uint64_t obytes; 110 uint64_t rpackets; 111 uint64_t opackets; 112 uint32_t rbcast; 113 uint32_t obcast; 114 uint32_t rmcast; 115 uint32_t omcast; 116 uint32_t rcv_internal_err; 117 }; 118 #define GEM_MAXTXSEGS 4 119 #define GEM_MAXRXSEGS 1 120 121 #define GEM_MAXTXFRAGS 8 122 #define GEM_MAXRXFRAGS 4 123 /* TX buffer management */ 124 struct txbuf { 125 struct txbuf *txb_next; 126 127 /* pointer to original mblk */ 128 mblk_t *txb_mp; 129 130 /* dma mapping for current packet */ 131 ddi_dma_cookie_t txb_dmacookie[GEM_MAXTXFRAGS]; 132 uint_t txb_nfrags; 133 134 /* bounce buffer management */ 135 ddi_dma_handle_t txb_bdh; 136 ddi_acc_handle_t txb_bah; 137 caddr_t txb_buf; /* vaddr of bounce buffer */ 138 uint64_t txb_buf_dma; /* paddr of bounce buffer */ 139 140 /* timeout management */ 141 clock_t txb_stime; 142 143 /* Hardware descriptor info */ 144 seqnum_t txb_desc; 145 int txb_ndescs; 146 uint64_t txb_flag; 147 }; 148 149 150 /* RX buffer management */ 151 struct rxbuf { 152 /* Hardware independent section */ 153 struct rxbuf *rxb_next; 154 struct gem_dev *rxb_devp; 155 156 /* dma mapping management */ 157 ddi_dma_handle_t rxb_dh; 158 caddr_t rxb_buf; 159 size_t rxb_buf_len; 160 ddi_dma_cookie_t rxb_dmacookie[GEM_MAXRXFRAGS]; 161 uint_t rxb_nfrags; 162 163 /* bounce buffer management */ 164 ddi_acc_handle_t rxb_bah; 165 }; 166 167 struct mcast_addr { 168 struct ether_addr addr; 169 uint32_t hash; 170 }; 171 172 #define GEM_MAXMC 64 173 #define GEM_MCALLOC (sizeof (struct mcast_addr) * GEM_MAXMC) 174 175 #define SUB(x, y) ((seqnum_t)((x) - (y))) 176 #define SLOT(seqnum, size) (((unsigned int)(seqnum)) & ((size)-1)) 177 178 /* 179 * mac soft state 180 */ 181 struct gem_dev { 182 dev_info_t *dip; 183 mac_handle_t mh; 184 char name[GEM_NAME_LEN]; 185 void *base_addr; 186 ddi_acc_handle_t regs_handle; 187 ddi_iblock_cookie_t iblock_cookie; 188 189 /* MAC address information */ 190 struct ether_addr cur_addr; 191 struct ether_addr dev_addr; 192 193 /* Descriptor rings, io area */ 194 ddi_dma_handle_t desc_dma_handle; 195 ddi_acc_handle_t desc_acc_handle; 196 caddr_t rx_ring; 197 caddr_t tx_ring; 198 caddr_t io_area; 199 /* caddr_t rx_buf; */ 200 201 uint64_t rx_ring_dma; 202 uint64_t tx_ring_dma; 203 uint64_t io_area_dma; 204 205 /* RX slot ring management */ 206 kmutex_t intrlock; 207 boolean_t intr_busy; 208 seqnum_t rx_active_head; 209 seqnum_t rx_active_tail; 210 mac_resource_handle_t mac_rx_ring_ha; 211 /* Rx buffer management */ 212 struct rxbuf *rx_buf_head; 213 struct rxbuf *rx_buf_tail; 214 struct rxbuf *rx_buf_freelist; 215 int rx_buf_allocated; 216 int rx_buf_freecnt; 217 int rx_buf_len; 218 219 /* TX descriptor ring management */ 220 seqnum_t tx_desc_head; 221 seqnum_t tx_desc_tail; 222 seqnum_t tx_desc_intr; 223 224 /* TX buffur ring management */ 225 kmutex_t xmitlock; 226 kcondvar_t tx_drain_cv; 227 seqnum_t tx_active_head; 228 seqnum_t tx_active_tail; 229 seqnum_t tx_softq_head; 230 seqnum_t tx_softq_tail; 231 seqnum_t tx_free_head; 232 seqnum_t tx_free_tail; 233 int tx_max_packets; 234 235 /* TX buffer resource management */ 236 struct txbuf *tx_buf; 237 seqnum_t tx_slots_base; 238 239 /* TX state management */ 240 int tx_busy; 241 int tx_reclaim_busy; 242 clock_t tx_blocked; 243 244 /* NIC state */ 245 volatile boolean_t mac_active; /* tx and rx are running */ 246 volatile int nic_state; /* logical driver state */ 247 #define NIC_STATE_STOPPED 0 248 #define NIC_STATE_INITIALIZED 1 249 #define NIC_STATE_ONLINE 2 250 volatile boolean_t mac_suspended; 251 252 /* robustness: timer and watchdog */ 253 volatile timeout_id_t timeout_id; 254 255 256 /* MII management */ 257 boolean_t anadv_autoneg:1; 258 boolean_t anadv_1000fdx:1; 259 boolean_t anadv_1000hdx:1; 260 boolean_t anadv_100t4:1; 261 boolean_t anadv_100fdx:1; 262 boolean_t anadv_100hdx:1; 263 boolean_t anadv_10fdx:1; 264 boolean_t anadv_10hdx:1; 265 boolean_t anadv_flow_control:2; 266 boolean_t mii_advert_ro:1; 267 268 boolean_t full_duplex:1; 269 int speed:3; 270 #define GEM_SPD_10 0 271 #define GEM_SPD_100 1 272 #define GEM_SPD_1000 2 273 #define GEM_SPD_NUM 3 274 unsigned int flow_control:2; 275 #define FLOW_CONTROL_NONE 0 276 #define FLOW_CONTROL_SYMMETRIC 1 277 #define FLOW_CONTROL_TX_PAUSE 2 278 #define FLOW_CONTROL_RX_PAUSE 3 279 280 boolean_t mii_supress_msg:1; 281 282 uint32_t mii_phy_id; 283 uint16_t mii_status; 284 uint16_t mii_advert; 285 uint16_t mii_lpable; 286 uint16_t mii_exp; 287 uint16_t mii_ctl1000; 288 uint16_t mii_stat1000; 289 uint16_t mii_xstatus; 290 int8_t mii_phy_addr; /* must be signed */ 291 292 uint8_t mii_state; 293 #define MII_STATE_UNKNOWN 0 294 #define MII_STATE_RESETTING 1 295 #define MII_STATE_AUTONEGOTIATING 2 296 #define MII_STATE_AN_DONE 3 297 #define MII_STATE_MEDIA_SETUP 4 298 #define MII_STATE_LINKUP 5 299 #define MII_STATE_LINKDOWN 6 300 301 clock_t mii_last_check; /* in tick */ 302 clock_t mii_timer; /* in tick */ 303 #define MII_RESET_TIMEOUT drv_usectohz(1000*1000) 304 #define MII_AN_TIMEOUT drv_usectohz(5000*1000) 305 #define MII_LINKDOWN_TIMEOUT drv_usectohz(10000*1000) 306 clock_t mii_interval; /* in tick */ 307 clock_t linkup_delay; /* in tick */ 308 309 volatile timeout_id_t link_watcher_id; 310 311 ddi_softintr_t soft_id; 312 313 /* multcast list management */ 314 int16_t mc_count; 315 int16_t mc_count_req; 316 struct mcast_addr *mc_list; 317 uint32_t rxmode; 318 #define RXMODE_PROMISC 0x01 319 #define RXMODE_ALLMULTI_REQ 0x02 320 #define RXMODE_MULTI_OVF 0x04 321 #define RXMODE_ENABLE 0x08 322 #define RXMODE_ALLMULTI (RXMODE_ALLMULTI_REQ | RXMODE_MULTI_OVF) 323 #define RXMODE_BITS \ 324 "\020" \ 325 "\004ENABLE" \ 326 "\003MULTI_OVF" \ 327 "\002ALLMULTI_REQ" \ 328 "\001PROMISC" 329 330 /* statistcs */ 331 struct gem_stats stats; 332 333 /* pointer to local structure */ 334 void *private; 335 int priv_size; 336 337 /* polling mode */ 338 int poll_pkt_delay; /* in number of packets */ 339 340 /* descriptor area */ 341 int tx_desc_size; 342 int rx_desc_size; 343 344 /* configuration */ 345 struct gem_conf { 346 /* name */ 347 char gc_name[GEM_NAME_LEN]; 348 349 /* specification on tx and rx dma engine */ 350 long gc_tx_buf_align; 351 int gc_tx_max_frags; 352 int gc_tx_max_descs_per_pkt; 353 int gc_tx_buf_size; 354 int gc_tx_buf_limit; 355 int gc_tx_desc_unit_shift; 356 int gc_tx_ring_size; 357 int gc_tx_ring_limit; 358 int gc_tx_copy_thresh; 359 boolean_t gc_tx_auto_pad; 360 boolean_t gc_tx_desc_write_oo; 361 362 long gc_rx_buf_align; 363 int gc_rx_max_frags; 364 int gc_rx_desc_unit_shift; 365 int gc_rx_ring_size; 366 int gc_rx_copy_thresh; 367 int gc_rx_buf_max; 368 int gc_rx_header_len; 369 370 int gc_io_area_size; 371 372 /* memory mapping attributes */ 373 struct ddi_device_acc_attr gc_dev_attr; 374 struct ddi_device_acc_attr gc_buf_attr; 375 struct ddi_device_acc_attr gc_desc_attr; 376 377 /* dma attributes */ 378 ddi_dma_attr_t gc_dma_attr_desc; 379 ddi_dma_attr_t gc_dma_attr_txbuf; 380 ddi_dma_attr_t gc_dma_attr_rxbuf; 381 382 /* tx time out parameters */ 383 clock_t gc_tx_timeout; 384 clock_t gc_tx_timeout_interval; 385 386 /* auto negotiation capability */ 387 int gc_flow_control; 388 389 /* MII mode */ 390 int gc_mii_mode; 391 #define GEM_MODE_100BASETX 0 392 #define GEM_MODE_1000BASET 1 393 #define GEM_MODE_1000BASETX 2 394 395 /* MII link state watch parameters */ 396 clock_t gc_mii_linkdown_timeout; 397 clock_t gc_mii_link_watch_interval; 398 clock_t gc_mii_reset_timeout; 399 400 clock_t gc_mii_an_watch_interval; 401 clock_t gc_mii_an_timeout; 402 clock_t gc_mii_an_wait; 403 clock_t gc_mii_an_delay; 404 405 /* MII configuration */ 406 int gc_mii_addr_min; 407 int gc_mii_linkdown_action; 408 int gc_mii_linkdown_timeout_action; 409 #define MII_ACTION_NONE 0 410 #define MII_ACTION_RESET 1 411 #define MII_ACTION_RSA 2 412 boolean_t gc_mii_dont_reset; 413 boolean_t gc_mii_an_oneshot; 414 boolean_t gc_mii_hw_link_detection; 415 boolean_t gc_mii_stop_mac_on_linkdown; 416 417 /* I/O methods */ 418 419 /* mac operation */ 420 int (*gc_attach_chip)(struct gem_dev *dp); 421 int (*gc_reset_chip)(struct gem_dev *dp); 422 int (*gc_init_chip)(struct gem_dev *dp); 423 int (*gc_start_chip)(struct gem_dev *dp); 424 int (*gc_stop_chip)(struct gem_dev *dp); 425 uint32_t (*gc_multicast_hash)(struct gem_dev *dp, uint8_t *); 426 int (*gc_set_rx_filter)(struct gem_dev *dp); 427 int (*gc_set_media)(struct gem_dev *dp); 428 int (*gc_get_stats)(struct gem_dev *dp); 429 uint_t (*gc_interrupt)(struct gem_dev *dp); 430 431 /* descriptor operation */ 432 int (*gc_tx_desc_write)(struct gem_dev *dp, int slot, 433 ddi_dma_cookie_t *dmacookie, 434 int frags, uint64_t flag); 435 #define GEM_TXFLAG_INTR 0x00000001ull 436 #define GEM_TXFLAG_TCP 0x00000002ull 437 #define GEM_TXFLAG_TCP_SHIFT 1ull 438 #define GEM_TXFLAG_UDP 0x00000004ull 439 #define GEM_TXFLAG_UDP_SHIFT 2ull 440 #define GEM_TXFLAG_IPv4 0x00000008ull 441 #define GEM_TXFLAG_IPv4_SHIFT 3ull 442 #define GEM_TXFLAG_IPv6 0x00000010ull 443 #define GEM_TXFLAG_IPv6_SHIFT 4ull 444 #define GEM_TXFLAG_HEAD 0x00000020ull 445 #define GEM_TXFLAG_TAIL 0x00000040ull 446 #define GEM_TXFLAG_SWVTAG 0x00000080ull 447 #define GEM_TXFLAG_PRIVATE 0x0000ff00ull 448 #define GEM_TXFLAG_PRIVATE_SHIFT 8ull 449 #define GEM_TXFLAG_PRIVATE_MASK 0xffull 450 #define GEM_TXFLAG_VID 0x0fff0000ull 451 #define GEM_TXFLAG_VID_SHIFT 16ull 452 #define GEM_TXFLAG_VID_MASK 0xfffull 453 #define GEM_TXFLAG_CFI 0x10000000ull 454 #define GEM_TXFLAG_PRI 0xe0000000ull 455 #define GEM_TXFLAG_PRI_SHIFT 29ull 456 #define GEM_TXFLAG_PRI_MASK 0x7ull 457 #define GEM_TXFLAG_VTAG 0xffff0000ull 458 #define GEM_TXFLAG_VTAG_SHIFT 16ull 459 #define GEM_TXFLAG_HCKSTART 0x000000ff00000000ull 460 #define GEM_TXFLAG_HCKSTART_SHIFT 32ull 461 #define GEM_TXFLAG_HCKSTUFF 0x0000ff0000000000ull 462 #define GEM_TXFLAG_HCKSTUFF_SHIFT 40ull 463 #define GEM_TXFLAG_TCPHLEN 0x0000ff0000000000ull 464 #define GEM_TXFLAG_TCPHLEN_SHIFT 40ull 465 #define GEM_TXFLAG_MSS 0xffff000000000000ull 466 #define GEM_TXFLAG_MSS_SHIFT 48ull 467 468 void (*gc_tx_start) (struct gem_dev *dp, int slot, int frags); 469 void (*gc_rx_desc_write)(struct gem_dev *dp, int slot, 470 ddi_dma_cookie_t *dmacookie, int frags); 471 void (*gc_rx_start)(struct gem_dev *dp, int slot, int frags); 472 473 uint_t (*gc_tx_desc_stat) 474 (struct gem_dev *dp, int slot, int descs); 475 #define GEM_TX_DONE 0x00010000 476 #define GEM_TX_ERR 0x00020000 477 478 479 uint64_t (*gc_rx_desc_stat) 480 (struct gem_dev *dp, int slot, int frags); 481 482 #define GEM_RX_CKSUM 0xffff000000000000ull 483 #define GEM_RX_CKSUM_SHIFT 48 484 #define GEM_RX_PRI 0x0000e00000000000ull 485 #define GEM_RX_PRI_SHIFT 45 486 #define GEM_RX_CFI 0x0000100000000000ull 487 #define GEM_RX_VID 0x00000fff00000000ull 488 #define GEM_RX_VID_SHIFT 32 489 #define GEM_RX_VTAG 0x0000ffff00000000ull 490 #define GEM_RX_VTAG_SHIFT 32 491 492 #define GEM_RX_CKSUM_IPv6 0x00080000ul 493 #define GEM_RX_CKSUM_IPv6_SHIFT 19 494 #define GEM_RX_CKSUM_IPv4 0x00040000ul 495 #define GEM_RX_CKSUM_IPv4_SHIFT 18 496 #define GEM_RX_CKSUM_UDP 0x00020000ul 497 #define GEM_RX_CKSUM_UDP_SHIFT 17 498 #define GEM_RX_CKSUM_TCP 0x00010000ul 499 #define GEM_RX_CKSUM_TCP_SHIFT 16 500 #define GEM_RX_ERR 0x00008000ul 501 #define GEM_RX_DONE 0x00004000ul 502 #define GEM_RX_LEN 0x00003ffful /* 16KB - 1 */ 503 504 void (*gc_tx_desc_init)(struct gem_dev *dp, int slot); 505 void (*gc_rx_desc_init)(struct gem_dev *dp, int slot); 506 void (*gc_tx_desc_clean)(struct gem_dev *dp, int slot); 507 void (*gc_rx_desc_clean)(struct gem_dev *dp, int slot); 508 509 /* mii operations */ 510 int (*gc_mii_probe)(struct gem_dev *dp); 511 int (*gc_mii_init)(struct gem_dev *dp); 512 int (*gc_mii_config)(struct gem_dev *dp); 513 void (*gc_mii_sync)(struct gem_dev *dp); 514 uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg); 515 void (*gc_mii_write)(struct gem_dev *dp, 516 uint_t reg, uint16_t val); 517 void (*gc_mii_tune_phy)(struct gem_dev *dp); 518 519 /* packet in/out operation for copy-style */ 520 void (*gc_put_packet)(struct gem_dev *dp, 521 mblk_t *, void *, size_t); 522 mblk_t *(*gc_get_packet)(struct gem_dev *dp, 523 struct rxbuf *, size_t); 524 int gc_nports; 525 526 /* hw checksum */ 527 uint32_t gc_hck_rx_start; 528 } gc; 529 530 uint32_t misc_flag; 531 #define GEM_LSO 0x00000400 532 #define GEM_CTRL_PKT 0x00000200 533 #define GEM_SOFTINTR 0x00000100 534 #define GEM_POLL_RXONLY 0x00000080 535 #define GEM_VLAN_HARD 0x00000040 536 #define GEM_VLAN_SOFT 0x00000020 537 #define GEM_VLAN (GEM_VLAN_HARD | GEM_VLAN_SOFT) 538 #define GEM_CKSUM_HEADER_IPv4 0x00000010 539 #define GEM_CKSUM_PARTIAL 0x00000008 540 #define GEM_CKSUM_FULL_IPv6 0x00000004 541 #define GEM_CKSUM_FULL_IPv4 0x00000002 542 #define GEM_NOINTR 0x00000001 543 544 volatile timeout_id_t intr_watcher_id; 545 546 uint_t mtu; 547 548 /* performance tuning parameters */ 549 uint_t txthr; /* tx fifo threshoold */ 550 uint_t txmaxdma; /* tx max dma burst size */ 551 uint_t rxthr; /* rx fifo threshoold */ 552 uint_t rxmaxdma; /* tx max dma burst size */ 553 554 /* kstat stuff */ 555 kstat_t *ksp; 556 557 /* multiple port device support */ 558 struct gem_dev *next; /* pointer to next port on the same device */ 559 int port; 560 561 /* ndd stuff */ 562 caddr_t nd_data_p; 563 caddr_t nd_arg_p; 564 565 #ifdef GEM_DEBUG_LEVEL 566 int tx_cnt; 567 #endif 568 }; 569 570 /* 571 * Exported functions 572 */ 573 boolean_t gem_get_mac_addr_conf(struct gem_dev *); 574 int gem_mii_probe_default(struct gem_dev *); 575 int gem_mii_config_default(struct gem_dev *); 576 boolean_t gem_mii_link_check(struct gem_dev *dp); 577 uint16_t gem_mii_read(struct gem_dev *, uint_t); 578 void gem_mii_write(struct gem_dev *, uint_t, uint16_t); 579 int gem_reclaim_txbuf(struct gem_dev *dp); 580 int gem_restart_nic(struct gem_dev *dp, uint_t flags); 581 #define GEM_RESTART_NOWAIT 0x00000002 582 #define GEM_RESTART_KEEP_BUF 0x00000001 583 boolean_t gem_tx_done(struct gem_dev *); 584 int gem_receive(struct gem_dev *); 585 int gem_receive_copy(struct gem_dev *); 586 struct gem_dev *gem_do_attach(dev_info_t *, int, 587 struct gem_conf *, void *, ddi_acc_handle_t *, void *, int); 588 589 mblk_t *gem_send_common(struct gem_dev *, mblk_t *, uint32_t); 590 #define GEM_SEND_COPY 0x00008000 591 #define GEM_SEND_CTRL 0x000000ff /* private flags for control packets */ 592 #define GEM_SEND_VTAG 0xffff0000 593 #define GEM_SEND_VTAG_SHIFT 16 594 595 mblk_t *gem_get_packet_default(struct gem_dev *, struct rxbuf *, size_t); 596 597 uint32_t gem_ether_crc_le(const uint8_t *addr, int len); 598 uint32_t gem_ether_crc_be(const uint8_t *addr, int len); 599 int gem_do_detach(dev_info_t *); 600 601 int gem_getlongprop_buf(dev_t dev, dev_info_t *dip, 602 int flags, char *name, void *buf, int *lenp); 603 int gem_getprop(dev_t dev, dev_info_t *dip, 604 int flags, char *name, int defvalue); 605 606 struct rxbuf *gem_get_rxbuf(struct gem_dev *, int); 607 608 void gem_rx_desc_dma_sync(struct gem_dev *, int, int, int); 609 void gem_tx_desc_dma_sync(struct gem_dev *, int, int, int); 610 611 int gem_resume(dev_info_t *); 612 int gem_suspend(dev_info_t *); 613 uint8_t gem_search_pci_cap(dev_info_t *dip, ddi_acc_handle_t, uint8_t); 614 int gem_pci_set_power_state(dev_info_t *, ddi_acc_handle_t, uint_t); 615 int gem_pci_regs_map_setup(dev_info_t *, uint32_t, uint32_t, 616 struct ddi_device_acc_attr *, caddr_t *, ddi_acc_handle_t *); 617 void gem_mod_init(struct dev_ops *, char *); 618 void gem_mod_fini(struct dev_ops *); 619 620 #define GEM_GET_DEV(dip) \ 621 ((struct gem_dev *)(ddi_get_driver_private(dip))) 622 #endif /* _SFE_UTIL_H_ */ 623