1f8919bdaSduboff /* 2f8919bdaSduboff * sfe_util.h: header to support the gem layer used by Masa Murayama 3f8919bdaSduboff * 423d366e3Sduboff * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved. 5f8919bdaSduboff * 6f8919bdaSduboff * Redistribution and use in source and binary forms, with or without 7f8919bdaSduboff * modification, are permitted provided that the following conditions are met: 8f8919bdaSduboff * 9f8919bdaSduboff * 1. Redistributions of source code must retain the above copyright notice, 10f8919bdaSduboff * this list of conditions and the following disclaimer. 11f8919bdaSduboff * 12f8919bdaSduboff * 2. Redistributions in binary form must reproduce the above copyright notice, 13f8919bdaSduboff * this list of conditions and the following disclaimer in the documentation 14f8919bdaSduboff * and/or other materials provided with the distribution. 15f8919bdaSduboff * 16f8919bdaSduboff * 3. Neither the name of the author nor the names of its contributors may be 17f8919bdaSduboff * used to endorse or promote products derived from this software without 18f8919bdaSduboff * specific prior written permission. 19f8919bdaSduboff * 20f8919bdaSduboff * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21f8919bdaSduboff * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22f8919bdaSduboff * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23f8919bdaSduboff * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24f8919bdaSduboff * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25f8919bdaSduboff * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26f8919bdaSduboff * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27f8919bdaSduboff * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28f8919bdaSduboff * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29f8919bdaSduboff * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30f8919bdaSduboff * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31f8919bdaSduboff * DAMAGE. 32f8919bdaSduboff */ 3323d366e3Sduboff 34*da14cebeSEric Cheng /* 35*da14cebeSEric Cheng * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 36*da14cebeSEric Cheng * Use is subject to license terms. 37*da14cebeSEric Cheng */ 38*da14cebeSEric Cheng 39f8919bdaSduboff #ifndef _SFE_UTIL_H_ 40f8919bdaSduboff #define _SFE_UTIL_H_ 41*da14cebeSEric Cheng #include <sys/mac_provider.h> 42f8919bdaSduboff #include <sys/mac_ether.h> 43f8919bdaSduboff 44f8919bdaSduboff /* 45f8919bdaSduboff * Useful macros and typedefs 46f8919bdaSduboff */ 47f8919bdaSduboff 48f8919bdaSduboff #define GEM_NAME_LEN 32 49f8919bdaSduboff 50f8919bdaSduboff #define GEM_TX_TIMEOUT (drv_usectohz(5*1000000)) 51f8919bdaSduboff #define GEM_TX_TIMEOUT_INTERVAL (drv_usectohz(1*1000000)) 52f8919bdaSduboff #define GEM_LINK_WATCH_INTERVAL (drv_usectohz(1*1000000)) /* 1 sec */ 53f8919bdaSduboff 54f8919bdaSduboff /* general return code */ 55f8919bdaSduboff #define GEM_SUCCESS 0 56f8919bdaSduboff #define GEM_FAILURE (-1) 57f8919bdaSduboff 58f8919bdaSduboff /* return code of gem_tx_done */ 59f8919bdaSduboff #define INTR_RESTART_TX 0x80000000 60f8919bdaSduboff 61f8919bdaSduboff typedef int32_t seqnum_t; 62f8919bdaSduboff 63f8919bdaSduboff /* 64f8919bdaSduboff * I/O instructions 65f8919bdaSduboff */ 66f8919bdaSduboff #define OUTB(dp, p, v) \ 67f8919bdaSduboff ddi_put8((dp)->regs_handle, \ 68f8919bdaSduboff (void *)((caddr_t)((dp)->base_addr) + (p)), v) 69f8919bdaSduboff #define OUTW(dp, p, v) \ 70f8919bdaSduboff ddi_put16((dp)->regs_handle, \ 71f8919bdaSduboff (void *)((caddr_t)((dp)->base_addr) + (p)), v) 72f8919bdaSduboff #define OUTL(dp, p, v) \ 73f8919bdaSduboff ddi_put32((dp)->regs_handle, \ 74f8919bdaSduboff (void *)((caddr_t)((dp)->base_addr) + (p)), v) 75915ebf8dSAlan Duboff #define OUTLINL(dp, p, v) \ 76915ebf8dSAlan Duboff ddi_put32((dp)->regs_handle, \ 77915ebf8dSAlan Duboff (void *)((caddr_t)((dp)->base_addr) + (p)), v); \ 78915ebf8dSAlan Duboff (void) INL((dp), (p)) 79f8919bdaSduboff #define INB(dp, p) \ 80f8919bdaSduboff ddi_get8((dp)->regs_handle, \ 81f8919bdaSduboff (void *)(((caddr_t)(dp)->base_addr) + (p))) 82f8919bdaSduboff #define INW(dp, p) \ 83f8919bdaSduboff ddi_get16((dp)->regs_handle, \ 84f8919bdaSduboff (void *)(((caddr_t)(dp)->base_addr) + (p))) 85f8919bdaSduboff #define INL(dp, p) \ 86f8919bdaSduboff ddi_get32((dp)->regs_handle, \ 87f8919bdaSduboff (void *)(((caddr_t)(dp)->base_addr) + (p))) 88f8919bdaSduboff 89f8919bdaSduboff struct gem_stats { 90f8919bdaSduboff uint32_t intr; 91f8919bdaSduboff 92f8919bdaSduboff uint32_t crc; 93f8919bdaSduboff uint32_t errrcv; 94f8919bdaSduboff uint32_t overflow; 95f8919bdaSduboff uint32_t frame; 96f8919bdaSduboff uint32_t missed; 97f8919bdaSduboff uint32_t runt; 98f8919bdaSduboff uint32_t frame_too_long; 99f8919bdaSduboff uint32_t norcvbuf; 100f8919bdaSduboff uint32_t sqe; 101f8919bdaSduboff 102f8919bdaSduboff uint32_t collisions; 103f8919bdaSduboff uint32_t first_coll; 104f8919bdaSduboff uint32_t multi_coll; 105f8919bdaSduboff uint32_t excoll; 106f8919bdaSduboff uint32_t xmit_internal_err; 107f8919bdaSduboff uint32_t nocarrier; 108f8919bdaSduboff uint32_t defer; 109f8919bdaSduboff uint32_t errxmt; 110f8919bdaSduboff uint32_t underflow; 111f8919bdaSduboff uint32_t xmtlatecoll; 112f8919bdaSduboff uint32_t noxmtbuf; 113f8919bdaSduboff uint32_t jabber; 114f8919bdaSduboff 115f8919bdaSduboff uint64_t rbytes; 116f8919bdaSduboff uint64_t obytes; 117f8919bdaSduboff uint64_t rpackets; 118f8919bdaSduboff uint64_t opackets; 119f8919bdaSduboff uint32_t rbcast; 120f8919bdaSduboff uint32_t obcast; 121f8919bdaSduboff uint32_t rmcast; 122f8919bdaSduboff uint32_t omcast; 123f8919bdaSduboff uint32_t rcv_internal_err; 124f8919bdaSduboff }; 125f8919bdaSduboff #define GEM_MAXTXSEGS 4 126f8919bdaSduboff #define GEM_MAXRXSEGS 1 127f8919bdaSduboff 128f8919bdaSduboff #define GEM_MAXTXFRAGS 8 129f8919bdaSduboff #define GEM_MAXRXFRAGS 4 130f8919bdaSduboff /* TX buffer management */ 131f8919bdaSduboff struct txbuf { 132f8919bdaSduboff struct txbuf *txb_next; 133f8919bdaSduboff 134f8919bdaSduboff /* pointer to original mblk */ 135f8919bdaSduboff mblk_t *txb_mp; 136f8919bdaSduboff 137f8919bdaSduboff /* dma mapping for current packet */ 138f8919bdaSduboff ddi_dma_cookie_t txb_dmacookie[GEM_MAXTXFRAGS]; 139f8919bdaSduboff uint_t txb_nfrags; 140f8919bdaSduboff 141f8919bdaSduboff /* bounce buffer management */ 142f8919bdaSduboff ddi_dma_handle_t txb_bdh; 143f8919bdaSduboff ddi_acc_handle_t txb_bah; 144f8919bdaSduboff caddr_t txb_buf; /* vaddr of bounce buffer */ 145f8919bdaSduboff uint64_t txb_buf_dma; /* paddr of bounce buffer */ 146f8919bdaSduboff 147f8919bdaSduboff /* timeout management */ 148f8919bdaSduboff clock_t txb_stime; 149f8919bdaSduboff 150f8919bdaSduboff /* Hardware descriptor info */ 151f8919bdaSduboff seqnum_t txb_desc; 152f8919bdaSduboff int txb_ndescs; 153f8919bdaSduboff uint64_t txb_flag; 154f8919bdaSduboff }; 155f8919bdaSduboff 156f8919bdaSduboff 157f8919bdaSduboff /* RX buffer management */ 158f8919bdaSduboff struct rxbuf { 15923d366e3Sduboff /* Hardware independent section */ 160f8919bdaSduboff struct rxbuf *rxb_next; 161f8919bdaSduboff struct gem_dev *rxb_devp; 162f8919bdaSduboff 163f8919bdaSduboff /* dma mapping management */ 164f8919bdaSduboff ddi_dma_handle_t rxb_dh; 165f8919bdaSduboff caddr_t rxb_buf; 166f8919bdaSduboff size_t rxb_buf_len; 167f8919bdaSduboff ddi_dma_cookie_t rxb_dmacookie[GEM_MAXRXFRAGS]; 168f8919bdaSduboff uint_t rxb_nfrags; 169f8919bdaSduboff 170f8919bdaSduboff /* bounce buffer management */ 171f8919bdaSduboff ddi_acc_handle_t rxb_bah; 172f8919bdaSduboff }; 173f8919bdaSduboff 174f8919bdaSduboff struct mcast_addr { 175f8919bdaSduboff struct ether_addr addr; 176f8919bdaSduboff uint32_t hash; 177f8919bdaSduboff }; 178f8919bdaSduboff 179f8919bdaSduboff #define GEM_MAXMC 64 180f8919bdaSduboff #define GEM_MCALLOC (sizeof (struct mcast_addr) * GEM_MAXMC) 181f8919bdaSduboff 182f8919bdaSduboff #define SUB(x, y) ((seqnum_t)((x) - (y))) 183f8919bdaSduboff #define SLOT(seqnum, size) (((unsigned int)(seqnum)) & ((size)-1)) 184f8919bdaSduboff 185f8919bdaSduboff /* 186f8919bdaSduboff * mac soft state 187f8919bdaSduboff */ 188f8919bdaSduboff struct gem_dev { 189f8919bdaSduboff dev_info_t *dip; 190f8919bdaSduboff mac_handle_t mh; 191f8919bdaSduboff char name[GEM_NAME_LEN]; 192f8919bdaSduboff void *base_addr; 193f8919bdaSduboff ddi_acc_handle_t regs_handle; 194f8919bdaSduboff ddi_iblock_cookie_t iblock_cookie; 195f8919bdaSduboff 196f8919bdaSduboff /* MAC address information */ 197f8919bdaSduboff struct ether_addr cur_addr; 198f8919bdaSduboff struct ether_addr dev_addr; 199f8919bdaSduboff 200f8919bdaSduboff /* Descriptor rings, io area */ 201f8919bdaSduboff ddi_dma_handle_t desc_dma_handle; 202f8919bdaSduboff ddi_acc_handle_t desc_acc_handle; 203f8919bdaSduboff caddr_t rx_ring; 204f8919bdaSduboff caddr_t tx_ring; 205f8919bdaSduboff caddr_t io_area; 206f8919bdaSduboff /* caddr_t rx_buf; */ 207f8919bdaSduboff 208f8919bdaSduboff uint64_t rx_ring_dma; 209f8919bdaSduboff uint64_t tx_ring_dma; 210f8919bdaSduboff uint64_t io_area_dma; 211f8919bdaSduboff 212f8919bdaSduboff /* RX slot ring management */ 213f8919bdaSduboff kmutex_t intrlock; 214f8919bdaSduboff boolean_t intr_busy; 215f8919bdaSduboff seqnum_t rx_active_head; 216f8919bdaSduboff seqnum_t rx_active_tail; 217f8919bdaSduboff mac_resource_handle_t mac_rx_ring_ha; 218f8919bdaSduboff /* Rx buffer management */ 219f8919bdaSduboff struct rxbuf *rx_buf_head; 220f8919bdaSduboff struct rxbuf *rx_buf_tail; 221f8919bdaSduboff struct rxbuf *rx_buf_freelist; 222f8919bdaSduboff int rx_buf_allocated; 223f8919bdaSduboff int rx_buf_freecnt; 224f8919bdaSduboff int rx_buf_len; 225f8919bdaSduboff 226f8919bdaSduboff /* TX descriptor ring management */ 227f8919bdaSduboff seqnum_t tx_desc_head; 228f8919bdaSduboff seqnum_t tx_desc_tail; 229f8919bdaSduboff seqnum_t tx_desc_intr; 230f8919bdaSduboff 231f8919bdaSduboff /* TX buffur ring management */ 232f8919bdaSduboff kmutex_t xmitlock; 233f8919bdaSduboff kcondvar_t tx_drain_cv; 234f8919bdaSduboff seqnum_t tx_active_head; 235f8919bdaSduboff seqnum_t tx_active_tail; 236f8919bdaSduboff seqnum_t tx_softq_head; 237f8919bdaSduboff seqnum_t tx_softq_tail; 238f8919bdaSduboff seqnum_t tx_free_head; 239f8919bdaSduboff seqnum_t tx_free_tail; 24023d366e3Sduboff int tx_max_packets; 241f8919bdaSduboff 242f8919bdaSduboff /* TX buffer resource management */ 243f8919bdaSduboff struct txbuf *tx_buf; 244f8919bdaSduboff seqnum_t tx_slots_base; 245f8919bdaSduboff 246f8919bdaSduboff /* TX state management */ 247f8919bdaSduboff int tx_busy; 248f8919bdaSduboff int tx_reclaim_busy; 24923d366e3Sduboff clock_t tx_blocked; 250f8919bdaSduboff 251f8919bdaSduboff /* NIC state */ 252f8919bdaSduboff volatile boolean_t mac_active; /* tx and rx are running */ 253f8919bdaSduboff volatile int nic_state; /* logical driver state */ 254f8919bdaSduboff #define NIC_STATE_STOPPED 0 255f8919bdaSduboff #define NIC_STATE_INITIALIZED 1 256f8919bdaSduboff #define NIC_STATE_ONLINE 2 257f8919bdaSduboff volatile boolean_t mac_suspended; 258f8919bdaSduboff 259f8919bdaSduboff /* robustness: timer and watchdog */ 260f8919bdaSduboff volatile timeout_id_t timeout_id; 261f8919bdaSduboff 262f8919bdaSduboff 263f8919bdaSduboff /* MII management */ 264f8919bdaSduboff boolean_t anadv_autoneg:1; 265f8919bdaSduboff boolean_t anadv_1000fdx:1; 266f8919bdaSduboff boolean_t anadv_1000hdx:1; 267f8919bdaSduboff boolean_t anadv_100t4:1; 268f8919bdaSduboff boolean_t anadv_100fdx:1; 269f8919bdaSduboff boolean_t anadv_100hdx:1; 270f8919bdaSduboff boolean_t anadv_10fdx:1; 271f8919bdaSduboff boolean_t anadv_10hdx:1; 272f8919bdaSduboff boolean_t anadv_flow_control:2; 273f8919bdaSduboff boolean_t mii_advert_ro:1; 274f8919bdaSduboff 275f8919bdaSduboff boolean_t full_duplex:1; 276f8919bdaSduboff int speed:3; 277f8919bdaSduboff #define GEM_SPD_10 0 278f8919bdaSduboff #define GEM_SPD_100 1 279f8919bdaSduboff #define GEM_SPD_1000 2 28023d366e3Sduboff #define GEM_SPD_NUM 3 281f8919bdaSduboff unsigned int flow_control:2; 282f8919bdaSduboff #define FLOW_CONTROL_NONE 0 283f8919bdaSduboff #define FLOW_CONTROL_SYMMETRIC 1 284f8919bdaSduboff #define FLOW_CONTROL_TX_PAUSE 2 285f8919bdaSduboff #define FLOW_CONTROL_RX_PAUSE 3 286f8919bdaSduboff 287f8919bdaSduboff boolean_t mii_supress_msg:1; 288f8919bdaSduboff 289f8919bdaSduboff uint32_t mii_phy_id; 290f8919bdaSduboff uint16_t mii_status; 291f8919bdaSduboff uint16_t mii_advert; 292f8919bdaSduboff uint16_t mii_lpable; 293f8919bdaSduboff uint16_t mii_exp; 294f8919bdaSduboff uint16_t mii_ctl1000; 295f8919bdaSduboff uint16_t mii_stat1000; 296f8919bdaSduboff uint16_t mii_xstatus; 297f8919bdaSduboff int8_t mii_phy_addr; /* must be signed */ 298f8919bdaSduboff 299f8919bdaSduboff uint8_t mii_state; 300f8919bdaSduboff #define MII_STATE_UNKNOWN 0 301f8919bdaSduboff #define MII_STATE_RESETTING 1 302f8919bdaSduboff #define MII_STATE_AUTONEGOTIATING 2 303f8919bdaSduboff #define MII_STATE_AN_DONE 3 304f8919bdaSduboff #define MII_STATE_MEDIA_SETUP 4 305f8919bdaSduboff #define MII_STATE_LINKUP 5 306f8919bdaSduboff #define MII_STATE_LINKDOWN 6 307f8919bdaSduboff 308f8919bdaSduboff clock_t mii_last_check; /* in tick */ 309f8919bdaSduboff clock_t mii_timer; /* in tick */ 310f8919bdaSduboff #define MII_RESET_TIMEOUT drv_usectohz(1000*1000) 311f8919bdaSduboff #define MII_AN_TIMEOUT drv_usectohz(5000*1000) 312f8919bdaSduboff #define MII_LINKDOWN_TIMEOUT drv_usectohz(10000*1000) 313f8919bdaSduboff clock_t mii_interval; /* in tick */ 31423d366e3Sduboff clock_t linkup_delay; /* in tick */ 315f8919bdaSduboff 316f8919bdaSduboff volatile timeout_id_t link_watcher_id; 317f8919bdaSduboff 318f8919bdaSduboff ddi_softintr_t soft_id; 319f8919bdaSduboff 320f8919bdaSduboff /* multcast list management */ 321f8919bdaSduboff int16_t mc_count; 322f8919bdaSduboff int16_t mc_count_req; 323f8919bdaSduboff struct mcast_addr *mc_list; 324f8919bdaSduboff uint32_t rxmode; 325f8919bdaSduboff #define RXMODE_PROMISC 0x01 326f8919bdaSduboff #define RXMODE_ALLMULTI_REQ 0x02 327f8919bdaSduboff #define RXMODE_MULTI_OVF 0x04 328f8919bdaSduboff #define RXMODE_ENABLE 0x08 329f8919bdaSduboff #define RXMODE_ALLMULTI (RXMODE_ALLMULTI_REQ | RXMODE_MULTI_OVF) 330f8919bdaSduboff #define RXMODE_BITS \ 331f8919bdaSduboff "\020" \ 332f8919bdaSduboff "\004ENABLE" \ 333f8919bdaSduboff "\003MULTI_OVF" \ 334f8919bdaSduboff "\002ALLMULTI_REQ" \ 335f8919bdaSduboff "\001PROMISC" 336f8919bdaSduboff 337f8919bdaSduboff /* statistcs */ 338f8919bdaSduboff struct gem_stats stats; 339f8919bdaSduboff 340f8919bdaSduboff /* pointer to local structure */ 341f8919bdaSduboff void *private; 342f8919bdaSduboff int priv_size; 343f8919bdaSduboff 344f8919bdaSduboff /* polling mode */ 345f8919bdaSduboff int poll_pkt_delay; /* in number of packets */ 346f8919bdaSduboff 347f8919bdaSduboff /* descriptor area */ 348f8919bdaSduboff int tx_desc_size; 349f8919bdaSduboff int rx_desc_size; 350f8919bdaSduboff 351f8919bdaSduboff /* configuration */ 352f8919bdaSduboff struct gem_conf { 353f8919bdaSduboff /* name */ 354f8919bdaSduboff char gc_name[GEM_NAME_LEN]; 355f8919bdaSduboff 356f8919bdaSduboff /* specification on tx and rx dma engine */ 357f8919bdaSduboff long gc_tx_buf_align; 358f8919bdaSduboff int gc_tx_max_frags; 359f8919bdaSduboff int gc_tx_max_descs_per_pkt; 360f8919bdaSduboff int gc_tx_buf_size; 361f8919bdaSduboff int gc_tx_buf_limit; 362f8919bdaSduboff int gc_tx_desc_unit_shift; 363f8919bdaSduboff int gc_tx_ring_size; 364f8919bdaSduboff int gc_tx_ring_limit; 365f8919bdaSduboff int gc_tx_copy_thresh; 366f8919bdaSduboff boolean_t gc_tx_auto_pad; 367f8919bdaSduboff boolean_t gc_tx_desc_write_oo; 368f8919bdaSduboff 369f8919bdaSduboff long gc_rx_buf_align; 370f8919bdaSduboff int gc_rx_max_frags; 371f8919bdaSduboff int gc_rx_desc_unit_shift; 372f8919bdaSduboff int gc_rx_ring_size; 373f8919bdaSduboff int gc_rx_copy_thresh; 374f8919bdaSduboff int gc_rx_buf_max; 375f8919bdaSduboff int gc_rx_header_len; 376f8919bdaSduboff 377f8919bdaSduboff int gc_io_area_size; 378f8919bdaSduboff 379f8919bdaSduboff /* memory mapping attributes */ 380f8919bdaSduboff struct ddi_device_acc_attr gc_dev_attr; 381f8919bdaSduboff struct ddi_device_acc_attr gc_buf_attr; 382f8919bdaSduboff struct ddi_device_acc_attr gc_desc_attr; 383f8919bdaSduboff 384f8919bdaSduboff /* dma attributes */ 385f8919bdaSduboff ddi_dma_attr_t gc_dma_attr_desc; 386f8919bdaSduboff ddi_dma_attr_t gc_dma_attr_txbuf; 387f8919bdaSduboff ddi_dma_attr_t gc_dma_attr_rxbuf; 388f8919bdaSduboff 389f8919bdaSduboff /* tx time out parameters */ 390f8919bdaSduboff clock_t gc_tx_timeout; 391f8919bdaSduboff clock_t gc_tx_timeout_interval; 392f8919bdaSduboff 393f8919bdaSduboff /* auto negotiation capability */ 394f8919bdaSduboff int gc_flow_control; 395f8919bdaSduboff 396f8919bdaSduboff /* MII mode */ 397f8919bdaSduboff int gc_mii_mode; 398f8919bdaSduboff #define GEM_MODE_100BASETX 0 399f8919bdaSduboff #define GEM_MODE_1000BASET 1 400f8919bdaSduboff #define GEM_MODE_1000BASETX 2 401f8919bdaSduboff 402f8919bdaSduboff /* MII link state watch parameters */ 403f8919bdaSduboff clock_t gc_mii_linkdown_timeout; 404f8919bdaSduboff clock_t gc_mii_link_watch_interval; 405f8919bdaSduboff clock_t gc_mii_reset_timeout; 406f8919bdaSduboff 407f8919bdaSduboff clock_t gc_mii_an_watch_interval; 408f8919bdaSduboff clock_t gc_mii_an_timeout; 409f8919bdaSduboff clock_t gc_mii_an_wait; 410f8919bdaSduboff clock_t gc_mii_an_delay; 411f8919bdaSduboff 412f8919bdaSduboff /* MII configuration */ 413f8919bdaSduboff int gc_mii_addr_min; 414f8919bdaSduboff int gc_mii_linkdown_action; 415f8919bdaSduboff int gc_mii_linkdown_timeout_action; 416f8919bdaSduboff #define MII_ACTION_NONE 0 417f8919bdaSduboff #define MII_ACTION_RESET 1 418f8919bdaSduboff #define MII_ACTION_RSA 2 419f8919bdaSduboff boolean_t gc_mii_dont_reset; 420f8919bdaSduboff boolean_t gc_mii_an_oneshot; 421f8919bdaSduboff boolean_t gc_mii_hw_link_detection; 422f8919bdaSduboff boolean_t gc_mii_stop_mac_on_linkdown; 423f8919bdaSduboff 424f8919bdaSduboff /* I/O methods */ 425f8919bdaSduboff 426f8919bdaSduboff /* mac operation */ 427f8919bdaSduboff int (*gc_attach_chip)(struct gem_dev *dp); 428f8919bdaSduboff int (*gc_reset_chip)(struct gem_dev *dp); 429f8919bdaSduboff int (*gc_init_chip)(struct gem_dev *dp); 430f8919bdaSduboff int (*gc_start_chip)(struct gem_dev *dp); 431f8919bdaSduboff int (*gc_stop_chip)(struct gem_dev *dp); 432f8919bdaSduboff uint32_t (*gc_multicast_hash)(struct gem_dev *dp, uint8_t *); 433f8919bdaSduboff int (*gc_set_rx_filter)(struct gem_dev *dp); 434f8919bdaSduboff int (*gc_set_media)(struct gem_dev *dp); 435f8919bdaSduboff int (*gc_get_stats)(struct gem_dev *dp); 436f8919bdaSduboff uint_t (*gc_interrupt)(struct gem_dev *dp); 437f8919bdaSduboff 438f8919bdaSduboff /* descriptor operation */ 439f8919bdaSduboff int (*gc_tx_desc_write)(struct gem_dev *dp, int slot, 440f8919bdaSduboff ddi_dma_cookie_t *dmacookie, 441f8919bdaSduboff int frags, uint64_t flag); 442f8919bdaSduboff #define GEM_TXFLAG_INTR 0x00000001ull 443f8919bdaSduboff #define GEM_TXFLAG_TCP 0x00000002ull 444f8919bdaSduboff #define GEM_TXFLAG_TCP_SHIFT 1ull 445f8919bdaSduboff #define GEM_TXFLAG_UDP 0x00000004ull 446f8919bdaSduboff #define GEM_TXFLAG_UDP_SHIFT 2ull 447f8919bdaSduboff #define GEM_TXFLAG_IPv4 0x00000008ull 448f8919bdaSduboff #define GEM_TXFLAG_IPv4_SHIFT 3ull 449f8919bdaSduboff #define GEM_TXFLAG_IPv6 0x00000010ull 450f8919bdaSduboff #define GEM_TXFLAG_IPv6_SHIFT 4ull 451f8919bdaSduboff #define GEM_TXFLAG_HEAD 0x00000020ull 452f8919bdaSduboff #define GEM_TXFLAG_TAIL 0x00000040ull 453f8919bdaSduboff #define GEM_TXFLAG_SWVTAG 0x00000080ull 454f8919bdaSduboff #define GEM_TXFLAG_PRIVATE 0x0000ff00ull 455f8919bdaSduboff #define GEM_TXFLAG_PRIVATE_SHIFT 8ull 456f8919bdaSduboff #define GEM_TXFLAG_PRIVATE_MASK 0xffull 457f8919bdaSduboff #define GEM_TXFLAG_VID 0x0fff0000ull 458f8919bdaSduboff #define GEM_TXFLAG_VID_SHIFT 16ull 459f8919bdaSduboff #define GEM_TXFLAG_VID_MASK 0xfffull 460f8919bdaSduboff #define GEM_TXFLAG_CFI 0x10000000ull 461f8919bdaSduboff #define GEM_TXFLAG_PRI 0xe0000000ull 462f8919bdaSduboff #define GEM_TXFLAG_PRI_SHIFT 29ull 463f8919bdaSduboff #define GEM_TXFLAG_PRI_MASK 0x7ull 464f8919bdaSduboff #define GEM_TXFLAG_VTAG 0xffff0000ull 465f8919bdaSduboff #define GEM_TXFLAG_VTAG_SHIFT 16ull 466f8919bdaSduboff #define GEM_TXFLAG_HCKSTART 0x000000ff00000000ull 467f8919bdaSduboff #define GEM_TXFLAG_HCKSTART_SHIFT 32ull 468f8919bdaSduboff #define GEM_TXFLAG_HCKSTUFF 0x0000ff0000000000ull 469f8919bdaSduboff #define GEM_TXFLAG_HCKSTUFF_SHIFT 40ull 47023d366e3Sduboff #define GEM_TXFLAG_TCPHLEN 0x0000ff0000000000ull 47123d366e3Sduboff #define GEM_TXFLAG_TCPHLEN_SHIFT 40ull 47223d366e3Sduboff #define GEM_TXFLAG_MSS 0xffff000000000000ull 47323d366e3Sduboff #define GEM_TXFLAG_MSS_SHIFT 48ull 474f8919bdaSduboff 475f8919bdaSduboff void (*gc_tx_start) (struct gem_dev *dp, int slot, int frags); 476f8919bdaSduboff void (*gc_rx_desc_write)(struct gem_dev *dp, int slot, 477f8919bdaSduboff ddi_dma_cookie_t *dmacookie, int frags); 478f8919bdaSduboff void (*gc_rx_start)(struct gem_dev *dp, int slot, int frags); 479f8919bdaSduboff 480f8919bdaSduboff uint_t (*gc_tx_desc_stat) 481f8919bdaSduboff (struct gem_dev *dp, int slot, int descs); 482f8919bdaSduboff #define GEM_TX_DONE 0x00010000 483f8919bdaSduboff #define GEM_TX_ERR 0x00020000 484f8919bdaSduboff 485f8919bdaSduboff 486f8919bdaSduboff uint64_t (*gc_rx_desc_stat) 487f8919bdaSduboff (struct gem_dev *dp, int slot, int frags); 488f8919bdaSduboff 489f8919bdaSduboff #define GEM_RX_CKSUM 0xffff000000000000ull 490f8919bdaSduboff #define GEM_RX_CKSUM_SHIFT 48 491f8919bdaSduboff #define GEM_RX_PRI 0x0000e00000000000ull 492f8919bdaSduboff #define GEM_RX_PRI_SHIFT 45 493f8919bdaSduboff #define GEM_RX_CFI 0x0000100000000000ull 494f8919bdaSduboff #define GEM_RX_VID 0x00000fff00000000ull 495f8919bdaSduboff #define GEM_RX_VID_SHIFT 32 496f8919bdaSduboff #define GEM_RX_VTAG 0x0000ffff00000000ull 497f8919bdaSduboff #define GEM_RX_VTAG_SHIFT 32 498f8919bdaSduboff 499f8919bdaSduboff #define GEM_RX_CKSUM_IPv6 0x00080000ul 500f8919bdaSduboff #define GEM_RX_CKSUM_IPv6_SHIFT 19 501f8919bdaSduboff #define GEM_RX_CKSUM_IPv4 0x00040000ul 502f8919bdaSduboff #define GEM_RX_CKSUM_IPv4_SHIFT 18 503f8919bdaSduboff #define GEM_RX_CKSUM_UDP 0x00020000ul 504f8919bdaSduboff #define GEM_RX_CKSUM_UDP_SHIFT 17 505f8919bdaSduboff #define GEM_RX_CKSUM_TCP 0x00010000ul 506f8919bdaSduboff #define GEM_RX_CKSUM_TCP_SHIFT 16 507f8919bdaSduboff #define GEM_RX_ERR 0x00008000ul 508f8919bdaSduboff #define GEM_RX_DONE 0x00004000ul 509f8919bdaSduboff #define GEM_RX_LEN 0x00003ffful /* 16KB - 1 */ 510f8919bdaSduboff 511f8919bdaSduboff void (*gc_tx_desc_init)(struct gem_dev *dp, int slot); 512f8919bdaSduboff void (*gc_rx_desc_init)(struct gem_dev *dp, int slot); 513f8919bdaSduboff void (*gc_tx_desc_clean)(struct gem_dev *dp, int slot); 514f8919bdaSduboff void (*gc_rx_desc_clean)(struct gem_dev *dp, int slot); 515f8919bdaSduboff 516f8919bdaSduboff /* mii operations */ 517f8919bdaSduboff int (*gc_mii_probe)(struct gem_dev *dp); 518f8919bdaSduboff int (*gc_mii_init)(struct gem_dev *dp); 519f8919bdaSduboff int (*gc_mii_config)(struct gem_dev *dp); 520f8919bdaSduboff void (*gc_mii_sync)(struct gem_dev *dp); 521f8919bdaSduboff uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg); 522f8919bdaSduboff void (*gc_mii_write)(struct gem_dev *dp, 523f8919bdaSduboff uint_t reg, uint16_t val); 524f8919bdaSduboff void (*gc_mii_tune_phy)(struct gem_dev *dp); 525f8919bdaSduboff 526f8919bdaSduboff /* packet in/out operation for copy-style */ 527f8919bdaSduboff void (*gc_put_packet)(struct gem_dev *dp, 528f8919bdaSduboff mblk_t *, void *, size_t); 529f8919bdaSduboff mblk_t *(*gc_get_packet)(struct gem_dev *dp, 530f8919bdaSduboff struct rxbuf *, size_t); 531f8919bdaSduboff int gc_nports; 532f8919bdaSduboff 533f8919bdaSduboff /* hw checksum */ 534f8919bdaSduboff uint32_t gc_hck_rx_start; 535f8919bdaSduboff } gc; 536f8919bdaSduboff 537f8919bdaSduboff uint32_t misc_flag; 53823d366e3Sduboff #define GEM_LSO 0x00000400 539f8919bdaSduboff #define GEM_CTRL_PKT 0x00000200 540f8919bdaSduboff #define GEM_SOFTINTR 0x00000100 541f8919bdaSduboff #define GEM_POLL_RXONLY 0x00000080 542f8919bdaSduboff #define GEM_VLAN_HARD 0x00000040 543f8919bdaSduboff #define GEM_VLAN_SOFT 0x00000020 544f8919bdaSduboff #define GEM_VLAN (GEM_VLAN_HARD | GEM_VLAN_SOFT) 545f8919bdaSduboff #define GEM_CKSUM_HEADER_IPv4 0x00000010 546f8919bdaSduboff #define GEM_CKSUM_PARTIAL 0x00000008 547f8919bdaSduboff #define GEM_CKSUM_FULL_IPv6 0x00000004 548f8919bdaSduboff #define GEM_CKSUM_FULL_IPv4 0x00000002 549f8919bdaSduboff #define GEM_NOINTR 0x00000001 550f8919bdaSduboff 551f8919bdaSduboff volatile timeout_id_t intr_watcher_id; 552f8919bdaSduboff 553f8919bdaSduboff uint_t mtu; 554f8919bdaSduboff 555f8919bdaSduboff /* performance tuning parameters */ 556f8919bdaSduboff uint_t txthr; /* tx fifo threshoold */ 557f8919bdaSduboff uint_t txmaxdma; /* tx max dma burst size */ 558f8919bdaSduboff uint_t rxthr; /* rx fifo threshoold */ 559f8919bdaSduboff uint_t rxmaxdma; /* tx max dma burst size */ 560f8919bdaSduboff 561f8919bdaSduboff /* kstat stuff */ 562f8919bdaSduboff kstat_t *ksp; 563f8919bdaSduboff 56423d366e3Sduboff /* multiple port device support */ 565f8919bdaSduboff struct gem_dev *next; /* pointer to next port on the same device */ 56623d366e3Sduboff int port; 567f8919bdaSduboff 568f8919bdaSduboff /* ndd stuff */ 569f8919bdaSduboff caddr_t nd_data_p; 570f8919bdaSduboff caddr_t nd_arg_p; 571f8919bdaSduboff 572f8919bdaSduboff #ifdef GEM_DEBUG_LEVEL 573f8919bdaSduboff int tx_cnt; 574f8919bdaSduboff #endif 575f8919bdaSduboff }; 576f8919bdaSduboff 577f8919bdaSduboff /* 578f8919bdaSduboff * Exported functions 579f8919bdaSduboff */ 580f8919bdaSduboff boolean_t gem_get_mac_addr_conf(struct gem_dev *); 581f8919bdaSduboff int gem_mii_probe_default(struct gem_dev *); 582f8919bdaSduboff int gem_mii_config_default(struct gem_dev *); 583f8919bdaSduboff boolean_t gem_mii_link_check(struct gem_dev *dp); 584f8919bdaSduboff uint16_t gem_mii_read(struct gem_dev *, uint_t); 585f8919bdaSduboff void gem_mii_write(struct gem_dev *, uint_t, uint16_t); 586f8919bdaSduboff int gem_reclaim_txbuf(struct gem_dev *dp); 587f8919bdaSduboff int gem_restart_nic(struct gem_dev *dp, uint_t flags); 588f8919bdaSduboff #define GEM_RESTART_NOWAIT 0x00000002 589f8919bdaSduboff #define GEM_RESTART_KEEP_BUF 0x00000001 590f8919bdaSduboff boolean_t gem_tx_done(struct gem_dev *); 591f8919bdaSduboff int gem_receive(struct gem_dev *); 592f8919bdaSduboff int gem_receive_copy(struct gem_dev *); 593f8919bdaSduboff struct gem_dev *gem_do_attach(dev_info_t *, int, 594f8919bdaSduboff struct gem_conf *, void *, ddi_acc_handle_t *, void *, int); 595f8919bdaSduboff 596f8919bdaSduboff mblk_t *gem_send_common(struct gem_dev *, mblk_t *, uint32_t); 597f8919bdaSduboff #define GEM_SEND_COPY 0x00008000 598f8919bdaSduboff #define GEM_SEND_CTRL 0x000000ff /* private flags for control packets */ 599f8919bdaSduboff #define GEM_SEND_VTAG 0xffff0000 600f8919bdaSduboff #define GEM_SEND_VTAG_SHIFT 16 601f8919bdaSduboff 602f8919bdaSduboff mblk_t *gem_get_packet_default(struct gem_dev *, struct rxbuf *, size_t); 603f8919bdaSduboff 604f8919bdaSduboff uint32_t gem_ether_crc_le(const uint8_t *addr, int len); 605f8919bdaSduboff uint32_t gem_ether_crc_be(const uint8_t *addr, int len); 606f8919bdaSduboff int gem_do_detach(dev_info_t *); 607f8919bdaSduboff 608f8919bdaSduboff int gem_getlongprop_buf(dev_t dev, dev_info_t *dip, 609f8919bdaSduboff int flags, char *name, void *buf, int *lenp); 610f8919bdaSduboff int gem_getprop(dev_t dev, dev_info_t *dip, 611f8919bdaSduboff int flags, char *name, int defvalue); 612f8919bdaSduboff 613f8919bdaSduboff struct rxbuf *gem_get_rxbuf(struct gem_dev *, int); 614f8919bdaSduboff 615f8919bdaSduboff void gem_rx_desc_dma_sync(struct gem_dev *, int, int, int); 616f8919bdaSduboff void gem_tx_desc_dma_sync(struct gem_dev *, int, int, int); 617f8919bdaSduboff 618f8919bdaSduboff int gem_resume(dev_info_t *); 619f8919bdaSduboff int gem_suspend(dev_info_t *); 620f8919bdaSduboff uint8_t gem_search_pci_cap(dev_info_t *dip, ddi_acc_handle_t, uint8_t); 621f8919bdaSduboff int gem_pci_set_power_state(dev_info_t *, ddi_acc_handle_t, uint_t); 622f8919bdaSduboff int gem_pci_regs_map_setup(dev_info_t *, uint32_t, uint32_t, 623f8919bdaSduboff struct ddi_device_acc_attr *, caddr_t *, ddi_acc_handle_t *); 624f8919bdaSduboff void gem_mod_init(struct dev_ops *, char *); 625f8919bdaSduboff void gem_mod_fini(struct dev_ops *); 626f8919bdaSduboff 627f8919bdaSduboff #define GEM_GET_DEV(dip) \ 628f8919bdaSduboff ((struct gem_dev *)(ddi_get_driver_private(dip))) 629f8919bdaSduboff #endif /* _SFE_UTIL_H_ */ 630