1 /* 2 * sfe_mii.h: mii header for gem 3 * 4 * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 #pragma ident "%Z%%M% %I% %E% SMI" /* sfe device driver */ 34 35 /* 36 * sfe_mii.h : MII registers 37 */ 38 #ifndef _SFE_MII_H_ 39 #define _SFE_MII_H_ 40 41 #include <sys/miiregs.h> 42 43 #define MII_AN_LPANXT 8 44 #define MII_MS_CONTROL 9 45 #define MII_MS_STATUS 10 46 #define MII_XSTATUS 15 47 48 /* for 1000BaseT support */ 49 #define MII_1000TC MII_MS_CONTROL 50 #define MII_1000TS MII_MS_STATUS 51 #define MII_CONTROL_SPEED 0x2040 52 53 #define MII_CONTROL_10MB 0x0000 54 #define MII_CONTROL_1000MB 0x0040 55 56 #define MII_CONTROL_BITS \ 57 "\020" \ 58 "\020RESET" \ 59 "\017LOOPBACK" \ 60 "\016100MB" \ 61 "\015ANE" \ 62 "\014PWRDN" \ 63 "\013ISOLATE" \ 64 "\012RSAN" \ 65 "\011FDUPLEX" \ 66 "\010COLTST" \ 67 "\0071000M" 68 #define MII_STATUS_XSTATUS 0x0100 69 #define MII_STATUS_100_BASE_T2_FD 0x0400 70 #define MII_STATUS_100_BASE_T2 0x0200 71 72 #define MII_STATUS_ABILITY_TECH \ 73 (MII_STATUS_100_BASE_T4 | \ 74 MII_STATUS_100_BASEX_FD | \ 75 MII_STATUS_100_BASEX | \ 76 MII_STATUS_10 | \ 77 MII_STATUS_10_FD) 78 79 80 #define MII_STATUS_BITS \ 81 "\020" \ 82 "\020100_BASE_T4" \ 83 "\017100_BASEX_FD" \ 84 "\016100_BASEX" \ 85 "\01510_BASE_FD" \ 86 "\01410_BASE" \ 87 "\013100_BASE_T2_FD" \ 88 "\012100_BASE_T2" \ 89 "\011XSTATUS" \ 90 "\007MFPRMBLSUPR" \ 91 "\006ANDONE" \ 92 "\005REMFAULT" \ 93 "\004CANAUTONEG" \ 94 "\003LINKUP" \ 95 "\002JABBERING" \ 96 "\001EXTENDED" 97 98 #define MII_ABILITY_ASM_DIR 0x0800 /* for annex 28B */ 99 #define MII_ABILITY_PAUSE 0x0400 /* for IEEE 802.3x */ 100 101 #define MII_AN_LPABLE_NP 0x8000 102 103 #define MII_ABILITY_TECH \ 104 (MII_ABILITY_100BASE_T4 | \ 105 MII_ABILITY_100BASE_TX_FD | \ 106 MII_ABILITY_100BASE_TX | \ 107 MII_ABILITY_10BASE_T | \ 108 MII_ABILITY_10BASE_T_FD) 109 110 #define MII_ABILITY_ALL \ 111 (MII_AN_ADVERT_REMFAULT | \ 112 MII_ABILITY_ASM_DIR | \ 113 MII_ABILITY_PAUSE | \ 114 MII_ABILITY_TECH) 115 116 117 #define MII_ABILITY_BITS \ 118 "\020" \ 119 "\016REMFAULT" \ 120 "\014ASM_DIR" \ 121 "\013PAUSE" \ 122 "\012100BASE_T4" \ 123 "\011100BASE_TX_FD" \ 124 "\010100BASE_TX" \ 125 "\00710BASE_T_FD" \ 126 "\00610BASE_T" 127 128 #define MII_AN_EXP_BITS \ 129 "\020" \ 130 "\005PARFAULT" \ 131 "\004LPCANNXTP" \ 132 "\003CANNXTPP" \ 133 "\002PAGERCVD" \ 134 "\001LPCANAN" 135 136 #define MII_1000TC_TESTMODE 0xe000 137 #define MII_1000TC_CFG_EN 0x1000 138 #define MII_1000TC_CFG_VAL 0x0800 139 #define MII_1000TC_PORTTYPE 0x0400 140 #define MII_1000TC_ADV_FULL 0x0200 141 #define MII_1000TC_ADV_HALF 0x0100 142 143 #define MII_1000TC_BITS \ 144 "\020" \ 145 "\015CFG_EN" \ 146 "\014CFG_VAL" \ 147 "\013PORTTYPE" \ 148 "\012FULL" \ 149 "\011HALF" 150 151 #define MII_1000TS_CFG_FAULT 0x8000 152 #define MII_1000TS_CFG_MASTER 0x4000 153 #define MII_1000TS_LOCALRXOK 0x2000 154 #define MII_1000TS_REMOTERXOK 0x1000 155 #define MII_1000TS_LP_FULL 0x0800 156 #define MII_1000TS_LP_HALF 0x0400 157 158 #define MII_1000TS_BITS \ 159 "\020" \ 160 "\020CFG_FAULT" \ 161 "\017CFG_MASTER" \ 162 "\014CFG_LOCALRXOK" \ 163 "\013CFG_REMOTERXOK" \ 164 "\012LP_FULL" \ 165 "\011LP_HALF" 166 167 #define MII_XSTATUS_1000BASEX_FD 0x8000 168 #define MII_XSTATUS_1000BASEX 0x4000 169 #define MII_XSTATUS_1000BASET_FD 0x2000 170 #define MII_XSTATUS_1000BASET 0x1000 171 172 #define MII_XSTATUS_BITS \ 173 "\020" \ 174 "\0201000BASEX_FD" \ 175 "\0171000BASEX" \ 176 "\0161000BASET_FD" \ 177 "\0151000BASET" 178 179 #define MII_READ_CMD(p, r) \ 180 ((6<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18)) 181 182 #define MII_WRITE_CMD(p, r, v) \ 183 ((5<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18) | (2 << 16) | (v)) 184 185 #endif /* _SFE_MII_H_ */ 186