xref: /titanic_41/usr/src/uts/common/io/rwd/rt2661_var.h (revision 4445fffbbb1ea25fd0e9ea68b9380dd7a6709025)
1 /*
2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2006
8  *	Damien Bergamini <damien.bergamini@free.fr>
9  *
10  * Permission to use, copy, modify, and distribute this software for any
11  * purpose with or without fee is hereby granted, provided that the above
12  * copyright notice and this permission notice appear in all copies.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21  */
22 
23 #ifndef	_RT2661_VAR_H
24 #define	_RT2661_VAR_H
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 struct dma_area {
31 	ddi_acc_handle_t	acc_hdl;	/* handle for memory */
32 	caddr_t			mem_va;		/* CPU VA of memory */
33 	uint32_t		nslots;		/* number of slots */
34 	uint32_t		size;		/* size per slot */
35 	size_t			alength;	/* allocated size */
36 
37 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
38 	offset_t		offset;		/* relative to handle */
39 	ddi_dma_cookie_t	cookie;		/* associated cookie */
40 	uint32_t		ncookies;	/* must be 1 */
41 	uint32_t		token;		/* arbitrary identifier */
42 };
43 
44 struct rt2661_tx_data {
45 	struct dma_area		txdata_dma;
46 	caddr_t			buf;
47 	uint32_t		paddr;
48 	struct ieee80211_node	*ni;
49 };
50 
51 struct rt2661_tx_ring {
52 	struct dma_area		txdesc_dma;
53 	uint32_t		paddr;
54 	struct rt2661_tx_desc	*desc;
55 	struct rt2661_tx_data	*data;
56 	int			count;
57 	int			queued;
58 	int			cur;
59 	int			next;
60 	int			stat;
61 };
62 
63 struct rt2661_rx_data {
64 	struct dma_area	rxdata_dma;
65 	caddr_t		buf;
66 	uint32_t	paddr;
67 };
68 
69 struct rt2661_rx_ring {
70 	struct dma_area		rxdesc_dma;
71 	uint32_t		paddr;
72 	struct rt2661_rx_desc	*desc;
73 	struct rt2661_rx_data	*data;
74 	int			count;
75 	int			cur;
76 	int			next;
77 };
78 
79 struct rt2661_amrr {
80 	uint_t	amrr_min_success_threshold;
81 	uint_t	amrr_max_success_threshold;
82 };
83 
84 struct rt2661_amrr_node {
85 	int	amn_success;
86 	int	amn_recovery;
87 	int	amn_success_threshold;
88 	int	amn_txcnt;
89 	int	amn_retrycnt;
90 };
91 
92 struct rt2661_node {
93 	struct ieee80211_node		ni;
94 	struct rt2661_amrr_node		amn;
95 };
96 
97 struct rt2661_softc {
98 	struct ieee80211com	sc_ic;
99 	dev_info_t		*sc_dev;
100 
101 	/* ddi reg handler */
102 	ddi_acc_handle_t	sc_cfg_handle;
103 	caddr_t			sc_cfg_base;
104 
105 	/* ddi i/o handler */
106 	ddi_acc_handle_t	sc_io_handle;
107 	caddr_t			sc_io_base;
108 
109 	uint16_t		sc_cachelsz;
110 	uint32_t		sc_dmabuf_size;
111 
112 	struct rt2661_amrr	amrr;
113 
114 	struct rt2661_tx_ring	txq[4];
115 	struct rt2661_tx_ring	mgtq;
116 	struct rt2661_rx_ring	rxq;
117 
118 	/* interrupt */
119 	ddi_iblock_cookie_t	sc_iblock;
120 	ddi_softint_handle_t	sc_softintr_hdl;
121 	ddi_intr_handle_t	*sc_intr_htable;
122 	uint_t			sc_intr_pri;
123 
124 	kmutex_t		sc_genlock;
125 	kmutex_t		sc_txlock;
126 	kmutex_t		sc_rxlock;
127 
128 	int			sc_tx_timer;
129 	uint32_t		sc_rx_pend;
130 	timeout_id_t		sc_scan_id;
131 	timeout_id_t		sc_rssadapt_id;
132 	timeout_id_t		sc_stat_id;
133 	enum ieee80211_state	sc_ostate;
134 
135 	struct ieee80211_channel *sc_curchan;
136 
137 	uint8_t			rf_rev;
138 	uint8_t			rfprog;
139 	uint8_t			rffreq;
140 
141 	uint32_t		rf_regs[4];
142 	int8_t			txpow[38];
143 
144 	struct {
145 		uint8_t	reg;
146 		uint8_t	val;
147 	}			bbp_prom[16];
148 
149 
150 	int			hw_radio;
151 	int			rx_ant;
152 	int			tx_ant;
153 	int			nb_ant;
154 	int			ext_2ghz_lna;
155 	int			ext_5ghz_lna;
156 	int			rssi_2ghz_corr;
157 	int			rssi_5ghz_corr;
158 
159 	int			ncalls;
160 	int			avg_rssi;
161 	int			sifs;
162 	uint8_t			bbp18;
163 	uint8_t			bbp21;
164 	uint8_t			bbp22;
165 	uint8_t			bbp16;
166 	uint8_t			bbp17;
167 	uint8_t			bbp64;
168 
169 	/* kstats */
170 	uint32_t		sc_tx_nobuf;
171 	uint32_t		sc_rx_nobuf;
172 	uint32_t		sc_tx_err;
173 	uint32_t		sc_rx_err;
174 	uint32_t		sc_tx_retries;
175 
176 	uint32_t		sc_need_sched;
177 	uint32_t		sc_flags;
178 	uint32_t		sc_rcr;
179 	int			(*sc_newstate)(struct ieee80211com *,
180 				    enum ieee80211_state, int);
181 };
182 
183 #define	RT2661_GLOCK(_sc)		mutex_enter(&(_sc)->sc_genlock)
184 #define	RT2661_GUNLOCK(_sc)		mutex_exit(&(_sc)->sc_genlock)
185 
186 #define	RT2661_INPUT_RUNNING	(1 << 0)
187 #define	RT2661_F_RUNNING	(1 << 1)
188 #define	RT2661_F_SUSPEND	(1 << 2)
189 #define	RT2661_F_FWLOADED	(1 << 3)
190 #define	RT2661_F_QUIESCE	(1 << 4)
191 
192 #define	RT2661_RCR_PROMISC	(1 << 0)
193 #define	RT2661_RCR_MULTI	(1 << 1)
194 
195 #define	RT2661_IS_RUNNING(_sc)		(((_sc)->sc_flags & RT2661_F_RUNNING))
196 #define	RT2661_IS_SUSPEND(_sc)		(((_sc)->sc_flags & RT2661_F_SUSPEND))
197 #define	RT2661_IS_FWLOADED(_sc)		(((_sc)->sc_flags & RT2661_F_FWLOADED))
198 #define	RT2661_IS_FASTREBOOT(_sc)	(((_sc)->sc_flags & RT2661_F_QUIESCE))
199 
200 #define	RT2661_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\
201 	(area).offset, (area).alength, (flag)))
202 
203 #define	RT2661_SUCCESS		0
204 #define	RT2661_FAILURE		-1
205 
206 #ifdef __cplusplus
207 }
208 #endif
209 
210 #endif /* _RT2661_VAR_H */
211