1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * Copyright (c) 2005 David Young. All rights reserved. 7 * 8 * This code was written by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 * OF SUCH DAMAGE. 34 */ 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifndef _SA2400REG_H_ 39 #define _SA2400REG_H_ 40 41 /* 42 * Serial bus format for Philips SA2400 Single-chip Transceiver. 43 */ 44 #define SA2400_TWI_DATA_MASK BITS(31, 8) 45 #define SA2400_TWI_WREN BIT(7) /* enable write */ 46 #define SA2400_TWI_ADDR_MASK BITS(6, 0) 47 48 /* 49 * Registers for Philips SA2400 Single-chip Transceiver. 50 */ 51 #define SA2400_SYNA 0 /* Synthesizer Register A */ 52 /* 53 * fractional modulus select, 54 * 0: /8 (default) 55 * 1: /5 56 */ 57 #define SA2400_SYNA_FM BIT(21) 58 /* 59 * fractional increment value, 60 * 0 to 7, default 4 61 */ 62 #define SA2400_SYNA_NF_MASK BITS(20, 18) 63 /* 64 * main divider division ratio, 65 * 512 to 65535, default 615 66 */ 67 #define SA2400_SYNA_N_MASK BITS(17, 2) 68 69 #define SA2400_SYNB 1 /* Synthesizer Register B */ 70 /* 71 * reference divider ratio, 72 * 4 to 1023, default 11 73 */ 74 75 #define SA2400_SYNB_R_MASK BITS(21, 12) 76 #define SA2400_SYNB_L_MASK BITS(11, 10) /* lock detect mode */ 77 #define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK) 78 #define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK) 79 #define SA2400_SYNB_L_NORMAL LSHIFT(2, SA2400_SYNB_L_MASK) 80 #define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK) 81 82 /* 83 * power on/off, 84 * 0: inverted chip mode control 85 * 1: as defined by chip mode (see SA2400_OPMODE) 86 */ 87 88 #define SA2400_SYNB_ON BIT(9) 89 #define SA2400_SYNB_ONE BIT(8) /* always 1 */ 90 /* 91 * fractional compensation 92 * charge pump current DAC, 93 * 0 to 255, default 80. 94 */ 95 96 #define SA2400_SYNB_FC_MASK BITS(7, 0) 97 #define SA2400_SYNC 2 /* Synthesizer Register C */ 98 #define SA2400_SYNC_CP_MASK BITS(7, 6) /* charge pump current setting */ 99 #define SA2400_SYNC_CP_NORMAL_ LSHIFT(0, SA2400_SYNC_CP_MASK) 100 #define SA2400_SYNC_CP_THIRD_ LSHIFT(1, SA2400_SYNC_CP_MASK) 101 #define SA2400_SYNC_CP_NORMAL LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */ 102 #define SA2400_SYNC_CP_THIRD LSHIFT(3, SA2400_SYNC_CP_MASK) 103 104 /* 105 * comparison divider select, 106 * 0 to 4, extra division 107 * ratio is 2**SM. 108 */ 109 #define SA2400_SYNC_SM_MASK BITS(5, 3) 110 #define SA2400_SYNC_ZERO BIT(2) /* always 0 */ 111 112 #define SA2400_SYND 3 /* Synthesizer Register D */ 113 #define SA2400_SYND_ZERO1_MASK BITS(21, 17) /* always 0 */ 114 /* 115 * T[phpsu], 1: disable 116 * PHP speedup pump, 117 * overrides SA2400_SYND_TSPU 118 */ 119 #define SA2400_SYND_TPHPSU BIT(16) 120 /* 121 * T[spu], 1: speedup on, 122 * 0: speedup off 123 */ 124 #define SA2400_SYND_TPSU BIT(15) 125 #define SA2400_SYND_ZERO2_MASK BITS(14, 3) /* always 0 */ 126 /* 127 * Operating mode, filter tuner, 128 * other controls 129 */ 130 #define SA2400_OPMODE 4 131 /* 132 * 1: in Rx mode, RSSI-ADC always on 133 * 0: RSSI-ADC only on during AGC 134 */ 135 #define SA2400_OPMODE_ADC BIT(19) 136 /* 137 * read-only filter tuner error: 138 * 1 if tuner out of range 139 */ 140 #define SA2400_OPMODE_FTERR BIT(18) 141 /* 142 * Rx & Tx filter tuning, write tuning value (test mode only) or 143 * read tuner setting (in normal mode). 144 */ 145 #define SA2400_OPMODE_FILTTUNE_MASK BITS(17, 15) 146 /* 147 * external reference voltage 148 * (pad v2p5) on 149 */ 150 #define SA2400_OPMODE_V2P5 BIT(14) 151 #define SA2400_OPMODE_I1M BIT(13) /* external reference current ... */ 152 #define SA2400_OPMODE_I0P3 BIT(12) /* external reference current ... */ 153 /* 154 * xtal input frequency, 155 * 0: 44 MHz 156 * 1: 22 MHz 157 */ 158 #define SA2400_OPMODE_IN22 BIT(10) 159 #define SA2400_OPMODE_CLK BIT(9) /* reference clock output on */ 160 #define SA2400_OPMODE_XO BIT(8) /* xtal oscillator on */ 161 #define SA2400_OPMODE_DIGIN BIT(7) /* use digital Tx inputs (FIRDAC) */ 162 /* 163 * Rx output common mode voltage, 164 * 0: V[DD]/2 165 * 1: 1.25V 166 */ 167 #define SA2400_OPMODE_RXLV BIT(6) 168 /* 169 * make internal vco 170 * available at vco pads (vcoextout) 171 */ 172 #define SA2400_OPMODE_VEO BIT(5) 173 #define SA2400_OPMODE_VEI BIT(4) /* use external vco input (vcoextin) */ 174 /* main operating mode */ 175 #define SA2400_OPMODE_MODE_MASK BITS(3, 0) 176 #define SA2400_OPMODE_MODE_SLEEP LSHIFT(0, SA2400_OPMODE_MODE_MASK) 177 #define SA2400_OPMODE_MODE_TXRX LSHIFT(1, SA2400_OPMODE_MODE_MASK) 178 #define SA2400_OPMODE_MODE_WAIT LSHIFT(2, SA2400_OPMODE_MODE_MASK) 179 #define SA2400_OPMODE_MODE_RXMGC LSHIFT(3, SA2400_OPMODE_MODE_MASK) 180 #define SA2400_OPMODE_MODE_FCALIB LSHIFT(4, SA2400_OPMODE_MODE_MASK) 181 #define SA2400_OPMODE_MODE_DCALIB LSHIFT(5, SA2400_OPMODE_MODE_MASK) 182 #define SA2400_OPMODE_MODE_FASTTXRXMGC LSHIFT(6, SA2400_OPMODE_MODE_MASK) 183 #define SA2400_OPMODE_MODE_RESET LSHIFT(7, SA2400_OPMODE_MODE_MASK) 184 #define SA2400_OPMODE_MODE_VCOCALIB LSHIFT(8, SA2400_OPMODE_MODE_MASK) 185 186 #define SA2400_OPMODE_DEFAULTS \ 187 (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \ 188 SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK)) 189 190 #define SA2400_AGC 5 /* AGC adjustment */ 191 /* 192 * fine-tune AGC target: 193 * -7dB to 7dB, sign bit ... 194 */ 195 #define SA2400_AGC_TARGETSIGN BIT(23) 196 #define SA2400_AGC_TARGET_MASK BITS(22, 20) /* ... plus 0dB - 7dB */ 197 /* 198 * maximum AGC gain, 0 to 31, (yields 54dB to 85dB) 199 */ 200 #define SA2400_AGC_MAXGAIN_MASK BITS(19, 15) 201 /* 202 * write: settling time after baseband gain switching, units of 203 * 182 nanoseconds. 204 * read: output of RSSI/Tx-peak detector's ADC in 5-bit Gray code. 205 */ 206 #define SA2400_AGC_BBPDELAY_MASK BITS(14, 10) 207 #define SA2400_AGC_ADCVAL_MASK SA2400_AGC_BBPDELAY_MASK 208 209 /* 210 * write: settling time after LNA gain switching, units of 211 * 182 nanoseconds 212 * read: 2nd sample of RSSI in AGC cycle 213 */ 214 #define SA2400_AGC_LNADELAY_MASK BITS(9, 5) 215 #define SA2400_AGC_SAMPLE2_MASK SA2400_AGC_LNADELAY_MASK 216 217 /* 218 * write: time between turning on Rx and AGCSET, units of 219 * 182 nanoseconds 220 * read: 1st sample of RSSI in AGC cycle 221 */ 222 #define SA2400_AGC_RXONDELAY_MASK BITS(4, 0) 223 #define SA2400_AGC_SAMPLE1_MASK SA2400_AGC_RXONDELAY_MASK 224 225 #define SA2400_MANRX 6 /* Manual receiver control settings */ 226 /* 227 * 1: AGC w/ high S/N---switch LNA at 228 * step 52 (recommended) 229 * 0: switch LNA at step 60 230 */ 231 #define SA2400_MANRX_AHSN BIT(23) 232 233 /* 234 * If _RXOSQON, Q offset is 235 * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts, 236 * otherwise, Q offset is 0. 237 * 238 * Ditto I offset. 239 */ 240 #define SA2400_MANRX_RXOSQON BIT(22) /* Rx Q-channel correction. */ 241 #define SA2400_MANRX_RXOSQSIGN BIT(21) 242 #define SA2400_MANRX_RXOSQ_MASK BITS(20, 18) 243 244 #define SA2400_MANRX_RXOSION BIT(17) /* Rx I-channel correction. */ 245 #define SA2400_MANRX_RXOSISIGN BIT(16) 246 #define SA2400_MANRX_RXOSI_MASK BITS(15, 13) 247 /* 248 * use 10MHz offset cancellation cornerpoint for brief period 249 * after each gain change 250 */ 251 #define SA2400_MANRX_TEN BIT(12) 252 253 /* 254 * DC offset cancellation cornerpoint select 255 * write: in RXMGC, set the cornerpoint 256 * read: in other modes, read AGC-controlled cornerpoint 257 */ 258 #define SA2400_MANRX_CORNERFREQ_MASK BITS(11, 10) 259 260 /* 261 * write: in RXMGC mode, sets receiver gain 262 * read: in other modes, read AGC-controlled gain 263 */ 264 #define SA2400_MANRX_RXGAIN_MASK BITS(9, 0) 265 266 #define SA2400_TX 7 /* Transmitter settings */ 267 /* 268 * Tx offsets 269 * write: in test mode, sets the offsets 270 * read: in normal mode, returns automatic settings 271 */ 272 #define SA2400_TX_TXOSQON BIT(19) 273 #define SA2400_TX_TXOSQSIGN BIT(18) 274 #define SA2400_TX_TXOSQ_MASK BITS(17, 15) 275 #define SA2400_TX_TXOSION BIT(14) 276 #define SA2400_TX_TXOSISIGN BIT(13) 277 #define SA2400_TX_TXOSI_MASK BITS(12, 10) 278 279 /* 280 * Ramp-up delay, 281 * 0: 1us 282 * 1: 2us 283 * 2: 3us 284 * 3: 4us 285 * datasheet says, "ramp-up 286 * time always 1us". huh? 287 */ 288 #define SA2400_TX_RAMP_MASK BITS(9, 8) 289 /* 290 * Transmitter gain settings 291 * for TXHI output 292 */ 293 #define SA2400_TX_HIGAIN_MASK BITS(7, 4) 294 /* 295 * Transmitter gain settings 296 * for TXLO output 297 */ 298 #define SA2400_TX_LOGAIN_MASK BITS(3, 0) 299 300 #define SA2400_VCO 8 /* VCO settings */ 301 #define SA2400_VCO_ZERO BITS(6, 5) /* always zero */ 302 /* 303 * VCO calibration error flag---no 304 * band with low enough frequency 305 * could be found 306 */ 307 #define SA2400_VCO_VCERR BIT(4) 308 /* 309 * VCO band, 310 * write: in test mode, sets 311 * VCO band 312 * read: in normal mode, 313 * the result of 314 * calibration (VCOCAL). 315 * 0 = highest 316 * frequencies 317 */ 318 #define SA2400_VCO_VCOBAND_MASK BITS(3, 0) 319 #endif /* _SA2400REG_H_ */ 320