1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * Copyright (c) 2004, 2005 David Young. All rights reserved. 7 * 8 * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of David Young may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 * OF SUCH DAMAGE. 34 */ 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifndef _RTWVAR_H_ 39 #define _RTWVAR_H_ 40 41 #include <sys/list.h> 42 #include <sys/net80211.h> 43 44 #ifndef __func__ 45 #define __func__ "" 46 #endif 47 48 extern void rtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...); 49 50 #define RTW_DEBUG_TUNE 0x000001 51 #define RTW_DEBUG_PKTFILT 0x000002 52 #define RTW_DEBUG_XMIT 0x000004 53 #define RTW_DEBUG_DMA 0x000008 54 #define RTW_DEBUG_NODE 0x000010 55 #define RTW_DEBUG_PWR 0x000020 56 #define RTW_DEBUG_ATTACH 0x000040 57 #define RTW_DEBUG_REGDUMP 0x000080 58 #define RTW_DEBUG_ACCESS 0x000100 59 #define RTW_DEBUG_RESET 0x000200 60 #define RTW_DEBUG_INIT 0x000400 61 #define RTW_DEBUG_PKTDUMP 0x000800 62 #define RTW_DEBUG_RECV 0x001000 63 #define RTW_DEBUG_RECV_DESC 0x002000 64 #define RTW_DEBUG_IOSTATE 0x004000 65 #define RTW_DEBUG_INTR 0x008000 66 #define RTW_DEBUG_PHY 0x010000 67 #define RTW_DEBUG_PHYIO 0x020000 68 #define RTW_DEBUG_PHYBITIO 0x040000 69 #define RTW_DEBUG_TIMEOUT 0x080000 70 #define RTW_DEBUG_BUGS 0x100000 71 #define RTW_DEBUG_BEACON 0x200000 72 #define RTW_DEBUG_WIFICFG 0x400000 73 #define RTW_DEBUG_80211 0x800000 74 #define RTW_DEBUG_MAX 0xffffff 75 76 #ifdef DEBUG 77 #define RTW_DPRINTF \ 78 rtw_dbg 79 #else /* DEBUG */ 80 #define RTW_DPRINTF 81 #endif /* DEBUG */ 82 83 enum rtw_locale { 84 RTW_LOCALE_USA = 0, 85 RTW_LOCALE_EUROPE, 86 RTW_LOCALE_JAPAN, 87 RTW_LOCALE_UNKNOWN 88 }; 89 90 enum rtw_rfchipid { 91 RTW_RFCHIPID_RESERVED = 0, 92 RTW_RFCHIPID_INTERSIL = 1, 93 RTW_RFCHIPID_RFMD = 2, 94 RTW_RFCHIPID_PHILIPS = 3, 95 RTW_RFCHIPID_MAXIM = 4, 96 RTW_RFCHIPID_GCT = 5 97 }; 98 99 /* 100 * sc_flags 101 */ 102 #define RTW_F_ENABLED 0x00000001 /* chip is enabled */ 103 #define RTW_F_DIGPHY 0x00000002 /* digital PHY */ 104 #define RTW_F_DFLANTB 0x00000004 /* B antenna is default */ 105 #define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */ 106 #define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */ 107 #define RTW_F_SLEEP 0x00000040 /* chip is asleep */ 108 #define RTW_F_INVALID 0x00000080 /* chip is absent */ 109 #define RTW_F_ATTACHED 0x01000000 /* driver is attached */ 110 /* 111 * all PHY flags 112 */ 113 #define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV) 114 115 enum rtw_access {RTW_ACCESS_NONE = 0, 116 RTW_ACCESS_CONFIG = 1, 117 RTW_ACCESS_ANAPARM = 2}; 118 119 struct rtw_regs { 120 ddi_acc_handle_t r_handle; 121 caddr_t r_base; 122 enum rtw_access r_access; 123 }; 124 125 #define RTW_SR_GET(sr, ofs) \ 126 (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff) 127 128 #define RTW_SR_GET16(sr, ofs) \ 129 (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8)) 130 131 struct rtw_srom { 132 uint16_t *sr_content; 133 uint16_t sr_size; 134 }; 135 136 137 #define RTW_NTXPRI 4 /* number of Tx priorities */ 138 #define RTW_TXPRILO 0 139 #define RTW_TXPRIMD 1 140 #define RTW_TXPRIHI 2 141 #define RTW_TXPRIBCN 3 /* beacon priority */ 142 143 #define RTW_MAXPKTSEGS 64 /* Max 64 segments per Tx packet */ 144 145 /* 146 * Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT 147 * boundaries. I allocate them consecutively from one buffer, so 148 * just round up. 149 */ 150 #define RTW_TXQLENLO 64 /* low-priority queue length */ 151 #define RTW_TXQLENMD 64 /* medium-priority */ 152 #define RTW_TXQLENHI 64 /* high-priority */ 153 #define RTW_TXQLENBCN 2 /* beacon */ 154 155 #define RTW_NTXDESCLO RTW_TXQLENLO 156 #define RTW_NTXDESCMD RTW_TXQLENMD 157 #define RTW_NTXDESCHI RTW_TXQLENHI 158 #define RTW_NTXDESCBCN RTW_TXQLENBCN 159 160 #define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \ 161 RTW_NTXDESCHI + RTW_NTXDESCBCN) 162 163 #define RTW_RXQLEN 64 164 #define RTW_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\ 165 (area).offset, (area).alength, (flag))) 166 167 #define RTW_DMA_SYNC_DESC(area, offset, len, flag) \ 168 ((void) ddi_dma_sync((area).dma_hdl, offset, len, (flag))) 169 170 #define RTW_MINC(x, y) (x) = ((x + 1) % y) 171 #define list_empty(a) ((a)->list_head.list_next == &(a)->list_head) 172 173 typedef struct dma_area { 174 ddi_acc_handle_t acc_hdl; /* handle for memory */ 175 caddr_t mem_va; /* CPU VA of memory */ 176 uint32_t nslots; /* number of slots */ 177 uint32_t size; /* size per slot */ 178 size_t alength; /* allocated size */ 179 /* >= product of above */ 180 181 ddi_dma_handle_t dma_hdl; /* DMA handle */ 182 offset_t offset; /* relative to handle */ 183 ddi_dma_cookie_t cookie; /* associated cookie */ 184 uint32_t ncookies; /* must be 1 */ 185 uint32_t token; /* arbitrary identifier */ 186 } dma_area_t; /* 0x50 (80) bytes */ 187 188 struct rtw_txbuf { 189 struct rtw_txdesc *txdesc; /* virtual addr of desc */ 190 uint32_t bf_daddr; /* physical addr of desc */ 191 uint32_t next_bf_daddr; /* physical addr of next desc */ 192 dma_area_t bf_dma; /* dma area for buf */ 193 struct ieee80211_node *bf_in; /* pointer to the node */ 194 list_node_t bf_node; 195 uint32_t order; 196 }; 197 198 struct rtw_rxbuf { 199 struct rtw_rxdesc *rxdesc; /* virtual addr of desc */ 200 uint32_t bf_daddr; /* physical addr of desc */ 201 dma_area_t bf_dma; /* dma area for buf */ 202 }; 203 204 struct rtw_txq { 205 struct rtw_txdesc *txdesc_h; 206 struct rtw_txbuf *txbuf_h; 207 uint32_t tx_prod; 208 uint32_t tx_cons; 209 uint32_t tx_nfree; 210 kmutex_t txbuf_lock; 211 list_t tx_free_list; 212 list_t tx_dirty_list; 213 }; 214 215 struct rtw_descs { 216 struct rtw_txdesc hd_txlo[RTW_NTXDESCLO]; 217 struct rtw_txdesc hd_txmd[RTW_NTXDESCMD]; 218 struct rtw_txdesc hd_txhi[RTW_NTXDESCHI]; 219 struct rtw_rxdesc hd_rx[RTW_RXQLEN]; 220 struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN]; 221 }; 222 #define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i]) 223 #define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0) 224 #define RTW_RING_BASE(baseaddr0, ring) \ 225 (baseaddr0 + RTW_RING_OFFSET(ring)) 226 227 /* 228 * One Time Unit (TU) is 1Kus = 1024 microseconds. 229 */ 230 #define IEEE80211_DUR_TU 1024 231 232 /* 233 * IEEE 802.11b durations for DSSS PHY in microseconds 234 */ 235 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144 236 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72 237 238 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48 239 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24 240 #define IEEE80211_DUR_DS_SLOW_ACK 112 241 #define IEEE80211_DUR_DS_FAST_ACK 56 242 #define IEEE80211_DUR_DS_SLOW_CTS 112 243 #define IEEE80211_DUR_DS_FAST_CTS 56 244 245 #define IEEE80211_DUR_DS_SLOT 20 246 #define IEEE80211_DUR_DS_SIFS 10 247 #define IEEE80211_DUR_DS_PIFS (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT) 248 #define IEEE80211_DUR_DS_DIFS (IEEE80211_DUR_DS_SIFS + \ 249 2 * IEEE80211_DUR_DS_SLOT) 250 #define IEEE80211_DUR_DS_EIFS (IEEE80211_DUR_DS_SIFS + \ 251 IEEE80211_DUR_DS_SLOW_ACK + \ 252 IEEE80211_DUR_DS_LONG_PREAMBLE + \ 253 IEEE80211_DUR_DS_SLOW_PLCPHDR + \ 254 IEEE80211_DUR_DIFS) 255 256 /* 257 * 802.11 frame duration definitions. 258 */ 259 struct rtw_ieee80211_duration { 260 uint16_t d_rts_dur; 261 uint16_t d_data_dur; 262 uint16_t d_plcp_len; 263 uint8_t d_residue; /* unused octets in time slot */ 264 uint8_t resv; 265 }; 266 267 268 #ifdef RTW_RADIOTAP 269 /* 270 * Radio capture format for RTL8180. 271 */ 272 273 #define RTW_RX_RADIOTAP_PRESENT \ 274 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 275 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 276 (1 << IEEE80211_RADIOTAP_RATE) | \ 277 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 278 (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ 279 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 280 0) 281 282 struct rtw_rx_radiotap_header { 283 struct ieee80211_radiotap_header rr_ihdr; 284 uint64_t rr_tsft; 285 uint8_t rr_flags; 286 uint8_t rr_rate; 287 uint16_t rr_chan_freq; 288 uint16_t rr_chan_flags; 289 uint16_t rr_barker_lock; 290 uint8_t rr_antsignal; 291 } __attribute__((__packed__)); 292 293 #define RTW_TX_RADIOTAP_PRESENT \ 294 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 295 (1 << IEEE80211_RADIOTAP_RATE) | \ 296 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 297 0) 298 299 struct rtw_tx_radiotap_header { 300 struct ieee80211_radiotap_header rt_ihdr; 301 uint8_t rt_flags; 302 uint8_t rt_rate; 303 uint16_t rt_chan_freq; 304 uint16_t rt_chan_flags; 305 } __attribute__((__packed__)); 306 #endif 307 308 enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE, 309 FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE, 310 FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM, 311 FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP, 312 FINISH_TXCTLBLK_SETUP, DETACHED}; 313 314 struct rtw_hooks { 315 void *rh_shutdown; /* shutdown hook */ 316 void *rh_power; /* power management hook */ 317 }; 318 319 enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON }; 320 321 typedef void (*rtw_continuous_tx_cb_t)(void *arg, int); 322 323 struct rtw_phy { 324 struct rtw_rf *p_rf; 325 struct rtw_regs *p_regs; 326 }; 327 328 struct rtw_bbpset { 329 uint_t bb_antatten; 330 uint_t bb_chestlim; 331 uint_t bb_chsqlim; 332 uint_t bb_ifagcdet; 333 uint_t bb_ifagcini; 334 uint_t bb_ifagclimit; 335 uint_t bb_lnadet; 336 uint_t bb_sys1; 337 uint_t bb_sys2; 338 uint_t bb_sys3; 339 uint_t bb_trl; 340 uint_t bb_txagc; 341 }; 342 343 struct rtw_rf { 344 void (*rf_destroy)(struct rtw_rf *); 345 /* 346 * args: frequency, txpower, power state 347 */ 348 int (*rf_init)(struct rtw_rf *, uint_t, uint8_t, enum rtw_pwrstate); 349 /* 350 * arg: power state 351 */ 352 int (*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate); 353 /* 354 * arg: frequency 355 */ 356 int (*rf_tune)(struct rtw_rf *, uint_t); 357 /* 358 * arg: txpower 359 */ 360 int (*rf_txpower)(struct rtw_rf *, uint8_t); 361 rtw_continuous_tx_cb_t rf_continuous_tx_cb; 362 void *rf_continuous_tx_arg; 363 struct rtw_bbpset rf_bbpset; 364 }; 365 366 typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, uint_t, 367 uint32_t); 368 369 struct rtw_rfbus { 370 struct rtw_regs *b_regs; 371 rtw_rf_write_t b_write; 372 }; 373 374 struct rtw_max2820 { 375 struct rtw_rf mx_rf; 376 struct rtw_rfbus mx_bus; 377 int mx_is_a; /* 1: MAX2820A/MAX2821A */ 378 }; 379 380 struct rtw_sa2400 { 381 struct rtw_rf sa_rf; 382 struct rtw_rfbus sa_bus; 383 int sa_digphy; /* 1: digital PHY */ 384 }; 385 386 typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int); 387 388 union rtw_keys { 389 uint8_t rk_keys[4][16]; 390 uint32_t rk_words[16]; 391 }; 392 393 #define RTW_LED_SLOW_TICKS MAX(1, hz/2) 394 #define RTW_LED_FAST_TICKS MAX(1, hz/10) 395 396 struct rtw_led_state { 397 #define RTW_LED0 0x1 398 #define RTW_LED1 0x2 399 uint8_t ls_slowblink:2; 400 uint8_t ls_actblink:2; 401 uint8_t ls_default:2; 402 uint8_t ls_state; 403 uint8_t ls_event; 404 #define RTW_LED_S_RX 0x1 405 #define RTW_LED_S_TX 0x2 406 #define RTW_LED_S_SLOW 0x4 407 }; 408 409 typedef struct rtw_softc { 410 ieee80211com_t sc_ic; /* IEEE 802.11 common */ 411 dev_info_t *sc_dev; /* back pointer to dev_info_t */ 412 kmutex_t sc_genlock; 413 struct rtw_regs sc_regs; 414 ddi_acc_handle_t sc_cfg_handle; 415 caddr_t sc_cfg_base; 416 enum ieee80211_phymode sc_curmode; 417 uint32_t sc_flags; 418 uint32_t sc_invalid; 419 ddi_iblock_cookie_t sc_iblock; 420 uint32_t sc_need_reschedule; 421 uint16_t sc_cachelsz; /* cache line size */ 422 uchar_t sc_macaddr[6]; 423 424 enum rtw_rfchipid sc_rfchipid; 425 enum rtw_locale sc_locale; 426 uint8_t sc_phydelay; 427 428 uint32_t sc_dmabuf_size; 429 dma_area_t sc_desc_dma; 430 431 struct rtw_txq sc_txq[RTW_NTXPRI]; 432 433 struct rtw_rxdesc *rxdesc_h; 434 struct rtw_rxbuf *rxbuf_h; 435 uint32_t rx_next; 436 kmutex_t rxbuf_lock; 437 kmutex_t sc_txlock; 438 439 struct rtw_srom sc_srom; 440 enum rtw_pwrstate sc_pwrstate; 441 rtw_pwrstate_t sc_pwrstate_cb; 442 struct rtw_rf *sc_rf; 443 444 uint16_t sc_inten; 445 446 void (*sc_intr_ack)(struct rtw_regs *); 447 448 int (*sc_enable)(struct rtw_softc *); 449 void (*sc_disable)(struct rtw_softc *); 450 void (*sc_power)(struct rtw_softc *, int); 451 struct rtw_hooks sc_hooks; 452 453 uint_t sc_cur_chan; 454 455 uint32_t sc_tsfth; /* most significant TSFT bits */ 456 uint32_t sc_rcr; /* RTW_RCR */ 457 uint8_t sc_csthr; /* carrier-sense threshold */ 458 459 uint8_t sc_rev; /* PCI/Cardbus revision */ 460 461 uint32_t sc_anaparm; /* register RTW_ANAPARM */ 462 #ifdef RTW_RADIOTAP 463 union { 464 struct rtw_rx_radiotap_header tap; 465 uint8_t pad[64]; 466 } sc_rxtapu; 467 union { 468 struct rtw_tx_radiotap_header tap; 469 uint8_t pad[64]; 470 } sc_txtapu; 471 #endif 472 union rtw_keys sc_keys; 473 int sc_txkey; 474 struct rtw_led_state sc_led_state; 475 int sc_hwverid; 476 477 int (*sc_newstate)(ieee80211com_t *, 478 enum ieee80211_state, int); 479 480 timeout_id_t sc_scan_id; 481 timeout_id_t sc_ratectl_id; 482 uint32_t sc_tx_ok; 483 uint32_t sc_tx_err; 484 uint32_t sc_tx_retr; 485 uint32_t sc_tx_upper; 486 uint32_t sc_xmtretry; 487 uint32_t sc_noxmtbuf; 488 uint32_t sc_norcvbuf; 489 uint32_t sc_bytexmt64; 490 uint32_t sc_bytercv64; 491 uint32_t sc_pktxmt64; 492 uint32_t sc_pktrcv64; 493 uint32_t sc_intr; 494 uint32_t sc_ioerror; 495 uint32_t hw_start; 496 uint32_t hw_go; 497 } rtw_softc_t; 498 499 #define RTW_SC(ic) ((rtw_softc_t *)ic) 500 501 #endif /* _RTWVAR_H_ */ 502