1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver. 29 * 30 * This product is covered by one or more of the following patents: 31 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 32 * US6,327,625. 33 * 34 * Currently supports: 35 * RTL8139 36 */ 37 38 39 #ifndef _SYS_RTLS_H 40 #define _SYS_RTLS_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Debug flags */ 47 #define RTLS_TRACE 0x01 48 #define RTLS_ERRS 0x02 49 #define RTLS_RECV 0x04 50 #define RTLS_DDI 0x08 51 #define RTLS_SEND 0x10 52 #define RTLS_INT 0x20 53 #define RTLS_SENSE 0x40 54 #define RTLS_REGCFG 0x80 55 56 #ifdef DEBUG 57 #define RTLS_DEBUG 1 58 #endif 59 60 /* 61 * Driver support device 62 */ 63 #define RT_VENDOR_ID 0x10EC /* RealTek */ 64 #define RT_DEVICE_8139 0x8139 65 #define RTLS_SUPPORT_DEVICE_1 ((RT_VENDOR_ID << 16) | RT_DEVICE_8139) 66 /* bind vendor and device id together */ 67 68 #define RTLS_VENDOR_ID_2 0x1186 /* D-link */ 69 #define RTLS_DEVICE_ID_2 0x1301 70 #define RTLS_SUPPORT_DEVICE_2 ((RTLS_VENDOR_ID_2 << 16) | RTLS_DEVICE_ID_2) 71 72 #define RTLS_VENDOR_ID_3 0x1113 /* Accton */ 73 #define RTLS_DEVICE_ID_3 0x1211 74 #define RTLS_SUPPORT_DEVICE_3 ((RTLS_VENDOR_ID_3 << 16) | RTLS_DEVICE_ID_3) 75 76 #define RTLS_VENDOR_ID_4 0x1186 /* D-link */ 77 #define RTLS_DEVICE_ID_4 0x1300 78 #define RTLS_SUPPORT_DEVICE_4 ((RTLS_VENDOR_ID_4 << 16) | RTLS_DEVICE_ID_4) 79 80 /* 81 * Driver tx/rx parameters 82 */ 83 #define RTLS_MAX_TX_DESC 4 84 #define RTLS_TX_BUF_COUNT 8 85 #define RTLS_TX_BUF_SIZE 2048 86 #define RTLS_RX_BUF_RING (32*1024) /* 32K */ 87 #define RTLS_RX_BUF_SIZE (RTLS_RX_BUF_RING + 2*1024) 88 #define RTLS_MCAST_BUF_SIZE 64 /* multicast hash table size in bits */ 89 90 /* 91 * RTL8139 CRC poly 92 */ 93 #define RTLS_HASH_POLY 0x04C11DB7 /* 0x04C11DB6 */ 94 #define RTLS_HASH_CRC 0xFFFFFFFFU 95 96 /* 97 * STREAMS parameters 98 */ 99 #define RTLS_HIWAT (RTLS_MAX_TX_DESC * ETHERMAX) 100 /* driver flow control high water */ 101 #define RTLS_LOWAT 1 /* driver flow control low water */ 102 #define RTLS_IDNUM 0 /* RTL Id; zero works */ 103 104 /* 105 * Helpful defines for register access 106 */ 107 #define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off)) 108 #define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off)) 109 #define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off)) 110 111 typedef struct { 112 ddi_acc_handle_t acc_hdl; /* handle for memory */ 113 void *mem_va; /* CPU VA of memory */ 114 size_t alength; /* allocated size */ 115 ddi_dma_handle_t dma_hdl; /* DMA handle */ 116 ddi_dma_cookie_t cookie; /* associated cookie */ 117 uint32_t ncookies; /* must be 1 */ 118 } dma_area_t; 119 120 typedef struct rtls_stats { 121 uint64_t ipackets; 122 uint64_t multi_rcv; /* ifInMulticastPkts */ 123 uint64_t brdcst_rcv; /* ifInBroadcastPkts */ 124 uint64_t rbytes; 125 uint64_t opackets; 126 uint64_t multi_xmt; 127 uint64_t brdcst_xmt; 128 uint64_t obytes; 129 uint32_t collisions; 130 uint32_t firstcol; 131 uint32_t multicol; 132 uint32_t rcv_err; /* ifInErrors */ 133 uint32_t xmt_err; /* ifOutErrors */ 134 uint32_t mac_rcv_err; 135 uint32_t mac_xmt_err; 136 uint32_t overflow; 137 uint32_t underflow; 138 uint32_t no_carrier; /* dot3StatsCarrierSenseErrors */ 139 uint32_t xmt_latecoll; /* dot3StatsLateCollisions */ 140 uint32_t defer; /* dot3StatsDeferredTransmissions */ 141 uint32_t frame_err; /* dot3StatsAlignErrors */ 142 uint32_t crc_err; /* dot3StatsFCSErrors */ 143 uint32_t in_short; 144 uint32_t too_long; 145 uint32_t no_rcvbuf; /* ifInDiscards */ 146 } rtls_stats_t; 147 148 typedef struct rtls_instance { 149 mac_handle_t mh; 150 mii_handle_t mii; 151 dev_info_t *devinfo; /* device instance */ 152 int32_t instance; 153 154 /* instance name: "rtls" + instance num, 32 bytes is enough */ 155 char ifname[32]; 156 157 caddr_t io_reg; /* mapped chip register address */ 158 159 160 /* io handle & iblock */ 161 ddi_acc_handle_t io_handle; /* ddi I/O handle */ 162 ddi_iblock_cookie_t iblk; 163 164 /* dma buffer alloc used */ 165 dma_area_t dma_area_rx; /* receive dma area */ 166 dma_area_t dma_area_tx[RTLS_MAX_TX_DESC]; 167 /* transmit dma area */ 168 169 uint8_t netaddr[ETHERADDRL]; /* mac address */ 170 uint16_t int_mask; /* interrupt mask */ 171 172 /* used for multicast set */ 173 char multicast_cnt[RTLS_MCAST_BUF_SIZE]; 174 uint32_t multi_hash[2]; 175 176 boolean_t promisc; /* promisc state flag */ 177 178 /* used for send */ 179 uint8_t *tx_buf[RTLS_MAX_TX_DESC]; 180 uint16_t tx_current_desc; /* Current Tx page */ 181 uint16_t tx_first_loop; 182 183 uint32_t tx_retry; 184 185 /* used for recv */ 186 uint8_t *rx_ring; 187 uint32_t cur_rx; 188 189 /* mutex */ 190 kmutex_t rtls_io_lock; /* i/o reg access */ 191 kmutex_t rtls_tx_lock; /* send access */ 192 kmutex_t rtls_rx_lock; /* receive access */ 193 194 /* send reschedule used */ 195 boolean_t need_sched; 196 197 boolean_t chip_error; /* chip error flag */ 198 199 /* current MAC state */ 200 boolean_t rtls_running; 201 boolean_t rtls_suspended; 202 203 /* rtls statistics */ 204 rtls_stats_t stats; 205 } rtls_t; 206 207 #define RTLS_TX_RETRY_NUM 16 208 #define RTLS_TX_WAIT_TIMEOUT (void) (drv_usectohz(100 * 1000)) /* 100ms */ 209 #define RTLS_RESET_WAIT_NUM 0x100 210 #define RTLS_RESET_WAIT_INTERVAL (void) (drv_usecwait(100)) 211 #define RTLS_RX_ADDR_ALIGNED(addr) (((addr + 3) & ~3) % RTLS_RX_BUF_RING) 212 /* 4-bytes aligned, also with RTLS_RX_BUF_RING boundary */ 213 214 /* parameter definition in rtls.conf file */ 215 #define FOECE_NONE 0 /* no force */ 216 #define FORCE_AUTO_NEGO 5 /* auto negotioation mode */ 217 #define FORCE_100_FDX 4 /* 100 full_duplex mode */ 218 #define FORCE_100_HDX 3 /* 100 half_duplex mode */ 219 #define FORCE_10_FDX 2 /* 10 full_duplex mode */ 220 #define FORCE_10_HDX 1 /* 10 half_duplex mode */ 221 222 /* 223 * RealTek 8129/8139 register offsets definition 224 */ 225 226 /* 227 * MAC address register, initial value isautoloaded from the 228 * EEPROM EthernetID field 229 */ 230 #define ID_0_REG 0x0000 231 #define ID_1_REG 0x0001 232 #define ID_2_REG 0x0002 233 #define ID_3_REG 0x0003 234 #define ID_4_REG 0x0004 235 #define ID_5_REG 0x0005 236 237 /* 238 * Multicast register 239 */ 240 #define MULTICAST_0_REG 0x0008 241 #define MULTICAST_1_REG 0x0009 242 #define MULTICAST_2_REG 0x000a 243 #define MULTICAST_3_REG 0x000b 244 #define MULTICAST_4_REG 0x000c 245 #define MULTICAST_5_REG 0x000d 246 #define MULTICAST_6_REG 0x000e 247 #define MULTICAST_7_REG 0x000f 248 249 #define RCV_ALL_MULTI_PACKETS 0xffffffff 250 251 /* 252 * Transmit status register 253 */ 254 #define TX_STATUS_DESC0_REG 0x0010 255 #define TX_STATUS_DESC1_REG 0x0014 256 #define TX_STATUS_DESC2_REG 0x0018 257 #define TX_STATUS_DESC3_REG 0x001c 258 #define TX_STATUS_CS_LOST 0x80000000 /* Carrier Sense Lost */ 259 #define TX_STATUS_TX_ABORT 0x40000000 /* Transmit Abort */ 260 #define TX_STATUS_OWC 0x20000000 /* Out of Window Collision */ 261 #define TX_STATUS_CDH 0x10000000 /* CD Heart Beat */ 262 #define TX_STATUS_NCC 0x0f000000 /* Number of Collision Count */ 263 #define TX_STATUS_NCC_SHIFT 24 264 #define TX_STATUS_TX_THRESHOLD 0x003f0000 /* Early Tx Threshold */ 265 #define TX_STATUS_TX_THRESHOLD_SHIFT 16 266 #define TX_STATUS_TX_THRESHOLD_MAX 0x3f /* 0x3f * 32 Bytes */ 267 #define TX_STATUS_TX_OK 0x00008000 /* Transmit OK */ 268 #define TX_STATUS_TX_UNDERRUN 0x00004000 /* Transmit FIFO Underrun */ 269 #define TX_STATUS_OWN 0x00002000 /* RTL8139 Own bit */ 270 #define TX_STATUS_PACKET_SIZE 0x00001fff 271 /* The total size in bytes of the data in this descriptor */ 272 273 /* 274 * The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared 275 * by the RTL8139 when the Transmit Byte Count (bit12-0) in the corresponding 276 * Tx descriptor is written. If h/w transmit finish, at least some of these 277 * bits are none zero. 278 */ 279 #define TX_COMPLETE_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_OK | \ 280 TX_STATUS_TX_UNDERRUN) 281 #define TX_ERR_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_UNDERRUN | \ 282 TX_STATUS_CS_LOST | TX_STATUS_OWC) 283 284 /* 285 * Transmit start address of descriptors 286 */ 287 #define TX_ADDR_DESC0_REG 0x0020 288 #define TX_ADDR_DESC1_REG 0x0024 289 #define TX_ADDR_DESC2_REG 0x0028 290 #define TX_ADDR_DESC3_REG 0x002c 291 292 /* 293 * Receive buffer start address 294 */ 295 #define RX_BUFF_ADDR_REG 0x0030 296 297 /* 298 * Early receive byte count register 299 */ 300 #define RX_STATUS_REG 0x0036 301 #define RX_STATUS_GOOD 0x08 302 #define RX_STARUS_BAD 0x04 303 #define RX_STATUS_COVERWRITE 0x02 304 #define RX_STATUS_OK 0x01 305 306 /* 307 * Commond register 308 */ 309 #define RT_COMMAND_REG 0x0037 310 #define RT_COMMAND_REG_RESERVE 0xe0 311 #define RT_COMMAND_RESET 0x10 312 #define RT_COMMAND_RX_ENABLE 0x08 313 #define RT_COMMAND_TX_ENABLE 0x04 314 #define RT_COMMAND_BUFF_EMPTY 0x01 315 316 /* 317 * Rx current read address register 318 */ 319 #define RX_CURRENT_READ_ADDR_REG 0x0038 320 #define RX_READ_RESET_VAL 0xfff0 321 /* 322 * Value in RX_CURRENT_READ_ADDR_REG is 16 less than 323 * the actual rx read address 324 */ 325 #define READ_ADDR_GAP 16 326 327 #define RX_CURRENT_BUFF_ADDR_REG 0x003a 328 329 /* 330 * Interrupt register 331 */ 332 #define RT_INT_MASK_REG 0x003c 333 #define RT_INT_STATUS_REG 0x003e 334 #define RT_INT_STATUS_INTS 0xe07f 335 #define SYS_ERR_INT 0x8000 336 #define TIME_OUT_INT 0x4000 337 #define CABLE_LEN_CHANGE_INT 0x2000 338 #define RX_FIFO_OVERFLOW_INT 0x0040 339 #define LINK_CHANGE_INT 0x0020 340 #define RX_BUF_OVERFLOW_INT 0x0010 341 #define TX_ERR_INT 0x0008 342 #define TX_OK_INT 0x0004 343 #define RX_ERR_INT 0x0002 344 #define RX_OK_INT 0x0001 345 346 #define RTLS_INT_MASK_ALL 0xe07f 347 #define RTLS_INT_MASK_NONE 0x0000 348 #define RTLS_RX_INT (RX_OK_INT | RX_ERR_INT | \ 349 RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT) 350 #define RX_OVERFLOW_INT (RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT) 351 #define RTLS_INT_MASK (LINK_CHANGE_INT | TX_ERR_INT | TX_OK_INT | \ 352 RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT | \ 353 RX_ERR_INT | RX_OK_INT) 354 355 /* 356 * Transmit configuration register 357 */ 358 #define TX_CONFIG_REG 0x0040 359 #define TX_CONSIG_REG_RESERVE 0x8078f80e 360 #define HW_VERSION_ID_5 0x7c000000 361 #define TX_INTERFRAME_GAP_BITS 0x03000000 362 #define TX_INTERFRAME_GAP_SHIFT 24 363 #define TX_INTERFRAME_GAP_802_3 0x03000000 364 #define HW_VERSION_ID_1 0x00800000 365 #define LOOPBACK_MODE_ENABLE 0x00060000 366 #define CRC_APPEND_ENABLE 0x00010000 367 #define TX_DMA_BURST_BYTES 0x00000700 368 #define TX_DMA_BURST_2048B 0x00000700 369 #define TX_DMA_BURST_1024B 0x00000600 370 #define TX_RETRY_COUNT_BITS 0x000000f0 371 #define TX_RETRY_COUNT_DEFUALT 0x00000010 372 /* re-transmit count (16 + 1 * 16) = 32 times before aborting */ 373 #define TX_CLEAR_ABORT 0x00000001 374 375 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 376 TX_DMA_BURST_1024B | \ 377 TX_RETRY_COUNT_DEFUALT) 378 #define TX_FIFO_THRESHHOLD 1024 379 /* 380 * Receive configuration register 381 */ 382 #define RX_CONFIG_REG 0x0044 383 #define RX_CONSIG_REG_RESERVE 0xf0fc0000 384 385 #define RX_THRESHOLD_BITS 0x0f000000 386 #define RX_EARLY_INT_SEL 0x00020000 387 #define RX_RER8_ENABLE 0x00010000 388 389 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 390 #define RX_FIFO_THRESHOLD_16B 0x00000000 391 #define RX_FIFO_THRESHOLD_32B 0x00002000 392 #define RX_FIFO_THRESHOLD_64B 0x00004000 393 #define RX_FIFO_THRESHOLD_128B 0x00006000 394 #define RX_FIFO_THRESHOLD_256B 0x00008000 395 #define RX_FIFO_THRESHOLD_512B 0x0000a000 396 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 397 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 398 399 #define RX_BUF_LEN_BITS 0x00001800 400 #define RX_BUF_LEN_8K 0x00000000 401 #define RX_BUF_LEN_16K 0x00000800 402 #define RX_BUF_LEN_32K 0x00001000 403 #define RX_BUF_LEN_64K 0x00001800 404 405 #define RX_DMA_BURST_BYTES 0x00000700 406 #define RX_DMA_BURST_16B 0x00000000 407 #define RX_DMA_BURST_32B 0x00000100 408 #define RX_DMA_BURST_64B 0x00000200 409 #define RX_DMA_BURST_128B 0x00000300 410 #define RX_DMA_BURST_256B 0x00000400 411 #define RX_DMA_BURST_512B 0x00000500 412 #define RX_DMA_BURST_1024B 0x00000600 413 #define RX_DMA_BURST_UNLIMITED 0x00000700 414 415 #define RX_NOWRAP_ENABLE 0x00000080 416 #define RX_EEPROM_9356 0x00000040 417 #define RX_ACCEPT_ERR_PACKET 0x00000020 418 #define RX_ACCEPT_RUNT_PACKET 0x00000010 419 #define RX_ACCEPT_BROADCAST_PACKET 0x000000008 420 #define RX_ACCEPT_MULTICAST_PACKET 0x000000004 421 #define RX_ACCEPT_MAC_MATCH_PACKET 0x000000002 422 #define RX_ACCEPT_ALL_PACKET 0x000000001 423 424 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 425 RX_BUF_LEN_32K | \ 426 RX_DMA_BURST_1024B | \ 427 RX_ACCEPT_BROADCAST_PACKET | \ 428 RX_ACCEPT_MULTICAST_PACKET | \ 429 RX_ACCEPT_MAC_MATCH_PACKET) 430 /* 431 * Missed packet counter: indicates the number of packets 432 * discarded due to rx FIFO overflow 433 */ 434 #define RX_PACKET_MISS_COUNT_REG 0x004c 435 436 /* 437 * 93c46(93c56) commond register: 438 */ 439 #define RT_93c46_COMMAND_REG 0x0050 440 #define RT_93c46_MODE_BITS 0xc0 441 #define RT_93c46_MODE_NORMAL 0x00 442 #define RT_93c46_MODE_AUTOLOAD 0x40 443 #define RT_93c46_MODE_PROGRAM 0x80 444 #define RT_93c46_MODE_CONFIG 0xc0 445 446 #define RT_93c46_EECS 0x08 447 #define RT_93c46_EESK 0x04 448 #define RT_93c46_EEDI 0x02 449 #define RT_93c46_EEDO 0x01 450 451 /* 452 * Configuration registers 453 */ 454 #define RT_CONFIG_0_REG 0x0051 455 #define RT_CONFIG_1_REG 0x0052 456 #define RT_CONFIG_3_REG 0x0059 457 #define RT_CONFIG_4_REG 0x005a 458 459 /* 460 * Media status register 461 */ 462 #define MEDIA_STATUS_REG 0x0058 463 #define MEDIA_STATUS_LINK 0x04 464 #define MEDIA_STATUS_SPEED 0x08 465 466 #define RTLS_SPEED_100M 100000000 467 #define RTLS_SPEED_10M 10000000 468 #define RTLS_SPEED_UNKNOWN 0 469 /* 470 * Multiple interrupt select register 471 */ 472 #define RT_MUL_INTSEL_REG 0x005c 473 #define RT_MUL_INTSEL_BITS 0x0fff 474 475 /* 476 * Transmit status of all descriptor registers register 477 */ 478 #define TX_DESC_STAUS_REG 0x0060 479 #define TX_DESC_STAUS_OWN_0 0x0001 480 #define TX_DESC_STAUS_ABORT_0 0x0010 481 #define TX_DESC_STAUS_UNDERRUN_0 0x0100 482 #define TX_DESC_STAUS_TXOK_0 0x1000 483 #define TX_DESC_STAUS_OWN_1 0x0002 484 #define TX_DESC_STAUS_ABORT_1 0x0020 485 #define TX_DESC_STAUS_UNDERRUN_1 0x0200 486 #define TX_DESC_STAUS_TXOK_1 0x2000 487 #define TX_DESC_STAUS_OWN_2 0x0004 488 #define TX_DESC_STAUS_ABORT_2 0x0040 489 #define TX_DESC_STAUS_UNDERRUN_2 0x0400 490 #define TX_DESC_STAUS_TXOK_2 0x4000 491 #define TX_DESC_STAUS_OWN_3 0x0008 492 #define TX_DESC_STAUS_ABORT_3 0x0080 493 #define TX_DESC_STAUS_UNDERRUN_3 0x0800 494 #define TX_DESC_STAUS_TXOK_3 0x8000 495 496 /* 497 * Basic mode control register 498 */ 499 #define BASIC_MODE_CONTROL_REG 0x0062 500 #define BASIC_MODE_CONTROL_BITS 0x3300 501 502 #define BASIC_MODE_SPEED 0x2000 503 #define BASIC_MODE_SPEED_100 0x2000 504 505 #define BASIC_MODE_AUTONEGO 0x1000 506 507 #define BASIC_MODE_RESTAR_AUTONEGO 0x0200 508 509 #define BASIC_MODE_DUPLEX 0x0100 510 #define BASIC_MODE_DUPLEX_FULL 0x0100 511 512 /* 513 * Basic mode status register 514 */ 515 #define BASIC_MODE_STATUS_REG 0x0064 516 #define BASIC_MODE_STATUS_AUTONEGO_DONE 0x0020 517 #define BASIC_MODE_STATUS_REMOTE_FAULT 0x0010 518 519 /* 520 * Auto-negotiation advertisement register 521 */ 522 #define AUTO_NEGO_AD_REG 0x0066 523 #define AUTO_NEGO_MODE_BITS 0x01e0 524 #define AUTO_NEGO_100FULL 0x0100 525 #define AUTO_NEGO_100HALF 0x0080 526 #define AUTO_NEGO_10FULL 0x0040 527 #define AUTO_NEGO_10HALF 0x0020 528 529 /* 530 * Auto-negotiation link partner ability register 531 */ 532 #define AUTO_NEGO_LP_REG 0x0068 533 534 /* 535 * Auto-negotiation expansion register 536 */ 537 #define AUTO_NEGO_EXP_REG 0x006a 538 #define AUTO_NEGO_EXP_LPCANAN 0x0001 539 540 /* 541 * Receive status in rx packet header 542 */ 543 #define RX_HEADER_SIZE 4 544 545 #define RX_HEADER_LEN_BITS 0xffff0000 546 #define RX_HEADER_STATUS_BITS 0x0000ffff 547 #define RX_STATUS_DMA_BUSY 0xfff0 548 #define RX_HEADER_STATUS_MULTI 0x8000 549 #define RX_HEADER_STATUS_PAM 0x4000 550 #define RX_HEADER_STATUS_BCAST 0x2000 551 552 #define RX_HEADER_STATUS_ISE 0x0020 553 #define RX_HEADER_STATUS_RUNT 0x0010 554 #define RX_HEADER_STATUS_LONG 0x0008 555 #define RX_HEADER_STATUS_CRC 0x0004 556 #define RX_HEADER_STATUS_FAE 0x0002 557 #define RX_HEADER_STATUS_ROK 0x0001 558 559 #define RX_ERR_FLAGS (RX_HEADER_STATUS_ISE | RX_HEADER_STATUS_RUNT | \ 560 RX_HEADER_STATUS_FAE | RX_HEADER_STATUS_CRC) 561 562 #ifdef __cplusplus 563 } 564 #endif 565 566 #endif /* _SYS_RTLS_H */ 567