1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver. 29 * 30 * This product is covered by one or more of the following patents: 31 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 32 * US6,327,625. 33 * 34 * Currently supports: 35 * RTL8139 36 */ 37 38 39 #ifndef _SYS_RTLS_H 40 #define _SYS_RTLS_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Debug flags */ 47 #define RTLS_TRACE 0x01 48 #define RTLS_ERRS 0x02 49 #define RTLS_RECV 0x04 50 #define RTLS_DDI 0x08 51 #define RTLS_SEND 0x10 52 #define RTLS_INT 0x20 53 #define RTLS_SENSE 0x40 54 #define RTLS_REGCFG 0x80 55 56 #ifdef DEBUG 57 #define RTLS_DEBUG 1 58 #endif 59 60 /* 61 * Driver support device 62 */ 63 #define RT_VENDOR_ID 0x10EC /* RealTek */ 64 #define RT_DEVICE_8139 0x8139 65 #define RTLS_SUPPORT_DEVICE_1 ((RT_VENDOR_ID << 16) | RT_DEVICE_8139) 66 /* bind vendor and device id together */ 67 68 #define RTLS_VENDOR_ID_2 0x1186 /* D-link */ 69 #define RTLS_DEVICE_ID_2 0x1301 70 #define RTLS_SUPPORT_DEVICE_2 ((RTLS_VENDOR_ID_2 << 16) | RTLS_DEVICE_ID_2) 71 72 #define RTLS_VENDOR_ID_3 0x1113 /* Accton */ 73 #define RTLS_DEVICE_ID_3 0x1211 74 #define RTLS_SUPPORT_DEVICE_3 ((RTLS_VENDOR_ID_3 << 16) | RTLS_DEVICE_ID_3) 75 76 /* 77 * Driver tx/rx parameters 78 */ 79 #define RTLS_MAX_TX_DESC 4 80 #define RTLS_TX_BUF_COUNT 8 81 #define RTLS_TX_BUF_SIZE 2048 82 #define RTLS_RX_BUF_RING (32*1024) /* 32K */ 83 #define RTLS_RX_BUF_SIZE (RTLS_RX_BUF_RING + 2*1024) 84 #define RTLS_MCAST_BUF_SIZE 64 /* multicast hash table size in bits */ 85 86 /* 87 * RTL8139 CRC poly 88 */ 89 #define RTLS_HASH_POLY 0x04C11DB7 /* 0x04C11DB6 */ 90 #define RTLS_HASH_CRC 0xFFFFFFFFU 91 92 /* 93 * STREAMS parameters 94 */ 95 #define RTLS_HIWAT (RTLS_MAX_TX_DESC * ETHERMAX) 96 /* driver flow control high water */ 97 #define RTLS_LOWAT 1 /* driver flow control low water */ 98 #define RTLS_IDNUM 0 /* RTL Id; zero works */ 99 100 /* 101 * Helpful defines for register access 102 */ 103 #define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off)) 104 #define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off)) 105 #define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off)) 106 107 typedef struct { 108 ddi_acc_handle_t acc_hdl; /* handle for memory */ 109 void *mem_va; /* CPU VA of memory */ 110 size_t alength; /* allocated size */ 111 ddi_dma_handle_t dma_hdl; /* DMA handle */ 112 ddi_dma_cookie_t cookie; /* associated cookie */ 113 uint32_t ncookies; /* must be 1 */ 114 } dma_area_t; 115 116 typedef struct rtls_stats { 117 uint64_t ipackets; 118 uint64_t multi_rcv; /* ifInMulticastPkts */ 119 uint64_t brdcst_rcv; /* ifInBroadcastPkts */ 120 uint64_t rbytes; 121 uint64_t opackets; 122 uint64_t multi_xmt; 123 uint64_t brdcst_xmt; 124 uint64_t obytes; 125 uint32_t collisions; 126 uint32_t firstcol; 127 uint32_t multicol; 128 uint32_t rcv_err; /* ifInErrors */ 129 uint32_t xmt_err; /* ifOutErrors */ 130 uint32_t mac_rcv_err; 131 uint32_t mac_xmt_err; 132 uint32_t overflow; 133 uint32_t underflow; 134 uint32_t no_carrier; /* dot3StatsCarrierSenseErrors */ 135 uint32_t xmt_latecoll; /* dot3StatsLateCollisions */ 136 uint32_t defer; /* dot3StatsDeferredTransmissions */ 137 uint32_t frame_err; /* dot3StatsAlignErrors */ 138 uint32_t crc_err; /* dot3StatsFCSErrors */ 139 uint32_t in_short; 140 uint32_t too_long; 141 uint32_t no_rcvbuf; /* ifInDiscards */ 142 uint32_t speed; /* ifSpeed */ 143 uint32_t duplex; /* Invented for GLD */ 144 } rtls_stats_t; 145 146 typedef struct rtls_instance { 147 mac_handle_t mh; 148 dev_info_t *devinfo; /* device instance */ 149 int32_t instance; 150 151 /* instance name: "rtls" + instance num, 32 bytes is enough */ 152 char ifname[32]; 153 154 caddr_t io_reg; /* mapped chip register address */ 155 156 157 /* io handle & iblock */ 158 ddi_acc_handle_t io_handle; /* ddi I/O handle */ 159 ddi_iblock_cookie_t iblk; 160 161 /* dma buffer alloc used */ 162 dma_area_t dma_area_rx; /* receive dma area */ 163 dma_area_t dma_area_tx[RTLS_MAX_TX_DESC]; 164 /* transmit dma area */ 165 166 uint8_t netaddr[ETHERADDRL]; /* mac address */ 167 uint16_t int_mask; /* interrupt mask */ 168 169 /* used for multicast set */ 170 char multicast_cnt[RTLS_MCAST_BUF_SIZE]; 171 uint32_t multi_hash[2]; 172 173 boolean_t promisc; /* promisc state flag */ 174 175 /* used for send */ 176 uint8_t *tx_buf[RTLS_MAX_TX_DESC]; 177 uint16_t tx_current_desc; /* Current Tx page */ 178 uint16_t tx_first_loop; 179 180 uint32_t tx_retry; 181 182 /* used for recv */ 183 uint8_t *rx_ring; 184 uint32_t cur_rx; 185 186 /* mutex */ 187 kmutex_t rtls_io_lock; /* i/o reg access */ 188 kmutex_t rtls_tx_lock; /* send access */ 189 kmutex_t rtls_rx_lock; /* receive access */ 190 191 /* send reschedule used */ 192 boolean_t need_sched; 193 boolean_t sched_running; 194 ddi_softintr_t resched_id; /* reschedule callback */ 195 196 /* events:link change used */ 197 boolean_t link_change; 198 int32_t link_state; 199 ddi_softintr_t events_id; /* events callback */ 200 ddi_periodic_t periodic_id; 201 202 boolean_t chip_error; /* chip error flag */ 203 204 /* current MAC state */ 205 boolean_t rtls_running; 206 boolean_t rtls_suspended; 207 208 /* value of rtls.conf file, default 5:FORCE_AUTO_NEGO */ 209 uint_t force_speed_duplex; 210 211 /* rtls statistics */ 212 rtls_stats_t stats; 213 } rtls_t; 214 215 #define RTLS_TX_RETRY_NUM 16 216 #define RTLS_TX_WAIT_TIMEOUT (void) (drv_usectohz(100 * 1000)) /* 100ms */ 217 #define RTLS_RESET_WAIT_NUM 0x100 218 #define RTLS_RESET_WAIT_INTERVAL (void) (drv_usecwait(100)) 219 #define RTLS_RX_ADDR_ALIGNED(addr) (((addr + 3) & ~3) % RTLS_RX_BUF_RING) 220 /* 4-bytes aligned, also with RTLS_RX_BUF_RING boundary */ 221 222 /* parameter definition in rtls.conf file */ 223 #define FOECE_NONE 0 /* no force */ 224 #define FORCE_AUTO_NEGO 5 /* auto negotioation mode */ 225 #define FORCE_100_FDX 4 /* 100 full_duplex mode */ 226 #define FORCE_100_HDX 3 /* 100 half_duplex mode */ 227 #define FORCE_10_FDX 2 /* 10 full_duplex mode */ 228 #define FORCE_10_HDX 1 /* 10 half_duplex mode */ 229 230 /* 231 * RealTek 8129/8139 register offsets definition 232 */ 233 234 /* 235 * MAC address register, initial value isautoloaded from the 236 * EEPROM EthernetID field 237 */ 238 #define ID_0_REG 0x0000 239 #define ID_1_REG 0x0001 240 #define ID_2_REG 0x0002 241 #define ID_3_REG 0x0003 242 #define ID_4_REG 0x0004 243 #define ID_5_REG 0x0005 244 245 /* 246 * Multicast register 247 */ 248 #define MULTICAST_0_REG 0x0008 249 #define MULTICAST_1_REG 0x0009 250 #define MULTICAST_2_REG 0x000a 251 #define MULTICAST_3_REG 0x000b 252 #define MULTICAST_4_REG 0x000c 253 #define MULTICAST_5_REG 0x000d 254 #define MULTICAST_6_REG 0x000e 255 #define MULTICAST_7_REG 0x000f 256 257 #define RCV_ALL_MULTI_PACKETS 0xffffffff 258 259 /* 260 * Transmit status register 261 */ 262 #define TX_STATUS_DESC0_REG 0x0010 263 #define TX_STATUS_DESC1_REG 0x0014 264 #define TX_STATUS_DESC2_REG 0x0018 265 #define TX_STATUS_DESC3_REG 0x001c 266 #define TX_STATUS_CS_LOST 0x80000000 /* Carrier Sense Lost */ 267 #define TX_STATUS_TX_ABORT 0x40000000 /* Transmit Abort */ 268 #define TX_STATUS_OWC 0x20000000 /* Out of Window Collision */ 269 #define TX_STATUS_CDH 0x10000000 /* CD Heart Beat */ 270 #define TX_STATUS_NCC 0x0f000000 /* Number of Collision Count */ 271 #define TX_STATUS_NCC_SHIFT 24 272 #define TX_STATUS_TX_THRESHOLD 0x003f0000 /* Early Tx Threshold */ 273 #define TX_STATUS_TX_THRESHOLD_SHIFT 16 274 #define TX_STATUS_TX_THRESHOLD_MAX 0x3f /* 0x3f * 32 Bytes */ 275 #define TX_STATUS_TX_OK 0x00008000 /* Transmit OK */ 276 #define TX_STATUS_TX_UNDERRUN 0x00004000 /* Transmit FIFO Underrun */ 277 #define TX_STATUS_OWN 0x00002000 /* RTL8139 Own bit */ 278 #define TX_STATUS_PACKET_SIZE 0x00001fff 279 /* The total size in bytes of the data in this descriptor */ 280 281 /* 282 * The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared 283 * by the RTL8139 when the Transmit Byte Count (bit12-0) in the corresponding 284 * Tx descriptor is written. If h/w transmit finish, at least some of these 285 * bits are none zero. 286 */ 287 #define TX_COMPLETE_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_OK | \ 288 TX_STATUS_TX_UNDERRUN) 289 #define TX_ERR_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_UNDERRUN | \ 290 TX_STATUS_CS_LOST | TX_STATUS_OWC) 291 292 /* 293 * Transmit start address of descriptors 294 */ 295 #define TX_ADDR_DESC0_REG 0x0020 296 #define TX_ADDR_DESC1_REG 0x0024 297 #define TX_ADDR_DESC2_REG 0x0028 298 #define TX_ADDR_DESC3_REG 0x002c 299 300 /* 301 * Receive buffer start address 302 */ 303 #define RX_BUFF_ADDR_REG 0x0030 304 305 /* 306 * Early receive byte count register 307 */ 308 #define RX_STATUS_REG 0x0036 309 #define RX_STATUS_GOOD 0x08 310 #define RX_STARUS_BAD 0x04 311 #define RX_STATUS_COVERWRITE 0x02 312 #define RX_STATUS_OK 0x01 313 314 /* 315 * Commond register 316 */ 317 #define RT_COMMAND_REG 0x0037 318 #define RT_COMMAND_REG_RESERVE 0xe0 319 #define RT_COMMAND_RESET 0x10 320 #define RT_COMMAND_RX_ENABLE 0x08 321 #define RT_COMMAND_TX_ENABLE 0x04 322 #define RT_COMMAND_BUFF_EMPTY 0x01 323 324 /* 325 * Rx current read address register 326 */ 327 #define RX_CURRENT_READ_ADDR_REG 0x0038 328 #define RX_READ_RESET_VAL 0xfff0 329 /* 330 * Value in RX_CURRENT_READ_ADDR_REG is 16 less than 331 * the actual rx read address 332 */ 333 #define READ_ADDR_GAP 16 334 335 #define RX_CURRENT_BUFF_ADDR_REG 0x003a 336 337 /* 338 * Interrupt register 339 */ 340 #define RT_INT_MASK_REG 0x003c 341 #define RT_INT_STATUS_REG 0x003e 342 #define RT_INT_STATUS_INTS 0xe07f 343 #define SYS_ERR_INT 0x8000 344 #define TIME_OUT_INT 0x4000 345 #define CABLE_LEN_CHANGE_INT 0x2000 346 #define RX_FIFO_OVERFLOW_INT 0x0040 347 #define LINK_CHANGE_INT 0x0020 348 #define RX_BUF_OVERFLOW_INT 0x0010 349 #define TX_ERR_INT 0x0008 350 #define TX_OK_INT 0x0004 351 #define RX_ERR_INT 0x0002 352 #define RX_OK_INT 0x0001 353 354 #define RTLS_INT_MASK_ALL 0xe07f 355 #define RTLS_INT_MASK_NONE 0x0000 356 #define RTLS_RX_INT (RX_OK_INT | RX_ERR_INT | \ 357 RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT) 358 #define RX_OVERFLOW_INT (RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT) 359 #define RTLS_INT_MASK (LINK_CHANGE_INT | TX_ERR_INT | TX_OK_INT | \ 360 RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT | \ 361 RX_ERR_INT | RX_OK_INT) 362 363 /* 364 * Transmit configuration register 365 */ 366 #define TX_CONFIG_REG 0x0040 367 #define TX_CONSIG_REG_RESERVE 0x8078f80e 368 #define HW_VERSION_ID_5 0x7c000000 369 #define TX_INTERFRAME_GAP_BITS 0x03000000 370 #define TX_INTERFRAME_GAP_SHIFT 24 371 #define TX_INTERFRAME_GAP_802_3 0x03000000 372 #define HW_VERSION_ID_1 0x00800000 373 #define LOOPBACK_MODE_ENABLE 0x00060000 374 #define CRC_APPEND_ENABLE 0x00010000 375 #define TX_DMA_BURST_BYTES 0x00000700 376 #define TX_DMA_BURST_2048B 0x00000700 377 #define TX_DMA_BURST_1024B 0x00000600 378 #define TX_RETRY_COUNT_BITS 0x000000f0 379 #define TX_RETRY_COUNT_DEFUALT 0x00000010 380 /* re-transmit count (16 + 1 * 16) = 32 times before aborting */ 381 #define TX_CLEAR_ABORT 0x00000001 382 383 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 384 TX_DMA_BURST_1024B | \ 385 TX_RETRY_COUNT_DEFUALT) 386 #define TX_FIFO_THRESHHOLD 1024 387 /* 388 * Receive configuration register 389 */ 390 #define RX_CONFIG_REG 0x0044 391 #define RX_CONSIG_REG_RESERVE 0xf0fc0000 392 393 #define RX_THRESHOLD_BITS 0x0f000000 394 #define RX_EARLY_INT_SEL 0x00020000 395 #define RX_RER8_ENABLE 0x00010000 396 397 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 398 #define RX_FIFO_THRESHOLD_16B 0x00000000 399 #define RX_FIFO_THRESHOLD_32B 0x00002000 400 #define RX_FIFO_THRESHOLD_64B 0x00004000 401 #define RX_FIFO_THRESHOLD_128B 0x00006000 402 #define RX_FIFO_THRESHOLD_256B 0x00008000 403 #define RX_FIFO_THRESHOLD_512B 0x0000a000 404 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 405 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 406 407 #define RX_BUF_LEN_BITS 0x00001800 408 #define RX_BUF_LEN_8K 0x00000000 409 #define RX_BUF_LEN_16K 0x00000800 410 #define RX_BUF_LEN_32K 0x00001000 411 #define RX_BUF_LEN_64K 0x00001800 412 413 #define RX_DMA_BURST_BYTES 0x00000700 414 #define RX_DMA_BURST_16B 0x00000000 415 #define RX_DMA_BURST_32B 0x00000100 416 #define RX_DMA_BURST_64B 0x00000200 417 #define RX_DMA_BURST_128B 0x00000300 418 #define RX_DMA_BURST_256B 0x00000400 419 #define RX_DMA_BURST_512B 0x00000500 420 #define RX_DMA_BURST_1024B 0x00000600 421 #define RX_DMA_BURST_UNLIMITED 0x00000700 422 423 #define RX_NOWRAP_ENABLE 0x00000080 424 #define RX_EEPROM_9356 0x00000040 425 #define RX_ACCEPT_ERR_PACKET 0x00000020 426 #define RX_ACCEPT_RUNT_PACKET 0x00000010 427 #define RX_ACCEPT_BROADCAST_PACKET 0x000000008 428 #define RX_ACCEPT_MULTICAST_PACKET 0x000000004 429 #define RX_ACCEPT_MAC_MATCH_PACKET 0x000000002 430 #define RX_ACCEPT_ALL_PACKET 0x000000001 431 432 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 433 RX_BUF_LEN_32K | \ 434 RX_DMA_BURST_1024B | \ 435 RX_ACCEPT_BROADCAST_PACKET | \ 436 RX_ACCEPT_MULTICAST_PACKET | \ 437 RX_ACCEPT_MAC_MATCH_PACKET) 438 /* 439 * Missed packet counter: indicates the number of packets 440 * discarded due to rx FIFO overflow 441 */ 442 #define RX_PACKET_MISS_COUNT_REG 0x004c 443 444 /* 445 * 93c46(93c56) commond register: 446 */ 447 #define RT_93c46_COMMOND_REG 0x0050 448 #define RT_93c46_MODE_BITS 0xc0 449 #define RT_93c46_MODE_NORMAL 0x00 450 #define RT_93c46_MODE_AUTOLOAD 0x40 451 #define RT_93c46_MODE_PROGRAM 0x80 452 #define RT_93c46_MODE_CONFIG 0xc0 453 454 #define RT_93c46_EECS 0x08 455 #define RT_93c46_EESK 0x04 456 #define RT_93c46_EEDI 0x02 457 #define RT_93c46_EEDO 0x01 458 459 /* 460 * Configuration registers 461 */ 462 #define RT_CONFIG_0_REG 0x0051 463 #define RT_CONFIG_1_REG 0x0052 464 #define RT_CONFIG_3_REG 0x0059 465 #define RT_CONFIG_4_REG 0x005a 466 467 /* 468 * Media status register 469 */ 470 #define MEDIA_STATUS_REG 0x0058 471 #define MEDIA_STATUS_LINK 0x04 472 #define MEDIA_STATUS_SPEED 0x08 473 474 #define RTLS_SPEED_100M 100000000 475 #define RTLS_SPEED_10M 10000000 476 #define RTLS_SPEED_UNKNOWN 0 477 /* 478 * Multiple interrupt select register 479 */ 480 #define RT_MUL_INTSEL_REG 0x005c 481 #define RT_MUL_INTSEL_BITS 0x0fff 482 483 /* 484 * Transmit status of all descriptor registers register 485 */ 486 #define TX_DESC_STAUS_REG 0x0060 487 #define TX_DESC_STAUS_OWN_0 0x0001 488 #define TX_DESC_STAUS_ABORT_0 0x0010 489 #define TX_DESC_STAUS_UNDERRUN_0 0x0100 490 #define TX_DESC_STAUS_TXOK_0 0x1000 491 #define TX_DESC_STAUS_OWN_1 0x0002 492 #define TX_DESC_STAUS_ABORT_1 0x0020 493 #define TX_DESC_STAUS_UNDERRUN_1 0x0200 494 #define TX_DESC_STAUS_TXOK_1 0x2000 495 #define TX_DESC_STAUS_OWN_2 0x0004 496 #define TX_DESC_STAUS_ABORT_2 0x0040 497 #define TX_DESC_STAUS_UNDERRUN_2 0x0400 498 #define TX_DESC_STAUS_TXOK_2 0x4000 499 #define TX_DESC_STAUS_OWN_3 0x0008 500 #define TX_DESC_STAUS_ABORT_3 0x0080 501 #define TX_DESC_STAUS_UNDERRUN_3 0x0800 502 #define TX_DESC_STAUS_TXOK_3 0x8000 503 504 /* 505 * Basic mode control register 506 */ 507 #define BASIC_MODE_CONTROL_REG 0x0062 508 #define BASIC_MODE_CONTROL_BITS 0x3300 509 510 #define BASIC_MODE_SPEED 0x2000 511 #define BASIC_MODE_SPEED_100 0x2000 512 513 #define BASIC_MODE_AUTONEGO 0x1000 514 515 #define BASIC_MODE_RESTAR_AUTONEGO 0x0200 516 517 #define BASIC_MODE_DUPLEX 0x0100 518 #define BASIC_MODE_DUPLEX_FULL 0x0100 519 520 /* 521 * Basic mode status register 522 */ 523 #define BASIC_MODE_STATUS_REG 0x0064 524 #define BASIC_MODE_STATUS_AUTONEGO_DONE 0x0020 525 #define BASIC_MODE_STATUS_REMOTE_FAULT 0x0010 526 527 /* 528 * Auto-negotiation advertisement register 529 */ 530 #define AUTO_NEGO_AD_REG 0x0066 531 #define AUTO_NEGO_MODE_BITS 0x01e0 532 #define AUTO_NEGO_100FULL 0x0100 533 #define AUTO_NEGO_100HALF 0x0080 534 #define AUTO_NEGO_10FULL 0x0040 535 #define AUTO_NEGO_10HALF 0x0020 536 537 /* 538 * Auto-negotiation link partner ability register 539 */ 540 #define AUTO_NEGO_LP_REG 0x0068 541 542 /* 543 * Auto-negotiation expansion register 544 */ 545 #define AUTO_NEGO_EXP_REG 0x006a 546 #define AUTO_NEGO_EXP_LPCANAN 0x0001 547 548 /* 549 * Receive status in rx packet header 550 */ 551 #define RX_HEADER_SIZE 4 552 553 #define RX_HEADER_LEN_BITS 0xffff0000 554 #define RX_HEADER_STATUS_BITS 0x0000ffff 555 #define RX_STATUS_DMA_BUSY 0xfff0 556 #define RX_HEADER_STATUS_MULTI 0x8000 557 #define RX_HEADER_STATUS_PAM 0x4000 558 #define RX_HEADER_STATUS_BCAST 0x2000 559 560 #define RX_HEADER_STATUS_ISE 0x0020 561 #define RX_HEADER_STATUS_RUNT 0x0010 562 #define RX_HEADER_STATUS_LONG 0x0008 563 #define RX_HEADER_STATUS_CRC 0x0004 564 #define RX_HEADER_STATUS_FAE 0x0002 565 #define RX_HEADER_STATUS_ROK 0x0001 566 567 #define RX_ERR_FLAGS (RX_HEADER_STATUS_ISE | RX_HEADER_STATUS_RUNT | \ 568 RX_HEADER_STATUS_FAE | RX_HEADER_STATUS_CRC) 569 570 #ifdef __cplusplus 571 } 572 #endif 573 574 #endif /* _SYS_RTLS_H */ 575