1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the 29 * Generic LAN Driver utility functions in /kernel/misc/mac 30 * 31 * This product is covered by one or more of the following patents: 32 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 33 * US6,327,625. 34 * 35 * Currently supports: 36 * RTL8139 37 */ 38 39 #include <sys/types.h> 40 #include <sys/debug.h> 41 #include <sys/errno.h> 42 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/kmem.h> 46 #include <sys/conf.h> 47 #include <sys/ddi.h> 48 #include <sys/devops.h> 49 #include <sys/ksynch.h> 50 #include <sys/stat.h> 51 #include <sys/conf.h> 52 #include <sys/modctl.h> 53 #include <sys/dlpi.h> 54 #include <sys/ethernet.h> 55 #include <sys/vlan.h> 56 #include <sys/strsun.h> 57 #include <sys/pci.h> 58 #include <sys/sunddi.h> 59 #include <sys/mii.h> 60 #include <sys/miiregs.h> 61 #include <sys/mac_provider.h> 62 #include <sys/mac_ether.h> 63 64 #include "rtls.h" 65 66 /* 67 * Declarations and Module Linkage 68 */ 69 70 /* 71 * This is the string displayed by modinfo, etc. 72 */ 73 static char rtls_ident[] = "RealTek 8139 Ethernet driver"; 74 75 #ifdef RTLS_DEBUG 76 int rtls_debug = 0; 77 #endif 78 79 /* 80 * Required system entry points 81 */ 82 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t); 83 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t); 84 static int rtls_quiesce(dev_info_t *); 85 86 /* 87 * Required driver entry points for MAC 88 */ 89 static int rtls_m_start(void *); 90 static void rtls_m_stop(void *); 91 static int rtls_m_unicst(void *, const uint8_t *); 92 static int rtls_m_multicst(void *, boolean_t, const uint8_t *); 93 static int rtls_m_promisc(void *, boolean_t); 94 static mblk_t *rtls_m_tx(void *, mblk_t *); 95 static int rtls_m_stat(void *, uint_t, uint64_t *); 96 97 static uint_t rtls_intr(caddr_t); 98 99 /* 100 * MII entry points 101 */ 102 static uint16_t rtls_mii_read(void *, uint8_t, uint8_t); 103 static void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t); 104 static void rtls_mii_notify(void *, link_state_t); 105 106 /* 107 * Internal functions used by the above entry points 108 */ 109 static int rtls_chip_reset(rtls_t *, boolean_t); 110 static void rtls_chip_init(rtls_t *); 111 static void rtls_chip_stop(rtls_t *rtlsp); 112 static void rtls_chip_start(rtls_t *rtlsp); 113 static void rtls_chip_restart(rtls_t *rtlsp); 114 static void rtls_get_mac_addr(rtls_t *, uint8_t *); 115 static void rtls_set_mac_addr(rtls_t *, const uint8_t *); 116 static uint_t rtls_hash_index(const uint8_t *); 117 static boolean_t rtls_send(rtls_t *, mblk_t *); 118 static void rtls_receive(rtls_t *); 119 120 /* 121 * Buffer Management Routines 122 */ 123 static int rtls_alloc_bufs(rtls_t *); 124 static void rtls_free_bufs(rtls_t *); 125 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *, 126 uint_t, dma_area_t *); 127 static void rtls_free_dma_mem(dma_area_t *); 128 129 #ifdef RTLS_DEBUG 130 static void rtls_reg_print(rtls_t *); /* debug routine */ 131 #endif 132 133 #define RTLS_DRIVER_NAME "rtls" 134 135 /* 136 * Used for buffers allocated by ddi_dma_mem_alloc() 137 */ 138 static ddi_dma_attr_t dma_attr = { 139 DMA_ATTR_V0, /* dma_attr version */ 140 0, /* dma_attr_addr_lo */ 141 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 142 0x7FFFFFFF, /* dma_attr_count_max */ 143 4, /* dma_attr_align */ 144 0x3F, /* dma_attr_burstsizes */ 145 1, /* dma_attr_minxfer */ 146 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 147 (uint_t)0xFFFFFFFF, /* dma_attr_seg */ 148 1, /* dma_attr_sgllen */ 149 1, /* dma_attr_granular */ 150 0, /* dma_attr_flags */ 151 }; 152 153 /* 154 * PIO access attributes for registers 155 */ 156 static ddi_device_acc_attr_t rtls_reg_accattr = { 157 DDI_DEVICE_ATTR_V0, 158 DDI_STRUCTURE_LE_ACC, 159 DDI_STRICTORDER_ACC 160 }; 161 162 /* 163 * DMA access attributes for data 164 */ 165 static ddi_device_acc_attr_t rtls_buf_accattr = { 166 DDI_DEVICE_ATTR_V0, 167 DDI_NEVERSWAP_ACC, 168 DDI_STRICTORDER_ACC 169 }; 170 171 uchar_t rtls_broadcastaddr[] = { 172 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 173 }; 174 175 static mac_callbacks_t rtls_m_callbacks = { 176 MC_SETPROP | MC_GETPROP, 177 rtls_m_stat, 178 rtls_m_start, 179 rtls_m_stop, 180 rtls_m_promisc, 181 rtls_m_multicst, 182 rtls_m_unicst, 183 rtls_m_tx 184 }; 185 186 static mii_ops_t rtls_mii_ops = { 187 MII_OPS_VERSION, 188 rtls_mii_read, 189 rtls_mii_write, 190 rtls_mii_notify, /* notify */ 191 NULL, /* reset */ 192 }; 193 194 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach, 195 nodev, NULL, D_MP, NULL, rtls_quiesce); 196 197 /* 198 * Standard module linkage initialization for a MAC driver 199 */ 200 static struct modldrv rtls_modldrv = { 201 &mod_driverops, /* type of module. This one is a driver */ 202 rtls_ident, /* short description */ 203 &rtls_dev_ops /* driver specific ops */ 204 }; 205 206 static struct modlinkage modlinkage = { 207 MODREV_1, { (void *)&rtls_modldrv, NULL } 208 }; 209 210 /* 211 * ========== RealTek chip register access Routines ========== 212 */ 213 static uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg); 214 #pragma inline(rtls_reg_get8) 215 static uint8_t 216 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg) 217 { 218 uint8_t *addr; 219 220 addr = REG8(rtlsp->io_reg, reg); 221 return (ddi_get8(rtlsp->io_handle, addr)); 222 } 223 224 static uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg); 225 #pragma inline(rtls_reg_get16) 226 static uint16_t 227 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg) 228 { 229 uint16_t *addr; 230 231 addr = REG16(rtlsp->io_reg, reg); 232 return (ddi_get16(rtlsp->io_handle, addr)); 233 } 234 235 static uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg); 236 #pragma inline(rtls_reg_get32) 237 static uint32_t 238 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg) 239 { 240 uint32_t *addr; 241 242 addr = REG32(rtlsp->io_reg, reg); 243 return (ddi_get32(rtlsp->io_handle, addr)); 244 } 245 246 static void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value); 247 #pragma inline(rtls_reg_set8) 248 static void 249 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value) 250 { 251 uint8_t *addr; 252 253 addr = REG8(rtlsp->io_reg, reg); 254 ddi_put8(rtlsp->io_handle, addr, value); 255 } 256 257 static void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value); 258 #pragma inline(rtls_reg_set16) 259 static void 260 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value) 261 { 262 uint16_t *addr; 263 264 addr = REG16(rtlsp->io_reg, reg); 265 ddi_put16(rtlsp->io_handle, addr, value); 266 } 267 268 static void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value); 269 #pragma inline(rtls_reg_set32) 270 static void 271 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value) 272 { 273 uint32_t *addr; 274 275 addr = REG32(rtlsp->io_reg, reg); 276 ddi_put32(rtlsp->io_handle, addr, value); 277 } 278 279 /* 280 * ========== Module Loading Entry Points ========== 281 */ 282 int 283 _init(void) 284 { 285 int rv; 286 287 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME); 288 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) { 289 mac_fini_ops(&rtls_dev_ops); 290 } 291 return (rv); 292 } 293 294 int 295 _fini(void) 296 { 297 int rv; 298 299 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) { 300 mac_fini_ops(&rtls_dev_ops); 301 } 302 return (rv); 303 } 304 305 int 306 _info(struct modinfo *modinfop) 307 { 308 return (mod_info(&modlinkage, modinfop)); 309 } 310 311 312 /* 313 * ========== DDI Entry Points ========== 314 */ 315 316 /* 317 * attach(9E) -- Attach a device to the system 318 * 319 * Called once for each board successfully probed. 320 */ 321 static int 322 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 323 { 324 rtls_t *rtlsp; /* Our private device info */ 325 ddi_acc_handle_t pci_handle; 326 uint16_t pci_commond; 327 uint16_t vendorid; 328 uint16_t deviceid; 329 uint32_t device; 330 mac_register_t *macp; 331 int err; 332 333 switch (cmd) { 334 case DDI_ATTACH: 335 break; 336 case DDI_RESUME: 337 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 338 return (DDI_FAILURE); 339 } 340 mutex_enter(&rtlsp->rtls_io_lock); 341 mutex_enter(&rtlsp->rtls_rx_lock); 342 mutex_enter(&rtlsp->rtls_tx_lock); 343 /* 344 * Turn on Master Enable (DMA) and IO Enable bits. 345 * Enable PCI Memory Space accesses 346 * Disable Memory Write/Invalidate 347 */ 348 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 349 mutex_exit(&rtlsp->rtls_tx_lock); 350 mutex_exit(&rtlsp->rtls_rx_lock); 351 mutex_exit(&rtlsp->rtls_io_lock); 352 return (DDI_FAILURE); 353 } 354 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 355 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 356 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 357 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 358 pci_config_teardown(&pci_handle); 359 360 rtls_chip_restart(rtlsp); 361 rtlsp->chip_error = B_FALSE; 362 rtlsp->tx_retry = 0; 363 rtlsp->rtls_suspended = B_FALSE; 364 mutex_exit(&rtlsp->rtls_tx_lock); 365 mutex_exit(&rtlsp->rtls_rx_lock); 366 mutex_exit(&rtlsp->rtls_io_lock); 367 368 mii_resume(rtlsp->mii); 369 370 mac_tx_update(rtlsp->mh); 371 return (DDI_SUCCESS); 372 default: 373 return (DDI_FAILURE); 374 } 375 376 /* 377 * we don't support high level interrupts in the driver 378 */ 379 if (ddi_intr_hilevel(devinfo, 0) != 0) { 380 cmn_err(CE_WARN, "unsupported high level interrupt"); 381 return (DDI_FAILURE); 382 } 383 384 /* 385 * Get handle to access pci configuration space 386 */ 387 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 388 cmn_err(CE_WARN, "pci_config_setup fail."); 389 return (DDI_FAILURE); 390 } 391 392 /* 393 * Make sure we support this particular vendor/device 394 */ 395 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID); 396 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID); 397 device = vendorid; 398 device = (device << 16) | deviceid; /* combine two id together */ 399 400 /* 401 * See if we support this device 402 * We do not return for wrong device id. It's user risk. 403 */ 404 switch (device) { 405 default: 406 cmn_err(CE_WARN, 407 "RTLS doesn't support this device: " 408 "vendorID = 0x%x, deviceID = 0x%x", 409 vendorid, deviceid); 410 break; 411 case RTLS_SUPPORT_DEVICE_1: 412 case RTLS_SUPPORT_DEVICE_2: 413 case RTLS_SUPPORT_DEVICE_3: 414 case RTLS_SUPPORT_DEVICE_4: 415 break; 416 } 417 418 /* 419 * Turn on Master Enable (DMA) and IO Enable bits. 420 * Enable PCI Memory Space accesses 421 * Disable Memory Write/Invalidate 422 */ 423 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 424 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 425 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 426 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 427 428 /* 429 * Free handle to access pci configuration space 430 */ 431 pci_config_teardown(&pci_handle); 432 433 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP); 434 435 ddi_set_driver_private(devinfo, rtlsp); 436 rtlsp->devinfo = devinfo; 437 rtlsp->instance = ddi_get_instance(devinfo); 438 439 /* 440 * Map operating register 441 */ 442 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg, 443 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle); 444 if (err != DDI_SUCCESS) { 445 kmem_free((caddr_t)rtlsp, sizeof (rtls_t)); 446 cmn_err(CE_WARN, "ddi_regs_map_setup fail."); 447 return (DDI_FAILURE); 448 } 449 450 /* 451 * Allocate the TX and RX descriptors/buffers 452 */ 453 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) { 454 cmn_err(CE_WARN, "DMA buffer allocation fail."); 455 goto fail; 456 } 457 458 /* 459 * Reset the chip 460 */ 461 err = rtls_chip_reset(rtlsp, B_FALSE); 462 if (err != DDI_SUCCESS) 463 goto fail; 464 465 /* 466 * Init rtls_t structure 467 */ 468 rtls_get_mac_addr(rtlsp, rtlsp->netaddr); 469 470 /* 471 * Add the interrupt handler 472 * 473 * This will prevent receiving interrupts before device is ready, as 474 * we are initializing device after setting the interrupts. So we 475 * will not get our interrupt handler invoked by OS while our device 476 * is still coming up or timer routines will not start till we are 477 * all set to process... 478 */ 479 480 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr, 481 (caddr_t)rtlsp) != DDI_SUCCESS) { 482 cmn_err(CE_WARN, "ddi_add_intr fail."); 483 goto late_fail; 484 } 485 486 if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) { 487 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 488 goto late_fail; 489 } 490 /* 491 * Note: Some models of 8139 can support pause, but we have 492 * not implemented support for it at this time. This might be 493 * an interesting feature to add later. 494 */ 495 mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE); 496 497 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 498 cmn_err(CE_WARN, "mac_alloc fail."); 499 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 500 goto late_fail; 501 } 502 503 /* 504 * Init mutex 505 */ 506 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 507 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 508 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 509 510 /* 511 * Initialize pointers to device specific functions which will be 512 * used by the generic layer. 513 */ 514 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 515 macp->m_driver = rtlsp; 516 macp->m_dip = devinfo; 517 macp->m_src_addr = rtlsp->netaddr; 518 macp->m_callbacks = &rtls_m_callbacks; 519 macp->m_min_sdu = 0; 520 macp->m_max_sdu = ETHERMTU; 521 macp->m_margin = VLAN_TAGSZ; 522 523 if (mac_register(macp, &rtlsp->mh) != 0) { 524 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 525 mutex_destroy(&rtlsp->rtls_io_lock); 526 mutex_destroy(&rtlsp->rtls_tx_lock); 527 mutex_destroy(&rtlsp->rtls_rx_lock); 528 goto late_fail; 529 } 530 531 mac_free(macp); 532 533 return (DDI_SUCCESS); 534 535 late_fail: 536 if (macp) 537 mac_free(macp); 538 if (rtlsp->mii) 539 mii_free(rtlsp->mii); 540 541 fail: 542 ddi_regs_map_free(&rtlsp->io_handle); 543 rtls_free_bufs(rtlsp); 544 kmem_free(rtlsp, sizeof (rtls_t)); 545 546 return (DDI_FAILURE); 547 } 548 549 /* 550 * detach(9E) -- Detach a device from the system 551 */ 552 static int 553 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 554 { 555 rtls_t *rtlsp; /* our private device info */ 556 557 /* 558 * Get the driver private structure 559 */ 560 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 561 return (DDI_FAILURE); 562 } 563 564 switch (cmd) { 565 case DDI_DETACH: 566 break; 567 568 case DDI_SUSPEND: 569 mii_suspend(rtlsp->mii); 570 571 mutex_enter(&rtlsp->rtls_io_lock); 572 mutex_enter(&rtlsp->rtls_rx_lock); 573 mutex_enter(&rtlsp->rtls_tx_lock); 574 575 rtlsp->rtls_suspended = B_TRUE; 576 rtls_chip_stop(rtlsp); 577 578 mutex_exit(&rtlsp->rtls_tx_lock); 579 mutex_exit(&rtlsp->rtls_rx_lock); 580 mutex_exit(&rtlsp->rtls_io_lock); 581 return (DDI_SUCCESS); 582 583 default: 584 return (DDI_FAILURE); 585 } 586 587 if (mac_unregister(rtlsp->mh) != 0) { 588 /* device busy */ 589 return (DDI_FAILURE); 590 } 591 592 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 593 594 mii_free(rtlsp->mii); 595 596 mutex_destroy(&rtlsp->rtls_io_lock); 597 mutex_destroy(&rtlsp->rtls_tx_lock); 598 mutex_destroy(&rtlsp->rtls_rx_lock); 599 600 ddi_regs_map_free(&rtlsp->io_handle); 601 rtls_free_bufs(rtlsp); 602 kmem_free(rtlsp, sizeof (rtls_t)); 603 604 return (DDI_SUCCESS); 605 } 606 607 /* 608 * quiesce(9E) entry point. 609 * 610 * This function is called when the system is single-threaded at high 611 * PIL with preemption disabled. Therefore, this function must not be 612 * blocked. 613 * 614 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 615 * DDI_FAILURE indicates an error condition and should almost never happen. 616 */ 617 static int 618 rtls_quiesce(dev_info_t *devinfo) 619 { 620 rtls_t *rtlsp; /* our private device info */ 621 622 /* 623 * Get the driver private structure 624 */ 625 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 626 return (DDI_FAILURE); 627 } 628 return (rtls_chip_reset(rtlsp, B_TRUE)); 629 } 630 631 /* 632 * ========== MAC Entry Points ========== 633 */ 634 635 /* 636 * rtls_m_start() -- start the board receiving and allow transmits 637 */ 638 static int 639 rtls_m_start(void *arg) 640 { 641 rtls_t *rtlsp = (rtls_t *)arg; 642 643 mutex_enter(&rtlsp->rtls_io_lock); 644 mutex_enter(&rtlsp->rtls_rx_lock); 645 mutex_enter(&rtlsp->rtls_tx_lock); 646 647 if (!rtlsp->rtls_suspended) 648 rtls_chip_restart(rtlsp); 649 650 rtlsp->rtls_running = B_TRUE; 651 652 mutex_exit(&rtlsp->rtls_tx_lock); 653 mutex_exit(&rtlsp->rtls_rx_lock); 654 mutex_exit(&rtlsp->rtls_io_lock); 655 656 drv_usecwait(100); 657 658 mii_start(rtlsp->mii); 659 660 return (0); 661 } 662 663 /* 664 * rtls_m_stop() -- stop board receiving and transmits 665 */ 666 static void 667 rtls_m_stop(void *arg) 668 { 669 rtls_t *rtlsp = (rtls_t *)arg; 670 671 mii_stop(rtlsp->mii); 672 673 mutex_enter(&rtlsp->rtls_io_lock); 674 675 if (!rtlsp->rtls_suspended) 676 rtls_chip_stop(rtlsp); 677 rtlsp->rtls_running = B_FALSE; 678 679 mutex_exit(&rtlsp->rtls_io_lock); 680 } 681 682 /* 683 * rtls_m_unicst() -- set the physical network address 684 * on the board 685 */ 686 static int 687 rtls_m_unicst(void *arg, const uint8_t *macaddr) 688 { 689 rtls_t *rtlsp = arg; 690 691 mutex_enter(&rtlsp->rtls_io_lock); 692 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL); 693 if (!rtlsp->rtls_suspended) 694 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 695 mutex_exit(&rtlsp->rtls_io_lock); 696 return (0); 697 } 698 699 /* 700 * rtls_m_multicst() -- set(enable) or disable a multicast address 701 * 702 * Program the hardware to enable/disable the multicast address in "mcast". 703 */ 704 static int 705 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast) 706 { 707 rtls_t *rtlsp = (rtls_t *)arg; 708 uint_t index; 709 uint32_t *hashp; 710 711 mutex_enter(&rtlsp->rtls_io_lock); 712 hashp = rtlsp->multi_hash; 713 index = rtls_hash_index(mcast); 714 /* index value is between 0 and 63 */ 715 716 if (enable) { 717 if (rtlsp->multicast_cnt[index]++) { 718 mutex_exit(&rtlsp->rtls_io_lock); 719 return (0); 720 } 721 hashp[index/32] |= 1<< (index % 32); 722 } else { 723 if (--rtlsp->multicast_cnt[index]) { 724 mutex_exit(&rtlsp->rtls_io_lock); 725 return (0); 726 } 727 hashp[index/32] &= ~(1<< (index % 32)); 728 } 729 730 /* 731 * Set multicast register 732 */ 733 if (!rtlsp->rtls_suspended) { 734 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]); 735 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]); 736 } 737 738 mutex_exit(&rtlsp->rtls_io_lock); 739 740 return (0); 741 } 742 743 /* 744 * rtls_hash_index() -- a hashing function used for setting the 745 * node address or a multicast address 746 */ 747 static uint_t 748 rtls_hash_index(const uint8_t *address) 749 { 750 uint32_t crc = (ulong_t)RTLS_HASH_CRC; 751 uint32_t const POLY = RTLS_HASH_POLY; 752 uint32_t msb; 753 int bytes; 754 uchar_t currentbyte; 755 uint_t index; 756 int bit; 757 758 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 759 currentbyte = address[bytes]; 760 for (bit = 0; bit < 8; bit++) { 761 msb = crc >> 31; 762 crc <<= 1; 763 if (msb ^ (currentbyte & 1)) { 764 crc ^= POLY; 765 crc |= 0x00000001; 766 } 767 currentbyte >>= 1; 768 } 769 } 770 771 index = crc >> 26; 772 773 return (index); 774 } 775 776 /* 777 * rtls_m_promisc() -- set or reset promiscuous mode on the board 778 */ 779 static int 780 rtls_m_promisc(void *arg, boolean_t on) 781 { 782 rtls_t *rtlsp = arg; 783 784 mutex_enter(&rtlsp->rtls_io_lock); 785 786 rtlsp->promisc = on; 787 if (!rtlsp->rtls_suspended) { 788 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 789 if (on) { 790 val32 |= RX_ACCEPT_ALL_PACKET; 791 } else { 792 val32 &= ~RX_ACCEPT_ALL_PACKET; 793 } 794 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32); 795 } 796 mutex_exit(&rtlsp->rtls_io_lock); 797 798 return (0); 799 } 800 801 /* 802 * rtls_m_stat() -- retrieve statistic 803 * 804 * MAC calls this routine just before it reads the driver's statistics 805 * structure. If your board maintains statistics, this is the time to 806 * read them in and update the values in the structure. If the driver 807 * maintains statistics continuously, this routine need do nothing. 808 */ 809 static int 810 rtls_m_stat(void *arg, uint_t stat, uint64_t *val) 811 { 812 rtls_t *rtlsp = arg; 813 814 if (mii_m_getstat(rtlsp->mii, stat, val) == 0) { 815 return (0); 816 } 817 818 switch (stat) { 819 case MAC_STAT_IPACKETS: 820 *val = rtlsp->stats.ipackets; 821 break; 822 case MAC_STAT_RBYTES: 823 *val = rtlsp->stats.rbytes; 824 break; 825 case MAC_STAT_OPACKETS: 826 *val = rtlsp->stats.opackets; 827 break; 828 case MAC_STAT_OBYTES: 829 *val = rtlsp->stats.obytes; 830 break; 831 case MAC_STAT_IERRORS: 832 *val = rtlsp->stats.rcv_err; 833 break; 834 case MAC_STAT_OERRORS: 835 *val = rtlsp->stats.xmt_err; 836 break; 837 case MAC_STAT_MULTIRCV: 838 *val = rtlsp->stats.multi_rcv; 839 break; 840 case MAC_STAT_BRDCSTRCV: 841 *val = rtlsp->stats.brdcst_rcv; 842 break; 843 case MAC_STAT_MULTIXMT: 844 *val = rtlsp->stats.multi_xmt; 845 break; 846 case MAC_STAT_BRDCSTXMT: 847 *val = rtlsp->stats.brdcst_xmt; 848 break; 849 case MAC_STAT_UNDERFLOWS: 850 *val = rtlsp->stats.underflow; 851 break; 852 case MAC_STAT_OVERFLOWS: 853 *val = rtlsp->stats.overflow; 854 break; 855 case MAC_STAT_NORCVBUF: 856 *val = rtlsp->stats.no_rcvbuf; 857 break; 858 case MAC_STAT_COLLISIONS: 859 *val = rtlsp->stats.collisions; 860 break; 861 case ETHER_STAT_FCS_ERRORS: 862 *val = rtlsp->stats.crc_err; 863 break; 864 case ETHER_STAT_ALIGN_ERRORS: 865 *val = rtlsp->stats.frame_err; 866 break; 867 case ETHER_STAT_DEFER_XMTS: 868 *val = rtlsp->stats.defer; 869 break; 870 case ETHER_STAT_TX_LATE_COLLISIONS: 871 *val = rtlsp->stats.xmt_latecoll; 872 break; 873 case ETHER_STAT_TOOLONG_ERRORS: 874 *val = rtlsp->stats.too_long; 875 break; 876 case ETHER_STAT_TOOSHORT_ERRORS: 877 *val = rtlsp->stats.in_short; 878 break; 879 case ETHER_STAT_CARRIER_ERRORS: 880 *val = rtlsp->stats.no_carrier; 881 break; 882 case ETHER_STAT_FIRST_COLLISIONS: 883 *val = rtlsp->stats.firstcol; 884 break; 885 case ETHER_STAT_MULTI_COLLISIONS: 886 *val = rtlsp->stats.multicol; 887 break; 888 default: 889 return (ENOTSUP); 890 } 891 892 /* 893 * RTL8139 don't support MII statistics, 894 * these values are maintained by the driver software. 895 */ 896 897 #ifdef RTLS_DEBUG 898 if (rtls_debug & RTLS_TRACE) 899 rtls_reg_print(rtlsp); 900 #endif 901 902 return (0); 903 } 904 905 /* 906 * rtls_send() -- send a packet 907 * 908 * Called when a packet is ready to be transmitted. A pointer to an 909 * M_DATA message that contains the packet is passed to this routine. 910 * The complete LLC header is contained in the message's first message 911 * block, and the remainder of the packet is contained within 912 * additional M_DATA message blocks linked to the first message block. 913 * 914 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if 915 * if the packet is being deferred and should be tried again later. 916 */ 917 918 static boolean_t 919 rtls_send(rtls_t *rtlsp, mblk_t *mp) 920 { 921 int totlen; 922 int ncc; 923 uint16_t cur_desc; 924 uint32_t tx_status; 925 926 ASSERT(mp != NULL); 927 ASSERT(rtlsp->rtls_running); 928 929 mutex_enter(&rtlsp->rtls_tx_lock); 930 931 if (rtlsp->rtls_suspended) { 932 mutex_exit(&rtlsp->rtls_tx_lock); 933 return (B_FALSE); 934 } 935 936 /* 937 * If chip error ... 938 */ 939 if (rtlsp->chip_error) { 940 #ifdef RTLS_DEBUG 941 cmn_err(CE_WARN, 942 "%s: send fail--CHIP ERROR!", 943 rtlsp->ifname); 944 #endif 945 mutex_exit(&rtlsp->rtls_tx_lock); 946 freemsg(mp); 947 return (B_TRUE); 948 } 949 950 /* 951 * If chip link down ... Note that experimentation shows that 952 * the device seems not to care about whether or not we have 953 * this check, but if we don't add the check here, it might 954 * not be properly reported as a carrier error. 955 */ 956 if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) { 957 #ifdef RTLS_DEBUG 958 cmn_err(CE_WARN, 959 "%s: send fail--LINK DOWN!", 960 rtlsp->ifname); 961 #endif 962 rtlsp->stats.no_carrier++; 963 mutex_exit(&rtlsp->rtls_tx_lock); 964 freemsg(mp); 965 return (B_TRUE); 966 } 967 968 /* 969 * Current transmit descriptor 970 */ 971 cur_desc = rtlsp->tx_current_desc; 972 ASSERT(cur_desc < RTLS_MAX_TX_DESC); 973 974 /* 975 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop 976 * of transmit,we needn't judge transmit status. 977 */ 978 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) { 979 rtlsp->tx_first_loop++; 980 goto tx_ready; 981 } 982 983 /* 984 * If it's not the first tx loop, we need judge whether the chip is 985 * busy or not. Otherwise, we have to reschedule send and wait... 986 */ 987 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc); 988 989 /* 990 * H/W doesn't complete packet transmit 991 */ 992 if (!(tx_status & TX_COMPLETE_FLAG)) { 993 #ifdef RTLS_DEBUG 994 if (rtls_debug & RTLS_SEND) { 995 cmn_err(CE_NOTE, 996 "%s: rtls_send: need_sched", rtlsp->ifname); 997 } 998 #endif 999 /* 1000 * Through test, we find RTL8139 tx status might be 1001 * not-completing all along. We have to reset chip 1002 * to make RTL8139 tansmit re-work. 1003 */ 1004 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) { 1005 1006 /* 1007 * Wait transmit h/w more time... 1008 */ 1009 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */ 1010 1011 /* 1012 * Judge tx status again, if it remains not-completing, 1013 * we can confirm RTL8139 is in chip error state 1014 * and must reset it. 1015 */ 1016 tx_status = rtls_reg_get32(rtlsp, 1017 TX_STATUS_DESC0_REG + 4 * cur_desc); 1018 if (!(tx_status & TX_COMPLETE_FLAG)) { 1019 #ifdef RTLS_DEBUG 1020 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x", 1021 rtlsp->ifname, tx_status); 1022 #endif 1023 rtlsp->tx_retry = 0; 1024 rtlsp->chip_error = B_TRUE; 1025 rtlsp->stats.xmt_err++; 1026 rtlsp->stats.mac_xmt_err++; 1027 mutex_exit(&rtlsp->rtls_tx_lock); 1028 freemsg(mp); 1029 return (B_TRUE); 1030 } 1031 } else { 1032 rtlsp->stats.defer++; 1033 rtlsp->need_sched = B_TRUE; 1034 mutex_exit(&rtlsp->rtls_tx_lock); 1035 return (B_FALSE); 1036 } 1037 } 1038 1039 /* 1040 * Transmit error? 1041 */ 1042 if (tx_status & TX_ERR_FLAG) { 1043 #ifdef RTLS_DEBUG 1044 if (rtls_debug & RTLS_SEND) { 1045 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x", 1046 rtlsp->ifname, tx_status); 1047 } 1048 #endif 1049 rtlsp->stats.xmt_err++; 1050 if (tx_status & TX_STATUS_TX_UNDERRUN) 1051 rtlsp->stats.underflow++; 1052 if (tx_status & TX_STATUS_CS_LOST) 1053 rtlsp->stats.no_carrier++; 1054 if (tx_status & TX_STATUS_OWC) 1055 rtlsp->stats.xmt_latecoll++; 1056 } 1057 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT); 1058 if (ncc != 0) { 1059 rtlsp->stats.collisions += ncc; 1060 rtlsp->stats.firstcol++; 1061 rtlsp->stats.multicol += ncc - 1; 1062 } 1063 1064 tx_ready: 1065 /* 1066 * Initialize variable 1067 */ 1068 rtlsp->tx_retry = 0; 1069 totlen = 0; 1070 1071 /* 1072 * Copy packet to tx descriptor buffer 1073 */ 1074 totlen = msgsize(mp); 1075 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */ 1076 cmn_err(CE_NOTE, 1077 "%s: rtls_send: try to send large %d packet", 1078 rtlsp->ifname, totlen); 1079 rtlsp->stats.mac_xmt_err++; 1080 rtlsp->stats.xmt_err++; 1081 freemsg(mp); 1082 mutex_exit(&rtlsp->rtls_tx_lock); 1083 return (B_TRUE); 1084 } 1085 1086 /* this will free the mblk */ 1087 mcopymsg(mp, rtlsp->tx_buf[cur_desc]); 1088 1089 /* update stats */ 1090 if (*rtlsp->tx_buf[cur_desc] & 0x1) { 1091 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc]; 1092 if ((ptr[0] == 0xffff) && 1093 (ptr[1] == 0xffff) && 1094 (ptr[2] == 0xffff)) { 1095 rtlsp->stats.brdcst_xmt++; 1096 } else { 1097 rtlsp->stats.multi_xmt++; 1098 } 1099 } 1100 rtlsp->stats.opackets++; 1101 rtlsp->stats.obytes += totlen; 1102 1103 if (totlen < ETHERMIN) { 1104 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen); 1105 totlen = ETHERMIN; 1106 } 1107 1108 /* make sure caches are flushed */ 1109 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen, 1110 DDI_DMA_SYNC_FORDEV); 1111 1112 /* 1113 * Start transmit 1114 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes 1115 * to avoid tx underrun. 1116 */ 1117 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc, 1118 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT)); 1119 1120 /* 1121 * Update the value of current tx descriptor 1122 */ 1123 cur_desc++; 1124 cur_desc %= RTLS_MAX_TX_DESC; 1125 rtlsp->tx_current_desc = cur_desc; 1126 1127 mutex_exit(&rtlsp->rtls_tx_lock); 1128 1129 return (B_TRUE); 1130 } 1131 1132 /* 1133 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next. 1134 */ 1135 static mblk_t * 1136 rtls_m_tx(void *arg, mblk_t *mp) 1137 { 1138 rtls_t *rtlsp = arg; 1139 mblk_t *next; 1140 1141 while (mp != NULL) { 1142 next = mp->b_next; 1143 mp->b_next = NULL; 1144 if (!rtls_send(rtlsp, mp)) { 1145 mp->b_next = next; 1146 break; 1147 } 1148 mp = next; 1149 } 1150 return (mp); 1151 } 1152 1153 /* 1154 * rtls_receive() -- receive packets 1155 * 1156 * Called when receive interrupts detected 1157 */ 1158 static void 1159 rtls_receive(rtls_t *rtlsp) 1160 { 1161 mblk_t *head = NULL; 1162 mblk_t **mpp; 1163 mblk_t *mp; 1164 uint16_t rx_status; 1165 uint16_t packet_len; 1166 int wrap_size; 1167 uint32_t cur_rx; 1168 uint8_t *rx_ptr; 1169 1170 mpp = &head; 1171 1172 mutex_enter(&rtlsp->rtls_rx_lock); 1173 1174 if (rtlsp->rtls_suspended) { 1175 mutex_exit(&rtlsp->rtls_rx_lock); 1176 return; 1177 } 1178 1179 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG) 1180 & RT_COMMAND_BUFF_EMPTY) == 0) { 1181 1182 /* 1183 * Chip error state 1184 */ 1185 if (rtlsp->chip_error) { 1186 #ifdef RTLS_DEBUG 1187 cmn_err(CE_WARN, 1188 "%s: receive fail--CHIP ERROR!", 1189 rtlsp->ifname); 1190 #endif 1191 break; 1192 } 1193 1194 cur_rx = rtlsp->cur_rx; 1195 rx_ptr = rtlsp->rx_ring + cur_rx; 1196 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]); 1197 rx_status = rx_ptr[0]; 1198 1199 /* 1200 * DMA still in progress 1201 */ 1202 if (packet_len == RX_STATUS_DMA_BUSY) { 1203 cmn_err(CE_NOTE, "%s: Rx DMA still in progress", 1204 rtlsp->ifname); 1205 break; 1206 } 1207 1208 /* 1209 * Check receive status 1210 */ 1211 if ((rx_status & RX_ERR_FLAGS) || 1212 (!(rx_status & RX_HEADER_STATUS_ROK)) || 1213 (packet_len < (ETHERMIN + ETHERFCSL)) || 1214 (packet_len > (ETHERMAX + ETHERFCSL + 4))) { 1215 #ifdef RTLS_DEBUG 1216 cmn_err(CE_NOTE, 1217 "%s: receive error, status = 0x%x, length = %d", 1218 rtlsp->ifname, rx_status, packet_len); 1219 #endif 1220 /* 1221 * Rx error statistics 1222 */ 1223 if ((rx_status & RX_HEADER_STATUS_RUNT) || 1224 (packet_len < (ETHERMIN + ETHERFCSL))) 1225 rtlsp->stats.in_short++; 1226 else if (packet_len > (ETHERMAX + ETHERFCSL + 4)) 1227 rtlsp->stats.too_long++; 1228 else if (rx_status & RX_HEADER_STATUS_CRC) 1229 rtlsp->stats.crc_err++; 1230 else if (rx_status & RX_HEADER_STATUS_FAE) 1231 rtlsp->stats.frame_err++; 1232 1233 /* 1234 * Set chip_error flag to reset chip: 1235 * (suggested in RealTek programming guide.) 1236 */ 1237 rtlsp->chip_error = B_TRUE; 1238 mutex_exit(&rtlsp->rtls_rx_lock); 1239 return; 1240 } 1241 1242 /* 1243 * We need not up-send ETHERFCSL bytes of receive packet 1244 */ 1245 packet_len -= ETHERFCSL; 1246 1247 /* 1248 * Allocate buffer to receive this good packet 1249 */ 1250 mp = allocb(packet_len, 0); 1251 1252 /* 1253 * Copy the data found into the new cluster, we have (+4) 1254 * to get us past the packet head data that the rtl chip 1255 * places at the start of the message 1256 */ 1257 if ((cur_rx + packet_len + RX_HEADER_SIZE) 1258 > RTLS_RX_BUF_RING) { 1259 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE 1260 - RTLS_RX_BUF_RING; 1261 #ifdef RTLS_DEBUG 1262 if (rtls_debug & RTLS_RECV) { 1263 cmn_err(CE_NOTE, 1264 "%s: Rx: packet_len = %d, wrap_size = %d", 1265 rtlsp->ifname, packet_len, wrap_size); 1266 } 1267 #endif 1268 1269 if (mp != NULL) { 1270 /* Flush caches */ 1271 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1272 cur_rx + RX_HEADER_SIZE, 1273 packet_len - wrap_size, 1274 DDI_DMA_SYNC_FORKERNEL); 1275 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1276 0, wrap_size, 1277 DDI_DMA_SYNC_FORKERNEL); 1278 1279 /* 1280 * Copy in first section of message as stored 1281 * at the end of the ring buffer 1282 */ 1283 bcopy(rx_ptr + RX_HEADER_SIZE, 1284 mp->b_wptr, packet_len - wrap_size); 1285 mp->b_wptr += packet_len - wrap_size; 1286 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size); 1287 mp->b_wptr += wrap_size; 1288 *mpp = mp; 1289 mpp = &mp->b_next; 1290 1291 rtlsp->stats.ipackets++; 1292 if (rx_status & RX_HEADER_STATUS_BCAST) 1293 rtlsp->stats.brdcst_rcv++; 1294 if (rx_status & RX_HEADER_STATUS_MULTI) 1295 rtlsp->stats.multi_rcv++; 1296 rtlsp->stats.rbytes += packet_len; 1297 } else { 1298 rtlsp->stats.no_rcvbuf++; 1299 } 1300 1301 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL); 1302 /* 4-byte aligned */ 1303 } else { 1304 1305 if (mp != NULL) { 1306 /* Flush caches */ 1307 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1308 cur_rx + RX_HEADER_SIZE, packet_len, 1309 DDI_DMA_SYNC_FORKERNEL); 1310 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr, 1311 packet_len); 1312 mp->b_wptr += packet_len; 1313 *mpp = mp; 1314 mpp = &mp->b_next; 1315 1316 rtlsp->stats.ipackets++; 1317 if (rx_status & RX_HEADER_STATUS_BCAST) 1318 rtlsp->stats.brdcst_rcv++; 1319 if (rx_status & RX_HEADER_STATUS_MULTI) 1320 rtlsp->stats.multi_rcv++; 1321 rtlsp->stats.rbytes += packet_len; 1322 } else { 1323 rtlsp->stats.no_rcvbuf++; 1324 } 1325 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL; 1326 1327 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx); 1328 /* 4-byte aligned */ 1329 } 1330 1331 /* 1332 * Update rx buffer ring read pointer: 1333 * give us a little leeway to ensure no overflow 1334 */ 1335 rtlsp->cur_rx = cur_rx; 1336 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, 1337 cur_rx - READ_ADDR_GAP); 1338 } 1339 mutex_exit(&rtlsp->rtls_rx_lock); 1340 1341 /* 1342 * Upsend packet 1343 */ 1344 if (head) { 1345 mac_rx(rtlsp->mh, NULL, head); 1346 } 1347 } 1348 1349 /* 1350 * rtls_intr() -- interrupt from board to inform us that a receive or 1351 * link change. 1352 */ 1353 static uint_t 1354 rtls_intr(caddr_t arg) 1355 { 1356 rtls_t *rtlsp = (void *)arg; 1357 uint32_t int_status; 1358 uint32_t val32; 1359 boolean_t resched = B_FALSE; 1360 1361 mutex_enter(&rtlsp->rtls_io_lock); 1362 if (rtlsp->rtls_suspended) { 1363 mutex_exit(&rtlsp->rtls_io_lock); 1364 return (DDI_INTR_UNCLAIMED); 1365 } 1366 1367 /* 1368 * Was this interrupt caused by our device... 1369 */ 1370 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1371 if (!(int_status & rtlsp->int_mask)) { 1372 mutex_exit(&rtlsp->rtls_io_lock); 1373 return (DDI_INTR_UNCLAIMED); 1374 /* indicate it wasn't our interrupt */ 1375 } 1376 1377 /* 1378 * Clear interrupt 1379 */ 1380 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status); 1381 1382 /* 1383 * If chip error, restart chip... 1384 */ 1385 if (rtlsp->chip_error) { 1386 mutex_enter(&rtlsp->rtls_rx_lock); 1387 mutex_enter(&rtlsp->rtls_tx_lock); 1388 rtls_chip_restart(rtlsp); 1389 rtlsp->chip_error = B_FALSE; 1390 rtlsp->tx_retry = 0; 1391 mutex_exit(&rtlsp->rtls_tx_lock); 1392 mutex_exit(&rtlsp->rtls_rx_lock); 1393 mutex_exit(&rtlsp->rtls_io_lock); 1394 return (DDI_INTR_CLAIMED); 1395 /* no need to hand other interrupts */ 1396 } 1397 1398 /* 1399 * Transmit error interrupt 1400 */ 1401 if (int_status & TX_ERR_INT) { 1402 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1403 val32 |= TX_CLEAR_ABORT; 1404 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32); 1405 cmn_err(CE_WARN, "%s: transmit abort!!!", rtlsp->ifname); 1406 } 1407 1408 /* 1409 * Trigger mac_tx_update 1410 */ 1411 if (rtlsp->need_sched) { 1412 rtlsp->need_sched = B_FALSE; 1413 resched = B_TRUE; 1414 } 1415 1416 mutex_exit(&rtlsp->rtls_io_lock); 1417 1418 /* 1419 * Receive interrupt 1420 */ 1421 if (int_status & RTLS_RX_INT) { 1422 if (int_status & RX_OVERFLOW_INT) { 1423 rtlsp->stats.overflow++; 1424 rtlsp->stats.rcv_err++; 1425 } 1426 rtls_receive(rtlsp); 1427 } 1428 1429 /* 1430 * Link change interrupt. 1431 */ 1432 if (int_status & LINK_CHANGE_INT) { 1433 mii_check(rtlsp->mii); 1434 } 1435 1436 if (resched) { 1437 mac_tx_update(rtlsp->mh); 1438 } 1439 1440 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1441 } 1442 1443 /* 1444 * ========== Buffer Management Routines ========== 1445 */ 1446 1447 /* 1448 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle 1449 * for accessing it 1450 */ 1451 static int 1452 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize, 1453 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p) 1454 { 1455 caddr_t vaddr; 1456 int err; 1457 1458 /* 1459 * Allocate handle 1460 */ 1461 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr, 1462 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 1463 if (err != DDI_SUCCESS) { 1464 cmn_err(CE_WARN, 1465 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d", 1466 rtlsp->ifname, err); 1467 dma_p->dma_hdl = NULL; 1468 return (DDI_FAILURE); 1469 } 1470 1471 /* 1472 * Allocate memory 1473 */ 1474 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1475 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 1476 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 1477 if (err != DDI_SUCCESS) { 1478 cmn_err(CE_WARN, 1479 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d", 1480 rtlsp->ifname, err); 1481 ddi_dma_free_handle(&dma_p->dma_hdl); 1482 dma_p->dma_hdl = NULL; 1483 dma_p->acc_hdl = NULL; 1484 return (DDI_FAILURE); 1485 } 1486 1487 /* 1488 * Bind the two together 1489 */ 1490 dma_p->mem_va = vaddr; 1491 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1492 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 1493 &dma_p->cookie, &dma_p->ncookies); 1494 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 1495 cmn_err(CE_WARN, 1496 "%s: rtls_alloc_dma_mem: " 1497 "ddi_dma_addr_bind_handle failed: %d", 1498 rtlsp->ifname, err); 1499 ddi_dma_mem_free(&dma_p->acc_hdl); 1500 ddi_dma_free_handle(&dma_p->dma_hdl); 1501 dma_p->acc_hdl = NULL; 1502 dma_p->dma_hdl = NULL; 1503 return (DDI_FAILURE); 1504 } 1505 1506 return (DDI_SUCCESS); 1507 } 1508 1509 /* 1510 * rtls_free_dma_mem() -- free one allocated area of DMAable memory 1511 */ 1512 static void 1513 rtls_free_dma_mem(dma_area_t *dma_p) 1514 { 1515 if (dma_p->dma_hdl != NULL) { 1516 if (dma_p->ncookies) { 1517 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1518 dma_p->ncookies = 0; 1519 } 1520 ddi_dma_free_handle(&dma_p->dma_hdl); 1521 dma_p->dma_hdl = NULL; 1522 } 1523 1524 if (dma_p->acc_hdl != NULL) { 1525 ddi_dma_mem_free(&dma_p->acc_hdl); 1526 dma_p->acc_hdl = NULL; 1527 } 1528 } 1529 1530 /* 1531 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance 1532 */ 1533 static int 1534 rtls_alloc_bufs(rtls_t *rtlsp) 1535 { 1536 int i; 1537 int err; 1538 1539 /* 1540 * Allocate memory & handle for Tx buffers 1541 */ 1542 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1543 err = rtls_alloc_dma_mem(rtlsp, 1544 RTLS_TX_BUF_SIZE, 1545 &rtls_buf_accattr, 1546 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1547 &rtlsp->dma_area_tx[i]); 1548 1549 if (err != DDI_SUCCESS) 1550 return (DDI_FAILURE); 1551 1552 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va; 1553 } 1554 1555 /* 1556 * Allocate memory & handle for Rx buffers 1557 */ 1558 err = rtls_alloc_dma_mem(rtlsp, 1559 RTLS_RX_BUF_SIZE, 1560 &rtls_buf_accattr, 1561 DDI_DMA_READ | DDI_DMA_STREAMING, 1562 &rtlsp->dma_area_rx); 1563 1564 if (err != DDI_SUCCESS) 1565 return (DDI_FAILURE); 1566 1567 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va; 1568 1569 return (DDI_SUCCESS); 1570 } 1571 1572 /* 1573 * rtls_free_bufs() -- free descriptors/buffers allocated for this 1574 * device instance. 1575 */ 1576 static void 1577 rtls_free_bufs(rtls_t *rtlsp) 1578 { 1579 int i; 1580 1581 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1582 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]); 1583 rtlsp->tx_buf[i] = NULL; 1584 } 1585 1586 rtls_free_dma_mem(&rtlsp->dma_area_rx); 1587 rtlsp->rx_ring = NULL; 1588 } 1589 1590 /* 1591 * ========== Chip H/W Operation Routines ========== 1592 */ 1593 1594 /* 1595 * rtls_chip_reset() -- reset chip 1596 */ 1597 static int 1598 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce) 1599 { 1600 int i; 1601 uint16_t val16; 1602 uint8_t val8; 1603 1604 /* 1605 * Chip should be in STOP state 1606 */ 1607 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1608 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1609 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1610 1611 /* 1612 * Disable interrupt 1613 */ 1614 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1615 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1616 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1617 1618 /* 1619 * Clear pended interrupt 1620 */ 1621 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1622 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1623 1624 /* 1625 * Reset chip 1626 */ 1627 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1628 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET); 1629 1630 /* 1631 * Wait for reset success 1632 */ 1633 i = 0; 1634 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) { 1635 if (++i > RTLS_RESET_WAIT_NUM) { 1636 /* 1637 * At quiesce path we can't call cmn_err(), as 1638 * it might block 1639 */ 1640 if (!quiesce) 1641 cmn_err(CE_WARN, 1642 "%s: chip reset fail.", rtlsp->ifname); 1643 return (DDI_FAILURE); 1644 } 1645 RTLS_RESET_WAIT_INTERVAL; 1646 } 1647 1648 return (DDI_SUCCESS); 1649 } 1650 1651 /* 1652 * rtls_chip_init() -- initialize the specified network board short of 1653 * actually starting the board. Call after rtls_chip_reset(). 1654 */ 1655 static void 1656 rtls_chip_init(rtls_t *rtlsp) 1657 { 1658 uint32_t val32; 1659 uint16_t val16; 1660 uint8_t val8; 1661 1662 /* 1663 * Initialize internal data structures 1664 */ 1665 rtlsp->cur_rx = 0; 1666 rtlsp->tx_current_desc = 0; 1667 rtlsp->tx_first_loop = 0; 1668 1669 /* 1670 * Set DMA physical rx/tx buffer address to register 1671 */ 1672 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG, 1673 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address); 1674 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG, 1675 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address); 1676 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG, 1677 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address); 1678 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG, 1679 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address); 1680 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG, 1681 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address); 1682 1683 /* 1684 * Start transmit/receive before set tx/rx configuration register 1685 */ 1686 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1687 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1688 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1689 1690 /* 1691 * Set transmit configuration register 1692 */ 1693 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1694 val32 &= TX_CONSIG_REG_RESERVE; 1695 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT); 1696 1697 /* 1698 * Set receive configuration register 1699 */ 1700 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1701 val32 &= RX_CONSIG_REG_RESERVE; 1702 if (rtlsp->promisc) 1703 val32 |= RX_ACCEPT_ALL_PACKET; 1704 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT); 1705 1706 /* 1707 * Set multicast register 1708 */ 1709 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]); 1710 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]); 1711 1712 /* 1713 * Set unicast address 1714 */ 1715 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 1716 1717 /* 1718 * Set current address of packet read 1719 */ 1720 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL); 1721 1722 /* 1723 * No early-rx interrupts 1724 */ 1725 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG); 1726 val16 &= ~RT_MUL_INTSEL_BITS; 1727 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16); 1728 } 1729 1730 /* 1731 * rtls_chip_start() -- start chip 1732 */ 1733 static void 1734 rtls_chip_start(rtls_t *rtlsp) 1735 { 1736 uint16_t val16; 1737 uint8_t val8; 1738 1739 /* 1740 * Start transmit/receive 1741 */ 1742 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1743 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1744 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1745 1746 /* 1747 * Enable interrupt 1748 */ 1749 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1750 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK); 1751 rtlsp->int_mask = RTLS_INT_MASK; 1752 } 1753 1754 /* 1755 * rtls_chip_restart() -- restart chip 1756 */ 1757 static void 1758 rtls_chip_restart(rtls_t *rtlsp) 1759 { 1760 (void) rtls_chip_reset(rtlsp, B_FALSE); 1761 rtls_chip_init(rtlsp); 1762 rtls_chip_start(rtlsp); 1763 } 1764 1765 /* 1766 * rtls_chip_stop() -- stop board receiving 1767 */ 1768 static void 1769 rtls_chip_stop(rtls_t *rtlsp) 1770 { 1771 uint16_t val16; 1772 uint8_t val8; 1773 1774 /* 1775 * Disable interrupt 1776 */ 1777 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1778 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1779 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1780 1781 /* 1782 * Clear pended interrupt 1783 */ 1784 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1785 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1786 1787 /* 1788 * Stop the board and disable transmit/receive 1789 */ 1790 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1791 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1792 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1793 } 1794 1795 /* 1796 * rtls_get_mac_addr() -- get the physical network address on the board 1797 */ 1798 static void 1799 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr) 1800 { 1801 uint32_t val32; 1802 1803 /* 1804 * Read first 4-byte of mac address 1805 */ 1806 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 1807 macaddr[0] = val32 & 0xff; 1808 val32 = val32 >> 8; 1809 macaddr[1] = val32 & 0xff; 1810 val32 = val32 >> 8; 1811 macaddr[2] = val32 & 0xff; 1812 val32 = val32 >> 8; 1813 macaddr[3] = val32 & 0xff; 1814 1815 /* 1816 * Read last 2-byte of mac address 1817 */ 1818 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 1819 macaddr[4] = val32 & 0xff; 1820 val32 = val32 >> 8; 1821 macaddr[5] = val32 & 0xff; 1822 } 1823 1824 static void 1825 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr) 1826 { 1827 uint32_t val32; 1828 uint8_t val8; 1829 1830 /* 1831 * Change to config register write enable mode 1832 */ 1833 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1834 val8 |= RT_93c46_MODE_CONFIG; 1835 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1836 1837 /* 1838 * Get first 4 bytes of mac address 1839 */ 1840 val32 = macaddr[3]; 1841 val32 = val32 << 8; 1842 val32 |= macaddr[2]; 1843 val32 = val32 << 8; 1844 val32 |= macaddr[1]; 1845 val32 = val32 << 8; 1846 val32 |= macaddr[0]; 1847 1848 /* 1849 * Set first 4 bytes of mac address 1850 */ 1851 rtls_reg_set32(rtlsp, ID_0_REG, val32); 1852 1853 /* 1854 * Get last 2 bytes of mac address 1855 */ 1856 val32 = macaddr[5]; 1857 val32 = val32 << 8; 1858 val32 |= macaddr[4]; 1859 1860 /* 1861 * Set last 2 bytes of mac address 1862 */ 1863 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff; 1864 rtls_reg_set32(rtlsp, ID_4_REG, val32); 1865 1866 /* 1867 * Return to normal network/host communication mode 1868 */ 1869 val8 &= ~RT_93c46_MODE_CONFIG; 1870 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1871 } 1872 1873 static uint16_t 1874 rtls_mii_read(void *arg, uint8_t phy, uint8_t reg) 1875 { 1876 rtls_t *rtlsp = arg; 1877 uint16_t val; 1878 1879 if (phy != 1) { 1880 return (0xffff); 1881 } 1882 switch (reg) { 1883 case MII_CONTROL: 1884 val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 1885 break; 1886 case MII_STATUS: 1887 val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG); 1888 break; 1889 case MII_AN_ADVERT: 1890 val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 1891 break; 1892 case MII_AN_LPABLE: 1893 val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG); 1894 break; 1895 case MII_AN_EXPANSION: 1896 val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG); 1897 break; 1898 case MII_VENDOR(0): 1899 /* 1900 * We "simulate" a vendor private register so that the 1901 * PHY layer can access it to determine detected link 1902 * speed/duplex. 1903 */ 1904 val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1905 break; 1906 case MII_PHYIDH: 1907 case MII_PHYIDL: 1908 default: 1909 val = 0; 1910 break; 1911 } 1912 return (val); 1913 } 1914 1915 void 1916 rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) 1917 { 1918 rtls_t *rtlsp = arg; 1919 uint8_t val8; 1920 1921 if (phy != 1) { 1922 return; 1923 } 1924 switch (reg) { 1925 case MII_CONTROL: 1926 /* Enable writes to all bits of BMCR */ 1927 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1928 val8 |= RT_93c46_MODE_CONFIG; 1929 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1930 /* write out the value */ 1931 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val); 1932 1933 /* Return to normal network/host communication mode */ 1934 val8 &= ~RT_93c46_MODE_CONFIG; 1935 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1936 return; 1937 1938 case MII_STATUS: 1939 rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val); 1940 break; 1941 case MII_AN_ADVERT: 1942 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val); 1943 break; 1944 case MII_AN_LPABLE: 1945 rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val); 1946 break; 1947 case MII_AN_EXPANSION: 1948 rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val); 1949 break; 1950 case MII_PHYIDH: 1951 case MII_PHYIDL: 1952 default: 1953 /* these are not writable */ 1954 break; 1955 } 1956 } 1957 1958 void 1959 rtls_mii_notify(void *arg, link_state_t link) 1960 { 1961 rtls_t *rtlsp = arg; 1962 1963 mac_link_update(rtlsp->mh, link); 1964 } 1965 1966 #ifdef RTLS_DEBUG 1967 /* 1968 * rtls_reg_print() -- print out reg value(for debug use only) 1969 */ 1970 static void 1971 rtls_reg_print(rtls_t *rtlsp) 1972 { 1973 uint8_t val8; 1974 uint16_t val16; 1975 uint32_t val32; 1976 1977 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1978 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x", 1979 rtlsp->ifname, val8); 1980 delay(drv_usectohz(1000)); 1981 1982 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1983 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x", 1984 rtlsp->ifname, val16); 1985 delay(drv_usectohz(1000)); 1986 1987 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1988 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x", 1989 rtlsp->ifname, val16); 1990 delay(drv_usectohz(1000)); 1991 1992 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1993 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x", 1994 rtlsp->ifname, val32); 1995 delay(drv_usectohz(1000)); 1996 1997 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG); 1998 cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d", 1999 rtlsp->ifname, val16, rtlsp->tx_current_desc); 2000 delay(drv_usectohz(1000)); 2001 2002 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG); 2003 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x", 2004 rtlsp->ifname, val32); 2005 delay(drv_usectohz(1000)); 2006 2007 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG); 2008 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x", 2009 rtlsp->ifname, val32); 2010 delay(drv_usectohz(1000)); 2011 2012 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG); 2013 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x", 2014 rtlsp->ifname, val32); 2015 delay(drv_usectohz(1000)); 2016 2017 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG); 2018 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x", 2019 rtlsp->ifname, val32); 2020 delay(drv_usectohz(1000)); 2021 2022 cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu", 2023 rtlsp->ifname, 2024 (unsigned long long)rtlsp->stats.ipackets, 2025 (unsigned long long)rtlsp->stats.multi_rcv, 2026 (unsigned long long)rtlsp->stats.brdcst_rcv); 2027 delay(drv_usectohz(1000)); 2028 } 2029 #endif 2030