1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the 29 * Generic LAN Driver utility functions in /kernel/misc/mac 30 * 31 * This product is covered by one or more of the following patents: 32 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 33 * US6,327,625. 34 * 35 * Currently supports: 36 * RTL8139 37 */ 38 39 #include <sys/types.h> 40 #include <sys/debug.h> 41 #include <sys/errno.h> 42 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/kmem.h> 46 #include <sys/conf.h> 47 #include <sys/ddi.h> 48 #include <sys/devops.h> 49 #include <sys/ksynch.h> 50 #include <sys/stat.h> 51 #include <sys/conf.h> 52 #include <sys/modctl.h> 53 #include <sys/dlpi.h> 54 #include <sys/ethernet.h> 55 #include <sys/vlan.h> 56 #include <sys/strsun.h> 57 #include <sys/pci.h> 58 #include <sys/sunddi.h> 59 #include <sys/mii.h> 60 #include <sys/miiregs.h> 61 #include <sys/mac_provider.h> 62 #include <sys/mac_ether.h> 63 64 #include "rtls.h" 65 66 /* 67 * Declarations and Module Linkage 68 */ 69 70 /* 71 * This is the string displayed by modinfo, etc. 72 */ 73 static char rtls_ident[] = "RealTek 8139 Ethernet driver"; 74 75 #ifdef RTLS_DEBUG 76 int rtls_debug = 0; 77 #endif 78 79 /* 80 * Required system entry points 81 */ 82 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t); 83 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t); 84 static int rtls_quiesce(dev_info_t *); 85 86 /* 87 * Required driver entry points for MAC 88 */ 89 static int rtls_m_start(void *); 90 static void rtls_m_stop(void *); 91 static int rtls_m_unicst(void *, const uint8_t *); 92 static int rtls_m_multicst(void *, boolean_t, const uint8_t *); 93 static int rtls_m_promisc(void *, boolean_t); 94 static mblk_t *rtls_m_tx(void *, mblk_t *); 95 static int rtls_m_stat(void *, uint_t, uint64_t *); 96 static int rtls_m_getprop(void *, const char *, mac_prop_id_t, uint_t, 97 uint_t, void *, uint_t *); 98 static int rtls_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 99 const void *); 100 101 static uint_t rtls_intr(caddr_t); 102 103 /* 104 * MII entry points 105 */ 106 static uint16_t rtls_mii_read(void *, uint8_t, uint8_t); 107 static void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t); 108 static void rtls_mii_notify(void *, link_state_t); 109 110 /* 111 * Internal functions used by the above entry points 112 */ 113 static int rtls_chip_reset(rtls_t *, boolean_t); 114 static void rtls_chip_init(rtls_t *); 115 static void rtls_chip_stop(rtls_t *rtlsp); 116 static void rtls_chip_start(rtls_t *rtlsp); 117 static void rtls_chip_restart(rtls_t *rtlsp); 118 static void rtls_get_mac_addr(rtls_t *, uint8_t *); 119 static void rtls_set_mac_addr(rtls_t *, const uint8_t *); 120 static uint_t rtls_hash_index(const uint8_t *); 121 static boolean_t rtls_send(rtls_t *, mblk_t *); 122 static void rtls_receive(rtls_t *); 123 124 /* 125 * Buffer Management Routines 126 */ 127 static int rtls_alloc_bufs(rtls_t *); 128 static void rtls_free_bufs(rtls_t *); 129 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *, 130 uint_t, dma_area_t *); 131 static void rtls_free_dma_mem(dma_area_t *); 132 133 #ifdef RTLS_DEBUG 134 static void rtls_reg_print(rtls_t *); /* debug routine */ 135 #endif 136 137 #define RTLS_DRIVER_NAME "rtls" 138 139 /* 140 * Used for buffers allocated by ddi_dma_mem_alloc() 141 */ 142 static ddi_dma_attr_t dma_attr = { 143 DMA_ATTR_V0, /* dma_attr version */ 144 0, /* dma_attr_addr_lo */ 145 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 146 0x7FFFFFFF, /* dma_attr_count_max */ 147 4, /* dma_attr_align */ 148 0x3F, /* dma_attr_burstsizes */ 149 1, /* dma_attr_minxfer */ 150 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 151 (uint_t)0xFFFFFFFF, /* dma_attr_seg */ 152 1, /* dma_attr_sgllen */ 153 1, /* dma_attr_granular */ 154 0, /* dma_attr_flags */ 155 }; 156 157 /* 158 * PIO access attributes for registers 159 */ 160 static ddi_device_acc_attr_t rtls_reg_accattr = { 161 DDI_DEVICE_ATTR_V0, 162 DDI_STRUCTURE_LE_ACC, 163 DDI_STRICTORDER_ACC 164 }; 165 166 /* 167 * DMA access attributes for data 168 */ 169 static ddi_device_acc_attr_t rtls_buf_accattr = { 170 DDI_DEVICE_ATTR_V0, 171 DDI_NEVERSWAP_ACC, 172 DDI_STRICTORDER_ACC 173 }; 174 175 uchar_t rtls_broadcastaddr[] = { 176 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 177 }; 178 179 static mac_callbacks_t rtls_m_callbacks = { 180 MC_SETPROP | MC_GETPROP, 181 rtls_m_stat, 182 rtls_m_start, 183 rtls_m_stop, 184 rtls_m_promisc, 185 rtls_m_multicst, 186 rtls_m_unicst, 187 rtls_m_tx, 188 NULL, /* mc_ioctl */ 189 NULL, /* mc_getcapab */ 190 NULL, /* mc_open */ 191 NULL, /* mc_close */ 192 rtls_m_setprop, 193 rtls_m_getprop, 194 }; 195 196 static mii_ops_t rtls_mii_ops = { 197 MII_OPS_VERSION, 198 rtls_mii_read, 199 rtls_mii_write, 200 rtls_mii_notify, /* notify */ 201 NULL, /* reset */ 202 }; 203 204 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach, 205 nodev, NULL, D_MP, NULL, rtls_quiesce); 206 207 /* 208 * Standard module linkage initialization for a MAC driver 209 */ 210 static struct modldrv rtls_modldrv = { 211 &mod_driverops, /* type of module. This one is a driver */ 212 rtls_ident, /* short description */ 213 &rtls_dev_ops /* driver specific ops */ 214 }; 215 216 static struct modlinkage modlinkage = { 217 MODREV_1, { (void *)&rtls_modldrv, NULL } 218 }; 219 220 /* 221 * ========== RealTek chip register access Routines ========== 222 */ 223 static uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg); 224 #pragma inline(rtls_reg_get8) 225 static uint8_t 226 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg) 227 { 228 uint8_t *addr; 229 230 addr = REG8(rtlsp->io_reg, reg); 231 return (ddi_get8(rtlsp->io_handle, addr)); 232 } 233 234 static uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg); 235 #pragma inline(rtls_reg_get16) 236 static uint16_t 237 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg) 238 { 239 uint16_t *addr; 240 241 addr = REG16(rtlsp->io_reg, reg); 242 return (ddi_get16(rtlsp->io_handle, addr)); 243 } 244 245 static uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg); 246 #pragma inline(rtls_reg_get32) 247 static uint32_t 248 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg) 249 { 250 uint32_t *addr; 251 252 addr = REG32(rtlsp->io_reg, reg); 253 return (ddi_get32(rtlsp->io_handle, addr)); 254 } 255 256 static void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value); 257 #pragma inline(rtls_reg_set8) 258 static void 259 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value) 260 { 261 uint8_t *addr; 262 263 addr = REG8(rtlsp->io_reg, reg); 264 ddi_put8(rtlsp->io_handle, addr, value); 265 } 266 267 static void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value); 268 #pragma inline(rtls_reg_set16) 269 static void 270 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value) 271 { 272 uint16_t *addr; 273 274 addr = REG16(rtlsp->io_reg, reg); 275 ddi_put16(rtlsp->io_handle, addr, value); 276 } 277 278 static void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value); 279 #pragma inline(rtls_reg_set32) 280 static void 281 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value) 282 { 283 uint32_t *addr; 284 285 addr = REG32(rtlsp->io_reg, reg); 286 ddi_put32(rtlsp->io_handle, addr, value); 287 } 288 289 /* 290 * ========== Module Loading Entry Points ========== 291 */ 292 int 293 _init(void) 294 { 295 int rv; 296 297 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME); 298 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) { 299 mac_fini_ops(&rtls_dev_ops); 300 } 301 return (rv); 302 } 303 304 int 305 _fini(void) 306 { 307 int rv; 308 309 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) { 310 mac_fini_ops(&rtls_dev_ops); 311 } 312 return (rv); 313 } 314 315 int 316 _info(struct modinfo *modinfop) 317 { 318 return (mod_info(&modlinkage, modinfop)); 319 } 320 321 322 /* 323 * ========== DDI Entry Points ========== 324 */ 325 326 /* 327 * attach(9E) -- Attach a device to the system 328 * 329 * Called once for each board successfully probed. 330 */ 331 static int 332 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 333 { 334 rtls_t *rtlsp; /* Our private device info */ 335 ddi_acc_handle_t pci_handle; 336 uint16_t pci_commond; 337 uint16_t vendorid; 338 uint16_t deviceid; 339 uint32_t device; 340 mac_register_t *macp; 341 int err; 342 343 switch (cmd) { 344 case DDI_ATTACH: 345 break; 346 case DDI_RESUME: 347 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 348 return (DDI_FAILURE); 349 } 350 mutex_enter(&rtlsp->rtls_io_lock); 351 mutex_enter(&rtlsp->rtls_rx_lock); 352 mutex_enter(&rtlsp->rtls_tx_lock); 353 /* 354 * Turn on Master Enable (DMA) and IO Enable bits. 355 * Enable PCI Memory Space accesses 356 * Disable Memory Write/Invalidate 357 */ 358 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 359 mutex_exit(&rtlsp->rtls_tx_lock); 360 mutex_exit(&rtlsp->rtls_rx_lock); 361 mutex_exit(&rtlsp->rtls_io_lock); 362 return (DDI_FAILURE); 363 } 364 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 365 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 366 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 367 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 368 pci_config_teardown(&pci_handle); 369 370 rtls_chip_restart(rtlsp); 371 rtlsp->chip_error = B_FALSE; 372 rtlsp->tx_retry = 0; 373 rtlsp->rtls_suspended = B_FALSE; 374 mutex_exit(&rtlsp->rtls_tx_lock); 375 mutex_exit(&rtlsp->rtls_rx_lock); 376 mutex_exit(&rtlsp->rtls_io_lock); 377 378 mii_resume(rtlsp->mii); 379 380 mac_tx_update(rtlsp->mh); 381 return (DDI_SUCCESS); 382 default: 383 return (DDI_FAILURE); 384 } 385 386 /* 387 * we don't support high level interrupts in the driver 388 */ 389 if (ddi_intr_hilevel(devinfo, 0) != 0) { 390 cmn_err(CE_WARN, "unsupported high level interrupt"); 391 return (DDI_FAILURE); 392 } 393 394 /* 395 * Get handle to access pci configuration space 396 */ 397 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 398 cmn_err(CE_WARN, "pci_config_setup fail."); 399 return (DDI_FAILURE); 400 } 401 402 /* 403 * Make sure we support this particular vendor/device 404 */ 405 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID); 406 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID); 407 device = vendorid; 408 device = (device << 16) | deviceid; /* combine two id together */ 409 410 /* 411 * See if we support this device 412 * We do not return for wrong device id. It's user risk. 413 */ 414 switch (device) { 415 default: 416 cmn_err(CE_WARN, 417 "RTLS doesn't support this device: " 418 "vendorID = 0x%x, deviceID = 0x%x", 419 vendorid, deviceid); 420 break; 421 case RTLS_SUPPORT_DEVICE_1: 422 case RTLS_SUPPORT_DEVICE_2: 423 case RTLS_SUPPORT_DEVICE_3: 424 case RTLS_SUPPORT_DEVICE_4: 425 break; 426 } 427 428 /* 429 * Turn on Master Enable (DMA) and IO Enable bits. 430 * Enable PCI Memory Space accesses 431 * Disable Memory Write/Invalidate 432 */ 433 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 434 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 435 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 436 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 437 438 /* 439 * Free handle to access pci configuration space 440 */ 441 pci_config_teardown(&pci_handle); 442 443 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP); 444 445 ddi_set_driver_private(devinfo, rtlsp); 446 rtlsp->devinfo = devinfo; 447 rtlsp->instance = ddi_get_instance(devinfo); 448 449 /* 450 * Map operating register 451 */ 452 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg, 453 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle); 454 if (err != DDI_SUCCESS) { 455 kmem_free((caddr_t)rtlsp, sizeof (rtls_t)); 456 cmn_err(CE_WARN, "ddi_regs_map_setup fail."); 457 return (DDI_FAILURE); 458 } 459 460 /* 461 * Allocate the TX and RX descriptors/buffers 462 */ 463 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) { 464 cmn_err(CE_WARN, "DMA buffer allocation fail."); 465 goto fail; 466 } 467 468 /* 469 * Reset the chip 470 */ 471 err = rtls_chip_reset(rtlsp, B_FALSE); 472 if (err != DDI_SUCCESS) 473 goto fail; 474 475 /* 476 * Init rtls_t structure 477 */ 478 rtls_get_mac_addr(rtlsp, rtlsp->netaddr); 479 480 /* 481 * Add the interrupt handler 482 * 483 * This will prevent receiving interrupts before device is ready, as 484 * we are initializing device after setting the interrupts. So we 485 * will not get our interrupt handler invoked by OS while our device 486 * is still coming up or timer routines will not start till we are 487 * all set to process... 488 */ 489 490 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr, 491 (caddr_t)rtlsp) != DDI_SUCCESS) { 492 cmn_err(CE_WARN, "ddi_add_intr fail."); 493 goto late_fail; 494 } 495 496 if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) { 497 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 498 goto late_fail; 499 } 500 /* 501 * Note: Some models of 8139 can support pause, but we have 502 * not implemented support for it at this time. This might be 503 * an interesting feature to add later. 504 */ 505 mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE); 506 507 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 508 cmn_err(CE_WARN, "mac_alloc fail."); 509 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 510 goto late_fail; 511 } 512 513 /* 514 * Init mutex 515 */ 516 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 517 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 518 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 519 520 /* 521 * Initialize pointers to device specific functions which will be 522 * used by the generic layer. 523 */ 524 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 525 macp->m_driver = rtlsp; 526 macp->m_dip = devinfo; 527 macp->m_src_addr = rtlsp->netaddr; 528 macp->m_callbacks = &rtls_m_callbacks; 529 macp->m_min_sdu = 0; 530 macp->m_max_sdu = ETHERMTU; 531 macp->m_margin = VLAN_TAGSZ; 532 533 if (mac_register(macp, &rtlsp->mh) != 0) { 534 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 535 mutex_destroy(&rtlsp->rtls_io_lock); 536 mutex_destroy(&rtlsp->rtls_tx_lock); 537 mutex_destroy(&rtlsp->rtls_rx_lock); 538 goto late_fail; 539 } 540 541 mac_free(macp); 542 543 return (DDI_SUCCESS); 544 545 late_fail: 546 if (macp) 547 mac_free(macp); 548 if (rtlsp->mii) 549 mii_free(rtlsp->mii); 550 551 fail: 552 ddi_regs_map_free(&rtlsp->io_handle); 553 rtls_free_bufs(rtlsp); 554 kmem_free(rtlsp, sizeof (rtls_t)); 555 556 return (DDI_FAILURE); 557 } 558 559 /* 560 * detach(9E) -- Detach a device from the system 561 */ 562 static int 563 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 564 { 565 rtls_t *rtlsp; /* our private device info */ 566 567 /* 568 * Get the driver private structure 569 */ 570 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 571 return (DDI_FAILURE); 572 } 573 574 switch (cmd) { 575 case DDI_DETACH: 576 break; 577 578 case DDI_SUSPEND: 579 mii_suspend(rtlsp->mii); 580 581 mutex_enter(&rtlsp->rtls_io_lock); 582 mutex_enter(&rtlsp->rtls_rx_lock); 583 mutex_enter(&rtlsp->rtls_tx_lock); 584 585 rtlsp->rtls_suspended = B_TRUE; 586 rtls_chip_stop(rtlsp); 587 588 mutex_exit(&rtlsp->rtls_tx_lock); 589 mutex_exit(&rtlsp->rtls_rx_lock); 590 mutex_exit(&rtlsp->rtls_io_lock); 591 return (DDI_SUCCESS); 592 593 default: 594 return (DDI_FAILURE); 595 } 596 597 if (mac_unregister(rtlsp->mh) != 0) { 598 /* device busy */ 599 return (DDI_FAILURE); 600 } 601 602 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 603 604 mii_free(rtlsp->mii); 605 606 mutex_destroy(&rtlsp->rtls_io_lock); 607 mutex_destroy(&rtlsp->rtls_tx_lock); 608 mutex_destroy(&rtlsp->rtls_rx_lock); 609 610 ddi_regs_map_free(&rtlsp->io_handle); 611 rtls_free_bufs(rtlsp); 612 kmem_free(rtlsp, sizeof (rtls_t)); 613 614 return (DDI_SUCCESS); 615 } 616 617 /* 618 * quiesce(9E) entry point. 619 * 620 * This function is called when the system is single-threaded at high 621 * PIL with preemption disabled. Therefore, this function must not be 622 * blocked. 623 * 624 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 625 * DDI_FAILURE indicates an error condition and should almost never happen. 626 */ 627 static int 628 rtls_quiesce(dev_info_t *devinfo) 629 { 630 rtls_t *rtlsp; /* our private device info */ 631 632 /* 633 * Get the driver private structure 634 */ 635 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 636 return (DDI_FAILURE); 637 } 638 return (rtls_chip_reset(rtlsp, B_TRUE)); 639 } 640 641 /* 642 * ========== MAC Entry Points ========== 643 */ 644 645 /* 646 * rtls_m_start() -- start the board receiving and allow transmits 647 */ 648 static int 649 rtls_m_start(void *arg) 650 { 651 rtls_t *rtlsp = (rtls_t *)arg; 652 653 mutex_enter(&rtlsp->rtls_io_lock); 654 mutex_enter(&rtlsp->rtls_rx_lock); 655 mutex_enter(&rtlsp->rtls_tx_lock); 656 657 if (!rtlsp->rtls_suspended) 658 rtls_chip_restart(rtlsp); 659 660 rtlsp->rtls_running = B_TRUE; 661 662 mutex_exit(&rtlsp->rtls_tx_lock); 663 mutex_exit(&rtlsp->rtls_rx_lock); 664 mutex_exit(&rtlsp->rtls_io_lock); 665 666 drv_usecwait(100); 667 668 mii_start(rtlsp->mii); 669 670 return (0); 671 } 672 673 /* 674 * rtls_m_stop() -- stop board receiving and transmits 675 */ 676 static void 677 rtls_m_stop(void *arg) 678 { 679 rtls_t *rtlsp = (rtls_t *)arg; 680 681 mii_stop(rtlsp->mii); 682 683 mutex_enter(&rtlsp->rtls_io_lock); 684 685 if (!rtlsp->rtls_suspended) 686 rtls_chip_stop(rtlsp); 687 rtlsp->rtls_running = B_FALSE; 688 689 mutex_exit(&rtlsp->rtls_io_lock); 690 } 691 692 /* 693 * rtls_m_unicst() -- set the physical network address 694 * on the board 695 */ 696 static int 697 rtls_m_unicst(void *arg, const uint8_t *macaddr) 698 { 699 rtls_t *rtlsp = arg; 700 701 mutex_enter(&rtlsp->rtls_io_lock); 702 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL); 703 if (!rtlsp->rtls_suspended) 704 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 705 mutex_exit(&rtlsp->rtls_io_lock); 706 return (0); 707 } 708 709 /* 710 * rtls_m_multicst() -- set(enable) or disable a multicast address 711 * 712 * Program the hardware to enable/disable the multicast address in "mcast". 713 */ 714 static int 715 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast) 716 { 717 rtls_t *rtlsp = (rtls_t *)arg; 718 uint_t index; 719 uint32_t *hashp; 720 721 mutex_enter(&rtlsp->rtls_io_lock); 722 hashp = rtlsp->multi_hash; 723 index = rtls_hash_index(mcast); 724 /* index value is between 0 and 63 */ 725 726 if (enable) { 727 if (rtlsp->multicast_cnt[index]++) { 728 mutex_exit(&rtlsp->rtls_io_lock); 729 return (0); 730 } 731 hashp[index/32] |= 1<< (index % 32); 732 } else { 733 if (--rtlsp->multicast_cnt[index]) { 734 mutex_exit(&rtlsp->rtls_io_lock); 735 return (0); 736 } 737 hashp[index/32] &= ~(1<< (index % 32)); 738 } 739 740 /* 741 * Set multicast register 742 */ 743 if (!rtlsp->rtls_suspended) { 744 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]); 745 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]); 746 } 747 748 mutex_exit(&rtlsp->rtls_io_lock); 749 750 return (0); 751 } 752 753 /* 754 * rtls_hash_index() -- a hashing function used for setting the 755 * node address or a multicast address 756 */ 757 static uint_t 758 rtls_hash_index(const uint8_t *address) 759 { 760 uint32_t crc = (ulong_t)RTLS_HASH_CRC; 761 uint32_t const POLY = RTLS_HASH_POLY; 762 uint32_t msb; 763 int bytes; 764 uchar_t currentbyte; 765 uint_t index; 766 int bit; 767 768 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 769 currentbyte = address[bytes]; 770 for (bit = 0; bit < 8; bit++) { 771 msb = crc >> 31; 772 crc <<= 1; 773 if (msb ^ (currentbyte & 1)) { 774 crc ^= POLY; 775 crc |= 0x00000001; 776 } 777 currentbyte >>= 1; 778 } 779 } 780 781 index = crc >> 26; 782 783 return (index); 784 } 785 786 /* 787 * rtls_m_promisc() -- set or reset promiscuous mode on the board 788 */ 789 static int 790 rtls_m_promisc(void *arg, boolean_t on) 791 { 792 rtls_t *rtlsp = arg; 793 794 mutex_enter(&rtlsp->rtls_io_lock); 795 796 rtlsp->promisc = on; 797 if (!rtlsp->rtls_suspended) { 798 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 799 if (on) { 800 val32 |= RX_ACCEPT_ALL_PACKET; 801 } else { 802 val32 &= ~RX_ACCEPT_ALL_PACKET; 803 } 804 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32); 805 } 806 mutex_exit(&rtlsp->rtls_io_lock); 807 808 return (0); 809 } 810 811 /* 812 * rtls_m_stat() -- retrieve statistic 813 * 814 * MAC calls this routine just before it reads the driver's statistics 815 * structure. If your board maintains statistics, this is the time to 816 * read them in and update the values in the structure. If the driver 817 * maintains statistics continuously, this routine need do nothing. 818 */ 819 static int 820 rtls_m_stat(void *arg, uint_t stat, uint64_t *val) 821 { 822 rtls_t *rtlsp = arg; 823 824 if (mii_m_getstat(rtlsp->mii, stat, val) == 0) { 825 return (0); 826 } 827 828 switch (stat) { 829 case MAC_STAT_IPACKETS: 830 *val = rtlsp->stats.ipackets; 831 break; 832 case MAC_STAT_RBYTES: 833 *val = rtlsp->stats.rbytes; 834 break; 835 case MAC_STAT_OPACKETS: 836 *val = rtlsp->stats.opackets; 837 break; 838 case MAC_STAT_OBYTES: 839 *val = rtlsp->stats.obytes; 840 break; 841 case MAC_STAT_IERRORS: 842 *val = rtlsp->stats.rcv_err; 843 break; 844 case MAC_STAT_OERRORS: 845 *val = rtlsp->stats.xmt_err; 846 break; 847 case MAC_STAT_MULTIRCV: 848 *val = rtlsp->stats.multi_rcv; 849 break; 850 case MAC_STAT_BRDCSTRCV: 851 *val = rtlsp->stats.brdcst_rcv; 852 break; 853 case MAC_STAT_MULTIXMT: 854 *val = rtlsp->stats.multi_xmt; 855 break; 856 case MAC_STAT_BRDCSTXMT: 857 *val = rtlsp->stats.brdcst_xmt; 858 break; 859 case MAC_STAT_UNDERFLOWS: 860 *val = rtlsp->stats.underflow; 861 break; 862 case MAC_STAT_OVERFLOWS: 863 *val = rtlsp->stats.overflow; 864 break; 865 case MAC_STAT_NORCVBUF: 866 *val = rtlsp->stats.no_rcvbuf; 867 break; 868 case MAC_STAT_COLLISIONS: 869 *val = rtlsp->stats.collisions; 870 break; 871 case ETHER_STAT_FCS_ERRORS: 872 *val = rtlsp->stats.crc_err; 873 break; 874 case ETHER_STAT_ALIGN_ERRORS: 875 *val = rtlsp->stats.frame_err; 876 break; 877 case ETHER_STAT_DEFER_XMTS: 878 *val = rtlsp->stats.defer; 879 break; 880 case ETHER_STAT_TX_LATE_COLLISIONS: 881 *val = rtlsp->stats.xmt_latecoll; 882 break; 883 case ETHER_STAT_TOOLONG_ERRORS: 884 *val = rtlsp->stats.too_long; 885 break; 886 case ETHER_STAT_TOOSHORT_ERRORS: 887 *val = rtlsp->stats.in_short; 888 break; 889 case ETHER_STAT_CARRIER_ERRORS: 890 *val = rtlsp->stats.no_carrier; 891 break; 892 case ETHER_STAT_FIRST_COLLISIONS: 893 *val = rtlsp->stats.firstcol; 894 break; 895 case ETHER_STAT_MULTI_COLLISIONS: 896 *val = rtlsp->stats.multicol; 897 break; 898 default: 899 return (ENOTSUP); 900 } 901 902 /* 903 * RTL8139 don't support MII statistics, 904 * these values are maintained by the driver software. 905 */ 906 907 #ifdef RTLS_DEBUG 908 if (rtls_debug & RTLS_TRACE) 909 rtls_reg_print(rtlsp); 910 #endif 911 912 return (0); 913 } 914 915 int 916 rtls_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t flags, 917 uint_t sz, void *val, uint_t *perm) 918 { 919 rtls_t *rtlsp = arg; 920 921 return (mii_m_getprop(rtlsp->mii, name, num, flags, sz, val, perm)); 922 } 923 924 int 925 rtls_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 926 const void *val) 927 { 928 rtls_t *rtlsp = arg; 929 930 return (mii_m_setprop(rtlsp->mii, name, num, sz, val)); 931 } 932 933 /* 934 * rtls_send() -- send a packet 935 * 936 * Called when a packet is ready to be transmitted. A pointer to an 937 * M_DATA message that contains the packet is passed to this routine. 938 * The complete LLC header is contained in the message's first message 939 * block, and the remainder of the packet is contained within 940 * additional M_DATA message blocks linked to the first message block. 941 * 942 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if 943 * if the packet is being deferred and should be tried again later. 944 */ 945 946 static boolean_t 947 rtls_send(rtls_t *rtlsp, mblk_t *mp) 948 { 949 int totlen; 950 int ncc; 951 uint16_t cur_desc; 952 uint32_t tx_status; 953 954 ASSERT(mp != NULL); 955 ASSERT(rtlsp->rtls_running); 956 957 mutex_enter(&rtlsp->rtls_tx_lock); 958 959 if (rtlsp->rtls_suspended) { 960 mutex_exit(&rtlsp->rtls_tx_lock); 961 return (B_FALSE); 962 } 963 964 /* 965 * If chip error ... 966 */ 967 if (rtlsp->chip_error) { 968 #ifdef RTLS_DEBUG 969 cmn_err(CE_WARN, 970 "%s: send fail--CHIP ERROR!", 971 rtlsp->ifname); 972 #endif 973 mutex_exit(&rtlsp->rtls_tx_lock); 974 freemsg(mp); 975 return (B_TRUE); 976 } 977 978 /* 979 * If chip link down ... Note that experimentation shows that 980 * the device seems not to care about whether or not we have 981 * this check, but if we don't add the check here, it might 982 * not be properly reported as a carrier error. 983 */ 984 if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) { 985 #ifdef RTLS_DEBUG 986 cmn_err(CE_WARN, 987 "%s: send fail--LINK DOWN!", 988 rtlsp->ifname); 989 #endif 990 rtlsp->stats.no_carrier++; 991 mutex_exit(&rtlsp->rtls_tx_lock); 992 freemsg(mp); 993 return (B_TRUE); 994 } 995 996 /* 997 * Current transmit descriptor 998 */ 999 cur_desc = rtlsp->tx_current_desc; 1000 ASSERT(cur_desc < RTLS_MAX_TX_DESC); 1001 1002 /* 1003 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop 1004 * of transmit,we needn't judge transmit status. 1005 */ 1006 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) { 1007 rtlsp->tx_first_loop++; 1008 goto tx_ready; 1009 } 1010 1011 /* 1012 * If it's not the first tx loop, we need judge whether the chip is 1013 * busy or not. Otherwise, we have to reschedule send and wait... 1014 */ 1015 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc); 1016 1017 /* 1018 * H/W doesn't complete packet transmit 1019 */ 1020 if (!(tx_status & TX_COMPLETE_FLAG)) { 1021 #ifdef RTLS_DEBUG 1022 if (rtls_debug & RTLS_SEND) { 1023 cmn_err(CE_NOTE, 1024 "%s: rtls_send: need_sched", rtlsp->ifname); 1025 } 1026 #endif 1027 /* 1028 * Through test, we find RTL8139 tx status might be 1029 * not-completing all along. We have to reset chip 1030 * to make RTL8139 tansmit re-work. 1031 */ 1032 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) { 1033 1034 /* 1035 * Wait transmit h/w more time... 1036 */ 1037 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */ 1038 1039 /* 1040 * Judge tx status again, if it remains not-completing, 1041 * we can confirm RTL8139 is in chip error state 1042 * and must reset it. 1043 */ 1044 tx_status = rtls_reg_get32(rtlsp, 1045 TX_STATUS_DESC0_REG + 4 * cur_desc); 1046 if (!(tx_status & TX_COMPLETE_FLAG)) { 1047 #ifdef RTLS_DEBUG 1048 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x", 1049 rtlsp->ifname, tx_status); 1050 #endif 1051 rtlsp->tx_retry = 0; 1052 rtlsp->chip_error = B_TRUE; 1053 rtlsp->stats.xmt_err++; 1054 rtlsp->stats.mac_xmt_err++; 1055 mutex_exit(&rtlsp->rtls_tx_lock); 1056 freemsg(mp); 1057 return (B_TRUE); 1058 } 1059 } else { 1060 rtlsp->stats.defer++; 1061 rtlsp->need_sched = B_TRUE; 1062 mutex_exit(&rtlsp->rtls_tx_lock); 1063 return (B_FALSE); 1064 } 1065 } 1066 1067 /* 1068 * Transmit error? 1069 */ 1070 if (tx_status & TX_ERR_FLAG) { 1071 #ifdef RTLS_DEBUG 1072 if (rtls_debug & RTLS_SEND) { 1073 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x", 1074 rtlsp->ifname, tx_status); 1075 } 1076 #endif 1077 rtlsp->stats.xmt_err++; 1078 if (tx_status & TX_STATUS_TX_UNDERRUN) 1079 rtlsp->stats.underflow++; 1080 if (tx_status & TX_STATUS_CS_LOST) 1081 rtlsp->stats.no_carrier++; 1082 if (tx_status & TX_STATUS_OWC) 1083 rtlsp->stats.xmt_latecoll++; 1084 } 1085 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT); 1086 if (ncc != 0) { 1087 rtlsp->stats.collisions += ncc; 1088 rtlsp->stats.firstcol++; 1089 rtlsp->stats.multicol += ncc - 1; 1090 } 1091 1092 tx_ready: 1093 /* 1094 * Initialize variable 1095 */ 1096 rtlsp->tx_retry = 0; 1097 totlen = 0; 1098 1099 /* 1100 * Copy packet to tx descriptor buffer 1101 */ 1102 totlen = msgsize(mp); 1103 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */ 1104 cmn_err(CE_NOTE, 1105 "%s: rtls_send: try to send large %d packet", 1106 rtlsp->ifname, totlen); 1107 rtlsp->stats.mac_xmt_err++; 1108 rtlsp->stats.xmt_err++; 1109 freemsg(mp); 1110 mutex_exit(&rtlsp->rtls_tx_lock); 1111 return (B_TRUE); 1112 } 1113 1114 /* this will free the mblk */ 1115 mcopymsg(mp, rtlsp->tx_buf[cur_desc]); 1116 1117 /* update stats */ 1118 if (*rtlsp->tx_buf[cur_desc] & 0x1) { 1119 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc]; 1120 if ((ptr[0] == 0xffff) && 1121 (ptr[1] == 0xffff) && 1122 (ptr[2] == 0xffff)) { 1123 rtlsp->stats.brdcst_xmt++; 1124 } else { 1125 rtlsp->stats.multi_xmt++; 1126 } 1127 } 1128 rtlsp->stats.opackets++; 1129 rtlsp->stats.obytes += totlen; 1130 1131 if (totlen < ETHERMIN) { 1132 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen); 1133 totlen = ETHERMIN; 1134 } 1135 1136 /* make sure caches are flushed */ 1137 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen, 1138 DDI_DMA_SYNC_FORDEV); 1139 1140 /* 1141 * Start transmit 1142 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes 1143 * to avoid tx underrun. 1144 */ 1145 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc, 1146 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT)); 1147 1148 /* 1149 * Update the value of current tx descriptor 1150 */ 1151 cur_desc++; 1152 cur_desc %= RTLS_MAX_TX_DESC; 1153 rtlsp->tx_current_desc = cur_desc; 1154 1155 mutex_exit(&rtlsp->rtls_tx_lock); 1156 1157 return (B_TRUE); 1158 } 1159 1160 /* 1161 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next. 1162 */ 1163 static mblk_t * 1164 rtls_m_tx(void *arg, mblk_t *mp) 1165 { 1166 rtls_t *rtlsp = arg; 1167 mblk_t *next; 1168 1169 while (mp != NULL) { 1170 next = mp->b_next; 1171 mp->b_next = NULL; 1172 if (!rtls_send(rtlsp, mp)) { 1173 mp->b_next = next; 1174 break; 1175 } 1176 mp = next; 1177 } 1178 return (mp); 1179 } 1180 1181 /* 1182 * rtls_receive() -- receive packets 1183 * 1184 * Called when receive interrupts detected 1185 */ 1186 static void 1187 rtls_receive(rtls_t *rtlsp) 1188 { 1189 mblk_t *head = NULL; 1190 mblk_t **mpp; 1191 mblk_t *mp; 1192 uint16_t rx_status; 1193 uint16_t packet_len; 1194 int wrap_size; 1195 uint32_t cur_rx; 1196 uint8_t *rx_ptr; 1197 1198 mpp = &head; 1199 1200 mutex_enter(&rtlsp->rtls_rx_lock); 1201 1202 if (rtlsp->rtls_suspended) { 1203 mutex_exit(&rtlsp->rtls_rx_lock); 1204 return; 1205 } 1206 1207 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG) 1208 & RT_COMMAND_BUFF_EMPTY) == 0) { 1209 1210 /* 1211 * Chip error state 1212 */ 1213 if (rtlsp->chip_error) { 1214 #ifdef RTLS_DEBUG 1215 cmn_err(CE_WARN, 1216 "%s: receive fail--CHIP ERROR!", 1217 rtlsp->ifname); 1218 #endif 1219 break; 1220 } 1221 1222 cur_rx = rtlsp->cur_rx; 1223 rx_ptr = rtlsp->rx_ring + cur_rx; 1224 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]); 1225 rx_status = rx_ptr[0]; 1226 1227 /* 1228 * DMA still in progress 1229 */ 1230 if (packet_len == RX_STATUS_DMA_BUSY) { 1231 cmn_err(CE_NOTE, "%s: Rx DMA still in progress", 1232 rtlsp->ifname); 1233 break; 1234 } 1235 1236 /* 1237 * Check receive status 1238 */ 1239 if ((rx_status & RX_ERR_FLAGS) || 1240 (!(rx_status & RX_HEADER_STATUS_ROK)) || 1241 (packet_len < (ETHERMIN + ETHERFCSL)) || 1242 (packet_len > (ETHERMAX + ETHERFCSL + 4))) { 1243 #ifdef RTLS_DEBUG 1244 cmn_err(CE_NOTE, 1245 "%s: receive error, status = 0x%x, length = %d", 1246 rtlsp->ifname, rx_status, packet_len); 1247 #endif 1248 /* 1249 * Rx error statistics 1250 */ 1251 if ((rx_status & RX_HEADER_STATUS_RUNT) || 1252 (packet_len < (ETHERMIN + ETHERFCSL))) 1253 rtlsp->stats.in_short++; 1254 else if (packet_len > (ETHERMAX + ETHERFCSL + 4)) 1255 rtlsp->stats.too_long++; 1256 else if (rx_status & RX_HEADER_STATUS_CRC) 1257 rtlsp->stats.crc_err++; 1258 else if (rx_status & RX_HEADER_STATUS_FAE) 1259 rtlsp->stats.frame_err++; 1260 1261 /* 1262 * Set chip_error flag to reset chip: 1263 * (suggested in RealTek programming guide.) 1264 */ 1265 rtlsp->chip_error = B_TRUE; 1266 mutex_exit(&rtlsp->rtls_rx_lock); 1267 return; 1268 } 1269 1270 /* 1271 * We need not up-send ETHERFCSL bytes of receive packet 1272 */ 1273 packet_len -= ETHERFCSL; 1274 1275 /* 1276 * Allocate buffer to receive this good packet 1277 */ 1278 mp = allocb(packet_len, 0); 1279 1280 /* 1281 * Copy the data found into the new cluster, we have (+4) 1282 * to get us past the packet head data that the rtl chip 1283 * places at the start of the message 1284 */ 1285 if ((cur_rx + packet_len + RX_HEADER_SIZE) 1286 > RTLS_RX_BUF_RING) { 1287 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE 1288 - RTLS_RX_BUF_RING; 1289 #ifdef RTLS_DEBUG 1290 if (rtls_debug & RTLS_RECV) { 1291 cmn_err(CE_NOTE, 1292 "%s: Rx: packet_len = %d, wrap_size = %d", 1293 rtlsp->ifname, packet_len, wrap_size); 1294 } 1295 #endif 1296 1297 if (mp != NULL) { 1298 /* Flush caches */ 1299 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1300 cur_rx + RX_HEADER_SIZE, 1301 packet_len - wrap_size, 1302 DDI_DMA_SYNC_FORKERNEL); 1303 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1304 0, wrap_size, 1305 DDI_DMA_SYNC_FORKERNEL); 1306 1307 /* 1308 * Copy in first section of message as stored 1309 * at the end of the ring buffer 1310 */ 1311 bcopy(rx_ptr + RX_HEADER_SIZE, 1312 mp->b_wptr, packet_len - wrap_size); 1313 mp->b_wptr += packet_len - wrap_size; 1314 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size); 1315 mp->b_wptr += wrap_size; 1316 *mpp = mp; 1317 mpp = &mp->b_next; 1318 1319 rtlsp->stats.ipackets++; 1320 if (rx_status & RX_HEADER_STATUS_BCAST) 1321 rtlsp->stats.brdcst_rcv++; 1322 if (rx_status & RX_HEADER_STATUS_MULTI) 1323 rtlsp->stats.multi_rcv++; 1324 rtlsp->stats.rbytes += packet_len; 1325 } else { 1326 rtlsp->stats.no_rcvbuf++; 1327 } 1328 1329 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL); 1330 /* 4-byte aligned */ 1331 } else { 1332 1333 if (mp != NULL) { 1334 /* Flush caches */ 1335 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1336 cur_rx + RX_HEADER_SIZE, packet_len, 1337 DDI_DMA_SYNC_FORKERNEL); 1338 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr, 1339 packet_len); 1340 mp->b_wptr += packet_len; 1341 *mpp = mp; 1342 mpp = &mp->b_next; 1343 1344 rtlsp->stats.ipackets++; 1345 if (rx_status & RX_HEADER_STATUS_BCAST) 1346 rtlsp->stats.brdcst_rcv++; 1347 if (rx_status & RX_HEADER_STATUS_MULTI) 1348 rtlsp->stats.multi_rcv++; 1349 rtlsp->stats.rbytes += packet_len; 1350 } else { 1351 rtlsp->stats.no_rcvbuf++; 1352 } 1353 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL; 1354 1355 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx); 1356 /* 4-byte aligned */ 1357 } 1358 1359 /* 1360 * Update rx buffer ring read pointer: 1361 * give us a little leeway to ensure no overflow 1362 */ 1363 rtlsp->cur_rx = cur_rx; 1364 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, 1365 cur_rx - READ_ADDR_GAP); 1366 } 1367 mutex_exit(&rtlsp->rtls_rx_lock); 1368 1369 /* 1370 * Upsend packet 1371 */ 1372 if (head) { 1373 mac_rx(rtlsp->mh, NULL, head); 1374 } 1375 } 1376 1377 /* 1378 * rtls_intr() -- interrupt from board to inform us that a receive or 1379 * link change. 1380 */ 1381 static uint_t 1382 rtls_intr(caddr_t arg) 1383 { 1384 rtls_t *rtlsp = (void *)arg; 1385 uint32_t int_status; 1386 uint32_t val32; 1387 boolean_t resched = B_FALSE; 1388 1389 mutex_enter(&rtlsp->rtls_io_lock); 1390 if (rtlsp->rtls_suspended) { 1391 mutex_exit(&rtlsp->rtls_io_lock); 1392 return (DDI_INTR_UNCLAIMED); 1393 } 1394 1395 /* 1396 * Was this interrupt caused by our device... 1397 */ 1398 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1399 if (!(int_status & rtlsp->int_mask)) { 1400 mutex_exit(&rtlsp->rtls_io_lock); 1401 return (DDI_INTR_UNCLAIMED); 1402 /* indicate it wasn't our interrupt */ 1403 } 1404 1405 /* 1406 * Clear interrupt 1407 */ 1408 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status); 1409 1410 /* 1411 * If chip error, restart chip... 1412 */ 1413 if (rtlsp->chip_error) { 1414 mutex_enter(&rtlsp->rtls_rx_lock); 1415 mutex_enter(&rtlsp->rtls_tx_lock); 1416 rtls_chip_restart(rtlsp); 1417 rtlsp->chip_error = B_FALSE; 1418 rtlsp->tx_retry = 0; 1419 mutex_exit(&rtlsp->rtls_tx_lock); 1420 mutex_exit(&rtlsp->rtls_rx_lock); 1421 mutex_exit(&rtlsp->rtls_io_lock); 1422 return (DDI_INTR_CLAIMED); 1423 /* no need to hand other interrupts */ 1424 } 1425 1426 /* 1427 * Transmit error interrupt 1428 */ 1429 if (int_status & TX_ERR_INT) { 1430 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1431 val32 |= TX_CLEAR_ABORT; 1432 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32); 1433 cmn_err(CE_WARN, "%s: transmit abort!!!", rtlsp->ifname); 1434 } 1435 1436 /* 1437 * Trigger mac_tx_update 1438 */ 1439 if (rtlsp->need_sched) { 1440 rtlsp->need_sched = B_FALSE; 1441 resched = B_TRUE; 1442 } 1443 1444 mutex_exit(&rtlsp->rtls_io_lock); 1445 1446 /* 1447 * Receive interrupt 1448 */ 1449 if (int_status & RTLS_RX_INT) { 1450 if (int_status & RX_OVERFLOW_INT) { 1451 rtlsp->stats.overflow++; 1452 rtlsp->stats.rcv_err++; 1453 } 1454 rtls_receive(rtlsp); 1455 } 1456 1457 /* 1458 * Link change interrupt. 1459 */ 1460 if (int_status & LINK_CHANGE_INT) { 1461 mii_check(rtlsp->mii); 1462 } 1463 1464 if (resched) { 1465 mac_tx_update(rtlsp->mh); 1466 } 1467 1468 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1469 } 1470 1471 /* 1472 * ========== Buffer Management Routines ========== 1473 */ 1474 1475 /* 1476 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle 1477 * for accessing it 1478 */ 1479 static int 1480 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize, 1481 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p) 1482 { 1483 caddr_t vaddr; 1484 int err; 1485 1486 /* 1487 * Allocate handle 1488 */ 1489 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr, 1490 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 1491 if (err != DDI_SUCCESS) { 1492 cmn_err(CE_WARN, 1493 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d", 1494 rtlsp->ifname, err); 1495 dma_p->dma_hdl = NULL; 1496 return (DDI_FAILURE); 1497 } 1498 1499 /* 1500 * Allocate memory 1501 */ 1502 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1503 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 1504 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 1505 if (err != DDI_SUCCESS) { 1506 cmn_err(CE_WARN, 1507 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d", 1508 rtlsp->ifname, err); 1509 ddi_dma_free_handle(&dma_p->dma_hdl); 1510 dma_p->dma_hdl = NULL; 1511 dma_p->acc_hdl = NULL; 1512 return (DDI_FAILURE); 1513 } 1514 1515 /* 1516 * Bind the two together 1517 */ 1518 dma_p->mem_va = vaddr; 1519 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1520 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 1521 &dma_p->cookie, &dma_p->ncookies); 1522 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 1523 cmn_err(CE_WARN, 1524 "%s: rtls_alloc_dma_mem: " 1525 "ddi_dma_addr_bind_handle failed: %d", 1526 rtlsp->ifname, err); 1527 ddi_dma_mem_free(&dma_p->acc_hdl); 1528 ddi_dma_free_handle(&dma_p->dma_hdl); 1529 dma_p->acc_hdl = NULL; 1530 dma_p->dma_hdl = NULL; 1531 return (DDI_FAILURE); 1532 } 1533 1534 return (DDI_SUCCESS); 1535 } 1536 1537 /* 1538 * rtls_free_dma_mem() -- free one allocated area of DMAable memory 1539 */ 1540 static void 1541 rtls_free_dma_mem(dma_area_t *dma_p) 1542 { 1543 if (dma_p->dma_hdl != NULL) { 1544 if (dma_p->ncookies) { 1545 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1546 dma_p->ncookies = 0; 1547 } 1548 ddi_dma_free_handle(&dma_p->dma_hdl); 1549 dma_p->dma_hdl = NULL; 1550 } 1551 1552 if (dma_p->acc_hdl != NULL) { 1553 ddi_dma_mem_free(&dma_p->acc_hdl); 1554 dma_p->acc_hdl = NULL; 1555 } 1556 } 1557 1558 /* 1559 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance 1560 */ 1561 static int 1562 rtls_alloc_bufs(rtls_t *rtlsp) 1563 { 1564 int i; 1565 int err; 1566 1567 /* 1568 * Allocate memory & handle for Tx buffers 1569 */ 1570 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1571 err = rtls_alloc_dma_mem(rtlsp, 1572 RTLS_TX_BUF_SIZE, 1573 &rtls_buf_accattr, 1574 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1575 &rtlsp->dma_area_tx[i]); 1576 1577 if (err != DDI_SUCCESS) 1578 return (DDI_FAILURE); 1579 1580 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va; 1581 } 1582 1583 /* 1584 * Allocate memory & handle for Rx buffers 1585 */ 1586 err = rtls_alloc_dma_mem(rtlsp, 1587 RTLS_RX_BUF_SIZE, 1588 &rtls_buf_accattr, 1589 DDI_DMA_READ | DDI_DMA_STREAMING, 1590 &rtlsp->dma_area_rx); 1591 1592 if (err != DDI_SUCCESS) 1593 return (DDI_FAILURE); 1594 1595 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va; 1596 1597 return (DDI_SUCCESS); 1598 } 1599 1600 /* 1601 * rtls_free_bufs() -- free descriptors/buffers allocated for this 1602 * device instance. 1603 */ 1604 static void 1605 rtls_free_bufs(rtls_t *rtlsp) 1606 { 1607 int i; 1608 1609 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1610 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]); 1611 rtlsp->tx_buf[i] = NULL; 1612 } 1613 1614 rtls_free_dma_mem(&rtlsp->dma_area_rx); 1615 rtlsp->rx_ring = NULL; 1616 } 1617 1618 /* 1619 * ========== Chip H/W Operation Routines ========== 1620 */ 1621 1622 /* 1623 * rtls_chip_reset() -- reset chip 1624 */ 1625 static int 1626 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce) 1627 { 1628 int i; 1629 uint16_t val16; 1630 uint8_t val8; 1631 1632 /* 1633 * Chip should be in STOP state 1634 */ 1635 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1636 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1637 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1638 1639 /* 1640 * Disable interrupt 1641 */ 1642 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1643 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1644 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1645 1646 /* 1647 * Clear pended interrupt 1648 */ 1649 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1650 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1651 1652 /* 1653 * Reset chip 1654 */ 1655 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1656 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET); 1657 1658 /* 1659 * Wait for reset success 1660 */ 1661 i = 0; 1662 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) { 1663 if (++i > RTLS_RESET_WAIT_NUM) { 1664 /* 1665 * At quiesce path we can't call cmn_err(), as 1666 * it might block 1667 */ 1668 if (!quiesce) 1669 cmn_err(CE_WARN, 1670 "%s: chip reset fail.", rtlsp->ifname); 1671 return (DDI_FAILURE); 1672 } 1673 RTLS_RESET_WAIT_INTERVAL; 1674 } 1675 1676 return (DDI_SUCCESS); 1677 } 1678 1679 /* 1680 * rtls_chip_init() -- initialize the specified network board short of 1681 * actually starting the board. Call after rtls_chip_reset(). 1682 */ 1683 static void 1684 rtls_chip_init(rtls_t *rtlsp) 1685 { 1686 uint32_t val32; 1687 uint16_t val16; 1688 uint8_t val8; 1689 1690 /* 1691 * Initialize internal data structures 1692 */ 1693 rtlsp->cur_rx = 0; 1694 rtlsp->tx_current_desc = 0; 1695 rtlsp->tx_first_loop = 0; 1696 1697 /* 1698 * Set DMA physical rx/tx buffer address to register 1699 */ 1700 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG, 1701 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address); 1702 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG, 1703 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address); 1704 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG, 1705 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address); 1706 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG, 1707 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address); 1708 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG, 1709 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address); 1710 1711 /* 1712 * Start transmit/receive before set tx/rx configuration register 1713 */ 1714 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1715 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1716 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1717 1718 /* 1719 * Set transmit configuration register 1720 */ 1721 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1722 val32 &= TX_CONSIG_REG_RESERVE; 1723 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT); 1724 1725 /* 1726 * Set receive configuration register 1727 */ 1728 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1729 val32 &= RX_CONSIG_REG_RESERVE; 1730 if (rtlsp->promisc) 1731 val32 |= RX_ACCEPT_ALL_PACKET; 1732 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT); 1733 1734 /* 1735 * Set multicast register 1736 */ 1737 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]); 1738 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]); 1739 1740 /* 1741 * Set unicast address 1742 */ 1743 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 1744 1745 /* 1746 * Set current address of packet read 1747 */ 1748 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL); 1749 1750 /* 1751 * No early-rx interrupts 1752 */ 1753 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG); 1754 val16 &= ~RT_MUL_INTSEL_BITS; 1755 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16); 1756 } 1757 1758 /* 1759 * rtls_chip_start() -- start chip 1760 */ 1761 static void 1762 rtls_chip_start(rtls_t *rtlsp) 1763 { 1764 uint16_t val16; 1765 uint8_t val8; 1766 1767 /* 1768 * Start transmit/receive 1769 */ 1770 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1771 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1772 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1773 1774 /* 1775 * Enable interrupt 1776 */ 1777 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1778 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK); 1779 rtlsp->int_mask = RTLS_INT_MASK; 1780 } 1781 1782 /* 1783 * rtls_chip_restart() -- restart chip 1784 */ 1785 static void 1786 rtls_chip_restart(rtls_t *rtlsp) 1787 { 1788 (void) rtls_chip_reset(rtlsp, B_FALSE); 1789 rtls_chip_init(rtlsp); 1790 rtls_chip_start(rtlsp); 1791 } 1792 1793 /* 1794 * rtls_chip_stop() -- stop board receiving 1795 */ 1796 static void 1797 rtls_chip_stop(rtls_t *rtlsp) 1798 { 1799 uint16_t val16; 1800 uint8_t val8; 1801 1802 /* 1803 * Disable interrupt 1804 */ 1805 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1806 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1807 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1808 1809 /* 1810 * Clear pended interrupt 1811 */ 1812 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1813 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1814 1815 /* 1816 * Stop the board and disable transmit/receive 1817 */ 1818 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1819 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1820 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1821 } 1822 1823 /* 1824 * rtls_get_mac_addr() -- get the physical network address on the board 1825 */ 1826 static void 1827 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr) 1828 { 1829 uint32_t val32; 1830 1831 /* 1832 * Read first 4-byte of mac address 1833 */ 1834 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 1835 macaddr[0] = val32 & 0xff; 1836 val32 = val32 >> 8; 1837 macaddr[1] = val32 & 0xff; 1838 val32 = val32 >> 8; 1839 macaddr[2] = val32 & 0xff; 1840 val32 = val32 >> 8; 1841 macaddr[3] = val32 & 0xff; 1842 1843 /* 1844 * Read last 2-byte of mac address 1845 */ 1846 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 1847 macaddr[4] = val32 & 0xff; 1848 val32 = val32 >> 8; 1849 macaddr[5] = val32 & 0xff; 1850 } 1851 1852 static void 1853 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr) 1854 { 1855 uint32_t val32; 1856 uint8_t val8; 1857 1858 /* 1859 * Change to config register write enable mode 1860 */ 1861 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1862 val8 |= RT_93c46_MODE_CONFIG; 1863 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1864 1865 /* 1866 * Get first 4 bytes of mac address 1867 */ 1868 val32 = macaddr[3]; 1869 val32 = val32 << 8; 1870 val32 |= macaddr[2]; 1871 val32 = val32 << 8; 1872 val32 |= macaddr[1]; 1873 val32 = val32 << 8; 1874 val32 |= macaddr[0]; 1875 1876 /* 1877 * Set first 4 bytes of mac address 1878 */ 1879 rtls_reg_set32(rtlsp, ID_0_REG, val32); 1880 1881 /* 1882 * Get last 2 bytes of mac address 1883 */ 1884 val32 = macaddr[5]; 1885 val32 = val32 << 8; 1886 val32 |= macaddr[4]; 1887 1888 /* 1889 * Set last 2 bytes of mac address 1890 */ 1891 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff; 1892 rtls_reg_set32(rtlsp, ID_4_REG, val32); 1893 1894 /* 1895 * Return to normal network/host communication mode 1896 */ 1897 val8 &= ~RT_93c46_MODE_CONFIG; 1898 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1899 } 1900 1901 static uint16_t 1902 rtls_mii_read(void *arg, uint8_t phy, uint8_t reg) 1903 { 1904 rtls_t *rtlsp = arg; 1905 uint16_t val; 1906 1907 if (phy != 1) { 1908 return (0xffff); 1909 } 1910 switch (reg) { 1911 case MII_CONTROL: 1912 val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 1913 break; 1914 case MII_STATUS: 1915 val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG); 1916 break; 1917 case MII_AN_ADVERT: 1918 val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 1919 break; 1920 case MII_AN_LPABLE: 1921 val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG); 1922 break; 1923 case MII_AN_EXPANSION: 1924 val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG); 1925 break; 1926 case MII_VENDOR(0): 1927 /* 1928 * We "simulate" a vendor private register so that the 1929 * PHY layer can access it to determine detected link 1930 * speed/duplex. 1931 */ 1932 val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1933 break; 1934 case MII_PHYIDH: 1935 case MII_PHYIDL: 1936 default: 1937 val = 0; 1938 break; 1939 } 1940 return (val); 1941 } 1942 1943 void 1944 rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) 1945 { 1946 rtls_t *rtlsp = arg; 1947 uint8_t val8; 1948 1949 if (phy != 1) { 1950 return; 1951 } 1952 switch (reg) { 1953 case MII_CONTROL: 1954 /* Enable writes to all bits of BMCR */ 1955 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1956 val8 |= RT_93c46_MODE_CONFIG; 1957 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1958 /* write out the value */ 1959 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val); 1960 1961 /* Return to normal network/host communication mode */ 1962 val8 &= ~RT_93c46_MODE_CONFIG; 1963 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1964 return; 1965 1966 case MII_STATUS: 1967 rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val); 1968 break; 1969 case MII_AN_ADVERT: 1970 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val); 1971 break; 1972 case MII_AN_LPABLE: 1973 rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val); 1974 break; 1975 case MII_AN_EXPANSION: 1976 rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val); 1977 break; 1978 case MII_PHYIDH: 1979 case MII_PHYIDL: 1980 default: 1981 /* these are not writable */ 1982 break; 1983 } 1984 } 1985 1986 void 1987 rtls_mii_notify(void *arg, link_state_t link) 1988 { 1989 rtls_t *rtlsp = arg; 1990 1991 mac_link_update(rtlsp->mh, link); 1992 } 1993 1994 #ifdef RTLS_DEBUG 1995 /* 1996 * rtls_reg_print() -- print out reg value(for debug use only) 1997 */ 1998 static void 1999 rtls_reg_print(rtls_t *rtlsp) 2000 { 2001 uint8_t val8; 2002 uint16_t val16; 2003 uint32_t val32; 2004 2005 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2006 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x", 2007 rtlsp->ifname, val8); 2008 delay(drv_usectohz(1000)); 2009 2010 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 2011 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x", 2012 rtlsp->ifname, val16); 2013 delay(drv_usectohz(1000)); 2014 2015 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2016 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x", 2017 rtlsp->ifname, val16); 2018 delay(drv_usectohz(1000)); 2019 2020 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 2021 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x", 2022 rtlsp->ifname, val32); 2023 delay(drv_usectohz(1000)); 2024 2025 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG); 2026 cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d", 2027 rtlsp->ifname, val16, rtlsp->tx_current_desc); 2028 delay(drv_usectohz(1000)); 2029 2030 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG); 2031 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x", 2032 rtlsp->ifname, val32); 2033 delay(drv_usectohz(1000)); 2034 2035 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG); 2036 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x", 2037 rtlsp->ifname, val32); 2038 delay(drv_usectohz(1000)); 2039 2040 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG); 2041 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x", 2042 rtlsp->ifname, val32); 2043 delay(drv_usectohz(1000)); 2044 2045 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG); 2046 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x", 2047 rtlsp->ifname, val32); 2048 delay(drv_usectohz(1000)); 2049 2050 cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu", 2051 rtlsp->ifname, 2052 (unsigned long long)rtlsp->stats.ipackets, 2053 (unsigned long long)rtlsp->stats.multi_rcv, 2054 (unsigned long long)rtlsp->stats.brdcst_rcv); 2055 delay(drv_usectohz(1000)); 2056 } 2057 #endif 2058