1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _RGE_HW_H 28 #define _RGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Realtek GigE chips 42 */ 43 44 /* 45 * Driver support device 46 */ 47 #define VENDOR_ID_REALTECK 0x10EC 48 #define DEVICE_ID_8169 0x8169 49 #define DEVICE_ID_8110 0x8110 50 51 #define RGE_REGISTER_MAX 0x0100 52 53 54 /* 55 * Second section: 56 * Offsets of important registers & definitions for bits therein 57 */ 58 /* 59 * MAC address register, initial value is autoloaded from the 60 * EEPROM EthernetID field 61 */ 62 #define ID_0_REG 0x0000 63 #define ID_1_REG 0x0001 64 #define ID_2_REG 0x0002 65 #define ID_3_REG 0x0003 66 #define ID_4_REG 0x0004 67 #define ID_5_REG 0x0005 68 69 /* 70 * Multicast register 71 */ 72 #define MULTICAST_0_REG 0x0008 73 #define MULTICAST_1_REG 0x0009 74 #define MULTICAST_2_REG 0x000a 75 #define MULTICAST_3_REG 0x000b 76 #define MULTICAST_4_REG 0x000c 77 #define MULTICAST_5_REG 0x000d 78 #define MULTICAST_6_REG 0x000e 79 #define MULTICAST_7_REG 0x000f 80 81 /* 82 * Dump Tally Counter Command register 83 */ 84 #define DUMP_COUNTER_REG_0 0x0010 85 #define DUMP_COUNTER_REG_RESV 0x00000037 86 #define DUMP_START 0x00000008 87 #define DUMP_COUNTER_REG_1 0x0014 88 89 /* 90 * Register for start address of transmit descriptors 91 */ 92 #define NORMAL_TX_RING_ADDR_LO_REG 0x0020 93 #define NORMAL_TX_RING_ADDR_HI_REG 0x0024 94 #define HIGH_TX_RING_ADDR_LO_REG 0x0028 95 #define HIGH_TX_RING_ADDR_HI_REG 0x002c 96 97 /* 98 * Commond register 99 */ 100 #define RT_COMMAND_REG 0x0037 101 #define RT_COMMAND_RESV 0xe3 102 #define RT_COMMAND_RESET 0x10 103 #define RT_COMMAND_RX_ENABLE 0x08 104 #define RT_COMMAND_TX_ENABLE 0x04 105 106 /* 107 * Transmit priority polling register 108 */ 109 #define TX_RINGS_POLL_REG 0x0038 110 #define HIGH_TX_RING_POLL 0x80 111 #define NORMAL_TX_RING_POLL 0x40 112 #define FORCE_SW_INT 0x01 113 114 /* 115 * Interrupt mask & status register 116 */ 117 #define INT_MASK_REG 0x003c 118 #define INT_STATUS_REG 0x003e 119 #define SYS_ERR_INT 0x8000 120 #define TIME_OUT_INT 0x4000 121 #define SW_INT 0x0100 122 #define NO_TXDESC_INT 0x0080 123 #define RX_FIFO_OVERFLOW_INT 0x0040 124 #define LINK_CHANGE_INT 0x0020 125 #define NO_RXDESC_INT 0x0010 126 #define TX_ERR_INT 0x0008 127 #define TX_OK_INT 0x0004 128 #define RX_ERR_INT 0x0002 129 #define RX_OK_INT 0x0001 130 131 #define INT_REG_RESV 0x3e00 132 #define INT_MASK_ALL 0xffff 133 #define INT_MASK_NONE 0x0000 134 #define RGE_RX_OVERFLOW_INT (NO_RXDESC_INT | RX_FIFO_OVERFLOW_INT) 135 #define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 136 RGE_RX_OVERFLOW_INT) 137 #define RGE_INT_MASK (RGE_RX_INT | LINK_CHANGE_INT) 138 139 /* 140 * Transmit configuration register 141 */ 142 #define TX_CONFIG_REG 0x0040 143 #define TX_CONFIG_REG_RESV 0x8070f8ff 144 #define HW_VERSION_ID_0 0x7c000000 145 #define INTER_FRAME_GAP_BITS 0x03080000 146 #define TX_INTERFRAME_GAP_802_3 0x03000000 147 #define HW_VERSION_ID_1 0x00800000 148 #define MAC_LOOPBACK_ENABLE 0x00060000 149 #define CRC_APPEND_ENABLE 0x00010000 150 #define TX_DMA_BURST_BITS 0x00000700 151 152 #define TX_DMA_BURST_UNLIMIT 0x00000700 153 #define TX_DMA_BURST_1024B 0x00000600 154 #define TX_DMA_BURST_512B 0x00000500 155 #define TX_DMA_BURST_256B 0x00000400 156 #define TX_DMA_BURST_128B 0x00000300 157 #define TX_DMA_BURST_64B 0x00000200 158 #define TX_DMA_BURST_32B 0x00000100 159 #define TX_DMA_BURST_16B 0x00000000 160 161 #define MAC_VER_NS 0x00000000 162 #define MAC_VER_SD 0x00800000 163 #define MAC_VER_SE 0x04000000 164 #define MAC_VER_SB 0x10000000 165 166 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 167 TX_DMA_BURST_1024B) 168 /* 169 * Receive configuration register 170 */ 171 #define RX_CONFIG_REG 0x0044 172 #define RX_CONFIG_REG_RESV 0xfffe1880 173 #define RX_RER8_ENABLE 0x00010000 174 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 175 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 176 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 177 #define RX_FIFO_THRESHOLD_512B 0x0000a000 178 #define RX_FIFO_THRESHOLD_256B 0x00008000 179 #define RX_FIFO_THRESHOLD_128B 0x00006000 180 #define RX_FIFO_THRESHOLD_64B 0x00004000 181 #define RX_DMA_BURST_BITS 0x00000700 182 #define RX_DMA_BURST_UNLIMITED 0x00000700 183 #define RX_DMA_BURST_1024B 0x00000600 184 #define RX_DMA_BURST_512B 0x00000500 185 #define RX_DMA_BURST_256B 0x00000400 186 #define RX_DMA_BURST_128B 0x00000300 187 #define RX_DMA_BURST_64B 0x00000200 188 #define RX_EEPROM_9356 0x00000040 189 #define RX_ACCEPT_ERR_PKT 0x00000020 190 #define RX_ACCEPT_RUNT_PKT 0x00000010 191 #define RX_ACCEPT_BROADCAST_PKT 0x000000008 192 #define RX_ACCEPT_MULTICAST_PKT 0x000000004 193 #define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 194 #define RX_ACCEPT_ALL_PKT 0x000000001 195 196 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 197 RX_DMA_BURST_1024B | \ 198 RX_ACCEPT_BROADCAST_PKT | \ 199 RX_ACCEPT_MULTICAST_PKT | \ 200 RX_ACCEPT_MAC_MATCH_PKT) 201 202 /* 203 * Timer count register 204 */ 205 #define TIMER_COUNT_REG 0x0048 206 207 /* 208 * Missed packet counter: indicates the number of packets 209 * discarded due to Rx FIFO overflow 210 */ 211 #define RX_PKT_MISS_COUNT_REG 0x004c 212 213 /* 214 * 93c46(93c56) commond register: 215 */ 216 #define RT_93c46_COMMOND_REG 0x0050 217 #define RT_93c46_MODE_BITS 0xc0 218 #define RT_93c46_MODE_NORMAL 0x00 219 #define RT_93c46_MODE_AUTOLOAD 0x40 220 #define RT_93c46_MODE_PROGRAM 0x80 221 #define RT_93c46_MODE_CONFIG 0xc0 222 223 #define RT_93c46_EECS 0x08 224 #define RT_93c46_EESK 0x04 225 #define RT_93c46_EEDI 0x02 226 #define RT_93c46_EEDO 0x01 227 228 /* 229 * Configuration registers 230 */ 231 #define RT_CONFIG_0_REG 0x0051 232 #define RT_CONFIG_1_REG 0x0052 233 #define RT_CONFIG_2_REG 0x0053 234 #define RT_CONFIG_3_REG 0x0054 235 #define RT_CONFIG_4_REG 0x0055 236 #define RT_CONFIG_5_REG 0x0056 237 238 /* 239 * Timer interrupt register 240 */ 241 #define TIMER_INT_REG 0x0058 242 #define TIMER_INT_NONE 0x00000000 243 244 /* 245 * PHY access register 246 */ 247 #define PHY_ACCESS_REG 0x0060 248 #define PHY_ACCESS_WR_FLAG 0x80000000 249 #define PHY_ACCESS_REG_BITS 0x001f0000 250 #define PHY_ACCESS_DATA_BITS 0x0000ffff 251 #define PHY_DATA_MASK 0xffff 252 #define PHY_REG_MASK 0x1f 253 #define PHY_REG_SHIFT 16 254 255 /* 256 * PHY status register 257 */ 258 #define PHY_STATUS_REG 0x006c 259 #define PHY_STATUS_TBI 0x80 260 #define PHY_STATUS_TX_FLOW 0x40 261 #define PHY_STATUS_RX_FLOW 0x20 262 #define PHY_STATUS_1000MF 0x10 263 #define PHY_STATUS_100M 0x08 264 #define PHY_STATUS_10M 0x04 265 #define PHY_STATUS_LINK_UP 0x02 266 #define PHY_STATUS_DUPLEX_FULL 0x01 267 268 #define RGE_SPEED_1000M 1000 269 #define RGE_SPEED_100M 100 270 #define RGE_SPEED_10M 10 271 #define RGE_SPEED_UNKNOWN 0 272 273 /* 274 * Receive packet maximum size register 275 * -- the maximum rx size supported is (16K - 1) bytes 276 */ 277 #define RX_MAX_PKTSIZE_REG 0x00da 278 #define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 279 #define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 280 281 /* 282 * C+ command register 283 */ 284 #define CPLUS_COMMAND_REG 0x00e0 285 #define CPLUS_RESERVE 0xfd87 286 #define CPLUS_BIT14 0x4000 287 #define CPLUS_BIG_ENDIAN 0x0400 288 #define RX_VLAN_DETAG 0x0040 289 #define RX_CKSM_OFFLOAD 0x0020 290 #define DUAL_PCI_CYCLE 0x0010 291 #define MUL_PCI_RW_ENABLE 0x0008 292 293 /* 294 * Receive descriptor start address 295 */ 296 #define RX_RING_ADDR_LO_REG 0x00e4 297 #define RX_RING_ADDR_HI_REG 0x00e8 298 299 /* 300 * Max transmit packet size register 301 */ 302 #define TX_MAX_PKTSIZE_REG 0x00ec 303 #define TX_MAX_PKTSIZE_REG_RESV 0xc0 304 #define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 305 #define TX_PKTSIZE_STD 0x32 /* document suggested value */ 306 307 #define RESV_82_REG 0x0082 308 #define RESV_E2_REG 0x00e2 309 310 /* 311 * PHY registers 312 */ 313 /* 314 * Basic mode control register 315 */ 316 #define PHY_BMCR_REG 0x00 317 #define PHY_RESET 0x8000 318 #define PHY_LOOPBACK 0x4000 319 #define PHY_SPEED_0 0x2000 320 #define PHY_SPEED_1 0x0040 321 #define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 322 #define PHY_SPEED_1000M PHY_SPEED_1 323 #define PHY_SPEED_100M PHY_SPEED_0 324 #define PHY_SPEED_10M 0x0000 325 #define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 326 #define PHY_AUTO_NEGO 0x1000 327 #define PHY_RESTART_ANTO_NEGO 0x0200 328 #define PHY_DUPLEX_FULL 0x0100 329 #define PHY_BMCR_CLEAR 0xff40 330 331 /* 332 * Basic mode status register 333 */ 334 #define PHY_BMSR_REG 0x01 335 #define PHY_100BASE_T4 0x8000 336 #define PHY_100BASE_TX_FULL 0x4000 337 #define PHY_100BASE_TX_HALF 0x2000 338 #define PHY_10BASE_T_FULL 0x1000 339 #define PHY_10BASE_T_HALF 0x0800 340 #define PHY_100BASE_T2_FULL 0x0400 341 #define PHY_100BASE_T2_HALF 0x0200 342 #define PHY_1000BASE_T_EXT 0x0100 343 #define PHY_AUTO_NEGO_END 0x0020 344 #define PHY_REMOTE_FAULT 0x0010 345 #define PHY_AUTO_NEGO_ABLE 0x0008 346 #define PHY_LINK_UP 0x0004 347 #define PHY_JABBER_DETECT 0x0002 348 #define PHY_EXT_ABLE 0x0001 349 350 /* 351 * PHY identifier register 352 */ 353 #define PHY_ID_REG_1 0x02 354 #define PHY_ID_REG_2 0x03 355 #define PHY_VER_MASK 0x000f 356 #define PHY_VER_S 0x0000 357 #define PHY_VER_SB 0x0010 358 359 /* 360 * Auto-negotiation advertising register 361 */ 362 #define PHY_ANAR_REG 0x04 363 #define ANAR_NEXT_PAGE 0x8000 364 #define ANAR_REMOTE_FAULT 0x2000 365 #define ANAR_ASY_PAUSE 0x0800 366 #define ANAR_PAUSE 0x0400 367 #define ANAR_100BASE_T4 0x0200 368 #define ANAR_100BASE_TX_FULL 0x0100 369 #define ANAR_100BASE_TX_HALF 0x0080 370 #define ANAR_10BASE_T_FULL 0x0040 371 #define ANAR_10BASE_T_HALF 0x0020 372 #define ANAR_RESV_BITS 0x501f 373 374 /* 375 * Auto-negotiation link partner ability register 376 */ 377 #define PHY_ANLPAR_REG 0x05 378 379 /* 380 * Auto-negotiation expansion register 381 */ 382 #define PHY_ANER_REG 0x06 383 384 /* 385 * Auto-negotiation next page transmit register 386 */ 387 #define PHY_ANNPTR_REG 0x07 388 389 /* 390 * Auto-negotiation next page receive register 391 */ 392 #define PHY_ANNPRR_REG 0x08 393 394 /* 395 * 1000Base-T control register 396 */ 397 #define PHY_GBCR_REG 0x09 398 #define GBCR_MODE_JITTER 0x2000 399 #define GBCR_MODE_MASTER 0x4000 400 #define GBCR_MODE_SLAVE 0x6000 401 #define GBCR_1000BASE_T_FULL 0x0200 402 #define GBCR_1000BASE_T_HALF 0x0100 403 #define GBCR_DEFAULT 0x273a 404 405 /* 406 * 1000Base-T status register 407 */ 408 #define PHY_GBSR_REG 0x0a 409 #define LP_1000BASE_T_FULL 0x0800 410 #define LP_1000BASE_T_HALF 0x0400 411 412 /* 413 * 1000Base-T extended status register 414 */ 415 #define PHY_GBESR_REG 0x0f 416 417 #define PHY_1F_REG 0x1f 418 #define PHY_1B_REG 0x1b 419 #define PHY_15_REG 0x15 420 #define PHY_18_REG 0x18 421 #define PHY_0B_REG 0x0b 422 #define PHY_0E_REG 0x0e 423 424 /* 425 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 426 */ 427 428 #define MII_AN_LPNXTPG 8 429 #define MII_1000BASE_T_CONTROL 9 430 #define MII_1000BASE_T_STATUS 10 431 #define MII_IEEE_EXT_STATUS 15 432 433 /* 434 * New bits in the MII_CONTROL register 435 */ 436 #define MII_CONTROL_1000MB 0x0040 437 438 /* 439 * New bits in the MII_AN_ADVERT register 440 */ 441 #define MII_ABILITY_ASYM_PAUSE 0x0800 442 #define MII_ABILITY_PAUSE 0x0400 443 444 /* 445 * Values for the <selector> field of the MII_AN_ADVERT register 446 */ 447 #define MII_AN_SELECTOR_8023 0x0001 448 449 /* 450 * Bits in the MII_1000BASE_T_CONTROL register 451 * 452 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 453 * (otherwise, roles are automatically negotiated). When this bit is set, 454 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 455 */ 456 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 457 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 458 #define MII_1000BT_CTL_ADV_FDX 0x0200 459 #define MII_1000BT_CTL_ADV_HDX 0x0100 460 461 /* 462 * Vendor-specific MII registers 463 */ 464 #define MII_EXT_CONTROL MII_VENDOR(0) 465 #define MII_EXT_STATUS MII_VENDOR(1) 466 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 467 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 468 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 469 #define MII_AUX_CONTROL MII_VENDOR(8) 470 #define MII_AUX_STATUS MII_VENDOR(9) 471 #define MII_INTR_STATUS MII_VENDOR(10) 472 #define MII_INTR_MASK MII_VENDOR(11) 473 #define MII_HCD_STATUS MII_VENDOR(13) 474 475 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 476 477 /* 478 * Bits in the MII_AUX_STATUS register 479 */ 480 #define MII_AUX_STATUS_MODE_MASK 0x0700 481 #define MII_AUX_STATUS_MODE_1000_F 0x0700 482 #define MII_AUX_STATUS_MODE_1000_H 0x0600 483 #define MII_AUX_STATUS_MODE_100_F 0x0500 484 #define MII_AUX_STATUS_MODE_100_4 0x0400 485 #define MII_AUX_STATUS_MODE_100_H 0x0300 486 #define MII_AUX_STATUS_MODE_10_F 0x0200 487 #define MII_AUX_STATUS_MODE_10_H 0x0100 488 #define MII_AUX_STATUS_MODE_NONE 0x0000 489 #define MII_AUX_STATUS_MODE_SHIFT 8 490 491 #define MII_AUX_STATUS_PAR_FAULT 0x0080 492 #define MII_AUX_STATUS_REM_FAULT 0x0040 493 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 494 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 495 496 #define MII_AUX_STATUS_LINKUP 0x0004 497 #define MII_AUX_STATUS_RX_PAUSE 0x0002 498 #define MII_AUX_STATUS_TX_PAUSE 0x0001 499 500 /* 501 * Third section: 502 * Hardware-defined data structures 503 * 504 * Note that the chip is naturally little-endian, so, for a little-endian 505 * host, the structures defined below match those descibed in the PRM. 506 * For big-endian hosts, some structures have to be swapped around. 507 */ 508 509 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 510 #error Host endianness not defined 511 #endif 512 513 /* 514 * Architectural constants: absolute maximum numbers of each type of ring 515 */ 516 517 #define RGE_SEND_SLOTS 1024 518 #define RGE_RECV_SLOTS 1024 519 #define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 520 #define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 521 #define RGE_JUMBO_SIZE 7014 522 #define RGE_STATS_DUMP_SIZE 64 523 524 typedef struct rge_bd { 525 volatile uint32_t flags_len; 526 volatile uint32_t vlan_tag; 527 volatile uint32_t host_buf_addr; 528 volatile uint32_t host_buf_addr_hi; 529 } rge_bd_t; 530 531 #define BD_FLAG_HW_OWN 0x80000000 532 #define BD_FLAG_EOR 0x40000000 533 #define BD_FLAG_PKT_START 0x20000000 534 #define BD_FLAG_PKT_END 0x10000000 535 536 #define RBD_FLAG_MULTICAST 0x08000000 537 #define RBD_FLAG_UNICAST 0x04000000 538 #define RBD_FLAG_BROADCAST 0x02000000 539 #define RBD_FLAG_PKT_4096 0x00400000 540 #define RBD_FLAG_ERROR 0x00200000 541 #define RBD_FLAG_RUNT 0x00100000 542 #define RBD_FLAG_CRC_ERR 0x00080000 543 #define RBD_FLAG_PROTOCOL 0x00060000 544 #define RBD_FLAG_IP 0x00060000 545 #define RBD_FLAG_UDP 0x00040000 546 #define RBD_FLAG_TCP 0x00020000 547 #define RBD_FLAG_NONE_IP 0x00000000 548 #define RBD_IP_CKSUM_ERR 0x00010000 549 #define RBD_UDP_CKSUM_ERR 0x00008000 550 #define RBD_TCP_CKSUM_ERR 0x00004000 551 #define RBD_CKSUM_ERR 0x0001c000 552 #define RBD_FLAGS_MASK 0xffffc000 553 #define RBD_LEN_MASK 0x00003fff 554 555 #define RBD_VLAN_PKT 0x00010000 556 #define RBD_VLAN_TAG 0x0000ffff 557 558 559 #define SBD_FLAG_LARGE_SEND 0x08000000 560 #define SBD_FLAG_SEG_MAX 0x07ff0000 561 #define SBD_FLAG_IP_CKSUM 0x00040000 562 #define SBD_FLAG_UDP_CKSUM 0x00020000 563 #define SBD_FLAG_TCP_CKSUM 0x00010000 564 #define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 565 #define SBD_LEN_MASK 0x0000ffff 566 567 #define SBD_VLAN_PKT 0x00020000 568 #define SBD_VLAN_TAG 0x0000ffff 569 570 #define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 571 BD_FLAG_PKT_END) 572 573 /* 574 * Chip VLAN TCI format 575 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 576 * bit4: CFI Canonical format indicator 577 * bit5-7: 3-bit 8-level priority 578 * bit8-15: The low 8 bits of a 12-bit VLAN ID 579 */ 580 #define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 581 #define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 582 583 /* 584 * Hardware-defined Status Block 585 */ 586 typedef struct rge_hw_stats { 587 uint64_t xmt_ok; 588 uint64_t rcv_ok; 589 uint64_t xmt_err; 590 uint32_t rcv_err; 591 uint16_t in_discards; 592 uint16_t frame_err; 593 uint32_t xmt_1col; 594 uint32_t xmt_mcol; 595 uint64_t unicast_rcv; 596 uint64_t brdcst_rcv; 597 uint32_t multi_rcv; 598 uint16_t xmt_abt; 599 uint16_t xmt_undrn; 600 } rge_hw_stats_t; /* total 64 bytes */ 601 602 #ifdef __cplusplus 603 } 604 #endif 605 606 #endif /* _RGE_HW_H */ 607