1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_HW_H 27 #define _RGE_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 37 38 /* 39 * First section: 40 * Identification of the various Realtek GigE chips 41 */ 42 43 /* 44 * Driver support device 45 */ 46 #define VENDOR_ID_REALTECK 0x10EC 47 #define DEVICE_ID_8169 0x8169 48 #define DEVICE_ID_8110 0x8110 49 #define DEVICE_ID_8168 0x8168 50 #define DEVICE_ID_8111 0x8111 51 52 #define RGE_REGISTER_MAX 0x0100 53 54 55 /* 56 * Second section: 57 * Offsets of important registers & definitions for bits therein 58 */ 59 /* 60 * MAC address register, initial value is autoloaded from the 61 * EEPROM EthernetID field 62 */ 63 #define ID_0_REG 0x0000 64 #define ID_1_REG 0x0001 65 #define ID_2_REG 0x0002 66 #define ID_3_REG 0x0003 67 #define ID_4_REG 0x0004 68 #define ID_5_REG 0x0005 69 70 /* 71 * Multicast register 72 */ 73 #define MULTICAST_0_REG 0x0008 74 #define MULTICAST_1_REG 0x0009 75 #define MULTICAST_2_REG 0x000a 76 #define MULTICAST_3_REG 0x000b 77 #define MULTICAST_4_REG 0x000c 78 #define MULTICAST_5_REG 0x000d 79 #define MULTICAST_6_REG 0x000e 80 #define MULTICAST_7_REG 0x000f 81 #define RGE_MCAST_NUM 8 /* total 8 registers: MAR0 - MAR7 */ 82 83 /* 84 * Dump Tally Counter Command register 85 */ 86 #define DUMP_COUNTER_REG_0 0x0010 87 #define DUMP_COUNTER_REG_RESV 0x00000037 88 #define DUMP_START 0x00000008 89 #define DUMP_COUNTER_REG_1 0x0014 90 91 /* 92 * Register for start address of transmit descriptors 93 */ 94 #define NORMAL_TX_RING_ADDR_LO_REG 0x0020 95 #define NORMAL_TX_RING_ADDR_HI_REG 0x0024 96 #define HIGH_TX_RING_ADDR_LO_REG 0x0028 97 #define HIGH_TX_RING_ADDR_HI_REG 0x002c 98 99 /* 100 * Commond register 101 */ 102 #define RT_COMMAND_REG 0x0037 103 #define RT_COMMAND_RESV 0xe3 104 #define RT_COMMAND_RESET 0x10 105 #define RT_COMMAND_RX_ENABLE 0x08 106 #define RT_COMMAND_TX_ENABLE 0x04 107 108 /* 109 * Transmit priority polling register 110 */ 111 #define TX_RINGS_POLL_REG 0x0038 112 #define HIGH_TX_RING_POLL 0x80 113 #define NORMAL_TX_RING_POLL 0x40 114 #define FORCE_SW_INT 0x01 115 116 /* 117 * Interrupt mask & status register 118 */ 119 #define INT_MASK_REG 0x003c 120 #define INT_STATUS_REG 0x003e 121 #define SYS_ERR_INT 0x8000 122 #define TIME_OUT_INT 0x4000 123 #define SW_INT 0x0100 124 #define NO_TXDESC_INT 0x0080 125 #define RX_FIFO_OVERFLOW_INT 0x0040 126 #define LINK_CHANGE_INT 0x0020 127 #define NO_RXDESC_INT 0x0010 128 #define TX_ERR_INT 0x0008 129 #define TX_OK_INT 0x0004 130 #define RX_ERR_INT 0x0002 131 #define RX_OK_INT 0x0001 132 133 #define INT_REG_RESV 0x3e00 134 #define INT_MASK_ALL 0xffff 135 #define INT_MASK_NONE 0x0000 136 #define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 137 NO_RXDESC_INT) 138 #define RGE_INT_MASK (RGE_RX_INT | LINK_CHANGE_INT) 139 140 /* 141 * Transmit configuration register 142 */ 143 #define TX_CONFIG_REG 0x0040 144 #define TX_CONFIG_REG_RESV 0x8070f8ff 145 #define HW_VERSION_ID_0 0x7c000000 146 #define INTER_FRAME_GAP_BITS 0x03080000 147 #define TX_INTERFRAME_GAP_802_3 0x03000000 148 #define HW_VERSION_ID_1 0x00800000 149 #define MAC_LOOPBACK_ENABLE 0x00060000 150 #define CRC_APPEND_ENABLE 0x00010000 151 #define TX_DMA_BURST_BITS 0x00000700 152 153 #define TX_DMA_BURST_UNLIMIT 0x00000700 154 #define TX_DMA_BURST_1024B 0x00000600 155 #define TX_DMA_BURST_512B 0x00000500 156 #define TX_DMA_BURST_256B 0x00000400 157 #define TX_DMA_BURST_128B 0x00000300 158 #define TX_DMA_BURST_64B 0x00000200 159 #define TX_DMA_BURST_32B 0x00000100 160 #define TX_DMA_BURST_16B 0x00000000 161 162 #define MAC_VER_8169 0x00000000 163 #define MAC_VER_8169S_D 0x00800000 164 #define MAC_VER_8169S_E 0x04000000 165 #define MAC_VER_8169SB 0x10000000 166 #define MAC_VER_8168 0x20000000 167 #define MAC_VER_8168B_B 0x30000000 168 #define MAC_VER_8168B_C 0x38000000 169 170 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 171 TX_DMA_BURST_1024B) 172 /* 173 * Receive configuration register 174 */ 175 #define RX_CONFIG_REG 0x0044 176 #define RX_CONFIG_REG_RESV 0xfffe1880 177 #define RX_RER8_ENABLE 0x00010000 178 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 179 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 180 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 181 #define RX_FIFO_THRESHOLD_512B 0x0000a000 182 #define RX_FIFO_THRESHOLD_256B 0x00008000 183 #define RX_FIFO_THRESHOLD_128B 0x00006000 184 #define RX_FIFO_THRESHOLD_64B 0x00004000 185 #define RX_DMA_BURST_BITS 0x00000700 186 #define RX_DMA_BURST_UNLIMITED 0x00000700 187 #define RX_DMA_BURST_1024B 0x00000600 188 #define RX_DMA_BURST_512B 0x00000500 189 #define RX_DMA_BURST_256B 0x00000400 190 #define RX_DMA_BURST_128B 0x00000300 191 #define RX_DMA_BURST_64B 0x00000200 192 #define RX_EEPROM_9356 0x00000040 193 #define RX_ACCEPT_ERR_PKT 0x00000020 194 #define RX_ACCEPT_RUNT_PKT 0x00000010 195 #define RX_ACCEPT_BROADCAST_PKT 0x000000008 196 #define RX_ACCEPT_MULTICAST_PKT 0x000000004 197 #define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 198 #define RX_ACCEPT_ALL_PKT 0x000000001 199 200 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 201 RX_DMA_BURST_1024B | \ 202 RX_ACCEPT_BROADCAST_PKT | \ 203 RX_ACCEPT_MULTICAST_PKT | \ 204 RX_ACCEPT_MAC_MATCH_PKT) 205 206 /* 207 * Timer count register 208 */ 209 #define TIMER_COUNT_REG 0x0048 210 211 /* 212 * Missed packet counter: indicates the number of packets 213 * discarded due to Rx FIFO overflow 214 */ 215 #define RX_PKT_MISS_COUNT_REG 0x004c 216 217 /* 218 * 93c46(93c56) commond register: 219 */ 220 #define RT_93c46_COMMOND_REG 0x0050 221 #define RT_93c46_MODE_BITS 0xc0 222 #define RT_93c46_MODE_NORMAL 0x00 223 #define RT_93c46_MODE_AUTOLOAD 0x40 224 #define RT_93c46_MODE_PROGRAM 0x80 225 #define RT_93c46_MODE_CONFIG 0xc0 226 227 #define RT_93c46_EECS 0x08 228 #define RT_93c46_EESK 0x04 229 #define RT_93c46_EEDI 0x02 230 #define RT_93c46_EEDO 0x01 231 232 /* 233 * Configuration registers 234 */ 235 #define RT_CONFIG_0_REG 0x0051 236 #define RT_CONFIG_1_REG 0x0052 237 #define RT_CONFIG_2_REG 0x0053 238 #define RT_CONFIG_3_REG 0x0054 239 #define RT_CONFIG_4_REG 0x0055 240 #define RT_CONFIG_5_REG 0x0056 241 242 /* 243 * Timer interrupt register 244 */ 245 #define TIMER_INT_REG 0x0058 246 #define TIMER_INT_NONE 0x00000000 247 248 /* 249 * PHY access register 250 */ 251 #define PHY_ACCESS_REG 0x0060 252 #define PHY_ACCESS_WR_FLAG 0x80000000 253 #define PHY_ACCESS_REG_BITS 0x001f0000 254 #define PHY_ACCESS_DATA_BITS 0x0000ffff 255 #define PHY_DATA_MASK 0xffff 256 #define PHY_REG_MASK 0x1f 257 #define PHY_REG_SHIFT 16 258 259 /* 260 * CSI data register (for PCIE chipset) 261 */ 262 #define RT_CSI_DATA_REG 0x0064 263 264 /* 265 * CSI access register (for PCIE chipset) 266 */ 267 #define RT_CSI_ACCESS_REG 0x0068 268 269 /* 270 * PHY status register 271 */ 272 #define PHY_STATUS_REG 0x006c 273 #define PHY_STATUS_TBI 0x80 274 #define PHY_STATUS_TX_FLOW 0x40 275 #define PHY_STATUS_RX_FLOW 0x20 276 #define PHY_STATUS_1000MF 0x10 277 #define PHY_STATUS_100M 0x08 278 #define PHY_STATUS_10M 0x04 279 #define PHY_STATUS_LINK_UP 0x02 280 #define PHY_STATUS_DUPLEX_FULL 0x01 281 282 #define RGE_SPEED_1000M 1000 283 #define RGE_SPEED_100M 100 284 #define RGE_SPEED_10M 10 285 #define RGE_SPEED_UNKNOWN 0 286 287 /* 288 * EPHY access register (for PCIE chipset) 289 */ 290 #define EPHY_ACCESS_REG 0x0080 291 #define EPHY_ACCESS_WR_FLAG 0x80000000 292 #define EPHY_ACCESS_REG_BITS 0x001f0000 293 #define EPHY_ACCESS_DATA_BITS 0x0000ffff 294 #define EPHY_DATA_MASK 0xffff 295 #define EPHY_REG_MASK 0x1f 296 #define EPHY_REG_SHIFT 16 297 298 /* 299 * Receive packet maximum size register 300 * -- the maximum rx size supported is (16K - 1) bytes 301 */ 302 #define RX_MAX_PKTSIZE_REG 0x00da 303 #define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 304 #define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 305 306 /* 307 * C+ command register 308 */ 309 #define CPLUS_COMMAND_REG 0x00e0 310 #define CPLUS_RESERVE 0xfd87 311 #define CPLUS_BIT14 0x4000 312 #define CPLUS_BIG_ENDIAN 0x0400 313 #define RX_VLAN_DETAG 0x0040 314 #define RX_CKSM_OFFLOAD 0x0020 315 #define DUAL_PCI_CYCLE 0x0010 316 #define MUL_PCI_RW_ENABLE 0x0008 317 318 /* 319 * Receive descriptor start address 320 */ 321 #define RX_RING_ADDR_LO_REG 0x00e4 322 #define RX_RING_ADDR_HI_REG 0x00e8 323 324 /* 325 * Max transmit packet size register 326 */ 327 #define TX_MAX_PKTSIZE_REG 0x00ec 328 #define TX_MAX_PKTSIZE_REG_RESV 0xc0 329 #define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 330 #define TX_PKTSIZE_STD 0x32 /* document suggested value */ 331 332 #define RESV_82_REG 0x0082 333 #define RESV_E2_REG 0x00e2 334 335 /* 336 * PHY registers 337 */ 338 /* 339 * Basic mode control register 340 */ 341 #define PHY_BMCR_REG 0x00 342 #define PHY_RESET 0x8000 343 #define PHY_LOOPBACK 0x4000 344 #define PHY_SPEED_0 0x2000 345 #define PHY_SPEED_1 0x0040 346 #define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 347 #define PHY_SPEED_1000M PHY_SPEED_1 348 #define PHY_SPEED_100M PHY_SPEED_0 349 #define PHY_SPEED_10M 0x0000 350 #define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 351 #define PHY_AUTO_NEGO 0x1000 352 #define PHY_RESTART_ANTO_NEGO 0x0200 353 #define PHY_DUPLEX_FULL 0x0100 354 #define PHY_BMCR_CLEAR 0xff40 355 356 /* 357 * Basic mode status register 358 */ 359 #define PHY_BMSR_REG 0x01 360 #define PHY_100BASE_T4 0x8000 361 #define PHY_100BASE_TX_FULL 0x4000 362 #define PHY_100BASE_TX_HALF 0x2000 363 #define PHY_10BASE_T_FULL 0x1000 364 #define PHY_10BASE_T_HALF 0x0800 365 #define PHY_100BASE_T2_FULL 0x0400 366 #define PHY_100BASE_T2_HALF 0x0200 367 #define PHY_1000BASE_T_EXT 0x0100 368 #define PHY_AUTO_NEGO_END 0x0020 369 #define PHY_REMOTE_FAULT 0x0010 370 #define PHY_AUTO_NEGO_ABLE 0x0008 371 #define PHY_LINK_UP 0x0004 372 #define PHY_JABBER_DETECT 0x0002 373 #define PHY_EXT_ABLE 0x0001 374 375 /* 376 * PHY identifier register 377 */ 378 #define PHY_ID_REG_1 0x02 379 #define PHY_ID_REG_2 0x03 380 #define PHY_VER_MASK 0x000f 381 #define PHY_VER_S 0x0000 382 #define PHY_VER_SB 0x0010 383 384 /* 385 * Auto-negotiation advertising register 386 */ 387 #define PHY_ANAR_REG 0x04 388 #define ANAR_NEXT_PAGE 0x8000 389 #define ANAR_REMOTE_FAULT 0x2000 390 #define ANAR_ASY_PAUSE 0x0800 391 #define ANAR_PAUSE 0x0400 392 #define ANAR_100BASE_T4 0x0200 393 #define ANAR_100BASE_TX_FULL 0x0100 394 #define ANAR_100BASE_TX_HALF 0x0080 395 #define ANAR_10BASE_T_FULL 0x0040 396 #define ANAR_10BASE_T_HALF 0x0020 397 #define ANAR_RESV_BITS 0x501f 398 399 /* 400 * Auto-negotiation link partner ability register 401 */ 402 #define PHY_ANLPAR_REG 0x05 403 404 /* 405 * Auto-negotiation expansion register 406 */ 407 #define PHY_ANER_REG 0x06 408 409 /* 410 * Auto-negotiation next page transmit register 411 */ 412 #define PHY_ANNPTR_REG 0x07 413 414 /* 415 * Auto-negotiation next page receive register 416 */ 417 #define PHY_ANNPRR_REG 0x08 418 419 /* 420 * 1000Base-T control register 421 */ 422 #define PHY_GBCR_REG 0x09 423 #define GBCR_MODE_JITTER 0x2000 424 #define GBCR_MODE_MASTER 0x4000 425 #define GBCR_MODE_SLAVE 0x6000 426 #define GBCR_1000BASE_T_FULL 0x0200 427 #define GBCR_1000BASE_T_HALF 0x0100 428 #define GBCR_DEFAULT 0x273a 429 430 /* 431 * 1000Base-T status register 432 */ 433 #define PHY_GBSR_REG 0x0a 434 #define LP_1000BASE_T_FULL 0x0800 435 #define LP_1000BASE_T_HALF 0x0400 436 437 /* 438 * 1000Base-T extended status register 439 */ 440 #define PHY_GBESR_REG 0x0f 441 442 #define PHY_1F_REG 0x1f 443 #define PHY_1C_REG 0x1c 444 #define PHY_1B_REG 0x1b 445 #define PHY_18_REG 0x18 446 #define PHY_15_REG 0x15 447 #define PHY_12_REG 0x12 448 #define PHY_0E_REG 0x0e 449 #define PHY_0B_REG 0x0b 450 451 /* 452 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 453 */ 454 455 #define MII_AN_LPNXTPG 8 456 #define MII_1000BASE_T_CONTROL 9 457 #define MII_1000BASE_T_STATUS 10 458 #define MII_IEEE_EXT_STATUS 15 459 460 /* 461 * New bits in the MII_CONTROL register 462 */ 463 #define MII_CONTROL_1000MB 0x0040 464 465 /* 466 * New bits in the MII_AN_ADVERT register 467 */ 468 #define MII_ABILITY_ASYM_PAUSE 0x0800 469 #define MII_ABILITY_PAUSE 0x0400 470 471 /* 472 * Values for the <selector> field of the MII_AN_ADVERT register 473 */ 474 #define MII_AN_SELECTOR_8023 0x0001 475 476 /* 477 * Bits in the MII_1000BASE_T_CONTROL register 478 * 479 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 480 * (otherwise, roles are automatically negotiated). When this bit is set, 481 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 482 */ 483 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 484 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 485 #define MII_1000BT_CTL_ADV_FDX 0x0200 486 #define MII_1000BT_CTL_ADV_HDX 0x0100 487 488 /* 489 * Vendor-specific MII registers 490 */ 491 #define MII_EXT_CONTROL MII_VENDOR(0) 492 #define MII_EXT_STATUS MII_VENDOR(1) 493 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 494 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 495 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 496 #define MII_AUX_CONTROL MII_VENDOR(8) 497 #define MII_AUX_STATUS MII_VENDOR(9) 498 #define MII_INTR_STATUS MII_VENDOR(10) 499 #define MII_INTR_MASK MII_VENDOR(11) 500 #define MII_HCD_STATUS MII_VENDOR(13) 501 502 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 503 504 /* 505 * Bits in the MII_AUX_STATUS register 506 */ 507 #define MII_AUX_STATUS_MODE_MASK 0x0700 508 #define MII_AUX_STATUS_MODE_1000_F 0x0700 509 #define MII_AUX_STATUS_MODE_1000_H 0x0600 510 #define MII_AUX_STATUS_MODE_100_F 0x0500 511 #define MII_AUX_STATUS_MODE_100_4 0x0400 512 #define MII_AUX_STATUS_MODE_100_H 0x0300 513 #define MII_AUX_STATUS_MODE_10_F 0x0200 514 #define MII_AUX_STATUS_MODE_10_H 0x0100 515 #define MII_AUX_STATUS_MODE_NONE 0x0000 516 #define MII_AUX_STATUS_MODE_SHIFT 8 517 518 #define MII_AUX_STATUS_PAR_FAULT 0x0080 519 #define MII_AUX_STATUS_REM_FAULT 0x0040 520 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 521 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 522 523 #define MII_AUX_STATUS_LINKUP 0x0004 524 #define MII_AUX_STATUS_RX_PAUSE 0x0002 525 #define MII_AUX_STATUS_TX_PAUSE 0x0001 526 527 /* 528 * Third section: 529 * Hardware-defined data structures 530 * 531 * Note that the chip is naturally little-endian, so, for a little-endian 532 * host, the structures defined below match those descibed in the PRM. 533 * For big-endian hosts, some structures have to be swapped around. 534 */ 535 536 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 537 #error Host endianness not defined 538 #endif 539 540 /* 541 * Architectural constants: absolute maximum numbers of each type of ring 542 */ 543 544 #define RGE_SEND_SLOTS 1024 545 #define RGE_RECV_SLOTS 1024 546 #define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 547 #define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 548 #define RGE_JUMBO_SIZE 7014 549 #define RGE_JUMBO_MTU 7000 550 #define RGE_STATS_DUMP_SIZE 64 551 552 typedef struct rge_bd { 553 volatile uint32_t flags_len; 554 volatile uint32_t vlan_tag; 555 volatile uint32_t host_buf_addr; 556 volatile uint32_t host_buf_addr_hi; 557 } rge_bd_t; 558 559 #define BD_FLAG_HW_OWN 0x80000000 560 #define BD_FLAG_EOR 0x40000000 561 #define BD_FLAG_PKT_START 0x20000000 562 #define BD_FLAG_PKT_END 0x10000000 563 564 #define RBD_FLAG_MULTICAST 0x08000000 565 #define RBD_FLAG_UNICAST 0x04000000 566 #define RBD_FLAG_BROADCAST 0x02000000 567 #define RBD_FLAG_PKT_4096 0x00400000 568 #define RBD_FLAG_ERROR 0x00200000 569 #define RBD_FLAG_RUNT 0x00100000 570 #define RBD_FLAG_CRC_ERR 0x00080000 571 #define RBD_FLAG_PROTOCOL 0x00060000 572 #define RBD_FLAG_IP 0x00060000 573 #define RBD_FLAG_UDP 0x00040000 574 #define RBD_FLAG_TCP 0x00020000 575 #define RBD_FLAG_NONE_IP 0x00000000 576 #define RBD_IP_CKSUM_ERR 0x00010000 577 #define RBD_UDP_CKSUM_ERR 0x00008000 578 #define RBD_TCP_CKSUM_ERR 0x00004000 579 #define RBD_CKSUM_ERR 0x0001c000 580 #define RBD_FLAGS_MASK 0xffffc000 581 #define RBD_LEN_MASK 0x00003fff 582 583 #define RBD_VLAN_PKT 0x00010000 584 #define RBD_VLAN_TAG 0x0000ffff 585 586 587 #define SBD_FLAG_LARGE_SEND 0x08000000 588 #define SBD_FLAG_SEG_MAX 0x07ff0000 589 #define SBD_FLAG_IP_CKSUM 0x00040000 590 #define SBD_FLAG_UDP_CKSUM 0x00020000 591 #define SBD_FLAG_TCP_CKSUM 0x00010000 592 #define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 593 #define SBD_LEN_MASK 0x0000ffff 594 595 #define SBD_VLAN_PKT 0x00020000 596 #define SBD_VLAN_TAG 0x0000ffff 597 598 #define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 599 BD_FLAG_PKT_END) 600 601 /* 602 * Chip VLAN TCI format 603 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 604 * bit4: CFI Canonical format indicator 605 * bit5-7: 3-bit 8-level priority 606 * bit8-15: The low 8 bits of a 12-bit VLAN ID 607 */ 608 #define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 609 #define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 610 611 /* 612 * Hardware-defined Status Block 613 */ 614 typedef struct rge_hw_stats { 615 uint64_t xmt_ok; 616 uint64_t rcv_ok; 617 uint64_t xmt_err; 618 uint32_t rcv_err; 619 uint16_t in_discards; 620 uint16_t frame_err; 621 uint32_t xmt_1col; 622 uint32_t xmt_mcol; 623 uint64_t unicast_rcv; 624 uint64_t brdcst_rcv; 625 uint32_t multi_rcv; 626 uint16_t xmt_abt; 627 uint16_t xmt_undrn; 628 } rge_hw_stats_t; /* total 64 bytes */ 629 630 #ifdef __cplusplus 631 } 632 #endif 633 634 #endif /* _RGE_HW_H */ 635