1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 #if RGE_DEBUGGING 53 54 static void rge_pci_check(rge_t *rgep); 55 #pragma no_inline(rge_pci_check) 56 57 static void 58 rge_pci_check(rge_t *rgep) 59 { 60 uint16_t pcistatus; 61 62 pcistatus = pci_config_get16(rgep->cfg_handle, PCI_CONF_STAT); 63 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 64 RGE_DEBUG(("rge_pci_check($%p): PCI status 0x%x", 65 (void *)rgep, pcistatus)); 66 } 67 68 #endif /* RGE_DEBUGGING */ 69 70 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 71 #pragma inline(rge_reg_get32) 72 73 static uint32_t 74 rge_reg_get32(rge_t *rgep, uintptr_t regno) 75 { 76 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 77 (void *)rgep, regno)); 78 79 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 80 } 81 82 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 83 #pragma inline(rge_reg_put32) 84 85 static void 86 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 87 { 88 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 89 (void *)rgep, regno, data)); 90 91 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 92 RGE_PCICHK(rgep); 93 } 94 95 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 96 #pragma inline(rge_reg_set32) 97 98 static void 99 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 100 { 101 uint32_t regval; 102 103 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 104 (void *)rgep, regno, bits)); 105 106 regval = rge_reg_get32(rgep, regno); 107 regval |= bits; 108 rge_reg_put32(rgep, regno, regval); 109 } 110 111 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 112 #pragma inline(rge_reg_clr32) 113 114 static void 115 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 116 { 117 uint32_t regval; 118 119 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 120 (void *)rgep, regno, bits)); 121 122 regval = rge_reg_get32(rgep, regno); 123 regval &= ~bits; 124 rge_reg_put32(rgep, regno, regval); 125 } 126 127 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 128 #pragma inline(rge_reg_get16) 129 130 static uint16_t 131 rge_reg_get16(rge_t *rgep, uintptr_t regno) 132 { 133 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 134 (void *)rgep, regno)); 135 136 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 137 } 138 139 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 140 #pragma inline(rge_reg_put16) 141 142 static void 143 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 144 { 145 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 146 (void *)rgep, regno, data)); 147 148 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 149 RGE_PCICHK(rgep); 150 } 151 152 static void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits); 153 #pragma inline(rge_reg_set16) 154 155 static void 156 rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits) 157 { 158 uint16_t regval; 159 160 RGE_TRACE(("rge_reg_set16($%p, 0x%lx, 0x%x)", 161 (void *)rgep, regno, bits)); 162 163 regval = rge_reg_get16(rgep, regno); 164 regval |= bits; 165 rge_reg_put16(rgep, regno, regval); 166 } 167 168 static void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits); 169 #pragma inline(rge_reg_clr16) 170 171 static void 172 rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits) 173 { 174 uint16_t regval; 175 176 RGE_TRACE(("rge_reg_clr16($%p, 0x%lx, 0x%x)", 177 (void *)rgep, regno, bits)); 178 179 regval = rge_reg_get16(rgep, regno); 180 regval &= ~bits; 181 rge_reg_put16(rgep, regno, regval); 182 } 183 184 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 185 #pragma inline(rge_reg_get8) 186 187 static uint8_t 188 rge_reg_get8(rge_t *rgep, uintptr_t regno) 189 { 190 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 191 (void *)rgep, regno)); 192 193 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 194 } 195 196 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 197 #pragma inline(rge_reg_put8) 198 199 static void 200 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 201 { 202 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 203 (void *)rgep, regno, data)); 204 205 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 206 RGE_PCICHK(rgep); 207 } 208 209 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 210 #pragma inline(rge_reg_set8) 211 212 static void 213 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 214 { 215 uint8_t regval; 216 217 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 218 (void *)rgep, regno, bits)); 219 220 regval = rge_reg_get8(rgep, regno); 221 regval |= bits; 222 rge_reg_put8(rgep, regno, regval); 223 } 224 225 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 226 #pragma inline(rge_reg_clr8) 227 228 static void 229 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 230 { 231 uint8_t regval; 232 233 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 234 (void *)rgep, regno, bits)); 235 236 regval = rge_reg_get8(rgep, regno); 237 regval &= ~bits; 238 rge_reg_put8(rgep, regno, regval); 239 } 240 241 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 242 #pragma no_inline(rge_mii_get16) 243 244 uint16_t 245 rge_mii_get16(rge_t *rgep, uintptr_t mii) 246 { 247 uint32_t regval; 248 uint32_t val32; 249 uint32_t i; 250 251 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 252 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 253 254 /* 255 * Waiting for PHY reading OK 256 */ 257 for (i = 0; i < PHY_RESET_LOOP; i++) { 258 drv_usecwait(1000); 259 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 260 if (val32 & PHY_ACCESS_WR_FLAG) 261 return ((uint16_t)(val32 & 0xffff)); 262 } 263 264 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 265 return ((uint16_t)~0u); 266 } 267 268 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 269 #pragma no_inline(rge_mii_put16) 270 271 void 272 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 273 { 274 uint32_t regval; 275 uint32_t val32; 276 uint32_t i; 277 278 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 279 regval |= data & PHY_DATA_MASK; 280 regval |= PHY_ACCESS_WR_FLAG; 281 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 282 283 /* 284 * Waiting for PHY writing OK 285 */ 286 for (i = 0; i < PHY_RESET_LOOP; i++) { 287 drv_usecwait(1000); 288 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 289 if (!(val32 & PHY_ACCESS_WR_FLAG)) 290 return; 291 } 292 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 293 mii, data)); 294 } 295 296 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 297 #pragma no_inline(rge_ephy_put16) 298 299 void 300 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 301 { 302 uint32_t regval; 303 uint32_t val32; 304 uint32_t i; 305 306 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 307 regval |= data & EPHY_DATA_MASK; 308 regval |= EPHY_ACCESS_WR_FLAG; 309 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 310 311 /* 312 * Waiting for PHY writing OK 313 */ 314 for (i = 0; i < PHY_RESET_LOOP; i++) { 315 drv_usecwait(1000); 316 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 317 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 318 return; 319 } 320 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 321 emii, data)); 322 } 323 324 /* 325 * Atomically shift a 32-bit word left, returning 326 * the value it had *before* the shift was applied 327 */ 328 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 329 #pragma inline(rge_mii_put16) 330 331 static uint32_t 332 rge_atomic_shl32(uint32_t *sp, uint_t count) 333 { 334 uint32_t oldval; 335 uint32_t newval; 336 337 /* ATOMICALLY */ 338 do { 339 oldval = *sp; 340 newval = oldval << count; 341 } while (cas32(sp, oldval, newval) != oldval); 342 343 return (oldval); 344 } 345 346 /* 347 * PHY operation routines 348 */ 349 #if RGE_DEBUGGING 350 351 static void 352 rge_phydump(rge_t *rgep) 353 { 354 uint16_t regs[32]; 355 int i; 356 357 ASSERT(mutex_owned(rgep->genlock)); 358 359 for (i = 0; i < 32; ++i) { 360 regs[i] = rge_mii_get16(rgep, i); 361 } 362 363 for (i = 0; i < 32; i += 8) 364 RGE_DEBUG(("rge_phydump: " 365 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 366 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 367 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 368 } 369 370 #endif /* RGE_DEBUGGING */ 371 372 /* 373 * Basic low-level function to probe for a PHY 374 * 375 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 376 */ 377 static boolean_t 378 rge_phy_probe(rge_t *rgep) 379 { 380 uint16_t phy_status; 381 382 ASSERT(mutex_owned(rgep->genlock)); 383 384 /* 385 * Read the MII_STATUS register twice, in 386 * order to clear any sticky bits (but they should 387 * have been cleared by the RESET, I think). 388 */ 389 phy_status = rge_mii_get16(rgep, MII_STATUS); 390 phy_status = rge_mii_get16(rgep, MII_STATUS); 391 RGE_DEBUG(("rge_phy_probe: status 0x%x", phy_status)); 392 393 /* 394 * Now check the value read; it should have at least one bit set 395 * (for the device capabilities) and at least one clear (one of 396 * the error bits). So if we see all 0s or all 1s, there's a 397 * problem. In particular, rge_mii_get16() returns all 1s if 398 * communications fails ... 399 */ 400 switch (phy_status) { 401 case 0x0000: 402 case 0xffff: 403 return (B_FALSE); 404 405 default : 406 return (B_TRUE); 407 } 408 } 409 410 static void 411 rge_phy_check(rge_t *rgep) 412 { 413 uint16_t gig_ctl; 414 415 if (rgep->param_link_up == LINK_STATE_DOWN) { 416 /* 417 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 418 * every 15 seconds whin link down & advertise is 1000. 419 */ 420 if (rgep->chipid.phy_ver == PHY_VER_S) { 421 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 422 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 423 rgep->link_down_count++; 424 if (rgep->link_down_count > 15) { 425 (void) rge_phy_reset(rgep); 426 rgep->stats.phy_reset++; 427 rgep->link_down_count = 0; 428 } 429 } 430 } 431 } else { 432 rgep->link_down_count = 0; 433 } 434 } 435 436 /* 437 * Basic low-level function to reset the PHY. 438 * Doesn't incorporate any special-case workarounds. 439 * 440 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 441 */ 442 boolean_t 443 rge_phy_reset(rge_t *rgep) 444 { 445 uint16_t control; 446 uint_t count; 447 448 /* 449 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 450 */ 451 control = rge_mii_get16(rgep, MII_CONTROL); 452 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 453 for (count = 0; count < 5; count++) { 454 drv_usecwait(100); 455 control = rge_mii_get16(rgep, MII_CONTROL); 456 if (BIC(control, MII_CONTROL_RESET)) 457 return (B_TRUE); 458 } 459 460 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 461 return (B_FALSE); 462 } 463 464 /* 465 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 466 * and advertisements with the required settings as specified by the various 467 * param_* variables that can be poked via the NDD interface. 468 * 469 * We always reset the PHY and reprogram *all* the relevant registers, 470 * not just those changed. This should cause the link to go down, and then 471 * back up again once the link is stable and autonegotiation (if enabled) 472 * is complete. We should get a link state change interrupt somewhere along 473 * the way ... 474 * 475 * NOTE: <genlock> must already be held by the caller 476 */ 477 void 478 rge_phy_update(rge_t *rgep) 479 { 480 boolean_t adv_autoneg; 481 boolean_t adv_pause; 482 boolean_t adv_asym_pause; 483 boolean_t adv_1000fdx; 484 boolean_t adv_1000hdx; 485 boolean_t adv_100fdx; 486 boolean_t adv_100hdx; 487 boolean_t adv_10fdx; 488 boolean_t adv_10hdx; 489 490 uint16_t control; 491 uint16_t gigctrl; 492 uint16_t anar; 493 494 ASSERT(mutex_owned(rgep->genlock)); 495 496 RGE_DEBUG(("rge_phy_update: autoneg %d " 497 "pause %d asym_pause %d " 498 "1000fdx %d 1000hdx %d " 499 "100fdx %d 100hdx %d " 500 "10fdx %d 10hdx %d ", 501 rgep->param_adv_autoneg, 502 rgep->param_adv_pause, rgep->param_adv_asym_pause, 503 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 504 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 505 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 506 507 control = gigctrl = anar = 0; 508 509 /* 510 * PHY settings are normally based on the param_* variables, 511 * but if any loopback mode is in effect, that takes precedence. 512 * 513 * RGE supports MAC-internal loopback, PHY-internal loopback, 514 * and External loopback at a variety of speeds (with a special 515 * cable). In all cases, autoneg is turned OFF, full-duplex 516 * is turned ON, and the speed/mastership is forced. 517 */ 518 switch (rgep->param_loop_mode) { 519 case RGE_LOOP_NONE: 520 default: 521 adv_autoneg = rgep->param_adv_autoneg; 522 adv_pause = rgep->param_adv_pause; 523 adv_asym_pause = rgep->param_adv_asym_pause; 524 adv_1000fdx = rgep->param_adv_1000fdx; 525 adv_1000hdx = rgep->param_adv_1000hdx; 526 adv_100fdx = rgep->param_adv_100fdx; 527 adv_100hdx = rgep->param_adv_100hdx; 528 adv_10fdx = rgep->param_adv_10fdx; 529 adv_10hdx = rgep->param_adv_10hdx; 530 break; 531 532 case RGE_LOOP_INTERNAL_PHY: 533 case RGE_LOOP_INTERNAL_MAC: 534 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 535 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 536 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 537 rgep->param_link_duplex = LINK_DUPLEX_FULL; 538 539 switch (rgep->param_loop_mode) { 540 case RGE_LOOP_INTERNAL_PHY: 541 rgep->param_link_speed = 1000; 542 adv_1000fdx = B_TRUE; 543 control = MII_CONTROL_LOOPBACK; 544 break; 545 546 case RGE_LOOP_INTERNAL_MAC: 547 rgep->param_link_speed = 1000; 548 adv_1000fdx = B_TRUE; 549 break; 550 } 551 } 552 553 RGE_DEBUG(("rge_phy_update: autoneg %d " 554 "pause %d asym_pause %d " 555 "1000fdx %d 1000hdx %d " 556 "100fdx %d 100hdx %d " 557 "10fdx %d 10hdx %d ", 558 adv_autoneg, 559 adv_pause, adv_asym_pause, 560 adv_1000fdx, adv_1000hdx, 561 adv_100fdx, adv_100hdx, 562 adv_10fdx, adv_10hdx)); 563 564 /* 565 * We should have at least one technology capability set; 566 * if not, we select a default of 1000Mb/s full-duplex 567 */ 568 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 569 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 570 adv_1000fdx = B_TRUE; 571 572 /* 573 * Now transform the adv_* variables into the proper settings 574 * of the PHY registers ... 575 * 576 * If autonegotiation is (now) enabled, we want to trigger 577 * a new autonegotiation cycle once the PHY has been 578 * programmed with the capabilities to be advertised. 579 * 580 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 581 */ 582 if (adv_autoneg) 583 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 584 585 if (adv_1000fdx) 586 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 587 else if (adv_1000hdx) 588 control |= MII_CONTROL_1000MB; 589 else if (adv_100fdx) 590 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 591 else if (adv_100hdx) 592 control |= MII_CONTROL_100MB; 593 else if (adv_10fdx) 594 control |= MII_CONTROL_FDUPLEX; 595 else if (adv_10hdx) 596 control |= 0; 597 else 598 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 599 600 if (adv_1000fdx) { 601 gigctrl |= MII_1000BT_CTL_ADV_FDX; 602 /* 603 * Chipset limitation: need set other capabilities to true 604 */ 605 if (rgep->chipid.is_pcie) 606 adv_1000hdx = B_TRUE; 607 adv_100fdx = B_TRUE; 608 adv_100hdx = B_TRUE; 609 adv_10fdx = B_TRUE; 610 adv_10hdx = B_TRUE; 611 } 612 613 if (adv_1000hdx) 614 gigctrl |= MII_1000BT_CTL_ADV_HDX; 615 616 if (adv_100fdx) 617 anar |= MII_ABILITY_100BASE_TX_FD; 618 if (adv_100hdx) 619 anar |= MII_ABILITY_100BASE_TX; 620 if (adv_10fdx) 621 anar |= MII_ABILITY_10BASE_T_FD; 622 if (adv_10hdx) 623 anar |= MII_ABILITY_10BASE_T; 624 625 if (adv_pause) 626 anar |= MII_ABILITY_PAUSE; 627 if (adv_asym_pause) 628 anar |= MII_ABILITY_ASYM_PAUSE; 629 630 /* 631 * Munge in any other fixed bits we require ... 632 */ 633 anar |= MII_AN_SELECTOR_8023; 634 635 /* 636 * Restart the PHY and write the new values. Note the 637 * time, so that we can say whether subsequent link state 638 * changes can be attributed to our reprogramming the PHY 639 */ 640 rge_phy_init(rgep); 641 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 642 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 643 rge_mii_put16(rgep, MII_CONTROL, control); 644 645 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 646 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 647 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 648 } 649 650 void rge_phy_init(rge_t *rgep); 651 #pragma no_inline(rge_phy_init) 652 653 void 654 rge_phy_init(rge_t *rgep) 655 { 656 rgep->phy_mii_addr = 1; 657 658 /* 659 * Below phy config steps are copied from the Programming Guide 660 * (there's no detail comments for these steps.) 661 */ 662 switch (rgep->chipid.mac_ver) { 663 case MAC_VER_8169S_D: 664 case MAC_VER_8169S_E : 665 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 666 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 667 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 668 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 669 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 670 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 671 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 672 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 673 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 674 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 675 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 676 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 677 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 678 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 679 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 680 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 681 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 682 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 683 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 684 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 685 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 686 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 687 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 688 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 689 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 690 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 691 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 692 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 693 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 694 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 695 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 696 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 697 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 698 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 699 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 700 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 701 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 702 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 703 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 704 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 705 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 706 break; 707 708 case MAC_VER_8169SB: 709 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 710 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 711 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 712 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 713 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 714 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 715 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 716 break; 717 718 case MAC_VER_8169SC: 719 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 720 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 721 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 722 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 723 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 724 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 725 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 726 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 727 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 728 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 729 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 730 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 731 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 732 break; 733 734 case MAC_VER_8168: 735 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 736 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 737 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 738 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 739 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 740 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 741 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 742 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 743 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 744 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 745 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 746 break; 747 748 case MAC_VER_8168B_B: 749 case MAC_VER_8168B_C: 750 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 751 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 752 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 753 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 754 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 755 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 756 break; 757 } 758 } 759 760 void rge_chip_ident(rge_t *rgep); 761 #pragma no_inline(rge_chip_ident) 762 763 void 764 rge_chip_ident(rge_t *rgep) 765 { 766 chip_id_t *chip = &rgep->chipid; 767 uint32_t val32; 768 uint16_t val16; 769 770 /* 771 * Read and record MAC version 772 */ 773 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 774 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 775 chip->mac_ver = val32; 776 switch (chip->mac_ver) { 777 case MAC_VER_8168: 778 case MAC_VER_8168B_B: 779 case MAC_VER_8168B_C: 780 chip->is_pcie = B_TRUE; 781 break; 782 783 default: 784 chip->is_pcie = B_FALSE; 785 break; 786 } 787 788 /* 789 * Read and record PHY version 790 */ 791 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 792 val16 &= PHY_VER_MASK; 793 chip->phy_ver = val16; 794 795 /* set pci latency timer */ 796 if (chip->mac_ver == MAC_VER_8169 || 797 chip->mac_ver == MAC_VER_8169S_D || 798 chip->mac_ver == MAC_VER_8169SC) 799 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 800 801 if (chip->mac_ver == MAC_VER_8169SC) { 802 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 803 val16 &= 0x0300; 804 if (val16 == 0x1) /* 66Mhz PCI */ 805 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 806 else if (val16 == 0x0) /* 33Mhz PCI */ 807 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 808 } 809 810 /* 811 * PCIE chipset require the Rx buffer start address must be 812 * 8-byte alignment and the Rx buffer size must be multiple of 8. 813 * We'll just use bcopy in receive procedure for the PCIE chipset. 814 */ 815 if (chip->is_pcie) { 816 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 817 if (rgep->default_mtu > ETHERMTU) { 818 rge_notice(rgep, "Jumbo packets not supported " 819 "for this PCIE chipset"); 820 rgep->default_mtu = ETHERMTU; 821 } 822 } 823 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 824 rgep->head_room = 0; 825 else 826 rgep->head_room = RGE_HEADROOM; 827 828 /* 829 * Initialize other variables. 830 */ 831 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 832 rgep->default_mtu = ETHERMTU; 833 if (rgep->default_mtu > ETHERMTU) { 834 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 835 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 836 rgep->ethmax_size = RGE_JUMBO_SIZE; 837 } else { 838 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 839 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 840 rgep->ethmax_size = ETHERMAX; 841 } 842 chip->rxconfig = RX_CONFIG_DEFAULT; 843 chip->txconfig = TX_CONFIG_DEFAULT; 844 845 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 846 rgep->ifname, chip->mac_ver, chip->phy_ver)); 847 } 848 849 /* 850 * Perform first-stage chip (re-)initialisation, using only config-space 851 * accesses: 852 * 853 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 854 * returning the data in the structure pointed to by <idp>. 855 * + Enable Memory Space accesses. 856 * + Enable Bus Mastering according. 857 */ 858 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 859 #pragma no_inline(rge_chip_cfg_init) 860 861 void 862 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 863 { 864 ddi_acc_handle_t handle; 865 uint16_t commd; 866 867 handle = rgep->cfg_handle; 868 869 /* 870 * Save PCI cache line size and subsystem vendor ID 871 */ 872 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 873 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 874 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 875 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 876 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 877 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 878 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 879 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 880 881 /* 882 * Turn on Master Enable (DMA) and IO Enable bits. 883 * Enable PCI Memory Space accesses 884 */ 885 commd = cidp->command; 886 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 887 pci_config_put16(handle, PCI_CONF_COMM, commd); 888 889 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 890 cidp->vendor, cidp->device, cidp->revision)); 891 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 892 cidp->subven, cidp->subdev)); 893 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 894 cidp->clsize, cidp->latency, cidp->command)); 895 } 896 897 int rge_chip_reset(rge_t *rgep); 898 #pragma no_inline(rge_chip_reset) 899 900 int 901 rge_chip_reset(rge_t *rgep) 902 { 903 int i; 904 uint8_t val8; 905 906 /* 907 * Chip should be in STOP state 908 */ 909 rge_reg_clr8(rgep, RT_COMMAND_REG, 910 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 911 912 /* 913 * Disable interrupt 914 */ 915 rgep->int_mask = INT_MASK_NONE; 916 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 917 918 /* 919 * Clear pended interrupt 920 */ 921 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 922 923 /* 924 * Reset chip 925 */ 926 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 927 928 /* 929 * Wait for reset success 930 */ 931 for (i = 0; i < CHIP_RESET_LOOP; i++) { 932 drv_usecwait(10); 933 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 934 if (!(val8 & RT_COMMAND_RESET)) { 935 rgep->rge_chip_state = RGE_CHIP_RESET; 936 return (0); 937 } 938 } 939 RGE_REPORT((rgep, "rge_chip_reset fail.")); 940 return (-1); 941 } 942 943 void rge_chip_init(rge_t *rgep); 944 #pragma no_inline(rge_chip_init) 945 946 void 947 rge_chip_init(rge_t *rgep) 948 { 949 uint32_t val32; 950 uint32_t val16; 951 uint32_t *hashp; 952 chip_id_t *chip = &rgep->chipid; 953 954 if (chip->is_pcie) { 955 /* 956 * Increase the threshold voltage of RX sensitivity 957 */ 958 if (chip->mac_ver != MAC_VER_8168) 959 rge_ephy_put16(rgep, 0x01, 0x1bd3); 960 961 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 962 val16 = 0x12<<8 | val16; 963 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 964 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 965 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 966 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 967 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 968 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 969 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 970 val32 |= 0x7000; 971 val32 &= 0xffff5fff; 972 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 973 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 974 } 975 976 /* 977 * Config MII register 978 */ 979 rgep->param_link_up = LINK_STATE_DOWN; 980 rge_phy_update(rgep); 981 982 /* 983 * Enable Rx checksum offload. 984 * Then for vlan support, we must enable receive vlan de-tagging. 985 * Otherwise, there'll be checksum error. 986 */ 987 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 988 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 989 if (chip->mac_ver == MAC_VER_8169S_D) { 990 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 991 rge_reg_put8(rgep, RESV_82_REG, 0x01); 992 } 993 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 994 995 /* 996 * Start transmit/receive before set tx/rx configuration register 997 */ 998 if (!chip->is_pcie) 999 rge_reg_set8(rgep, RT_COMMAND_REG, 1000 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1001 1002 /* 1003 * Set dump tally counter register 1004 */ 1005 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 1006 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 1007 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 1008 val32 &= DUMP_COUNTER_REG_RESV; 1009 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 1010 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 1011 1012 /* 1013 * Change to config register write enable mode 1014 */ 1015 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1016 1017 /* 1018 * Set Tx/Rx maximum packet size 1019 */ 1020 if (rgep->default_mtu > ETHERMTU) { 1021 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 1022 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 1023 } else { 1024 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 1025 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 1026 } 1027 1028 /* 1029 * Set receive configuration register 1030 */ 1031 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 1032 val32 &= RX_CONFIG_REG_RESV; 1033 if (rgep->promisc) 1034 val32 |= RX_ACCEPT_ALL_PKT; 1035 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 1036 1037 /* 1038 * Set transmit configuration register 1039 */ 1040 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 1041 val32 &= TX_CONFIG_REG_RESV; 1042 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 1043 1044 /* 1045 * Set Tx/Rx descriptor register 1046 */ 1047 val32 = rgep->tx_desc.cookie.dmac_laddress; 1048 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 1049 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 1050 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 1051 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 1052 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 1053 val32 = rgep->rx_desc.cookie.dmac_laddress; 1054 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 1055 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 1056 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 1057 1058 /* 1059 * Suggested setting from Realtek 1060 */ 1061 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1062 1063 /* 1064 * Set multicast register 1065 */ 1066 hashp = (uint32_t *)rgep->mcast_hash; 1067 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1068 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1069 1070 /* 1071 * Msic register setting: 1072 * -- Missed packet counter: clear it 1073 * -- TimerInt Register 1074 * -- Timer count register 1075 */ 1076 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1077 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1078 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1079 1080 /* 1081 * Return to normal network/host communication mode 1082 */ 1083 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1084 drv_usecwait(20); 1085 } 1086 1087 /* 1088 * rge_chip_start() -- start the chip transmitting and/or receiving, 1089 * including enabling interrupts 1090 */ 1091 void rge_chip_start(rge_t *rgep); 1092 #pragma no_inline(rge_chip_start) 1093 1094 void 1095 rge_chip_start(rge_t *rgep) 1096 { 1097 /* 1098 * Clear statistics 1099 */ 1100 bzero(&rgep->stats, sizeof (rge_stats_t)); 1101 DMA_ZERO(rgep->dma_area_stats); 1102 1103 /* 1104 * Start transmit/receive 1105 */ 1106 rge_reg_set8(rgep, RT_COMMAND_REG, 1107 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1108 1109 /* 1110 * Enable interrupt 1111 */ 1112 rgep->int_mask = RGE_INT_MASK; 1113 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1114 1115 /* 1116 * All done! 1117 */ 1118 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1119 } 1120 1121 /* 1122 * rge_chip_stop() -- stop board receiving 1123 */ 1124 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1125 #pragma no_inline(rge_chip_stop) 1126 1127 void 1128 rge_chip_stop(rge_t *rgep, boolean_t fault) 1129 { 1130 /* 1131 * Disable interrupt 1132 */ 1133 rgep->int_mask = INT_MASK_NONE; 1134 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1135 1136 /* 1137 * Clear pended interrupt 1138 */ 1139 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1140 1141 /* 1142 * Stop the board and disable transmit/receive 1143 */ 1144 rge_reg_clr8(rgep, RT_COMMAND_REG, 1145 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1146 1147 if (fault) 1148 rgep->rge_chip_state = RGE_CHIP_FAULT; 1149 else 1150 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1151 } 1152 1153 /* 1154 * rge_get_mac_addr() -- get the MAC address on NIC 1155 */ 1156 static void rge_get_mac_addr(rge_t *rgep); 1157 #pragma inline(rge_get_mac_addr) 1158 1159 static void 1160 rge_get_mac_addr(rge_t *rgep) 1161 { 1162 uint8_t *macaddr = rgep->netaddr; 1163 uint32_t val32; 1164 1165 /* 1166 * Read first 4-byte of mac address 1167 */ 1168 val32 = rge_reg_get32(rgep, ID_0_REG); 1169 macaddr[0] = val32 & 0xff; 1170 val32 = val32 >> 8; 1171 macaddr[1] = val32 & 0xff; 1172 val32 = val32 >> 8; 1173 macaddr[2] = val32 & 0xff; 1174 val32 = val32 >> 8; 1175 macaddr[3] = val32 & 0xff; 1176 1177 /* 1178 * Read last 2-byte of mac address 1179 */ 1180 val32 = rge_reg_get32(rgep, ID_4_REG); 1181 macaddr[4] = val32 & 0xff; 1182 val32 = val32 >> 8; 1183 macaddr[5] = val32 & 0xff; 1184 } 1185 1186 static void rge_set_mac_addr(rge_t *rgep); 1187 #pragma inline(rge_set_mac_addr) 1188 1189 static void 1190 rge_set_mac_addr(rge_t *rgep) 1191 { 1192 uint8_t *p = rgep->netaddr; 1193 uint32_t val32; 1194 1195 /* 1196 * Change to config register write enable mode 1197 */ 1198 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1199 1200 /* 1201 * Get first 4 bytes of mac address 1202 */ 1203 val32 = p[3]; 1204 val32 = val32 << 8; 1205 val32 |= p[2]; 1206 val32 = val32 << 8; 1207 val32 |= p[1]; 1208 val32 = val32 << 8; 1209 val32 |= p[0]; 1210 1211 /* 1212 * Set first 4 bytes of mac address 1213 */ 1214 rge_reg_put32(rgep, ID_0_REG, val32); 1215 1216 /* 1217 * Get last 2 bytes of mac address 1218 */ 1219 val32 = p[5]; 1220 val32 = val32 << 8; 1221 val32 |= p[4]; 1222 1223 /* 1224 * Set last 2 bytes of mac address 1225 */ 1226 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1227 rge_reg_put32(rgep, ID_4_REG, val32); 1228 1229 /* 1230 * Return to normal network/host communication mode 1231 */ 1232 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1233 } 1234 1235 static void rge_set_multi_addr(rge_t *rgep); 1236 #pragma inline(rge_set_multi_addr) 1237 1238 static void 1239 rge_set_multi_addr(rge_t *rgep) 1240 { 1241 uint32_t *hashp; 1242 1243 hashp = (uint32_t *)rgep->mcast_hash; 1244 1245 /* 1246 * Change to config register write enable mode 1247 */ 1248 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1249 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1250 1251 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1252 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1253 1254 /* 1255 * Return to normal network/host communication mode 1256 */ 1257 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1258 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1259 } 1260 1261 static void rge_set_promisc(rge_t *rgep); 1262 #pragma inline(rge_set_promisc) 1263 1264 static void 1265 rge_set_promisc(rge_t *rgep) 1266 { 1267 if (rgep->promisc) 1268 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1269 else 1270 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1271 } 1272 1273 /* 1274 * rge_chip_sync() -- program the chip with the unicast MAC address, 1275 * the multicast hash table, the required level of promiscuity, and 1276 * the current loopback mode ... 1277 */ 1278 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1279 #pragma no_inline(rge_chip_sync) 1280 1281 void 1282 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1283 { 1284 switch (todo) { 1285 case RGE_GET_MAC: 1286 rge_get_mac_addr(rgep); 1287 break; 1288 case RGE_SET_MAC: 1289 /* Reprogram the unicast MAC address(es) ... */ 1290 rge_set_mac_addr(rgep); 1291 break; 1292 case RGE_SET_MUL: 1293 /* Reprogram the hashed multicast address table ... */ 1294 rge_set_multi_addr(rgep); 1295 break; 1296 case RGE_SET_PROMISC: 1297 /* Set or clear the PROMISCUOUS mode bit */ 1298 rge_set_promisc(rgep); 1299 break; 1300 default: 1301 break; 1302 } 1303 } 1304 1305 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1306 #pragma no_inline(rge_chip_blank) 1307 1308 void 1309 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1310 { 1311 _NOTE(ARGUNUSED(arg, ticks, count)); 1312 } 1313 1314 void rge_tx_trigger(rge_t *rgep); 1315 #pragma no_inline(rge_tx_trigger) 1316 1317 void 1318 rge_tx_trigger(rge_t *rgep) 1319 { 1320 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1321 } 1322 1323 void rge_hw_stats_dump(rge_t *rgep); 1324 #pragma no_inline(rge_tx_trigger) 1325 1326 void 1327 rge_hw_stats_dump(rge_t *rgep) 1328 { 1329 int i = 0; 1330 1331 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1332 drv_usecwait(100); 1333 if (++i > STATS_DUMP_LOOP) { 1334 RGE_DEBUG(("rge h/w statistics dump fail!")); 1335 rgep->rge_chip_state = RGE_CHIP_ERROR; 1336 return; 1337 } 1338 } 1339 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1340 1341 /* 1342 * Start H/W statistics dump for RTL8169 chip 1343 */ 1344 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1345 } 1346 1347 /* 1348 * ========== Hardware interrupt handler ========== 1349 */ 1350 1351 #undef RGE_DBG 1352 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1353 1354 static void rge_wake_factotum(rge_t *rgep); 1355 #pragma inline(rge_wake_factotum) 1356 1357 static void 1358 rge_wake_factotum(rge_t *rgep) 1359 { 1360 if (rgep->factotum_flag == 0) { 1361 rgep->factotum_flag = 1; 1362 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1363 } 1364 } 1365 1366 /* 1367 * rge_intr() -- handle chip interrupts 1368 */ 1369 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1370 #pragma no_inline(rge_intr) 1371 1372 uint_t 1373 rge_intr(caddr_t arg1, caddr_t arg2) 1374 { 1375 rge_t *rgep = (rge_t *)arg1; 1376 uint16_t int_status; 1377 1378 _NOTE(ARGUNUSED(arg2)) 1379 1380 mutex_enter(rgep->genlock); 1381 /* 1382 * Was this interrupt caused by our device... 1383 */ 1384 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1385 if (!(int_status & rgep->int_mask)) { 1386 mutex_exit(rgep->genlock); 1387 return (DDI_INTR_UNCLAIMED); 1388 /* indicate it wasn't our interrupt */ 1389 } 1390 rgep->stats.intr++; 1391 1392 /* 1393 * Clear interrupt 1394 * For PCIE chipset, we need disable interrupt first. 1395 */ 1396 if (rgep->chipid.is_pcie) 1397 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1398 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1399 1400 /* 1401 * Cable link change interrupt 1402 */ 1403 if (int_status & LINK_CHANGE_INT) { 1404 rge_chip_cyclic(rgep); 1405 } 1406 1407 mutex_exit(rgep->genlock); 1408 1409 /* 1410 * Receive interrupt 1411 */ 1412 if (int_status & RGE_RX_INT) 1413 rge_receive(rgep); 1414 1415 /* 1416 * Re-enable interrupt for PCIE chipset 1417 */ 1418 if (rgep->chipid.is_pcie) 1419 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1420 1421 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1422 } 1423 1424 /* 1425 * ========== Factotum, implemented as a softint handler ========== 1426 */ 1427 1428 #undef RGE_DBG 1429 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1430 1431 static boolean_t rge_factotum_link_check(rge_t *rgep); 1432 #pragma no_inline(rge_factotum_link_check) 1433 1434 static boolean_t 1435 rge_factotum_link_check(rge_t *rgep) 1436 { 1437 uint8_t media_status; 1438 int32_t link; 1439 1440 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1441 link = (media_status & PHY_STATUS_LINK_UP) ? 1442 LINK_STATE_UP : LINK_STATE_DOWN; 1443 if (rgep->param_link_up != link) { 1444 /* 1445 * Link change. 1446 */ 1447 rgep->param_link_up = link; 1448 1449 if (link == LINK_STATE_UP) { 1450 if (media_status & PHY_STATUS_1000MF) { 1451 rgep->param_link_speed = RGE_SPEED_1000M; 1452 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1453 } else { 1454 rgep->param_link_speed = 1455 (media_status & PHY_STATUS_100M) ? 1456 RGE_SPEED_100M : RGE_SPEED_10M; 1457 rgep->param_link_duplex = 1458 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1459 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1460 } 1461 } 1462 return (B_TRUE); 1463 } 1464 return (B_FALSE); 1465 } 1466 1467 /* 1468 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1469 */ 1470 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1471 #pragma no_inline(rge_factotum_stall_check) 1472 1473 static boolean_t 1474 rge_factotum_stall_check(rge_t *rgep) 1475 { 1476 uint32_t dogval; 1477 1478 ASSERT(mutex_owned(rgep->genlock)); 1479 1480 /* 1481 * Specific check for Tx stall ... 1482 * 1483 * The 'watchdog' counter is incremented whenever a packet 1484 * is queued, reset to 1 when some (but not all) buffers 1485 * are reclaimed, reset to 0 (disabled) when all buffers 1486 * are reclaimed, and shifted left here. If it exceeds the 1487 * threshold value, the chip is assumed to have stalled and 1488 * is put into the ERROR state. The factotum will then reset 1489 * it on the next pass. 1490 * 1491 * All of which should ensure that we don't get into a state 1492 * where packets are left pending indefinitely! 1493 */ 1494 if (rgep->resched_needed) 1495 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1496 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1497 if (dogval < rge_watchdog_count) 1498 return (B_FALSE); 1499 1500 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1501 return (B_TRUE); 1502 1503 } 1504 1505 /* 1506 * The factotum is woken up when there's something to do that we'd rather 1507 * not do from inside a hardware interrupt handler or high-level cyclic. 1508 * Its two main tasks are: 1509 * reset & restart the chip after an error 1510 * check the link status whenever necessary 1511 */ 1512 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1513 #pragma no_inline(rge_chip_factotum) 1514 1515 uint_t 1516 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1517 { 1518 rge_t *rgep; 1519 uint_t result; 1520 boolean_t error; 1521 boolean_t linkchg; 1522 1523 rgep = (rge_t *)arg1; 1524 _NOTE(ARGUNUSED(arg2)) 1525 1526 if (rgep->factotum_flag == 0) 1527 return (DDI_INTR_UNCLAIMED); 1528 1529 rgep->factotum_flag = 0; 1530 result = DDI_INTR_CLAIMED; 1531 error = B_FALSE; 1532 linkchg = B_FALSE; 1533 1534 mutex_enter(rgep->genlock); 1535 switch (rgep->rge_chip_state) { 1536 default: 1537 break; 1538 1539 case RGE_CHIP_RUNNING: 1540 linkchg = rge_factotum_link_check(rgep); 1541 error = rge_factotum_stall_check(rgep); 1542 break; 1543 1544 case RGE_CHIP_ERROR: 1545 error = B_TRUE; 1546 break; 1547 1548 case RGE_CHIP_FAULT: 1549 /* 1550 * Fault detected, time to reset ... 1551 */ 1552 if (rge_autorecover) { 1553 RGE_REPORT((rgep, "automatic recovery activated")); 1554 rge_restart(rgep); 1555 } 1556 break; 1557 } 1558 1559 /* 1560 * If an error is detected, stop the chip now, marking it as 1561 * faulty, so that it will be reset next time through ... 1562 */ 1563 if (error) 1564 rge_chip_stop(rgep, B_TRUE); 1565 mutex_exit(rgep->genlock); 1566 1567 /* 1568 * If the link state changed, tell the world about it. 1569 * Note: can't do this while still holding the mutex. 1570 */ 1571 if (linkchg) 1572 mac_link_update(rgep->mh, rgep->param_link_up); 1573 1574 return (result); 1575 } 1576 1577 /* 1578 * High-level cyclic handler 1579 * 1580 * This routine schedules a (low-level) softint callback to the 1581 * factotum, and prods the chip to update the status block (which 1582 * will cause a hardware interrupt when complete). 1583 */ 1584 void rge_chip_cyclic(void *arg); 1585 #pragma no_inline(rge_chip_cyclic) 1586 1587 void 1588 rge_chip_cyclic(void *arg) 1589 { 1590 rge_t *rgep; 1591 1592 rgep = arg; 1593 1594 switch (rgep->rge_chip_state) { 1595 default: 1596 return; 1597 1598 case RGE_CHIP_RUNNING: 1599 rge_phy_check(rgep); 1600 break; 1601 1602 case RGE_CHIP_FAULT: 1603 case RGE_CHIP_ERROR: 1604 break; 1605 } 1606 1607 rge_wake_factotum(rgep); 1608 } 1609 1610 1611 /* 1612 * ========== Ioctl subfunctions ========== 1613 */ 1614 1615 #undef RGE_DBG 1616 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1617 1618 #if RGE_DEBUGGING || RGE_DO_PPIO 1619 1620 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1621 #pragma no_inline(rge_chip_peek_cfg) 1622 1623 static void 1624 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1625 { 1626 uint64_t regval; 1627 uint64_t regno; 1628 1629 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1630 (void *)rgep, (void *)ppd)); 1631 1632 regno = ppd->pp_acc_offset; 1633 1634 switch (ppd->pp_acc_size) { 1635 case 1: 1636 regval = pci_config_get8(rgep->cfg_handle, regno); 1637 break; 1638 1639 case 2: 1640 regval = pci_config_get16(rgep->cfg_handle, regno); 1641 break; 1642 1643 case 4: 1644 regval = pci_config_get32(rgep->cfg_handle, regno); 1645 break; 1646 1647 case 8: 1648 regval = pci_config_get64(rgep->cfg_handle, regno); 1649 break; 1650 } 1651 1652 ppd->pp_acc_data = regval; 1653 } 1654 1655 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1656 #pragma no_inline(rge_chip_poke_cfg) 1657 1658 static void 1659 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1660 { 1661 uint64_t regval; 1662 uint64_t regno; 1663 1664 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1665 (void *)rgep, (void *)ppd)); 1666 1667 regno = ppd->pp_acc_offset; 1668 regval = ppd->pp_acc_data; 1669 1670 switch (ppd->pp_acc_size) { 1671 case 1: 1672 pci_config_put8(rgep->cfg_handle, regno, regval); 1673 break; 1674 1675 case 2: 1676 pci_config_put16(rgep->cfg_handle, regno, regval); 1677 break; 1678 1679 case 4: 1680 pci_config_put32(rgep->cfg_handle, regno, regval); 1681 break; 1682 1683 case 8: 1684 pci_config_put64(rgep->cfg_handle, regno, regval); 1685 break; 1686 } 1687 } 1688 1689 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1690 #pragma no_inline(rge_chip_peek_reg) 1691 1692 static void 1693 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1694 { 1695 uint64_t regval; 1696 void *regaddr; 1697 1698 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1699 (void *)rgep, (void *)ppd)); 1700 1701 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1702 1703 switch (ppd->pp_acc_size) { 1704 case 1: 1705 regval = ddi_get8(rgep->io_handle, regaddr); 1706 break; 1707 1708 case 2: 1709 regval = ddi_get16(rgep->io_handle, regaddr); 1710 break; 1711 1712 case 4: 1713 regval = ddi_get32(rgep->io_handle, regaddr); 1714 break; 1715 1716 case 8: 1717 regval = ddi_get64(rgep->io_handle, regaddr); 1718 break; 1719 } 1720 1721 ppd->pp_acc_data = regval; 1722 } 1723 1724 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1725 #pragma no_inline(rge_chip_peek_reg) 1726 1727 static void 1728 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1729 { 1730 uint64_t regval; 1731 void *regaddr; 1732 1733 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1734 (void *)rgep, (void *)ppd)); 1735 1736 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1737 regval = ppd->pp_acc_data; 1738 1739 switch (ppd->pp_acc_size) { 1740 case 1: 1741 ddi_put8(rgep->io_handle, regaddr, regval); 1742 break; 1743 1744 case 2: 1745 ddi_put16(rgep->io_handle, regaddr, regval); 1746 break; 1747 1748 case 4: 1749 ddi_put32(rgep->io_handle, regaddr, regval); 1750 break; 1751 1752 case 8: 1753 ddi_put64(rgep->io_handle, regaddr, regval); 1754 break; 1755 } 1756 RGE_PCICHK(rgep); 1757 } 1758 1759 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1760 #pragma no_inline(rge_chip_peek_mii) 1761 1762 static void 1763 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1764 { 1765 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1766 (void *)rgep, (void *)ppd)); 1767 1768 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1769 } 1770 1771 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1772 #pragma no_inline(rge_chip_poke_mii) 1773 1774 static void 1775 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1776 { 1777 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1778 (void *)rgep, (void *)ppd)); 1779 1780 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1781 } 1782 1783 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1784 #pragma no_inline(rge_chip_peek_mem) 1785 1786 static void 1787 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1788 { 1789 uint64_t regval; 1790 void *vaddr; 1791 1792 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1793 (void *)rgep, (void *)ppd)); 1794 1795 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1796 1797 switch (ppd->pp_acc_size) { 1798 case 1: 1799 regval = *(uint8_t *)vaddr; 1800 break; 1801 1802 case 2: 1803 regval = *(uint16_t *)vaddr; 1804 break; 1805 1806 case 4: 1807 regval = *(uint32_t *)vaddr; 1808 break; 1809 1810 case 8: 1811 regval = *(uint64_t *)vaddr; 1812 break; 1813 } 1814 1815 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1816 (void *)rgep, (void *)ppd, regval, vaddr)); 1817 1818 ppd->pp_acc_data = regval; 1819 } 1820 1821 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1822 #pragma no_inline(rge_chip_poke_mem) 1823 1824 static void 1825 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1826 { 1827 uint64_t regval; 1828 void *vaddr; 1829 1830 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1831 (void *)rgep, (void *)ppd)); 1832 1833 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1834 regval = ppd->pp_acc_data; 1835 1836 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1837 (void *)rgep, (void *)ppd, regval, vaddr)); 1838 1839 switch (ppd->pp_acc_size) { 1840 case 1: 1841 *(uint8_t *)vaddr = (uint8_t)regval; 1842 break; 1843 1844 case 2: 1845 *(uint16_t *)vaddr = (uint16_t)regval; 1846 break; 1847 1848 case 4: 1849 *(uint32_t *)vaddr = (uint32_t)regval; 1850 break; 1851 1852 case 8: 1853 *(uint64_t *)vaddr = (uint64_t)regval; 1854 break; 1855 } 1856 } 1857 1858 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1859 struct iocblk *iocp); 1860 #pragma no_inline(rge_pp_ioctl) 1861 1862 static enum ioc_reply 1863 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1864 { 1865 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1866 rge_peekpoke_t *ppd; 1867 dma_area_t *areap; 1868 uint64_t sizemask; 1869 uint64_t mem_va; 1870 uint64_t maxoff; 1871 boolean_t peek; 1872 1873 switch (cmd) { 1874 default: 1875 /* NOTREACHED */ 1876 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1877 return (IOC_INVAL); 1878 1879 case RGE_PEEK: 1880 peek = B_TRUE; 1881 break; 1882 1883 case RGE_POKE: 1884 peek = B_FALSE; 1885 break; 1886 } 1887 1888 /* 1889 * Validate format of ioctl 1890 */ 1891 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1892 return (IOC_INVAL); 1893 if (mp->b_cont == NULL) 1894 return (IOC_INVAL); 1895 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1896 1897 /* 1898 * Validate request parameters 1899 */ 1900 switch (ppd->pp_acc_space) { 1901 default: 1902 return (IOC_INVAL); 1903 1904 case RGE_PP_SPACE_CFG: 1905 /* 1906 * Config space 1907 */ 1908 sizemask = 8|4|2|1; 1909 mem_va = 0; 1910 maxoff = PCI_CONF_HDR_SIZE; 1911 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1912 break; 1913 1914 case RGE_PP_SPACE_REG: 1915 /* 1916 * Memory-mapped I/O space 1917 */ 1918 sizemask = 8|4|2|1; 1919 mem_va = 0; 1920 maxoff = RGE_REGISTER_MAX; 1921 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1922 break; 1923 1924 case RGE_PP_SPACE_MII: 1925 /* 1926 * PHY's MII registers 1927 * NB: all PHY registers are two bytes, but the 1928 * addresses increment in ones (word addressing). 1929 * So we scale the address here, then undo the 1930 * transformation inside the peek/poke functions. 1931 */ 1932 ppd->pp_acc_offset *= 2; 1933 sizemask = 2; 1934 mem_va = 0; 1935 maxoff = (MII_MAXREG+1)*2; 1936 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1937 break; 1938 1939 case RGE_PP_SPACE_RGE: 1940 /* 1941 * RGE data structure! 1942 */ 1943 sizemask = 8|4|2|1; 1944 mem_va = (uintptr_t)rgep; 1945 maxoff = sizeof (*rgep); 1946 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1947 break; 1948 1949 case RGE_PP_SPACE_STATISTICS: 1950 case RGE_PP_SPACE_TXDESC: 1951 case RGE_PP_SPACE_TXBUFF: 1952 case RGE_PP_SPACE_RXDESC: 1953 case RGE_PP_SPACE_RXBUFF: 1954 /* 1955 * Various DMA_AREAs 1956 */ 1957 switch (ppd->pp_acc_space) { 1958 case RGE_PP_SPACE_TXDESC: 1959 areap = &rgep->dma_area_txdesc; 1960 break; 1961 case RGE_PP_SPACE_RXDESC: 1962 areap = &rgep->dma_area_rxdesc; 1963 break; 1964 case RGE_PP_SPACE_STATISTICS: 1965 areap = &rgep->dma_area_stats; 1966 break; 1967 } 1968 1969 sizemask = 8|4|2|1; 1970 mem_va = (uintptr_t)areap->mem_va; 1971 maxoff = areap->alength; 1972 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1973 break; 1974 } 1975 1976 switch (ppd->pp_acc_size) { 1977 default: 1978 return (IOC_INVAL); 1979 1980 case 8: 1981 case 4: 1982 case 2: 1983 case 1: 1984 if ((ppd->pp_acc_size & sizemask) == 0) 1985 return (IOC_INVAL); 1986 break; 1987 } 1988 1989 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1990 return (IOC_INVAL); 1991 1992 if (ppd->pp_acc_offset >= maxoff) 1993 return (IOC_INVAL); 1994 1995 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1996 return (IOC_INVAL); 1997 1998 /* 1999 * All OK - go do it! 2000 */ 2001 ppd->pp_acc_offset += mem_va; 2002 (*ppfn)(rgep, ppd); 2003 return (peek ? IOC_REPLY : IOC_ACK); 2004 } 2005 2006 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2007 struct iocblk *iocp); 2008 #pragma no_inline(rge_diag_ioctl) 2009 2010 static enum ioc_reply 2011 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2012 { 2013 ASSERT(mutex_owned(rgep->genlock)); 2014 2015 switch (cmd) { 2016 default: 2017 /* NOTREACHED */ 2018 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 2019 return (IOC_INVAL); 2020 2021 case RGE_DIAG: 2022 /* 2023 * Currently a no-op 2024 */ 2025 return (IOC_ACK); 2026 2027 case RGE_PEEK: 2028 case RGE_POKE: 2029 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 2030 2031 case RGE_PHY_RESET: 2032 return (IOC_RESTART_ACK); 2033 2034 case RGE_SOFT_RESET: 2035 case RGE_HARD_RESET: 2036 /* 2037 * Reset and reinitialise the 570x hardware 2038 */ 2039 rge_restart(rgep); 2040 return (IOC_ACK); 2041 } 2042 2043 /* NOTREACHED */ 2044 } 2045 2046 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2047 2048 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2049 struct iocblk *iocp); 2050 #pragma no_inline(rge_mii_ioctl) 2051 2052 static enum ioc_reply 2053 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2054 { 2055 struct rge_mii_rw *miirwp; 2056 2057 /* 2058 * Validate format of ioctl 2059 */ 2060 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2061 return (IOC_INVAL); 2062 if (mp->b_cont == NULL) 2063 return (IOC_INVAL); 2064 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2065 2066 /* 2067 * Validate request parameters ... 2068 */ 2069 if (miirwp->mii_reg > MII_MAXREG) 2070 return (IOC_INVAL); 2071 2072 switch (cmd) { 2073 default: 2074 /* NOTREACHED */ 2075 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2076 return (IOC_INVAL); 2077 2078 case RGE_MII_READ: 2079 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2080 return (IOC_REPLY); 2081 2082 case RGE_MII_WRITE: 2083 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2084 return (IOC_ACK); 2085 } 2086 2087 /* NOTREACHED */ 2088 } 2089 2090 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2091 struct iocblk *iocp); 2092 #pragma no_inline(rge_chip_ioctl) 2093 2094 enum ioc_reply 2095 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2096 { 2097 int cmd; 2098 2099 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2100 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2101 2102 ASSERT(mutex_owned(rgep->genlock)); 2103 2104 cmd = iocp->ioc_cmd; 2105 switch (cmd) { 2106 default: 2107 /* NOTREACHED */ 2108 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2109 return (IOC_INVAL); 2110 2111 case RGE_DIAG: 2112 case RGE_PEEK: 2113 case RGE_POKE: 2114 case RGE_PHY_RESET: 2115 case RGE_SOFT_RESET: 2116 case RGE_HARD_RESET: 2117 #if RGE_DEBUGGING || RGE_DO_PPIO 2118 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2119 #else 2120 return (IOC_INVAL); 2121 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2122 2123 case RGE_MII_READ: 2124 case RGE_MII_WRITE: 2125 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2126 2127 } 2128 2129 /* NOTREACHED */ 2130 } 2131