1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/syshw.h> 88 #include "cardbus/cardbus.h" 89 90 #define SOFTC_SIZE (sizeof (anp_t)) 91 92 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 93 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 94 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 95 static uint_t pcic_intr(caddr_t, caddr_t); 96 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 97 static int pcic_probe(dev_info_t *); 98 99 static int pcic_open(dev_t *, int, int, cred_t *); 100 static int pcic_close(dev_t, int, int, cred_t *); 101 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 102 103 typedef struct pcm_regs pcm_regs_t; 104 105 static void pcic_init_assigned(dev_info_t *); 106 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 107 pci_regspec_t *, int); 108 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 109 110 /* 111 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 112 * are xlated into DMA ctlops. To make this nexus work on x86, we 113 * need to have the default ddi_dma_mctl ctlops in the bus_ops 114 * structure, just to pass the request to the parent. The correct 115 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 116 */ 117 static 118 struct bus_ops pcmciabus_ops = { 119 BUSO_REV, 120 pcmcia_bus_map, 121 NULL, 122 NULL, 123 NULL, 124 i_ddi_map_fault, 125 ddi_no_dma_map, 126 ddi_no_dma_allochdl, 127 ddi_no_dma_freehdl, 128 ddi_no_dma_bindhdl, 129 ddi_no_dma_unbindhdl, 130 ddi_no_dma_flush, 131 ddi_no_dma_win, 132 ddi_dma_mctl, 133 pcmcia_ctlops, 134 pcmcia_prop_op, 135 NULL, /* (*bus_get_eventcookie)(); */ 136 NULL, /* (*bus_add_eventcall)(); */ 137 NULL, /* (*bus_remove_eventcall)(); */ 138 NULL, /* (*bus_post_event)(); */ 139 NULL, /* (*bus_intr_ctl)(); */ 140 NULL, /* (*bus_config)(); */ 141 NULL, /* (*bus_unconfig)(); */ 142 NULL, /* (*bus_fm_init)(); */ 143 NULL, /* (*bus_fm_fini)(); */ 144 NULL, /* (*bus_enter)() */ 145 NULL, /* (*bus_exit)() */ 146 NULL, /* (*bus_power)() */ 147 pcmcia_intr_ops /* (*bus_intr_op)(); */ 148 }; 149 150 static struct cb_ops pcic_cbops = { 151 pcic_open, 152 pcic_close, 153 nodev, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 pcic_ioctl, 159 nodev, 160 nodev, 161 nodev, 162 nochpoll, 163 ddi_prop_op, 164 NULL, 165 #ifdef CARDBUS 166 D_NEW | D_MP | D_HOTPLUG 167 #else 168 D_NEW | D_MP 169 #endif 170 }; 171 172 static struct dev_ops pcic_devops = { 173 DEVO_REV, 174 0, 175 pcic_getinfo, 176 nulldev, 177 pcic_probe, 178 pcic_attach, 179 pcic_detach, 180 nulldev, 181 &pcic_cbops, 182 &pcmciabus_ops, 183 NULL 184 }; 185 186 void *pcic_soft_state_p = NULL; 187 static int pcic_maxinst = -1; 188 static timeout_id_t pcic_delayed_resume_toid; 189 190 int pcic_do_insertion = 1; 191 int pcic_do_removal = 1; 192 193 struct irqmap { 194 int irq; 195 int count; 196 } pcic_irq_map[16]; 197 198 199 int pcic_debug = 0x0; 200 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 201 extern void cardbus_dump_pci_config(dev_info_t *dip); 202 extern void cardbus_dump_socket(dev_info_t *dip); 203 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 204 static void pcic_dump_debqueue(char *msg); 205 206 #if defined(PCIC_DEBUG) 207 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 208 209 #define pcic_mutex_enter(a) \ 210 { \ 211 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 212 mutex_enter(a); \ 213 }; 214 215 #define pcic_mutex_exit(a) \ 216 { \ 217 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 218 mutex_exit(a); \ 219 }; 220 221 #else 222 #define pcic_mutex_enter(a) mutex_enter(a) 223 #define pcic_mutex_exit(a) mutex_exit(a) 224 #endif 225 226 #define PCIC_VCC_3VLEVEL 1 227 #define PCIC_VCC_5VLEVEL 2 228 #define PCIC_VCC_12LEVEL 3 229 230 /* bit patterns to select voltage levels */ 231 int pcic_vpp_levels[13] = { 232 0, 0, 0, 233 1, /* 3.3V */ 234 0, 235 1, /* 5V */ 236 0, 0, 0, 0, 0, 0, 237 2 /* 12V */ 238 }; 239 240 uint8_t pcic_cbv_levels[13] = { 241 0, 0, 0, 242 3, /* 3.3V */ 243 0, 244 2, /* 5V */ 245 0, 0, 0, 0, 0, 0, 246 1 /* 12V */ 247 }; 248 249 struct power_entry pcic_power[4] = { 250 { 251 0, VCC|VPP1|VPP2 252 }, 253 { 254 33, /* 3.3Volt */ 255 VCC|VPP1|VPP2 256 }, 257 { 258 5*10, /* 5Volt */ 259 VCC|VPP1|VPP2 /* currently only know about this */ 260 }, 261 { 262 12*10, /* 12Volt */ 263 VPP1|VPP2 264 } 265 }; 266 267 /* 268 * Base used to allocate ranges of PCI memory on x86 systems 269 * Each instance gets a chunk above the base that is used to map 270 * in the memory and I/O windows for that device. 271 * Pages below the base are also allocated for the EXCA registers, 272 * one per instance. 273 */ 274 #define PCIC_PCI_MEMCHUNK 0x1000000 275 276 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 277 static int pcic_debounce_time = 200000; /* In micro-seconds */ 278 279 struct debounce { 280 pcic_socket_t *pcs; 281 clock_t expire; 282 struct debounce *next; 283 }; 284 285 static syshw_t pcic_syshw = { 286 0, "PC Card Socket 0", SH_CONNECTION, 287 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID|SYSHW_VAL0_VALID, 288 B_FALSE, {2, 0, 0, 0} 289 }; 290 291 static struct debounce *pcic_deb_queue = NULL; 292 static kmutex_t pcic_deb_mtx; 293 static kcondvar_t pcic_deb_cv; 294 static kthread_t *pcic_deb_threadid; 295 296 static inthandler_t *pcic_handlers; 297 298 static void pcic_setup_adapter(pcicdev_t *); 299 static int pcic_change(pcicdev_t *, int); 300 static int pcic_ll_reset(pcicdev_t *, int); 301 static void pcic_mswait(pcicdev_t *, int, int); 302 static boolean_t pcic_check_ready(pcicdev_t *, int); 303 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 304 static void pcic_ready_wait(pcicdev_t *, int); 305 extern int pcmcia_get_intr(dev_info_t *, int); 306 extern int pcmcia_return_intr(dev_info_t *, int); 307 308 static int pcic_callback(dev_info_t *, int (*)(), int); 309 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 310 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 311 static int pcic_get_page(dev_info_t *, get_page_t *); 312 static int pcic_get_socket(dev_info_t *, get_socket_t *); 313 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 314 static int pcic_get_window(dev_info_t *, get_window_t *); 315 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 316 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 317 static int pcic_reset_socket(dev_info_t *, int, int); 318 static int pcic_set_page(dev_info_t *, set_page_t *); 319 static int pcic_set_window(dev_info_t *, set_window_t *); 320 static int pcic_set_socket(dev_info_t *, set_socket_t *); 321 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 322 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 323 static void pcic_pm_detection(void *); 324 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 325 static int clext_reg_read(pcicdev_t *, int, uchar_t); 326 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 327 static int pcic_calc_speed(pcicdev_t *, uint32_t); 328 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 329 static int pcic_find_pci_type(pcicdev_t *); 330 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 331 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 332 static uint_t pcic_cd_softint(caddr_t, caddr_t); 333 static uint8_t pcic_getb(pcicdev_t *, int, int); 334 static void pcic_putb(pcicdev_t *, int, int, int8_t); 335 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 336 static uint_t pcic_softintr(caddr_t, caddr_t); 337 338 static void pcic_debounce(pcic_socket_t *); 339 static void pcic_delayed_resume(void *); 340 static void *pcic_add_debqueue(pcic_socket_t *, int); 341 static void pcic_rm_debqueue(void *); 342 static void pcic_deb_thread(); 343 344 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 345 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 347 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 348 static void pcic_cb_enable_intr(dev_info_t *); 349 static void pcic_cb_disable_intr(dev_info_t *); 350 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 351 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 352 353 static cb_nexus_cb_t pcic_cbnexus_ops = { 354 pcic_cb_enable_intr, 355 pcic_cb_disable_intr 356 }; 357 358 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 359 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 360 361 static void pcic_syshw_cardstate(syshw_t *, void *); 362 363 #if defined(__sparc) 364 static int pcic_fault(enum pci_fault_ops op, void *arg); 365 #endif 366 367 /* 368 * Default to support for Voyager IIi if sparc is defined. 369 * Appart from the PCI base addresses this only effect the TI1250. 370 */ 371 #if defined(sparc) 372 #define VOYAGER 373 #endif 374 375 376 /* 377 * pcmcia_attach() uses 0 and 128 upwards for the initpcmcia and devctl 378 * interfaces so we use 254. 379 */ 380 #define SYSHW_MINOR 254 381 382 /* 383 * Forward declarations for syshw interface (See end of file). 384 */ 385 static void syshw_attach(pcicdev_t *); 386 static void syshw_detach(pcicdev_t *); 387 static void syshw_resume(pcicdev_t *); 388 389 #ifdef VOYAGER 390 static uint_t syshw_intr(caddr_t); 391 static uint_t syshw_intr_hi(pcicdev_t *); 392 #endif 393 394 static int syshw_open(dev_t *, int, int, cred_t *); 395 static int syshw_close(dev_t, int, int, cred_t *); 396 static int syshw_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 397 static uint32_t syshw_add2map(syshw_t *, void (*)(syshw_t *, void *), void *); 398 static void syshw_send_signal(int); 399 400 /* 401 * pcmcia interface operations structure 402 * this is the private interface that is exported to the nexus 403 */ 404 pcmcia_if_t pcic_if_ops = { 405 PCIF_MAGIC, 406 PCIF_VERSION, 407 pcic_callback, 408 pcic_get_adapter, 409 pcic_get_page, 410 pcic_get_socket, 411 pcic_get_status, 412 pcic_get_window, 413 pcic_inquire_adapter, 414 pcic_inquire_socket, 415 pcic_inquire_window, 416 pcic_reset_socket, 417 pcic_set_page, 418 pcic_set_window, 419 pcic_set_socket, 420 pcic_set_interrupt, 421 pcic_clear_interrupt, 422 NULL, 423 }; 424 425 /* 426 * chip type identification routines 427 * this list of functions is searched until one of them succeeds 428 * or all fail. i82365SL is assumed if failed. 429 */ 430 static int pcic_ci_cirrus(pcicdev_t *); 431 static int pcic_ci_vadem(pcicdev_t *); 432 static int pcic_ci_ricoh(pcicdev_t *); 433 434 int (*pcic_ci_funcs[])(pcicdev_t *) = { 435 pcic_ci_cirrus, 436 pcic_ci_vadem, 437 pcic_ci_ricoh, 438 NULL 439 }; 440 441 static struct modldrv modldrv = { 442 &mod_driverops, /* Type of module. This one is a driver */ 443 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 444 &pcic_devops, /* driver ops */ 445 }; 446 447 static struct modlinkage modlinkage = { 448 MODREV_1, (void *)&modldrv, NULL 449 }; 450 451 int 452 _init() 453 { 454 int stat; 455 456 /* Allocate soft state */ 457 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 458 SOFTC_SIZE, 2)) != DDI_SUCCESS) 459 return (stat); 460 461 if ((stat = mod_install(&modlinkage)) != 0) 462 ddi_soft_state_fini(&pcic_soft_state_p); 463 464 return (stat); 465 } 466 467 int 468 _fini() 469 { 470 int stat = 0; 471 472 if ((stat = mod_remove(&modlinkage)) != 0) 473 return (stat); 474 475 if (pcic_deb_threadid) { 476 mutex_enter(&pcic_deb_mtx); 477 pcic_deb_threadid = 0; 478 while (!pcic_deb_threadid) 479 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 480 pcic_deb_threadid = 0; 481 mutex_exit(&pcic_deb_mtx); 482 483 mutex_destroy(&pcic_deb_mtx); 484 cv_destroy(&pcic_deb_cv); 485 } 486 487 ddi_soft_state_fini(&pcic_soft_state_p); 488 489 return (stat); 490 } 491 492 int 493 _info(struct modinfo *modinfop) 494 { 495 return (mod_info(&modlinkage, modinfop)); 496 } 497 498 /* 499 * pcic_getinfo() 500 * provide instance/device information about driver 501 */ 502 /*ARGSUSED*/ 503 static int 504 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 505 { 506 anp_t *anp; 507 int error = DDI_SUCCESS; 508 minor_t minor; 509 510 switch (cmd) { 511 case DDI_INFO_DEVT2DEVINFO: 512 minor = getminor((dev_t)arg); 513 if (minor == SYSHW_MINOR) 514 minor = 0; 515 else 516 minor &= 0x7f; 517 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 518 *result = NULL; 519 else 520 *result = anp->an_dip; 521 break; 522 case DDI_INFO_DEVT2INSTANCE: 523 minor = getminor((dev_t)arg); 524 if (minor == SYSHW_MINOR) 525 minor = 0; 526 else 527 minor &= 0x7f; 528 *result = (void *)((long)minor); 529 break; 530 default: 531 error = DDI_FAILURE; 532 break; 533 } 534 return (error); 535 } 536 537 static int 538 pcic_probe(dev_info_t *dip) 539 { 540 int value; 541 ddi_device_acc_attr_t attr; 542 ddi_acc_handle_t handle; 543 uchar_t *index, *data; 544 545 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 546 return (DDI_PROBE_DONTCARE); 547 548 /* 549 * find a PCIC device (any vendor) 550 * while there can be up to 4 such devices in 551 * a system, we currently only look for 1 552 * per probe. There will be up to 2 chips per 553 * instance since they share I/O space 554 */ 555 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 556 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 557 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 558 559 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 560 (caddr_t *)&index, 561 PCIC_ISA_CONTROL_REG_OFFSET, 562 PCIC_ISA_CONTROL_REG_LENGTH, 563 &attr, &handle) != DDI_SUCCESS) 564 return (DDI_PROBE_FAILURE); 565 566 data = index + 1; 567 568 #if defined(PCIC_DEBUG) 569 if (pcic_debug) 570 cmn_err(CE_CONT, "pcic_probe: entered\n"); 571 if (pcic_debug) 572 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 573 #endif 574 ddi_put8(handle, index, PCIC_CHIP_REVISION); 575 ddi_put8(handle, data, 0); 576 value = ddi_get8(handle, data); 577 #if defined(PCIC_DEBUG) 578 if (pcic_debug) 579 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 580 #endif 581 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 582 (value & 0x30) == 0) { 583 /* 584 * we probably have a PCIC chip in the system 585 * do a little more checking. If we find one, 586 * reset everything in case of softboot 587 */ 588 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 589 ddi_put8(handle, data, 0); 590 value = ddi_get8(handle, data); 591 #if defined(PCIC_DEBUG) 592 if (pcic_debug) 593 cmn_err(CE_CONT, "\tzero test = %x\n", value); 594 #endif 595 /* should read back as zero */ 596 if (value == 0) { 597 /* 598 * we do have one and it is off the bus 599 */ 600 #if defined(PCIC_DEBUG) 601 if (pcic_debug) 602 cmn_err(CE_CONT, "pcic_probe: success\n"); 603 #endif 604 ddi_regs_map_free(&handle); 605 return (DDI_PROBE_SUCCESS); 606 } 607 } 608 #if defined(PCIC_DEBUG) 609 if (pcic_debug) 610 cmn_err(CE_CONT, "pcic_probe: failed\n"); 611 #endif 612 ddi_regs_map_free(&handle); 613 return (DDI_PROBE_FAILURE); 614 } 615 616 /* 617 * These are just defaults they can also be changed via a property in the 618 * conf file. 619 */ 620 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 621 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 622 static int pcic_do_pcmcia_sr = 0; 623 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 624 625 /* 626 * enable insertion/removal interrupt for 32bit cards 627 */ 628 static int 629 cardbus_enable_cd_intr(dev_info_t *dip) 630 { 631 ddi_acc_handle_t iohandle; 632 caddr_t ioaddr; 633 ddi_device_acc_attr_t attr; 634 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 635 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 636 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 637 (void) ddi_regs_map_setup(dip, 1, 638 (caddr_t *)&ioaddr, 639 0, 640 4096, 641 &attr, &iohandle); 642 643 /* CSC Interrupt: Card detect interrupt on */ 644 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 645 ddi_get32(iohandle, 646 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 647 648 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 649 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 650 651 ddi_regs_map_free(&iohandle); 652 return (1); 653 } 654 655 /* 656 * pcic_attach() 657 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 658 * to the system. This is a child of "sysbus" since that is where 659 * the hardware lives, but it provides services to the "pcmcia" 660 * nexus driver. It gives a pointer back via its private data 661 * structure which contains both the dip and socket services entry 662 * points 663 */ 664 static int 665 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 666 { 667 anp_t *pcic_nexus; 668 pcicdev_t *pcic; 669 int irqlevel, value; 670 int pci_cfrn, pci_ctrn; 671 int i, j, smi, actual; 672 char *typename; 673 char bus_type[16] = "(unknown)"; 674 int len = sizeof (bus_type); 675 ddi_device_acc_attr_t attr; 676 anp_t *anp = ddi_get_driver_private(dip); 677 uint_t pri; 678 syshw_t *shwp; 679 680 #if defined(PCIC_DEBUG) 681 if (pcic_debug) { 682 cmn_err(CE_CONT, "pcic_attach: entered\n"); 683 } 684 #endif 685 switch (cmd) { 686 case DDI_ATTACH: 687 break; 688 case DDI_RESUME: 689 pcic = anp->an_private; 690 /* 691 * for now, this is a simulated resume. 692 * a real one may need different things. 693 */ 694 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 695 mutex_enter(&pcic->pc_lock); 696 /* should probe for new sockets showing up */ 697 pcic_setup_adapter(pcic); 698 syshw_resume(pcic); 699 pcic->pc_flags &= ~PCF_SUSPENDED; 700 mutex_exit(&pcic->pc_lock); 701 (void) pcmcia_begin_resume(dip); 702 /* 703 * this will do the CARD_INSERTION 704 * due to needing time for threads to 705 * run, it must be delayed for a short amount 706 * of time. pcmcia_wait_insert checks for all 707 * children to be removed and then triggers insert. 708 */ 709 /* 710 * The reason for having a single timeout here 711 * rather than seperate timeout()s for each instance 712 * is due to the limited number (2) of callout threads 713 * available in Solaris 2.6. A single 1250A ends up 714 * as two instances of the interface with one slot each. 715 * The pcic_delayed_resume() function ends by calling 716 * pcmcia_wait_insert() which at one point does a 717 * delay(). delay() is implemented with a timeout() 718 * call so you end up with both the callout() 719 * threads waiting to be woken up by another callout(). 720 * This situation locks up the machine hence the 721 * convolution here to only use one timeout. 722 */ 723 if (!pcic_delayed_resume_toid) 724 pcic_delayed_resume_toid = 725 timeout(pcic_delayed_resume, (caddr_t)0, 726 drv_usectohz(pcic_wait_insert_time)); 727 728 /* 729 * for complete implementation need END_RESUME (later) 730 */ 731 return (DDI_SUCCESS); 732 733 } 734 return (DDI_SUCCESS); 735 default: 736 return (DDI_FAILURE); 737 } 738 739 /* 740 * Allocate soft state associated with this instance. 741 */ 742 if (ddi_soft_state_zalloc(pcic_soft_state_p, 743 ddi_get_instance(dip)) != DDI_SUCCESS) { 744 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 745 ddi_get_instance(dip)); 746 return (DDI_FAILURE); 747 } 748 749 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 750 ddi_get_instance(dip)); 751 752 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 753 754 pcic->dip = dip; 755 pcic_nexus->an_dip = dip; 756 pcic_nexus->an_if = &pcic_if_ops; 757 pcic_nexus->an_private = pcic; 758 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 759 pcic->pc_power = pcic_power; 760 761 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 762 "pci-control-reg-number", pci_control_reg_num); 763 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 764 "pci-config-reg-number", pci_config_reg_num); 765 766 ddi_set_driver_private(dip, pcic_nexus); 767 768 /* 769 * pcic->pc_irq is really the IPL level we want to run at 770 * set the default values here and override from intr spec 771 */ 772 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 773 "interrupt-priorities", -1); 774 775 if (pcic->pc_irq == -1) { 776 int actual; 777 uint_t pri; 778 ddi_intr_handle_t hdl; 779 780 /* see if intrspec tells us different */ 781 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 782 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 783 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 784 pcic->pc_irq = pri; 785 else 786 pcic->pc_irq = LOCK_LEVEL + 1; 787 (void) ddi_intr_free(hdl); 788 } 789 } 790 pcic_nexus->an_ipl = pcic->pc_irq; 791 792 /* 793 * Check our parent bus type. We do different things based on which 794 * bus we're on. 795 */ 796 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 797 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 798 "device_type", (caddr_t)&bus_type[0], &len) != 799 DDI_PROP_SUCCESS) { 800 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 801 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 802 "bus-type", (caddr_t)&bus_type[0], &len) != 803 DDI_PROP_SUCCESS) { 804 805 cmn_err(CE_CONT, 806 "pcic%d: can't find parent bus type\n", 807 ddi_get_instance(dip)); 808 809 kmem_free(pcic, sizeof (pcicdev_t)); 810 return (DDI_FAILURE); 811 } 812 } /* ddi_prop_op("device_type") */ 813 814 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0) { 815 pcic->pc_flags = PCF_PCIBUS; 816 } else { 817 #if defined(__sparc) 818 cmn_err(CE_CONT, "pcic%d: unsupported parent bus type: [%s]\n", 819 ddi_get_instance(dip), bus_type); 820 821 kmem_free(pcic, sizeof (pcicdev_t)); 822 return (DDI_FAILURE); 823 #else 824 pcic->pc_flags = 0; 825 #endif 826 } 827 828 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 829 DDI_PROP_CANSLEEP, 830 "clock-frequency", 0)) == 0) { 831 if (pcic->pc_flags & PCF_PCIBUS) 832 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 833 else 834 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 835 } else { 836 /* 837 * OBP can declare the speed in Hz... 838 */ 839 if (pcic->bus_speed > 1000000) 840 pcic->bus_speed /= 1000000; 841 } /* ddi_prop_op("clock-frequency") */ 842 843 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 844 845 #ifdef PCIC_DEBUG 846 if (pcic_debug) { 847 cmn_err(CE_CONT, 848 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 849 ddi_get_instance(dip), 850 bus_type, pcic->bus_speed); 851 } 852 #endif 853 854 /* 855 * The reg properties on a PCI node are different than those 856 * on a non-PCI node. Handle that difference here. 857 * If it turns out to be a CardBus chip, we have even more 858 * differences. 859 */ 860 if (pcic->pc_flags & PCF_PCIBUS) { 861 int class_code; 862 #if defined(__i386) || defined(__amd64) 863 pcic->pc_base = 0x1000000; 864 pcic->pc_bound = (uint32_t)~0; 865 pcic->pc_iobase = 0x1000; 866 pcic->pc_iobound = 0xefff; 867 #elif defined(__sparc) 868 pcic->pc_base = 0x0; 869 pcic->pc_bound = (uint32_t)~0; 870 pcic->pc_iobase = 0x00000; 871 pcic->pc_iobound = 0xffff; 872 #endif 873 874 /* usually need to get at config space so map first */ 875 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 876 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 877 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 878 879 if (ddi_regs_map_setup(dip, pci_cfrn, 880 (caddr_t *)&pcic->cfgaddr, 881 PCIC_PCI_CONFIG_REG_OFFSET, 882 PCIC_PCI_CONFIG_REG_LENGTH, 883 &attr, 884 &pcic->cfg_handle) != 885 DDI_SUCCESS) { 886 cmn_err(CE_CONT, 887 "pcic%d: unable to map config space" 888 "regs\n", 889 ddi_get_instance(dip)); 890 891 kmem_free(pcic, sizeof (pcicdev_t)); 892 return (DDI_FAILURE); 893 } /* ddi_regs_map_setup */ 894 895 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 896 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 897 "class-code", -1); 898 #ifdef PCIC_DEBUG 899 if (pcic_debug) { 900 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 901 class_code); 902 } 903 #endif 904 905 switch (class_code) { 906 case PCIC_PCI_CARDBUS: 907 pcic->pc_flags |= PCF_CARDBUS; 908 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 909 /* 910 * Get access to the adapter registers on the 911 * PCI bus. A 4K memory page 912 */ 913 #if defined(PCIC_DEBUG) 914 pcic_err(dip, 8, "Is Cardbus device\n"); 915 if (pcic_debug) { 916 int nr; 917 long rs; 918 (void) ddi_dev_nregs(dip, &nr); 919 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 920 "cfghndl 0x%p nregs %d", 921 (void *)pcic->cfgaddr, 922 (void *)pcic->cfg_handle, nr); 923 924 (void) ddi_dev_regsize(dip, 925 PCIC_PCI_CONTROL_REG_NUM, &rs); 926 927 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 928 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 929 } 930 #endif 931 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 932 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 933 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 934 935 if (ddi_regs_map_setup(dip, pci_ctrn, 936 (caddr_t *)&pcic->ioaddr, 937 PCIC_PCI_CONTROL_REG_OFFSET, 938 PCIC_CB_CONTROL_REG_LENGTH, 939 &attr, &pcic->handle) != 940 DDI_SUCCESS) { 941 cmn_err(CE_CONT, 942 "pcic%d: unable to map PCI regs\n", 943 ddi_get_instance(dip)); 944 ddi_regs_map_free(&pcic->cfg_handle); 945 kmem_free(pcic, sizeof (pcicdev_t)); 946 return (DDI_FAILURE); 947 } /* ddi_regs_map_setup */ 948 949 /* 950 * Find out the chip type - If we're on a PCI bus, 951 * the adapter has that information in the PCI 952 * config space. 953 * Note that we call pcic_find_pci_type here since 954 * it needs a valid mapped pcic->handle to 955 * access some of the adapter registers in 956 * some cases. 957 */ 958 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 959 ddi_regs_map_free(&pcic->handle); 960 ddi_regs_map_free(&pcic->cfg_handle); 961 kmem_free(pcic, sizeof (pcicdev_t)); 962 cmn_err(CE_WARN, "pcic: %s: unsupported " 963 "bridge\n", 964 ddi_get_name_addr(dip)); 965 return (DDI_FAILURE); 966 } 967 break; 968 969 default: 970 case PCIC_PCI_PCMCIA: 971 /* 972 * Get access to the adapter IO registers on the 973 * PCI bus config space. 974 */ 975 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 976 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 977 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 978 979 /* 980 * We need a default mapping to the adapter's IO 981 * control register space. For most adapters 982 * that are of class PCIC_PCI_PCMCIA (or of 983 * a default class) the control registers 984 * will be using the 82365-type control/data 985 * format. 986 */ 987 if (ddi_regs_map_setup(dip, pci_ctrn, 988 (caddr_t *)&pcic->ioaddr, 989 PCIC_PCI_CONTROL_REG_OFFSET, 990 PCIC_PCI_CONTROL_REG_LENGTH, 991 &attr, 992 &pcic->handle) != DDI_SUCCESS) { 993 cmn_err(CE_CONT, 994 "pcic%d: unable to map PCI regs\n", 995 ddi_get_instance(dip)); 996 ddi_regs_map_free(&pcic->cfg_handle); 997 kmem_free(pcic, sizeof (pcicdev_t)); 998 return (DDI_FAILURE); 999 } /* ddi_regs_map_setup */ 1000 1001 /* 1002 * Find out the chip type - If we're on a PCI bus, 1003 * the adapter has that information in the PCI 1004 * config space. 1005 * Note that we call pcic_find_pci_type here since 1006 * it needs a valid mapped pcic->handle to 1007 * access some of the adapter registers in 1008 * some cases. 1009 */ 1010 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 1011 ddi_regs_map_free(&pcic->handle); 1012 ddi_regs_map_free(&pcic->cfg_handle); 1013 kmem_free(pcic, sizeof (pcicdev_t)); 1014 cmn_err(CE_WARN, "pcic: %s: unsupported " 1015 "bridge\n", 1016 ddi_get_name_addr(dip)); 1017 return (DDI_FAILURE); 1018 } 1019 1020 /* 1021 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 1022 * for extended registers even though they are 1023 * not CardBus adapters. For those adapters, 1024 * re-map pcic->handle to be large enough to 1025 * encompass the Yenta registers. 1026 */ 1027 switch (pcic->pc_type) { 1028 case PCIC_TI_PCI1031: 1029 ddi_regs_map_free(&pcic->handle); 1030 1031 if (ddi_regs_map_setup(dip, 1032 PCIC_PCI_CONTROL_REG_NUM, 1033 (caddr_t *)&pcic->ioaddr, 1034 PCIC_PCI_CONTROL_REG_OFFSET, 1035 PCIC_CB_CONTROL_REG_LENGTH, 1036 &attr, 1037 &pcic->handle) != DDI_SUCCESS) { 1038 cmn_err(CE_CONT, 1039 "pcic%d: unable to map " 1040 "PCI regs\n", 1041 ddi_get_instance(dip)); 1042 ddi_regs_map_free(&pcic->cfg_handle); 1043 kmem_free(pcic, sizeof (pcicdev_t)); 1044 return (DDI_FAILURE); 1045 } /* ddi_regs_map_setup */ 1046 break; 1047 default: 1048 break; 1049 } /* switch (pcic->pc_type) */ 1050 break; 1051 } /* switch (class_code) */ 1052 } else { 1053 /* 1054 * We're not on a PCI bus, so assume an ISA bus type 1055 * register property. Get access to the adapter IO 1056 * registers on a non-PCI bus. 1057 */ 1058 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1059 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1060 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1061 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1062 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1063 1064 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1065 (caddr_t *)&pcic->ioaddr, 1066 PCIC_ISA_CONTROL_REG_OFFSET, 1067 PCIC_ISA_CONTROL_REG_LENGTH, 1068 &attr, 1069 &pcic->handle) != DDI_SUCCESS) { 1070 cmn_err(CE_CONT, 1071 "pcic%d: unable to map ISA registers\n", 1072 ddi_get_instance(dip)); 1073 1074 kmem_free(pcic, sizeof (pcicdev_t)); 1075 return (DDI_FAILURE); 1076 } /* ddi_regs_map_setup */ 1077 1078 /* ISA bus is limited to 24-bits, but not first 640K */ 1079 pcic->pc_base = 0xd0000; 1080 pcic->pc_bound = (uint32_t)~0; 1081 pcic->pc_iobase = 0x1000; 1082 pcic->pc_iobound = 0xefff; 1083 } /* !PCF_PCIBUS */ 1084 1085 #ifdef PCIC_DEBUG 1086 if (pcic_debug) { 1087 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1088 pcic->pc_flags, pcic->pc_type); 1089 } 1090 #endif 1091 1092 /* 1093 * Setup various adapter registers for the PCI case. For the 1094 * non-PCI case, find out the chip type. 1095 */ 1096 if (pcic->pc_flags & PCF_PCIBUS) { 1097 int iline; 1098 #if defined(__sparc) 1099 iline = 0; 1100 #else 1101 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1102 #endif 1103 1104 /* set flags and socket counts based on chip type */ 1105 switch (pcic->pc_type) { 1106 uint32_t cfg; 1107 case PCIC_INTEL_i82092: 1108 cfg = ddi_get8(pcic->cfg_handle, 1109 pcic->cfgaddr + PCIC_82092_PCICON); 1110 /* we can only support 4 Socket version */ 1111 if (cfg & PCIC_82092_4_SOCKETS) { 1112 pcic->pc_numsockets = 4; 1113 pcic->pc_type = PCIC_INTEL_i82092; 1114 if (iline != 0xFF) 1115 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1116 else 1117 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1118 } else { 1119 cmn_err(CE_CONT, 1120 "pcic%d: Intel 82092 adapter " 1121 "in unsupported configuration: 0x%x", 1122 ddi_get_instance(pcic->dip), cfg); 1123 pcic->pc_numsockets = 0; 1124 } /* PCIC_82092_4_SOCKETS */ 1125 break; 1126 case PCIC_CL_PD6730: 1127 case PCIC_CL_PD6729: 1128 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1129 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1130 DDI_PROP_CANSLEEP, 1131 "interrupts", 0); 1132 /* if not interrupt pin then must use ISA style IRQs */ 1133 if (cfg == 0 || iline == 0xFF) 1134 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1135 else { 1136 /* 1137 * we have the option to use PCI interrupts. 1138 * this might not be optimal but in some cases 1139 * is the only thing possible (sparc case). 1140 * we now deterine what is possible. 1141 */ 1142 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1143 } 1144 pcic->pc_numsockets = 2; 1145 pcic->pc_flags |= PCF_IO_REMAP; 1146 break; 1147 case PCIC_TI_PCI1031: 1148 /* this chip doesn't do CardBus but looks like one */ 1149 pcic->pc_flags &= ~PCF_CARDBUS; 1150 /* FALLTHROUGH */ 1151 default: 1152 pcic->pc_flags |= PCF_IO_REMAP; 1153 /* FALLTHROUGH */ 1154 /* indicate feature even if not supported */ 1155 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1156 /* Not sure if these apply to all these chips */ 1157 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1158 pcic->pc_flags |= pcic_use_cbpwrctl; 1159 1160 pcic->pc_numsockets = 1; /* one per function */ 1161 if (iline != 0xFF) { 1162 uint8_t cfg; 1163 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1164 1165 cfg = ddi_get8(pcic->cfg_handle, 1166 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1167 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1168 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1169 PCIC_BRIDGE_CTL_REG), cfg); 1170 } 1171 else 1172 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1173 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1174 break; 1175 } 1176 } else { 1177 /* 1178 * We're not on a PCI bus so do some more 1179 * checking for adapter type here. 1180 * For the non-PCI bus case: 1181 * It could be any one of a number of different chips 1182 * If we can't determine anything else, it is assumed 1183 * to be an Intel 82365SL. The Cirrus Logic PD6710 1184 * has an extension register that provides unique 1185 * identification. Toshiba chip isn't detailed as yet. 1186 */ 1187 1188 /* Init the CL id mode */ 1189 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1190 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1191 1192 /* default to Intel i82365SL and then refine */ 1193 pcic->pc_type = PCIC_I82365SL; 1194 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1195 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1196 /* go until one succeeds or none left */ 1197 if (pcic_ci_funcs[value](pcic)) 1198 break; 1199 } 1200 1201 /* any chip specific flags get set here */ 1202 switch (pcic->pc_type) { 1203 case PCIC_CL_PD6722: 1204 pcic->pc_flags |= PCF_DMA; 1205 } 1206 1207 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1208 /* 1209 * look for total number of sockets. 1210 * basically check each possible socket for 1211 * presence like in probe 1212 */ 1213 1214 /* turn all windows off */ 1215 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1216 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1217 1218 /* 1219 * if a zero is read back, then this socket 1220 * might be present. It would be except for 1221 * some systems that map the secondary PCIC 1222 * chip space back to the first. 1223 */ 1224 if (value != 0) { 1225 /* definitely not so skip */ 1226 /* note: this is for Compaq support */ 1227 continue; 1228 } 1229 1230 /* further tests */ 1231 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1232 PCIC_REV_MASK; 1233 if (!(value >= PCIC_REV_LEVEL_LOW && 1234 value <= PCIC_REV_LEVEL_HI)) 1235 break; 1236 1237 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1238 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1239 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1240 1241 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1242 if (value != 0xaa || j != 0x55) 1243 break; 1244 1245 /* 1246 * at this point we know if we have hardware 1247 * of some type and not just the bus holding 1248 * a pattern for us. We still have to determine 1249 * the case where more than 2 sockets are 1250 * really the same due to peculiar mappings of 1251 * hardware. 1252 */ 1253 j = pcic->pc_numsockets++; 1254 pcic->pc_sockets[j].pcs_flags = 0; 1255 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1256 pcic->pc_sockets[j].pcs_socket = i; 1257 1258 /* put PC Card into RESET, just in case */ 1259 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1260 pcic_putb(pcic, i, PCIC_INTERRUPT, 1261 value & ~PCIC_RESET); 1262 } 1263 1264 #if defined(PCIC_DEBUG) 1265 if (pcic_debug) 1266 cmn_err(CE_CONT, "num sockets = %d\n", 1267 pcic->pc_numsockets); 1268 #endif 1269 if (pcic->pc_numsockets == 0) { 1270 ddi_regs_map_free(&pcic->handle); 1271 kmem_free(pcic, sizeof (pcicdev_t)); 1272 return (DDI_FAILURE); 1273 } 1274 1275 /* 1276 * need to think this through again in light of 1277 * Compaq not following the model that all the 1278 * chip vendors recommend. IBM 755 seems to be 1279 * afflicted as well. Basically, if the vendor 1280 * wired things wrong, socket 0 responds for socket 2 1281 * accesses, etc. 1282 */ 1283 if (pcic->pc_numsockets > 2) { 1284 int count = pcic->pc_numsockets / 4; 1285 for (i = 0; i < count; i++) { 1286 /* put pattern into socket 0 */ 1287 pcic_putb(pcic, i, 1288 PCIC_SYSMEM_0_STARTLOW, 0x11); 1289 1290 /* put pattern into socket 2 */ 1291 pcic_putb(pcic, i + 2, 1292 PCIC_SYSMEM_0_STARTLOW, 0x33); 1293 1294 /* read back socket 0 */ 1295 value = pcic_getb(pcic, i, 1296 PCIC_SYSMEM_0_STARTLOW); 1297 1298 /* read back chip 1 socket 0 */ 1299 j = pcic_getb(pcic, i + 2, 1300 PCIC_SYSMEM_0_STARTLOW); 1301 if (j == value) { 1302 pcic->pc_numsockets -= 2; 1303 } 1304 } 1305 } 1306 1307 smi = 0xff; /* no more override */ 1308 1309 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1310 DDI_PROP_DONTPASS, "need-mult-irq", 1311 0xffff) != 0xffff) 1312 pcic->pc_flags |= PCF_MULT_IRQ; 1313 1314 } /* !PCF_PCIBUS */ 1315 1316 /* 1317 * some platforms/busses need to have resources setup 1318 * this is temporary until a real resource allocator is 1319 * implemented. 1320 */ 1321 1322 pcic_init_assigned(dip); 1323 1324 typename = pcic->pc_chipname; 1325 1326 #ifdef PCIC_DEBUG 1327 if (pcic_debug) { 1328 int nregs, nintrs; 1329 1330 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1331 nregs = 0; 1332 1333 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1334 nintrs = 0; 1335 1336 cmn_err(CE_CONT, 1337 "pcic%d: %d register sets, %d interrupts\n", 1338 ddi_get_instance(dip), nregs, nintrs); 1339 1340 nintrs = 0; 1341 while (nregs--) { 1342 off_t size; 1343 1344 if (ddi_dev_regsize(dip, nintrs, &size) == 1345 DDI_SUCCESS) { 1346 cmn_err(CE_CONT, 1347 "\tregnum %d size %ld (0x%lx)" 1348 "bytes", 1349 nintrs, size, size); 1350 if (nintrs == 1351 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1352 PCIC_ISA_CONTROL_REG_NUM : 1353 PCIC_PCI_CONTROL_REG_NUM)) 1354 cmn_err(CE_CONT, 1355 " mapped at: 0x%p\n", 1356 (void *)pcic->ioaddr); 1357 else 1358 cmn_err(CE_CONT, "\n"); 1359 } else { 1360 cmn_err(CE_CONT, 1361 "\tddi_dev_regsize(rnumber" 1362 "= %d) returns DDI_FAILURE\n", 1363 nintrs); 1364 } 1365 nintrs++; 1366 } /* while */ 1367 } /* if (pcic_debug) */ 1368 #endif 1369 1370 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1371 1372 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1373 "disable-audio", 0)) 1374 pcic->pc_flags |= PCF_AUDIO; 1375 1376 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1377 "disable-cardbus", 0)) 1378 pcic->pc_flags &= ~PCF_CARDBUS; 1379 1380 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1381 typename); 1382 1383 /* 1384 * Init all socket SMI levels to 0 (no SMI) 1385 */ 1386 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1387 pcic->pc_sockets[i].pcs_smi = 0; 1388 pcic->pc_sockets[i].pcs_debounce_id = 0; 1389 pcic->pc_sockets[i].pcs_pcic = pcic; 1390 } 1391 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1392 1393 /* 1394 * Setup the IRQ handler(s) 1395 */ 1396 switch (pcic->pc_intr_mode) { 1397 int xx; 1398 case PCIC_INTR_MODE_ISA: 1399 /* 1400 * On a non-PCI bus, we just use whatever SMI IRQ level was 1401 * specified above, and the IO IRQ levels are allocated 1402 * dynamically. 1403 */ 1404 for (xx = 15, smi = 0; xx >= 0; xx--) { 1405 if (PCIC_IRQ(xx) & 1406 PCIC_AVAIL_IRQS) { 1407 smi = pcmcia_get_intr(dip, xx); 1408 if (smi >= 0) 1409 break; 1410 } 1411 } 1412 #if defined(PCIC_DEBUG) 1413 if (pcic_debug) 1414 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1415 #endif 1416 /* init to same so share is easy */ 1417 for (i = 0; i < pcic->pc_numsockets; i++) 1418 pcic->pc_sockets[i].pcs_smi = smi; 1419 /* any special handling of IRQ levels */ 1420 if (pcic->pc_flags & PCF_MULT_IRQ) { 1421 for (i = 2; i < pcic->pc_numsockets; i++) { 1422 if ((i & 1) == 0) { 1423 int xx; 1424 for (xx = 15, smi = 0; xx >= 0; xx--) { 1425 if (PCIC_IRQ(xx) & 1426 PCIC_AVAIL_IRQS) { 1427 smi = 1428 pcmcia_get_intr(dip, 1429 xx); 1430 if (smi >= 0) 1431 break; 1432 } 1433 } 1434 } 1435 if (smi >= 0) 1436 pcic->pc_sockets[i].pcs_smi = smi; 1437 } 1438 } 1439 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1440 sizeof (ddi_intr_handle_t), KM_SLEEP); 1441 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1442 struct intrspec *ispecp; 1443 struct ddi_parent_private_data *pdp; 1444 1445 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1446 continue; 1447 else { 1448 irqlevel = pcic->pc_sockets[i].pcs_smi; 1449 } 1450 /* 1451 * now convert the allocated IRQ into an intrspec 1452 * and ask our parent to add it. Don't use 1453 * the ddi_add_intr since we don't have a 1454 * default intrspec in all cases. 1455 * 1456 * note: this sort of violates DDI but we don't 1457 * get hardware intrspecs for many of the devices. 1458 * at the same time, we know how to allocate them 1459 * so we do the right thing. 1460 */ 1461 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1462 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1463 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1464 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1465 ddi_get_name(dip)); 1466 goto isa_exit1; 1467 } 1468 1469 /* 1470 * See earlier note: 1471 * Since some devices don't have 'intrspec' 1472 * we make one up in rootnex. 1473 * 1474 * However, it is not properly initialized as 1475 * the data it needs is present in this driver 1476 * and there is no interface to pass that up. 1477 * Specially 'irqlevel' is very important and 1478 * it is part of pcic struct. 1479 * 1480 * Set 'intrspec' up here; otherwise adding the 1481 * interrupt will fail. 1482 */ 1483 pdp = ddi_get_parent_data(dip); 1484 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1485 ispecp->intrspec_vec = irqlevel; 1486 ispecp->intrspec_pri = pcic->pc_irq; 1487 1488 /* Stay compatible w/ PCMCIA */ 1489 pcic->pc_pri = (ddi_iblock_cookie_t) 1490 (uintptr_t)pcic->pc_irq; 1491 pcic->pc_dcookie.idev_priority = 1492 (uintptr_t)pcic->pc_pri; 1493 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1494 1495 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1496 pcic->pc_irq); 1497 1498 if (i == 0) { 1499 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1500 DDI_INTR_PRI(pcic->pc_irq)); 1501 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1502 NULL); 1503 } 1504 1505 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1506 pcic_intr, (caddr_t)pcic, NULL)) { 1507 cmn_err(CE_WARN, 1508 "%s: ddi_intr_add_handler failed", 1509 ddi_get_name(dip)); 1510 goto isa_exit2; 1511 } 1512 1513 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1514 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1515 ddi_get_name(dip)); 1516 for (j = i; j < 0; j--) 1517 (void) ddi_intr_remove_handler( 1518 pcic->pc_intr_htblp[j]); 1519 goto isa_exit2; 1520 } 1521 } 1522 break; 1523 case PCIC_INTR_MODE_PCI_1: 1524 case PCIC_INTR_MODE_PCI: 1525 /* 1526 * If we're on a PCI bus, we route all interrupts, both SMI 1527 * and IO interrupts, through a single interrupt line. 1528 * Assign the SMI IRQ level to the IO IRQ level here. 1529 */ 1530 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1531 KM_SLEEP); 1532 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1533 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1534 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1535 goto pci_exit1; 1536 1537 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1538 &pri) != DDI_SUCCESS) { 1539 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1540 goto pci_exit1; 1541 } 1542 1543 pcic->pc_pri = (void *)(uintptr_t)pri; 1544 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1545 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1546 1547 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1548 pcic_intr, (caddr_t)pcic, NULL)) 1549 goto pci_exit2; 1550 1551 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1552 (void) ddi_intr_remove_handler( 1553 pcic->pc_pci_intr_hdlp[0]); 1554 goto pci_exit2; 1555 } 1556 1557 /* Stay compatible w/ PCMCIA */ 1558 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1559 1560 /* init to same (PCI) so share is easy */ 1561 for (i = 0; i < pcic->pc_numsockets; i++) 1562 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1563 break; 1564 } 1565 1566 /* 1567 * Setup the adapter hardware to some reasonable defaults. 1568 */ 1569 mutex_enter(&pcic->pc_lock); 1570 /* mark the driver state as attached */ 1571 pcic->pc_flags |= PCF_ATTACHED; 1572 pcic_setup_adapter(pcic); 1573 1574 for (j = 0; j < pcic->pc_numsockets; j++) 1575 if (ddi_intr_add_softint(dip, 1576 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1577 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1578 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1579 goto pci_exit2; 1580 1581 #if defined(PCIC_DEBUG) 1582 if (pcic_debug) 1583 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1584 pcic->pc_numsockets); 1585 #endif 1586 1587 pcic_nexus->an_iblock = &pcic->pc_pri; 1588 pcic_nexus->an_idev = &pcic->pc_dcookie; 1589 1590 mutex_exit(&pcic->pc_lock); 1591 1592 #ifdef CARDBUS 1593 (void) cardbus_enable_cd_intr(dip); 1594 if (pcic_debug) { 1595 1596 cardbus_dump_pci_config(dip); 1597 cardbus_dump_socket(dip); 1598 } 1599 1600 /* 1601 * Give the Cardbus misc module a chance to do it's per-adapter 1602 * instance setup. Note that there is no corresponding detach() 1603 * call. 1604 */ 1605 if (pcic->pc_flags & PCF_CARDBUS) 1606 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1607 cmn_err(CE_CONT, 1608 "pcic_attach: cardbus_attach failed\n"); 1609 goto pci_exit2; 1610 } 1611 #endif 1612 1613 /* 1614 * Give the PCMCIA misc module a chance to do it's per-adapter 1615 * instance setup. 1616 */ 1617 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1618 goto pci_exit2; 1619 1620 syshw_attach(pcic); 1621 if (pcic_maxinst == -1) { 1622 /* This assumes that all instances run at the same IPL. */ 1623 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1624 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1625 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1626 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1627 v.v_maxsyspri - 2); 1628 } 1629 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1630 /* 1631 * Setup a debounce timeout to do an initial card detect 1632 * and enable interrupts. 1633 */ 1634 for (j = 0; j < pcic->pc_numsockets; j++) { 1635 shwp = kmem_alloc(sizeof (syshw_t), KM_SLEEP); 1636 if (shwp) { 1637 bcopy(&pcic_syshw, shwp, sizeof (pcic_syshw)); 1638 pcic_syshw.id_string[15]++; 1639 pcic->pc_sockets[j].pcs_syshwsig = 1640 syshw_add2map(shwp, pcic_syshw_cardstate, 1641 &pcic->pc_sockets[j]); 1642 } 1643 pcic->pc_sockets[j].pcs_debounce_id = 1644 pcic_add_debqueue(&pcic->pc_sockets[j], 1645 drv_usectohz(pcic_debounce_time)); 1646 } 1647 1648 return (i); 1649 1650 isa_exit2: 1651 mutex_destroy(&pcic->intr_lock); 1652 mutex_destroy(&pcic->pc_lock); 1653 for (j = i; j < 0; j--) 1654 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1655 isa_exit1: 1656 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1657 ddi_regs_map_free(&pcic->handle); 1658 if (pcic->pc_flags & PCF_PCIBUS) 1659 ddi_regs_map_free(&pcic->cfg_handle); 1660 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1661 sizeof (ddi_intr_handle_t)); 1662 kmem_free(pcic, sizeof (pcicdev_t)); 1663 return (DDI_FAILURE); 1664 1665 pci_exit2: 1666 mutex_destroy(&pcic->intr_lock); 1667 mutex_destroy(&pcic->pc_lock); 1668 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1669 pci_exit1: 1670 ddi_regs_map_free(&pcic->handle); 1671 if (pcic->pc_flags & PCF_PCIBUS) 1672 ddi_regs_map_free(&pcic->cfg_handle); 1673 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1674 kmem_free(pcic, sizeof (pcicdev_t)); 1675 return (DDI_FAILURE); 1676 } 1677 1678 /* 1679 * pcic_detach() 1680 * request to detach from the system 1681 */ 1682 static int 1683 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1684 { 1685 anp_t *anp = ddi_get_driver_private(dip); 1686 pcicdev_t *pcic = anp->an_private; 1687 int i; 1688 1689 switch (cmd) { 1690 case DDI_DETACH: 1691 /* don't detach if the nexus still talks to us */ 1692 if (pcic->pc_callback != NULL) 1693 return (DDI_FAILURE); 1694 syshw_detach(pcic); 1695 1696 /* kill off the pm simulation */ 1697 if (pcic->pc_pmtimer) 1698 (void) untimeout(pcic->pc_pmtimer); 1699 1700 /* turn everything off for all sockets and chips */ 1701 for (i = 0; i < pcic->pc_numsockets; i++) { 1702 if (pcic->pc_sockets[i].pcs_debounce_id) 1703 pcic_rm_debqueue( 1704 pcic->pc_sockets[i].pcs_debounce_id); 1705 pcic->pc_sockets[i].pcs_debounce_id = 0; 1706 1707 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1708 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1709 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1710 /* disable interrupts and put card into RESET */ 1711 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1712 } 1713 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1714 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1715 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1716 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1717 pcic->pc_flags = 0; 1718 mutex_destroy(&pcic->pc_lock); 1719 mutex_destroy(&pcic->intr_lock); 1720 cv_destroy(&pcic->pm_cv); 1721 if (pcic->pc_flags & PCF_PCIBUS) 1722 ddi_regs_map_free(&pcic->cfg_handle); 1723 if (pcic->handle) 1724 ddi_regs_map_free(&pcic->handle); 1725 kmem_free(pcic, sizeof (pcicdev_t)); 1726 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1727 return (DDI_SUCCESS); 1728 1729 case DDI_SUSPEND: 1730 case DDI_PM_SUSPEND: 1731 /* 1732 * we got a suspend event (either real or imagined) 1733 * so notify the nexus proper that all existing cards 1734 * should go away. 1735 */ 1736 mutex_enter(&pcic->pc_lock); 1737 #ifdef CARDBUS 1738 if (pcic->pc_flags & PCF_CARDBUS) 1739 for (i = 0; i < pcic->pc_numsockets; i++) 1740 if ((pcic->pc_sockets[i].pcs_flags & 1741 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1742 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1743 if (!cardbus_can_suspend(dip)) { 1744 mutex_exit(&pcic->pc_lock); 1745 cmn_err(CE_WARN, 1746 "Please unconfigure all " 1747 "CardBus devices before " 1748 "attempting to suspend\n"); 1749 return (DDI_FAILURE); 1750 } 1751 #endif 1752 /* turn everything off for all sockets and chips */ 1753 for (i = 0; i < pcic->pc_numsockets; i++) { 1754 if (pcic->pc_sockets[i].pcs_debounce_id) 1755 pcic_rm_debqueue( 1756 pcic->pc_sockets[i].pcs_debounce_id); 1757 pcic->pc_sockets[i].pcs_debounce_id = 0; 1758 1759 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1760 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1761 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1762 /* disable interrupts and put card into RESET */ 1763 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1764 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1765 if (pcic->pc_flags & PCF_CBPWRCTL) 1766 pcic_putcb(pcic, CB_CONTROL, 0); 1767 1768 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1769 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1770 /* 1771 * Because we are half way through a save 1772 * all this does is schedule a removal event 1773 * to cs for when the system comes back. 1774 * This doesn't actually matter. 1775 */ 1776 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1777 pcic->pc_callback) { 1778 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1779 PCE_CARD_REMOVAL, 1780 pcic->pc_sockets[i].pcs_socket); 1781 } 1782 } 1783 } 1784 1785 pcic->pc_flags |= PCF_SUSPENDED; 1786 mutex_exit(&pcic->pc_lock); 1787 pcic_delayed_resume_toid = 0; 1788 1789 /* 1790 * when true power management exists, save the adapter 1791 * state here to enable a recovery. For the emulation 1792 * condition, the state is gone 1793 */ 1794 return (DDI_SUCCESS); 1795 1796 default: 1797 return (EINVAL); 1798 } 1799 } 1800 1801 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1802 static uint32_t pcic_tisysctl_offbits = 0; 1803 static uint32_t pcic_default_latency = 0x40; 1804 1805 static void 1806 pcic_setup_adapter(pcicdev_t *pcic) 1807 { 1808 int i; 1809 int value, flags; 1810 1811 if (pcic->pc_flags & PCF_PCIBUS) { 1812 /* 1813 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1814 */ 1815 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1816 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1817 } 1818 /* enable each socket */ 1819 for (i = 0; i < pcic->pc_numsockets; i++) { 1820 pcic->pc_sockets[i].pcs_flags = 0; 1821 /* find out the socket capabilities (I/O vs memory) */ 1822 value = pcic_getb(pcic, i, 1823 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1824 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1825 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1826 1827 /* disable all windows just in case */ 1828 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1829 1830 switch (pcic->pc_type) { 1831 uint32_t cfg32; 1832 uint16_t cfg16; 1833 uint8_t cfg; 1834 1835 /* enable extended registers for Vadem */ 1836 case PCIC_VADEM_VG469: 1837 case PCIC_VADEM: 1838 1839 /* enable card status change interrupt for socket */ 1840 break; 1841 1842 case PCIC_I82365SL: 1843 break; 1844 1845 case PCIC_CL_PD6710: 1846 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1847 break; 1848 1849 /* 1850 * On the CL_6730, we need to set up the interrupt 1851 * signalling mode (PCI mode) and set the SMI and 1852 * IRQ interrupt lines to PCI/level-mode. 1853 */ 1854 case PCIC_CL_PD6730: 1855 switch (pcic->pc_intr_mode) { 1856 case PCIC_INTR_MODE_PCI_1: 1857 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1858 ((clext_reg_read(pcic, i, 1859 PCIC_CLEXT_MISC_CTL_3) & 1860 ~PCIC_CLEXT_INT_PCI) | 1861 PCIC_CLEXT_INT_PCI)); 1862 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1863 (PCIC_CLEXT_IRQ_LVL_MODE | 1864 PCIC_CLEXT_SMI_LVL_MODE)); 1865 cfg = PCIC_CL_LP_DYN_MODE; 1866 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1867 break; 1868 case PCIC_INTR_MODE_ISA: 1869 break; 1870 } 1871 break; 1872 /* 1873 * On the CL_6729, we set the SMI and IRQ interrupt 1874 * lines to PCI/level-mode. as well as program the 1875 * correct clock speed divider bit. 1876 */ 1877 case PCIC_CL_PD6729: 1878 switch (pcic->pc_intr_mode) { 1879 case PCIC_INTR_MODE_PCI_1: 1880 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1881 (PCIC_CLEXT_IRQ_LVL_MODE | 1882 PCIC_CLEXT_SMI_LVL_MODE)); 1883 1884 break; 1885 case PCIC_INTR_MODE_ISA: 1886 break; 1887 } 1888 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1889 cfg = 0; 1890 cfg |= PCIC_CL_TIMER_CLK_DIV; 1891 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1892 } 1893 break; 1894 case PCIC_INTEL_i82092: 1895 cfg = PCIC_82092_EN_TIMING; 1896 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1897 cfg |= PCIC_82092_PCICLK_25MHZ; 1898 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1899 PCIC_82092_PCICON, cfg); 1900 break; 1901 case PCIC_TI_PCI1130: 1902 case PCIC_TI_PCI1131: 1903 case PCIC_TI_PCI1250: 1904 case PCIC_TI_PCI1031: 1905 cfg = ddi_get8(pcic->cfg_handle, 1906 pcic->cfgaddr + PCIC_DEVCTL_REG); 1907 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1908 switch (pcic->pc_intr_mode) { 1909 case PCIC_INTR_MODE_ISA: 1910 cfg |= PCIC_DEVCTL_INTR_ISA; 1911 break; 1912 } 1913 #ifdef PCIC_DEBUG 1914 if (pcic_debug) { 1915 cmn_err(CE_CONT, "pcic_setup_adapter: " 1916 "write reg 0x%x=%x \n", 1917 PCIC_DEVCTL_REG, cfg); 1918 } 1919 #endif 1920 ddi_put8(pcic->cfg_handle, 1921 pcic->cfgaddr + PCIC_DEVCTL_REG, 1922 cfg); 1923 1924 cfg = ddi_get8(pcic->cfg_handle, 1925 pcic->cfgaddr + PCIC_CRDCTL_REG); 1926 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1927 PCIC_CRDCTL_PCIFUNC); 1928 switch (pcic->pc_intr_mode) { 1929 case PCIC_INTR_MODE_PCI_1: 1930 cfg |= PCIC_CRDCTL_PCIINTR | 1931 PCIC_CRDCTL_PCICSC | 1932 PCIC_CRDCTL_PCIFUNC; 1933 pcic->pc_flags |= PCF_USE_SMI; 1934 break; 1935 } 1936 #ifdef PCIC_DEBUG 1937 if (pcic_debug) { 1938 cmn_err(CE_CONT, "pcic_setup_adapter: " 1939 " write reg 0x%x=%x \n", 1940 PCIC_CRDCTL_REG, cfg); 1941 } 1942 #endif 1943 ddi_put8(pcic->cfg_handle, 1944 pcic->cfgaddr + PCIC_CRDCTL_REG, 1945 cfg); 1946 break; 1947 case PCIC_TI_PCI1221: 1948 case PCIC_TI_PCI1225: 1949 cfg = ddi_get8(pcic->cfg_handle, 1950 pcic->cfgaddr + PCIC_DEVCTL_REG); 1951 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1952 #ifdef PCIC_DEBUG 1953 if (pcic_debug) { 1954 cmn_err(CE_CONT, "pcic_setup_adapter: " 1955 " write reg 0x%x=%x \n", 1956 PCIC_DEVCTL_REG, cfg); 1957 } 1958 #endif 1959 ddi_put8(pcic->cfg_handle, 1960 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1961 1962 cfg = ddi_get8(pcic->cfg_handle, 1963 pcic->cfgaddr + PCIC_DIAG_REG); 1964 if (pcic->pc_type == PCIC_TI_PCI1225) { 1965 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1966 } else { 1967 cfg |= PCIC_DIAG_ASYNC; 1968 } 1969 pcic->pc_flags |= PCF_USE_SMI; 1970 #ifdef PCIC_DEBUG 1971 if (pcic_debug) { 1972 cmn_err(CE_CONT, "pcic_setup_adapter: " 1973 " write reg 0x%x=%x \n", 1974 PCIC_DIAG_REG, cfg); 1975 } 1976 #endif 1977 ddi_put8(pcic->cfg_handle, 1978 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1979 break; 1980 case PCIC_TI_PCI1520: 1981 case PCIC_TI_PCI1510: 1982 case PCIC_TI_VENDOR: 1983 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1984 cfg = ddi_get8(pcic->cfg_handle, 1985 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1986 cfg |= PCIC_FUN_INT_MOD_ISA; 1987 ddi_put8(pcic->cfg_handle, 1988 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1989 cfg); 1990 } 1991 cfg = ddi_get8(pcic->cfg_handle, 1992 pcic->cfgaddr + PCIC_DEVCTL_REG); 1993 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1994 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1995 cfg |= PCIC_DEVCTL_INTR_ISA; 1996 ddi_put8(pcic->cfg_handle, 1997 pcic->cfgaddr + PCIC_DEVCTL_REG, 1998 cfg); 1999 2000 /* tie INTA and INTB together */ 2001 cfg = ddi_get8(pcic->cfg_handle, 2002 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2003 cfg |= PCIC_SYSCTL_INTRTIE; 2004 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2005 PCIC_SYSCTL_REG + 3), cfg); 2006 cfg = ddi_get8(pcic->cfg_handle, 2007 pcic->cfgaddr + PCIC_DIAG_REG); 2008 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2009 ddi_put8(pcic->cfg_handle, 2010 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2011 break; 2012 case PCIC_TI_PCI1410: 2013 cfg = ddi_get8(pcic->cfg_handle, 2014 pcic->cfgaddr + PCIC_DIAG_REG); 2015 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2016 ddi_put8(pcic->cfg_handle, 2017 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2018 break; 2019 case PCIC_TOSHIBA_TOPIC100: 2020 case PCIC_TOSHIBA_TOPIC95: 2021 case PCIC_TOSHIBA_VENDOR: 2022 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2023 PCIC_TOSHIBA_SLOT_CTL_REG); 2024 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2025 PCIC_TOSHIBA_SCR_SLOTEN); 2026 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2027 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2028 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2029 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2030 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2031 PCIC_TOSHIBA_INTR_CTL_REG); 2032 switch (pcic->pc_intr_mode) { 2033 case PCIC_INTR_MODE_ISA: 2034 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2035 ddi_put8(pcic->cfg_handle, 2036 pcic->cfgaddr + 2037 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2038 2039 cfg = ddi_get8(pcic->cfg_handle, 2040 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2041 cfg |= PCIC_FUN_INT_MOD_ISA; 2042 ddi_put8(pcic->cfg_handle, 2043 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2044 cfg); 2045 break; 2046 case PCIC_INTR_MODE_PCI_1: 2047 cfg |= PCIC_TOSHIBA_ICR_SRC; 2048 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2049 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2050 ddi_put8(pcic->cfg_handle, 2051 pcic->cfgaddr + 2052 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2053 break; 2054 } 2055 break; 2056 case PCIC_O2MICRO_VENDOR: 2057 cfg32 = ddi_get32(pcic->cfg_handle, 2058 (uint32_t *)(pcic->cfgaddr + 2059 PCIC_O2MICRO_MISC_CTL)); 2060 switch (pcic->pc_intr_mode) { 2061 case PCIC_INTR_MODE_ISA: 2062 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2063 PCIC_O2MICRO_INT_MOD_PCI); 2064 ddi_put32(pcic->cfg_handle, 2065 (uint32_t *)(pcic->cfgaddr + 2066 PCIC_O2MICRO_MISC_CTL), 2067 cfg32); 2068 cfg = ddi_get8(pcic->cfg_handle, 2069 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2070 cfg |= PCIC_FUN_INT_MOD_ISA; 2071 ddi_put8(pcic->cfg_handle, 2072 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2073 cfg); 2074 break; 2075 case PCIC_INTR_MODE_PCI_1: 2076 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2077 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2078 ddi_put32(pcic->cfg_handle, 2079 (uint32_t *)(pcic->cfgaddr + 2080 PCIC_O2MICRO_MISC_CTL), 2081 cfg32); 2082 break; 2083 } 2084 break; 2085 case PCIC_RICOH_VENDOR: 2086 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2087 cfg16 = ddi_get16(pcic->cfg_handle, 2088 (uint16_t *)(pcic->cfgaddr + 2089 PCIC_RICOH_MISC_CTL_2)); 2090 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2091 PCIC_RICOH_FUN_INT_MOD); 2092 ddi_put16(pcic->cfg_handle, 2093 (uint16_t *)(pcic->cfgaddr + 2094 PCIC_RICOH_MISC_CTL_2), 2095 cfg16); 2096 2097 cfg16 = ddi_get16(pcic->cfg_handle, 2098 (uint16_t *)(pcic->cfgaddr + 2099 PCIC_RICOH_MISC_CTL)); 2100 cfg16 |= PCIC_RICOH_SIRQ_EN; 2101 ddi_put16(pcic->cfg_handle, 2102 (uint16_t *)(pcic->cfgaddr + 2103 PCIC_RICOH_MISC_CTL), 2104 cfg16); 2105 2106 cfg = ddi_get8(pcic->cfg_handle, 2107 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2108 cfg |= PCIC_FUN_INT_MOD_ISA; 2109 ddi_put8(pcic->cfg_handle, 2110 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2111 cfg); 2112 } 2113 break; 2114 default: 2115 break; 2116 } /* switch */ 2117 2118 /* setup general card status change interrupt */ 2119 switch (pcic->pc_type) { 2120 case PCIC_TI_PCI1225: 2121 case PCIC_TI_PCI1221: 2122 case PCIC_TI_PCI1031: 2123 case PCIC_TI_PCI1520: 2124 case PCIC_TI_PCI1410: 2125 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2126 PCIC_CHANGE_DEFAULT); 2127 break; 2128 default: 2129 if (pcic->pc_intr_mode == 2130 PCIC_INTR_MODE_PCI_1) { 2131 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2132 PCIC_CHANGE_DEFAULT); 2133 break; 2134 } else { 2135 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2136 PCIC_CHANGE_DEFAULT | 2137 (pcic->pc_sockets[i].pcs_smi << 4)); 2138 break; 2139 } 2140 } 2141 2142 pcic->pc_flags |= PCF_INTRENAB; 2143 2144 /* take card out of RESET */ 2145 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2146 /* turn power off and let CS do this */ 2147 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2148 2149 /* final chip specific initialization */ 2150 switch (pcic->pc_type) { 2151 case PCIC_VADEM: 2152 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2153 PCIC_VC_DELAYENABLE); 2154 pcic->pc_flags |= PCF_DEBOUNCE; 2155 /* FALLTHROUGH */ 2156 case PCIC_I82365SL: 2157 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2158 PCIC_GC_CSC_WRITE); 2159 /* clear any pending interrupts */ 2160 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2161 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2162 break; 2163 /* The 82092 uses PCI config space to enable interrupts */ 2164 case PCIC_INTEL_i82092: 2165 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2166 PCIC_82092_INT_ENABLE); 2167 break; 2168 case PCIC_CL_PD6729: 2169 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2170 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2171 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2172 value | PCIC_CL_TIMER_CLK_DIV); 2173 } 2174 break; 2175 } /* switch */ 2176 2177 #if defined(PCIC_DEBUG) 2178 if (pcic_debug) 2179 cmn_err(CE_CONT, 2180 "socket %d value=%x, flags = %x (%s)\n", 2181 i, value, pcic->pc_sockets[i].pcs_flags, 2182 (pcic->pc_sockets[i].pcs_flags & 2183 PCS_CARD_PRESENT) ? 2184 "card present" : "no card"); 2185 #endif 2186 } 2187 } 2188 2189 /* 2190 * pcic_intr(caddr_t, caddr_t) 2191 * interrupt handler for the PCIC style adapter 2192 * handles all basic interrupts and also checks 2193 * for status changes and notifies the nexus if 2194 * necessary 2195 * 2196 * On PCI bus adapters, also handles all card 2197 * IO interrupts. 2198 */ 2199 /*ARGSUSED*/ 2200 uint32_t 2201 pcic_intr(caddr_t arg1, caddr_t arg2) 2202 { 2203 pcicdev_t *pcic = (pcicdev_t *)arg1; 2204 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2205 uint8_t status; 2206 uint_t io_ints; 2207 2208 #if defined(PCIC_DEBUG) 2209 pcic_err(pcic->dip, 0xf, 2210 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2211 " pc_numsockets=%d \n", 2212 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2213 #endif 2214 2215 if (!(pcic->pc_flags & PCF_ATTACHED)) 2216 return (DDI_INTR_UNCLAIMED); 2217 2218 mutex_enter(&pcic->intr_lock); 2219 2220 if (pcic->pc_flags & PCF_SUSPENDED) { 2221 mutex_exit(&pcic->intr_lock); 2222 return (ret); 2223 } 2224 2225 /* 2226 * need to change to only ACK and touch the slot that 2227 * actually caused the interrupt. Currently everything 2228 * is acked 2229 * 2230 * we need to look at all known sockets to determine 2231 * what might have happened, so step through the list 2232 * of them 2233 */ 2234 #ifdef VOYAGER 2235 ret = syshw_intr_hi(pcic); 2236 #endif 2237 2238 /* 2239 * Set the bitmask for IO interrupts to initially include all sockets 2240 */ 2241 io_ints = (1 << pcic->pc_numsockets) - 1; 2242 2243 for (i = 0; i < pcic->pc_numsockets; i++) { 2244 int card_type; 2245 pcic_socket_t *sockp; 2246 int value_cb = 0; 2247 2248 sockp = &pcic->pc_sockets[i]; 2249 /* get the socket's I/O addresses */ 2250 2251 if (sockp->pcs_flags & PCS_WAITING) { 2252 io_ints &= ~(1 << i); 2253 continue; 2254 } 2255 2256 if (sockp->pcs_flags & PCS_CARD_IO) 2257 card_type = IF_IO; 2258 else 2259 card_type = IF_MEMORY; 2260 2261 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2262 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2263 2264 value = pcic_change(pcic, i); 2265 2266 if ((value != 0) || (value_cb != 0)) { 2267 int x = pcic->pc_cb_arg; 2268 2269 ret = DDI_INTR_CLAIMED; 2270 2271 #if defined(PCIC_DEBUG) 2272 pcic_err(pcic->dip, 0x9, 2273 "card_type = %d, value_cb = 0x%x\n", 2274 card_type, 2275 value_cb ? value_cb : 2276 pcic_getcb(pcic, CB_STATUS_EVENT)); 2277 if (pcic_debug) 2278 cmn_err(CE_CONT, 2279 "\tchange on socket %d (%x)\n", i, 2280 value); 2281 #endif 2282 /* find out what happened */ 2283 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2284 2285 /* acknowledge the interrupt */ 2286 if (value_cb) 2287 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2288 2289 if (value) 2290 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2291 value); 2292 2293 if (pcic->pc_callback == NULL) { 2294 /* if not callback handler, nothing to do */ 2295 continue; 2296 } 2297 2298 /* Card Detect */ 2299 if (value & PCIC_CD_DETECT || 2300 value_cb & CB_PS_CCDMASK) { 2301 uint8_t irq; 2302 #if defined(PCIC_DEBUG) 2303 if (pcic_debug) 2304 cmn_err(CE_CONT, 2305 "\tcd_detect: status=%x," 2306 " flags=%x\n", 2307 status, sockp->pcs_flags); 2308 #else 2309 #ifdef lint 2310 if (status == 0) 2311 status++; 2312 #endif 2313 #endif 2314 /* 2315 * Turn off all interrupts for this socket here. 2316 */ 2317 irq = pcic_getb(pcic, sockp->pcs_socket, 2318 PCIC_MANAGEMENT_INT); 2319 irq &= ~PCIC_CHANGE_MASK; 2320 pcic_putb(pcic, sockp->pcs_socket, 2321 PCIC_MANAGEMENT_INT, irq); 2322 2323 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2324 2325 if (!sockp->pcs_cd_softint_flg) { 2326 sockp->pcs_cd_softint_flg = 1; 2327 (void) ddi_intr_trigger_softint( 2328 sockp->pcs_cd_softint_hdl, NULL); 2329 } 2330 2331 io_ints &= ~(1 << i); 2332 } /* PCIC_CD_DETECT */ 2333 2334 /* Ready/Change Detect */ 2335 sockp->pcs_state ^= SBM_RDYBSY; 2336 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2337 sockp->pcs_flags |= PCS_READY; 2338 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2339 } 2340 2341 /* Battery Warn Detect */ 2342 if (card_type == IF_MEMORY && 2343 value & PCIC_BW_DETECT && 2344 !(sockp->pcs_state & SBM_BVD2)) { 2345 sockp->pcs_state |= SBM_BVD2; 2346 PC_CALLBACK(pcic->dip, x, 2347 PCE_CARD_BATTERY_WARN, i); 2348 } 2349 2350 /* Battery Dead Detect */ 2351 if (value & PCIC_BD_DETECT) { 2352 /* 2353 * need to work out event if RI not enabled 2354 * and card_type == IF_IO 2355 */ 2356 if (card_type == IF_MEMORY && 2357 !(sockp->pcs_state & SBM_BVD1)) { 2358 sockp->pcs_state |= SBM_BVD1; 2359 PC_CALLBACK(pcic->dip, x, 2360 PCE_CARD_BATTERY_DEAD, 2361 i); 2362 } else { 2363 /* 2364 * information in pin replacement 2365 * register if one is available 2366 */ 2367 PC_CALLBACK(pcic->dip, x, 2368 PCE_CARD_STATUS_CHANGE, 2369 i); 2370 } /* IF_MEMORY */ 2371 } /* PCIC_BD_DETECT */ 2372 } /* if pcic_change */ 2373 /* 2374 * for any controllers that we can detect whether a socket 2375 * had an interrupt for the PC Card, we should sort that out 2376 * here. 2377 */ 2378 } /* for pc_numsockets */ 2379 2380 /* 2381 * If we're on a PCI bus, we may need to cycle through each IO 2382 * interrupt handler that is registered since they all 2383 * share the same interrupt line. 2384 */ 2385 2386 2387 #if defined(PCIC_DEBUG) 2388 pcic_err(pcic->dip, 0xf, 2389 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2390 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2391 #endif 2392 2393 switch (pcic->pc_intr_mode) { 2394 case PCIC_INTR_MODE_PCI_1: 2395 value = ~0; 2396 /* fix value if adapter can tell us about I/O intrs */ 2397 switch (pcic->pc_type) { 2398 2399 case PCIC_TI_PCI1031: 2400 case PCIC_TI_PCI1130: 2401 case PCIC_TI_PCI1131: 2402 case PCIC_TI_PCI1250: 2403 case PCIC_TI_PCI1225: 2404 case PCIC_TI_PCI1221: 2405 case PCIC_TI_PCI1510: 2406 case PCIC_TI_PCI1520: 2407 case PCIC_TI_PCI1410: 2408 case PCIC_TI_VENDOR: 2409 i = ddi_get8(pcic->cfg_handle, 2410 pcic->cfgaddr + PCIC_CRDCTL_REG); 2411 if (i & PCIC_CRDCTL_IFG) 2412 value = 1; 2413 else 2414 value = 0; 2415 i |= PCIC_CRDCTL_IFG; 2416 /* clear the condition */ 2417 ddi_put8(pcic->cfg_handle, 2418 pcic->cfgaddr + PCIC_CRDCTL_REG, i); 2419 break; 2420 case PCIC_TOSHIBA_TOPIC100: 2421 case PCIC_TOSHIBA_TOPIC95: 2422 case PCIC_TOSHIBA_VENDOR: 2423 case PCIC_RICOH_VENDOR: 2424 case PCIC_O2MICRO_VENDOR: 2425 default: 2426 value = 1; 2427 break; 2428 } 2429 if (value && pcic_do_io_intr(pcic, value) == DDI_INTR_CLAIMED) 2430 ret = DDI_INTR_CLAIMED; 2431 break; 2432 default: 2433 break; 2434 } 2435 2436 mutex_exit(&pcic->intr_lock); 2437 2438 #if defined(PCIC_DEBUG) 2439 pcic_err(pcic->dip, 0xf, 2440 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2441 ret, value, DDI_INTR_CLAIMED); 2442 #endif 2443 2444 return (ret); 2445 } 2446 2447 /* 2448 * pcic_change() 2449 * check to see if this socket had a change in state 2450 * by checking the status change register 2451 */ 2452 static int 2453 pcic_change(pcicdev_t *pcic, int socket) 2454 { 2455 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2456 } 2457 2458 /* 2459 * pcic_do_io_intr - calls client interrupt handlers 2460 */ 2461 static int 2462 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2463 { 2464 inthandler_t *tmp; 2465 int ret = DDI_INTR_UNCLAIMED; 2466 2467 #if defined(PCIC_DEBUG) 2468 pcic_err(pcic->dip, 0xf, 2469 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2470 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2471 #endif 2472 2473 if (pcic->irq_top != NULL) { 2474 tmp = pcic->irq_current; 2475 2476 do { 2477 int cur = pcic->irq_current->socket; 2478 pcic_socket_t *sockp = 2479 &pcic->pc_sockets[cur]; 2480 2481 #if defined(PCIC_DEBUG) 2482 pcic_err(pcic->dip, 0xf, 2483 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2484 sockp->pcs_flags, PCS_CARD_PRESENT); 2485 pcic_err(pcic->dip, 0xf, 2486 "\t sockets=%d cur=%d intr=%p arg1=%p " 2487 "arg2=%p\n", 2488 sockets, cur, (void *)pcic->irq_current->intr, 2489 pcic->irq_current->arg1, 2490 pcic->irq_current->arg2); 2491 #endif 2492 if (sockp->pcs_flags & PCS_CARD_PRESENT && 2493 sockets & (1 << cur)) { 2494 2495 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2496 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2497 ret = DDI_INTR_CLAIMED; 2498 2499 #if defined(PCIC_DEBUG) 2500 pcic_err(pcic->dip, 0xf, 2501 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2502 ret, DDI_INTR_CLAIMED); 2503 #endif 2504 } 2505 2506 2507 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2508 pcic->irq_current = pcic->irq_top; 2509 2510 } while (pcic->irq_current != tmp); 2511 2512 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2513 pcic->irq_current = pcic->irq_top; 2514 2515 } else { 2516 ret = DDI_INTR_UNCLAIMED; 2517 } 2518 2519 #if defined(PCIC_DEBUG) 2520 pcic_err(pcic->dip, 0xf, 2521 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2522 ret, DDI_INTR_CLAIMED); 2523 #endif 2524 2525 return (ret); 2526 2527 } 2528 2529 /* 2530 * pcic_inquire_adapter() 2531 * SocketServices InquireAdapter function 2532 * get characteristics of the physical adapter 2533 */ 2534 /*ARGSUSED*/ 2535 static int 2536 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2537 { 2538 anp_t *anp = ddi_get_driver_private(dip); 2539 pcicdev_t *pcic = anp->an_private; 2540 2541 config->NumSockets = pcic->pc_numsockets; 2542 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2543 config->NumEDCs = 0; 2544 config->AdpCaps = 0; 2545 config->ActiveHigh = 0; 2546 config->ActiveLow = PCIC_AVAIL_IRQS; 2547 config->NumPower = pcic->pc_numpower; 2548 config->power_entry = pcic->pc_power; /* until we resolve this */ 2549 #if defined(PCIC_DEBUG) 2550 if (pcic_debug) { 2551 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2552 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2553 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2554 } 2555 #endif 2556 config->ResourceFlags = 0; 2557 switch (pcic->pc_intr_mode) { 2558 case PCIC_INTR_MODE_PCI_1: 2559 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2560 RES_IRQ_SHAREABLE; 2561 break; 2562 } 2563 return (SUCCESS); 2564 } 2565 2566 /* 2567 * pcic_callback() 2568 * The PCMCIA nexus calls us via this function 2569 * in order to set the callback function we are 2570 * to call the nexus with 2571 */ 2572 /*ARGSUSED*/ 2573 static int 2574 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2575 { 2576 anp_t *anp = ddi_get_driver_private(dip); 2577 pcicdev_t *pcic = anp->an_private; 2578 2579 if (handler != NULL) { 2580 pcic->pc_callback = handler; 2581 pcic->pc_cb_arg = arg; 2582 pcic->pc_flags |= PCF_CALLBACK; 2583 } else { 2584 pcic->pc_callback = NULL; 2585 pcic->pc_cb_arg = 0; 2586 pcic->pc_flags &= ~PCF_CALLBACK; 2587 } 2588 /* 2589 * we're now registered with the nexus 2590 * it is acceptable to do callbacks at this point. 2591 * don't call back from here though since it could block 2592 */ 2593 return (PC_SUCCESS); 2594 } 2595 2596 /* 2597 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2598 * calculate the speed bits from the specified memory speed 2599 * there may be more to do here 2600 */ 2601 2602 static int 2603 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2604 { 2605 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2606 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2607 2608 switch (pcic->pc_type) { 2609 case PCIC_I82365SL: 2610 case PCIC_VADEM: 2611 case PCIC_VADEM_VG469: 2612 default: 2613 /* Intel chip wants it in waitstates */ 2614 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2615 if (speed <= wspeed) 2616 wspeed = 0; 2617 else if (speed <= (wspeed += mhztons(bspeed))) 2618 wspeed = 1; 2619 else if (speed <= (wspeed += mhztons(bspeed))) 2620 wspeed = 2; 2621 else 2622 wspeed = 3; 2623 wspeed <<= 6; /* put in right bit positions */ 2624 break; 2625 2626 case PCIC_INTEL_i82092: 2627 wspeed = SYSMEM_82092_80NS; 2628 if (speed > 80) 2629 wspeed = SYSMEM_82092_100NS; 2630 if (speed > 100) 2631 wspeed = SYSMEM_82092_150NS; 2632 if (speed > 150) 2633 wspeed = SYSMEM_82092_200NS; 2634 if (speed > 200) 2635 wspeed = SYSMEM_82092_250NS; 2636 if (speed > 250) 2637 wspeed = SYSMEM_82092_600NS; 2638 wspeed <<= 5; /* put in right bit positions */ 2639 break; 2640 2641 } /* switch */ 2642 2643 return (wspeed); 2644 } 2645 2646 /* 2647 * These values are taken from the PC Card Standard Electrical Specification. 2648 * Generally the larger value is taken if 2 are possible. 2649 */ 2650 static struct pcic_card_times { 2651 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2652 uint16_t setup; /* Corresponding address setup time. */ 2653 uint16_t width; /* Corresponding width, OE or WE. */ 2654 uint16_t hold; /* Corresponding data or address hold time. */ 2655 } pcic_card_times[] = { 2656 2657 /* 2658 * Note: The rounded up times for 250, 200 & 150 have been increased 2659 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2660 * See BugID 00663. 2661 */ 2662 2663 /* 2664 * Rounded up times Original times from 2665 * that add up to the the PCMCIA Spec. 2666 * cycle time. 2667 */ 2668 {600, 180, 370, 140}, /* 100, 300, 70 */ 2669 {400, 120, 300, 90}, /* Made this one up */ 2670 {250, 100, 190, 70}, /* 30, 150, 30 */ 2671 {200, 80, 170, 70}, /* 20, 120, 30 */ 2672 {150, 50, 110, 40}, /* 20, 80, 20 */ 2673 {100, 40, 80, 40}, /* 10, 60, 15 */ 2674 {0, 10, 60, 15} /* 10, 60, 15 */ 2675 }; 2676 2677 /* 2678 * pcic_set_cdtimers 2679 * This is specific to several Cirrus Logic chips 2680 */ 2681 static void 2682 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2683 { 2684 int cmd, set, rec, offset, clk_pulse; 2685 struct pcic_card_times *ctp; 2686 2687 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2688 offset = 3; 2689 else 2690 offset = 0; 2691 2692 clk_pulse = mhztons(pcic->bus_speed); 2693 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2694 2695 /* 2696 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2697 */ 2698 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2699 if (set < 0) 2700 set = 0; 2701 2702 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2703 if (cmd < 0) 2704 cmd = 0; 2705 2706 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2707 if (rec < 0) 2708 rec = 0; 2709 2710 #if defined(PCIC_DEBUG) 2711 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2712 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2713 (unsigned)speed, offset == 3 ? 1 : 0, 2714 ctp->cycle, clk_pulse, cmd, set, rec); 2715 #endif 2716 2717 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2718 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2719 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2720 } 2721 2722 /* 2723 * pcic_set_window 2724 * essentially the same as the Socket Services specification 2725 * We use socket and not adapter since they are identifiable 2726 * but the rest is the same 2727 * 2728 * dip pcic driver's device information 2729 * window parameters for the request 2730 */ 2731 static int 2732 pcic_set_window(dev_info_t *dip, set_window_t *window) 2733 { 2734 anp_t *anp = ddi_get_driver_private(dip); 2735 pcicdev_t *pcic = anp->an_private; 2736 int select; 2737 int socket, pages, which, ret; 2738 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2739 ra_return_t res; 2740 ndi_ra_request_t req; 2741 uint32_t base = window->base; 2742 2743 #if defined(PCIC_DEBUG) 2744 if (pcic_debug) { 2745 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2746 cmn_err(CE_CONT, 2747 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2748 window->window, window->socket, window->WindowSize, 2749 window->speed); 2750 cmn_err(CE_CONT, 2751 "\tbase=%x, state=%x\n", (unsigned)window->base, 2752 (unsigned)window->state); 2753 } 2754 #endif 2755 2756 /* 2757 * do some basic sanity checking on what we support 2758 * we don't do paged mode 2759 */ 2760 if (window->state & WS_PAGED) { 2761 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2762 return (BAD_ATTRIBUTE); 2763 } 2764 2765 /* 2766 * we don't care about previous mappings. 2767 * Card Services will deal with that so don't 2768 * even check 2769 */ 2770 2771 socket = window->socket; 2772 2773 if (!(window->state & WS_IO)) { 2774 int win, tmp; 2775 pcs_memwin_t *memp; 2776 #if defined(PCIC_DEBUG) 2777 if (pcic_debug) 2778 cmn_err(CE_CONT, "\twindow type is memory\n"); 2779 #endif 2780 /* this is memory window mapping */ 2781 win = window->window % PCIC_NUMWINSOCK; 2782 tmp = window->window / PCIC_NUMWINSOCK; 2783 2784 /* only windows 2-6 can do memory mapping */ 2785 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2786 cmn_err(CE_CONT, 2787 "\tattempt to map to non-mem window\n"); 2788 return (BAD_WINDOW); 2789 } 2790 2791 if (window->WindowSize == 0) 2792 window->WindowSize = MEM_MIN; 2793 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2794 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2795 return (BAD_SIZE); 2796 } 2797 2798 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2799 2800 memp = &sockp->pcs_windows[win].mem; 2801 memp->pcw_speed = window->speed; 2802 2803 win -= PCIC_IOWINDOWS; /* put in right range */ 2804 2805 if (window->WindowSize != memp->pcw_len) 2806 which = memp->pcw_len; 2807 else 2808 which = 0; 2809 2810 if (window->state & WS_ENABLED) { 2811 uint32_t wspeed; 2812 #if defined(PCIC_DEBUG) 2813 if (pcic_debug) { 2814 cmn_err(CE_CONT, 2815 "\tbase=%x, win=%d\n", (unsigned)base, 2816 win); 2817 if (which) 2818 cmn_err(CE_CONT, 2819 "\tneed to remap window\n"); 2820 } 2821 #endif 2822 2823 if (which && (memp->pcw_status & PCW_MAPPED)) { 2824 ddi_regs_map_free(&memp->pcw_handle); 2825 res.ra_addr_lo = memp->pcw_base; 2826 res.ra_len = memp->pcw_len; 2827 (void) pcmcia_free_mem(dip, &res); 2828 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2829 memp->pcw_hostmem = NULL; 2830 memp->pcw_base = NULL; 2831 memp->pcw_len = 0; 2832 } 2833 2834 which = window->WindowSize >> PAGE_SHIFT; 2835 2836 if (!(memp->pcw_status & PCW_MAPPED)) { 2837 ret = 0; 2838 2839 memp->pcw_base = base; 2840 bzero(&req, sizeof (req)); 2841 req.ra_len = which << PAGE_SHIFT; 2842 req.ra_addr = (uint64_t)memp->pcw_base; 2843 req.ra_boundbase = pcic->pc_base; 2844 req.ra_boundlen = pcic->pc_bound; 2845 req.ra_flags = (memp->pcw_base ? 2846 NDI_RA_ALLOC_SPECIFIED : 0) | 2847 NDI_RA_ALLOC_BOUNDED; 2848 req.ra_align_mask = 2849 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2850 #if defined(PCIC_DEBUG) 2851 pcic_err(dip, 8, 2852 "\tlen 0x%"PRIx64 2853 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2854 " blen 0x%"PRIx64" flags 0x%x" 2855 " algn 0x%"PRIx64"\n", 2856 req.ra_len, req.ra_addr, 2857 req.ra_boundbase, 2858 req.ra_boundlen, req.ra_flags, 2859 req.ra_align_mask); 2860 #endif 2861 2862 ret = pcmcia_alloc_mem(dip, &req, &res); 2863 if (ret == DDI_FAILURE) { 2864 mutex_exit(&pcic->pc_lock); 2865 cmn_err(CE_WARN, 2866 "\tpcmcia_alloc_mem() failed\n"); 2867 return (BAD_SIZE); 2868 } 2869 memp->pcw_base = res.ra_addr_lo; 2870 base = memp->pcw_base; 2871 2872 #if defined(PCIC_DEBUG) 2873 if (pcic_debug) 2874 cmn_err(CE_CONT, 2875 "\tsetwindow: new base=%x\n", 2876 (unsigned)memp->pcw_base); 2877 #endif 2878 memp->pcw_len = window->WindowSize; 2879 2880 which = pcmcia_map_reg(pcic->dip, 2881 window->child, 2882 &res, 2883 (uint32_t)(window->state & 2884 0xffff) | 2885 (window->socket << 16), 2886 (caddr_t *)&memp->pcw_hostmem, 2887 &memp->pcw_handle, 2888 &window->attr, NULL); 2889 2890 if (which != DDI_SUCCESS) { 2891 2892 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2893 "failed\n"); 2894 2895 res.ra_addr_lo = memp->pcw_base; 2896 res.ra_len = memp->pcw_len; 2897 (void) pcmcia_free_mem(pcic->dip, &res); 2898 2899 mutex_exit(&pcic->pc_lock); 2900 2901 return (BAD_WINDOW); 2902 } 2903 memp->pcw_status |= PCW_MAPPED; 2904 #if defined(PCIC_DEBUG) 2905 if (pcic_debug) 2906 cmn_err(CE_CONT, 2907 "\tmap=%x, hostmem=%p\n", 2908 which, 2909 (void *)memp->pcw_hostmem); 2910 #endif 2911 } else { 2912 base = memp->pcw_base; 2913 } 2914 2915 /* report the handle back to caller */ 2916 window->handle = memp->pcw_handle; 2917 2918 #if defined(PCIC_DEBUG) 2919 if (pcic_debug) { 2920 cmn_err(CE_CONT, 2921 "\twindow mapped to %x@%x len=%d\n", 2922 (unsigned)window->base, 2923 (unsigned)memp->pcw_base, 2924 memp->pcw_len); 2925 } 2926 #endif 2927 2928 /* find the register set offset */ 2929 select = win * PCIC_MEM_1_OFFSET; 2930 #if defined(PCIC_DEBUG) 2931 if (pcic_debug) 2932 cmn_err(CE_CONT, "\tselect=%x\n", select); 2933 #endif 2934 2935 /* 2936 * at this point, the register window indicator has 2937 * been converted to be an offset from the first 2938 * set of registers that are used for programming 2939 * the window mapping and the offset used to select 2940 * the correct set of registers to access the 2941 * specified socket. This allows basing everything 2942 * off the _0 window 2943 */ 2944 2945 /* map the physical page base address */ 2946 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2947 which |= (window->speed <= MEM_SPEED_MIN) ? 2948 SYSMEM_ZERO_WAIT : 0; 2949 2950 /* need to select register set */ 2951 select = PCIC_MEM_1_OFFSET * win; 2952 2953 pcic_putb(pcic, socket, 2954 PCIC_SYSMEM_0_STARTLOW + select, 2955 SYSMEM_LOW(base)); 2956 pcic_putb(pcic, socket, 2957 PCIC_SYSMEM_0_STARTHI + select, 2958 SYSMEM_HIGH(base) | which); 2959 2960 /* 2961 * Some adapters can decode window addresses greater 2962 * than 16-bits worth, so handle them here. 2963 */ 2964 switch (pcic->pc_type) { 2965 case PCIC_INTEL_i82092: 2966 pcic_putb(pcic, socket, 2967 PCIC_82092_CPAGE, 2968 SYSMEM_EXT(base)); 2969 break; 2970 case PCIC_CL_PD6729: 2971 case PCIC_CL_PD6730: 2972 clext_reg_write(pcic, socket, 2973 PCIC_CLEXT_MMAP0_UA + win, 2974 SYSMEM_EXT(base)); 2975 break; 2976 case PCIC_TI_PCI1130: 2977 /* 2978 * Note that the TI chip has one upper byte 2979 * per socket so all windows get bound to a 2980 * 16MB segment. This must be detected and 2981 * handled appropriately. We can detect that 2982 * it is done by seeing if the pc_base has 2983 * changed and changing when the register 2984 * is first set. This will force the bounds 2985 * to be correct. 2986 */ 2987 if (pcic->pc_bound == 0xffffffff) { 2988 pcic_putb(pcic, socket, 2989 PCIC_TI_WINDOW_PAGE_PCI, 2990 SYSMEM_EXT(base)); 2991 pcic->pc_base = SYSMEM_EXT(base) << 24; 2992 pcic->pc_bound = 0x1000000; 2993 } 2994 break; 2995 case PCIC_TI_PCI1031: 2996 case PCIC_TI_PCI1131: 2997 case PCIC_TI_PCI1250: 2998 case PCIC_TI_PCI1225: 2999 case PCIC_TI_PCI1221: 3000 case PCIC_SMC_34C90: 3001 case PCIC_CL_PD6832: 3002 case PCIC_RICOH_RL5C466: 3003 case PCIC_TI_PCI1410: 3004 case PCIC_ENE_1410: 3005 case PCIC_TI_PCI1510: 3006 case PCIC_TI_PCI1520: 3007 case PCIC_O2_OZ6912: 3008 case PCIC_TI_PCI1420: 3009 case PCIC_ENE_1420: 3010 case PCIC_TI_VENDOR: 3011 case PCIC_TOSHIBA_TOPIC100: 3012 case PCIC_TOSHIBA_TOPIC95: 3013 case PCIC_TOSHIBA_VENDOR: 3014 case PCIC_RICOH_VENDOR: 3015 case PCIC_O2MICRO_VENDOR: 3016 pcic_putb(pcic, socket, 3017 PCIC_YENTA_MEM_PAGE + win, 3018 SYSMEM_EXT(base)); 3019 break; 3020 default: 3021 cmn_err(CE_NOTE, "pcic_set_window: unknown " 3022 "cardbus vendor:0x%X\n", 3023 pcic->pc_type); 3024 pcic_putb(pcic, socket, 3025 PCIC_YENTA_MEM_PAGE + win, 3026 SYSMEM_EXT(base)); 3027 3028 break; 3029 } /* switch */ 3030 3031 /* 3032 * specify the length of the mapped range 3033 * we convert to pages (rounding up) so that 3034 * the hardware gets the right thing 3035 */ 3036 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3037 3038 /* 3039 * Setup this window's timing. 3040 */ 3041 switch (pcic->pc_type) { 3042 case PCIC_CL_PD6729: 3043 case PCIC_CL_PD6730: 3044 case PCIC_CL_PD6710: 3045 case PCIC_CL_PD6722: 3046 wspeed = SYSMEM_CLTIMER_SET_0; 3047 pcic_set_cdtimers(pcic, socket, 3048 window->speed, 3049 wspeed); 3050 break; 3051 3052 case PCIC_INTEL_i82092: 3053 default: 3054 wspeed = pcic_calc_speed(pcic, window->speed); 3055 break; 3056 } /* switch */ 3057 3058 #if defined(PCIC_DEBUG) 3059 if (pcic_debug) 3060 cmn_err(CE_CONT, 3061 "\twindow %d speed bits = %x for " 3062 "%dns\n", 3063 win, (unsigned)wspeed, window->speed); 3064 #endif 3065 3066 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3067 SYSMEM_LOW(base + 3068 (pages * PCIC_PAGE)-1)); 3069 3070 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3071 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3072 wspeed); 3073 3074 /* 3075 * now map the card's memory pages - we start with page 3076 * 0 3077 * we also default to AM -- set page might change it 3078 */ 3079 base = memp->pcw_base; 3080 pcic_putb(pcic, socket, 3081 PCIC_CARDMEM_0_LOW + select, 3082 CARDMEM_LOW(0 - (uint32_t)base)); 3083 3084 pcic_putb(pcic, socket, 3085 PCIC_CARDMEM_0_HI + select, 3086 CARDMEM_HIGH(0 - (uint32_t)base) | 3087 CARDMEM_REG_ACTIVE); 3088 3089 /* 3090 * enable the window even though redundant 3091 * and SetPage may do it again. 3092 */ 3093 select = pcic_getb(pcic, socket, 3094 PCIC_MAPPING_ENABLE); 3095 select |= SYSMEM_WINDOW(win); 3096 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3097 memp->pcw_offset = 0; 3098 memp->pcw_status |= PCW_ENABLED; 3099 } else { 3100 /* 3101 * not only do we unmap the memory, the 3102 * window has been turned off. 3103 */ 3104 if (which && memp->pcw_status & PCW_MAPPED) { 3105 ddi_regs_map_free(&memp->pcw_handle); 3106 res.ra_addr_lo = memp->pcw_base; 3107 res.ra_len = memp->pcw_len; 3108 (void) pcmcia_free_mem(pcic->dip, &res); 3109 memp->pcw_hostmem = NULL; 3110 memp->pcw_status &= ~PCW_MAPPED; 3111 } 3112 3113 /* disable current mapping */ 3114 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3115 select &= ~SYSMEM_WINDOW(win); 3116 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3117 memp->pcw_status &= ~PCW_ENABLED; 3118 } 3119 memp->pcw_len = window->WindowSize; 3120 window->handle = memp->pcw_handle; 3121 #if defined(PCIC_DEBUG) 3122 if (pcic_debug) 3123 xxdmp_all_regs(pcic, window->socket, -1); 3124 #endif 3125 } else { 3126 /* 3127 * This is a request for an IO window 3128 */ 3129 int win, tmp; 3130 pcs_iowin_t *winp; 3131 /* I/O windows */ 3132 #if defined(PCIC_DEBUG) 3133 if (pcic_debug) 3134 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3135 #endif 3136 3137 /* only windows 0 and 1 can do I/O */ 3138 win = window->window % PCIC_NUMWINSOCK; 3139 tmp = window->window / PCIC_NUMWINSOCK; 3140 3141 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3142 cmn_err(CE_WARN, 3143 "\twindow is out of range (%d)\n", 3144 window->window); 3145 return (BAD_WINDOW); 3146 } 3147 3148 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3149 3150 winp = &sockp->pcs_windows[win].io; 3151 winp->pcw_speed = window->speed; 3152 if (window->WindowSize != 1 && window->WindowSize & 1) { 3153 /* we don't want an odd-size window */ 3154 window->WindowSize++; 3155 } 3156 winp->pcw_len = window->WindowSize; 3157 3158 if (window->state & WS_ENABLED) { 3159 if (winp->pcw_status & PCW_MAPPED) { 3160 ddi_regs_map_free(&winp->pcw_handle); 3161 res.ra_addr_lo = winp->pcw_base; 3162 res.ra_len = winp->pcw_len; 3163 (void) pcmcia_free_io(pcic->dip, &res); 3164 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3165 } 3166 3167 /* 3168 * if the I/O address wasn't allocated, allocate 3169 * it now. If it was allocated, it better 3170 * be free to use. 3171 * The winp->pcw_offset value is set and used 3172 * later on if the particular adapter 3173 * that we're running on has the ability 3174 * to translate IO accesses to the card 3175 * (such as some adapters in the Cirrus 3176 * Logic family). 3177 */ 3178 winp->pcw_offset = 0; 3179 3180 /* 3181 * Setup the request parameters for the 3182 * requested base and length. If 3183 * we're on an adapter that has 3184 * IO window offset registers, then 3185 * we don't need a specific base 3186 * address, just a length, and then 3187 * we'll cause the correct IO address 3188 * to be generated on the socket by 3189 * setting up the IO window offset 3190 * registers. 3191 * For adapters that support this capability, we 3192 * always use the IO window offset registers, 3193 * even if the passed base/length would be in 3194 * range. 3195 */ 3196 base = window->base; 3197 bzero(&req, sizeof (req)); 3198 req.ra_len = window->WindowSize; 3199 3200 req.ra_addr = (uint64_t) 3201 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3202 req.ra_flags = (req.ra_addr) ? 3203 NDI_RA_ALLOC_SPECIFIED : 0; 3204 3205 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3206 /* need to rethink this */ 3207 req.ra_boundbase = pcic->pc_iobase; 3208 req.ra_boundlen = pcic->pc_iobound; 3209 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3210 3211 #if defined(PCIC_DEBUG) 3212 pcic_err(dip, 8, 3213 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3214 "bbase 0x%"PRIx64 3215 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3216 PRIx64"\n", 3217 req.ra_len, (uint64_t)req.ra_addr, 3218 req.ra_boundbase, 3219 req.ra_boundlen, req.ra_flags, 3220 req.ra_align_mask); 3221 #endif 3222 3223 /* 3224 * Try to allocate the space. If we fail this, 3225 * return the appropriate error depending 3226 * on whether the caller specified a 3227 * specific base address or not. 3228 */ 3229 if (pcmcia_alloc_io(dip, &req, &res) == DDI_FAILURE) { 3230 winp->pcw_status &= ~PCW_ENABLED; 3231 mutex_exit(&pcic->pc_lock); 3232 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3233 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3234 "bbase 0x%" PRIx64 3235 "blen 0x%" PRIx64 "flags 0x%x" 3236 "algn 0x%" PRIx64 "\n", 3237 req.ra_len, req.ra_addr, 3238 req.ra_boundbase, 3239 req.ra_boundlen, req.ra_flags, 3240 req.ra_align_mask); 3241 3242 return (base?BAD_BASE:BAD_SIZE); 3243 } /* pcmcia_alloc_io */ 3244 3245 /* 3246 * Don't change the original base. Either we use 3247 * the offset registers below (PCF_IO_REMAP is set) 3248 * or it was allocated correctly anyway. 3249 */ 3250 winp->pcw_base = res.ra_addr_lo; 3251 3252 #if defined(PCIC_DEBUG) 3253 pcic_err(dip, 8, 3254 "\tsetwindow: new base=%x orig base 0x%x\n", 3255 (unsigned)winp->pcw_base, base); 3256 #endif 3257 3258 if ((which = pcmcia_map_reg(pcic->dip, 3259 window->child, 3260 &res, 3261 (uint32_t)(window->state & 3262 0xffff) | 3263 (window->socket << 16), 3264 (caddr_t *)&winp->pcw_hostmem, 3265 &winp->pcw_handle, 3266 &window->attr, 3267 base)) != DDI_SUCCESS) { 3268 3269 cmn_err(CE_WARN, "pcmcia_map_reg()" 3270 "failed\n"); 3271 3272 res.ra_addr_lo = winp->pcw_base; 3273 res.ra_len = winp->pcw_len; 3274 (void) pcmcia_free_io(pcic->dip, &res); 3275 3276 mutex_exit(&pcic->pc_lock); 3277 return (BAD_WINDOW); 3278 } 3279 3280 window->handle = winp->pcw_handle; 3281 winp->pcw_status |= PCW_MAPPED; 3282 3283 /* find the register set offset */ 3284 select = win * PCIC_IO_OFFSET; 3285 3286 #if defined(PCIC_DEBUG) 3287 if (pcic_debug) { 3288 cmn_err(CE_CONT, 3289 "\tenable: window=%d, select=%x, " 3290 "base=%x, handle=%p\n", 3291 win, select, 3292 (unsigned)window->base, 3293 (void *)window->handle); 3294 } 3295 #endif 3296 /* 3297 * at this point, the register window indicator has 3298 * been converted to be an offset from the first 3299 * set of registers that are used for programming 3300 * the window mapping and the offset used to select 3301 * the correct set of registers to access the 3302 * specified socket. This allows basing everything 3303 * off the _0 window 3304 */ 3305 3306 /* map the I/O base in */ 3307 pcic_putb(pcic, socket, 3308 PCIC_IO_ADDR_0_STARTLOW + select, 3309 LOW_BYTE((uint32_t)winp->pcw_base)); 3310 pcic_putb(pcic, socket, 3311 PCIC_IO_ADDR_0_STARTHI + select, 3312 HIGH_BYTE((uint32_t)winp->pcw_base)); 3313 3314 pcic_putb(pcic, socket, 3315 PCIC_IO_ADDR_0_STOPLOW + select, 3316 LOW_BYTE((uint32_t)winp->pcw_base + 3317 window->WindowSize - 1)); 3318 pcic_putb(pcic, socket, 3319 PCIC_IO_ADDR_0_STOPHI + select, 3320 HIGH_BYTE((uint32_t)winp->pcw_base + 3321 window->WindowSize - 1)); 3322 3323 /* 3324 * We've got the requested IO space, now see if we 3325 * need to adjust the IO window offset registers 3326 * so that the correct IO address is generated 3327 * at the socket. If this window doesn't have 3328 * this capability, then we're all done setting 3329 * up the IO resources. 3330 */ 3331 if (pcic->pc_flags & PCF_IO_REMAP) { 3332 3333 3334 /* 3335 * Note that only 16 bits are used to program 3336 * the registers but leave 32 bits on pcw_offset 3337 * so that we can generate the original base 3338 * in get_window() 3339 */ 3340 winp->pcw_offset = (base - winp->pcw_base); 3341 3342 pcic_putb(pcic, socket, 3343 PCIC_IO_OFFSET_LOW + 3344 (win * PCIC_IO_OFFSET_OFFSET), 3345 winp->pcw_offset & 0x0ff); 3346 pcic_putb(pcic, socket, 3347 PCIC_IO_OFFSET_HI + 3348 (win * PCIC_IO_OFFSET_OFFSET), 3349 (winp->pcw_offset >> 8) & 0x0ff); 3350 3351 } /* PCF_IO_REMAP */ 3352 3353 /* now get the other details (size, etc) right */ 3354 3355 /* 3356 * Set the data size control bits here. Most of the 3357 * adapters will ignore IOMEM_16BIT when 3358 * IOMEM_IOCS16 is set, except for the Intel 3359 * 82092, which only pays attention to the 3360 * IOMEM_16BIT bit. Sigh... Intel can't even 3361 * make a proper clone of their own chip. 3362 * The 82092 also apparently can't set the timing 3363 * of I/O windows. 3364 */ 3365 which = (window->state & WS_16BIT) ? 3366 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3367 3368 switch (pcic->pc_type) { 3369 case PCIC_CL_PD6729: 3370 case PCIC_CL_PD6730: 3371 case PCIC_CL_PD6710: 3372 case PCIC_CL_PD6722: 3373 case PCIC_CL_PD6832: 3374 /* 3375 * Select Timer Set 1 - this will take 3376 * effect when the PCIC_IO_CONTROL 3377 * register is written to later on; 3378 * the call to pcic_set_cdtimers 3379 * just sets up the timer itself. 3380 */ 3381 which |= IOMEM_CLTIMER_SET_1; 3382 pcic_set_cdtimers(pcic, socket, 3383 window->speed, 3384 IOMEM_CLTIMER_SET_1); 3385 which |= IOMEM_IOCS16; 3386 break; 3387 case PCIC_TI_PCI1031: 3388 3389 if (window->state & WS_16BIT) 3390 which |= IOMEM_WAIT16; 3391 3392 break; 3393 case PCIC_TI_PCI1130: 3394 3395 if (window->state & WS_16BIT) 3396 which |= IOMEM_WAIT16; 3397 3398 break; 3399 case PCIC_INTEL_i82092: 3400 break; 3401 default: 3402 if (window->speed > 3403 mhztons(pcic->bus_speed) * 3) 3404 which |= IOMEM_WAIT16; 3405 #ifdef notdef 3406 if (window->speed < 3407 mhztons(pcic->bus_speed) * 6) 3408 which |= IOMEM_ZERO_WAIT; 3409 #endif 3410 break; 3411 } /* switch (pc_type) */ 3412 3413 /* 3414 * Setup the data width and timing 3415 */ 3416 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3417 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3418 select |= IOMEM_SETWIN(win, which); 3419 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3420 3421 /* 3422 * Enable the IO window 3423 */ 3424 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3425 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3426 select | IOMEM_WINDOW(win)); 3427 3428 winp->pcw_status |= PCW_ENABLED; 3429 3430 #if defined(PCIC_DEBUG) 3431 if (pcic_debug) { 3432 cmn_err(CE_CONT, 3433 "\twhich = %x, select = %x (%x)\n", 3434 which, select, 3435 IOMEM_SETWIN(win, which)); 3436 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3437 } 3438 #endif 3439 } else { 3440 /* 3441 * not only do we unmap the IO space, the 3442 * window has been turned off. 3443 */ 3444 if (winp->pcw_status & PCW_MAPPED) { 3445 ddi_regs_map_free(&winp->pcw_handle); 3446 res.ra_addr_lo = winp->pcw_base; 3447 res.ra_len = winp->pcw_len; 3448 (void) pcmcia_free_io(pcic->dip, &res); 3449 winp->pcw_status &= ~PCW_MAPPED; 3450 } 3451 3452 /* disable current mapping */ 3453 select = pcic_getb(pcic, socket, 3454 PCIC_MAPPING_ENABLE); 3455 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3456 select &= ~IOMEM_WINDOW(win)); 3457 winp->pcw_status &= ~PCW_ENABLED; 3458 3459 winp->pcw_base = 0; 3460 winp->pcw_len = 0; 3461 winp->pcw_offset = 0; 3462 window->base = 0; 3463 /* now make sure we don't accidentally re-enable */ 3464 /* find the register set offset */ 3465 select = win * PCIC_IO_OFFSET; 3466 pcic_putb(pcic, socket, 3467 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3468 pcic_putb(pcic, socket, 3469 PCIC_IO_ADDR_0_STARTHI + select, 0); 3470 pcic_putb(pcic, socket, 3471 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3472 pcic_putb(pcic, socket, 3473 PCIC_IO_ADDR_0_STOPHI + select, 0); 3474 } 3475 } 3476 mutex_exit(&pcic->pc_lock); 3477 3478 return (SUCCESS); 3479 } 3480 3481 /* 3482 * pcic_card_state() 3483 * compute the instantaneous Card State information 3484 */ 3485 static int 3486 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3487 { 3488 int value, result; 3489 #if defined(PCIC_DEBUG) 3490 int orig_value; 3491 #endif 3492 3493 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3494 3495 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3496 3497 #if defined(PCIC_DEBUG) 3498 orig_value = value; 3499 if (pcic_debug >= 8) 3500 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3501 (void *)sockp, 3502 value, 3503 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3504 sockp->pcs_socket); 3505 #endif 3506 /* 3507 * Lie to socket services if we are not ready. 3508 * This is when we are starting up or during debounce timeouts 3509 * or if the card is a cardbus card. 3510 */ 3511 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3512 !sockp->pcs_debounce_id && 3513 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3514 result = SBM_CD; 3515 3516 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3517 result |= SBM_WP; 3518 if (value & PCIC_POWER_ON) { 3519 if (value & PCIC_READY) 3520 result |= SBM_RDYBSY; 3521 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3522 if (value & PCIC_BVD1) 3523 result |= SBM_BVD1; 3524 if (value & PCIC_BVD2) 3525 result |= SBM_BVD2; 3526 } 3527 } else 3528 result = 0; 3529 3530 mutex_exit(&pcic->pc_lock); 3531 3532 #if defined(PCIC_DEBUG) 3533 pcic_err(pcic->dip, 8, 3534 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3535 (void *) sockp, orig_value, 3536 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3537 sockp->pcs_socket, result); 3538 #endif 3539 3540 return (result); 3541 } 3542 3543 /* 3544 * pcic_set_page() 3545 * SocketServices SetPage function 3546 * set the page of PC Card memory that should be in the mapped 3547 * window 3548 */ 3549 /*ARGSUSED*/ 3550 static int 3551 pcic_set_page(dev_info_t *dip, set_page_t *page) 3552 { 3553 anp_t *anp = ddi_get_driver_private(dip); 3554 pcicdev_t *pcic = anp->an_private; 3555 int select; 3556 int which, socket, window; 3557 uint32_t base; 3558 pcs_memwin_t *memp; 3559 3560 /* get real socket/window numbers */ 3561 window = page->window % PCIC_NUMWINSOCK; 3562 socket = page->window / PCIC_NUMWINSOCK; 3563 3564 #if defined(PCIC_DEBUG) 3565 if (pcic_debug) { 3566 cmn_err(CE_CONT, 3567 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3568 window, socket, page->page); 3569 } 3570 #endif 3571 /* only windows 2-6 work on memory */ 3572 if (window < PCIC_IOWINDOWS) 3573 return (BAD_WINDOW); 3574 3575 /* only one page supported (but any size) */ 3576 if (page->page != 0) 3577 return (BAD_PAGE); 3578 3579 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3580 3581 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3582 window -= PCIC_IOWINDOWS; 3583 3584 #if defined(PCIC_DEBUG) 3585 if (pcic_debug) 3586 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3587 (uint32_t)memp->pcw_base, 3588 (void *)memp->pcw_hostmem, memp->pcw_len); 3589 #endif 3590 3591 /* window must be enabled */ 3592 if (!(memp->pcw_status & PCW_ENABLED)) 3593 return (BAD_ATTRIBUTE); 3594 3595 /* find the register set offset */ 3596 select = window * PCIC_MEM_1_OFFSET; 3597 #if defined(PCIC_DEBUG) 3598 if (pcic_debug) 3599 cmn_err(CE_CONT, "\tselect=%x\n", select); 3600 #endif 3601 3602 /* 3603 * now map the card's memory pages - we start with page 0 3604 */ 3605 3606 which = 0; /* assume simple case */ 3607 if (page->state & PS_ATTRIBUTE) { 3608 which |= CARDMEM_REG_ACTIVE; 3609 memp->pcw_status |= PCW_ATTRIBUTE; 3610 } else { 3611 memp->pcw_status &= ~PCW_ATTRIBUTE; 3612 } 3613 3614 /* 3615 * if caller says Write Protect, enforce it. 3616 */ 3617 if (page->state & PS_WP) { 3618 which |= CARDMEM_WRITE_PROTECT; 3619 memp->pcw_status |= PCW_WP; 3620 } else { 3621 memp->pcw_status &= ~PCW_WP; 3622 } 3623 #if defined(PCIC_DEBUG) 3624 if (pcic_debug) { 3625 cmn_err(CE_CONT, "\tmemory type = %s\n", 3626 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3627 if (which & CARDMEM_WRITE_PROTECT) 3628 cmn_err(CE_CONT, "\twrite protect\n"); 3629 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3630 (unsigned)page->offset, 3631 (unsigned)memp->pcw_base, 3632 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3633 } 3634 #endif 3635 /* address computation based on 64MB range and not larger */ 3636 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3637 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3638 CARDMEM_LOW((int)page->offset - (int)base)); 3639 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3640 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3641 CARDMEM_HIGH((int)page->offset - base) | which); 3642 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3643 3644 /* 3645 * while not really necessary, this just makes sure 3646 * nothing turned the window off behind our backs 3647 */ 3648 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3649 which |= SYSMEM_WINDOW(window); 3650 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3651 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3652 3653 memp->pcw_offset = (off_t)page->offset; 3654 3655 #if defined(PCIC_DEBUG) 3656 if (pcic_debug) { 3657 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3658 (void *)memp->pcw_hostmem, 3659 (uint32_t)*memp->pcw_hostmem); 3660 3661 xxdmp_all_regs(pcic, socket, -1); 3662 3663 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3664 (void *)memp->pcw_hostmem, 3665 (uint32_t)*memp->pcw_hostmem); 3666 } 3667 #endif 3668 3669 if (which & PCW_ATTRIBUTE) 3670 pcic_mswait(pcic, socket, 2); 3671 3672 mutex_exit(&pcic->pc_lock); 3673 3674 return (SUCCESS); 3675 } 3676 3677 /* 3678 * pcic_set_vcc_level() 3679 * 3680 * set voltage based on adapter information 3681 * 3682 * this routine implements a limited solution for support of 3.3v cards. 3683 * the general solution, which would fully support the pcmcia spec 3684 * as far as allowing client drivers to request which voltage levels 3685 * to be set, requires more framework support and driver changes - ess 3686 */ 3687 static int 3688 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3689 { 3690 uint32_t socket_present_state; 3691 3692 #if defined(PCIC_DEBUG) 3693 if (pcic_debug) { 3694 cmn_err(CE_CONT, 3695 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3696 (void *)pcic, socket->VccLevel); 3697 } 3698 #endif 3699 3700 /* 3701 * check VccLevel 3702 * if this is zero, power is being turned off 3703 * if it is non-zero, power is being turned on. 3704 */ 3705 if (socket->VccLevel == 0) { 3706 return (0); 3707 } 3708 3709 /* 3710 * range checking for sanity's sake 3711 */ 3712 if (socket->VccLevel >= pcic->pc_numpower) { 3713 return (BAD_VCC); 3714 } 3715 3716 switch (pcic->pc_io_type) { 3717 /* 3718 * Yenta-compliant adapters have vcc info in the extended registers 3719 * Other adapters can be added as needed, but the 'default' case 3720 * has been left as it was previously so as not to break existing 3721 * adapters. 3722 */ 3723 case PCIC_IO_TYPE_YENTA: 3724 /* 3725 * Here we ignore the VccLevel passed in and read the 3726 * card type from the adapter socket present state register 3727 */ 3728 socket_present_state = 3729 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3730 PCIC_PRESENT_STATE_REG)); 3731 #if defined(PCIC_DEBUG) 3732 if (pcic_debug) { 3733 cmn_err(CE_CONT, 3734 "socket present state = 0x%x\n", 3735 socket_present_state); 3736 } 3737 #endif 3738 switch (socket_present_state & PCIC_VCC_MASK) { 3739 case PCIC_VCC_3VCARD: 3740 /* fall through */ 3741 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3742 socket->VccLevel = PCIC_VCC_3VLEVEL; 3743 return 3744 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3745 case PCIC_VCC_5VCARD: 3746 socket->VccLevel = PCIC_VCC_5VLEVEL; 3747 return 3748 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3749 default: 3750 /* 3751 * if no card is present, this can be the 3752 * case of a client making a SetSocket call 3753 * after card removal. In this case we return 3754 * the current power level 3755 */ 3756 return ((unsigned)ddi_get8(pcic->handle, 3757 pcic->ioaddr + CB_R2_OFFSET + 3758 PCIC_POWER_CONTROL)); 3759 } 3760 3761 default: 3762 3763 switch (socket->VccLevel) { 3764 case PCIC_VCC_3VLEVEL: 3765 return (BAD_VCC); 3766 case PCIC_VCC_5VLEVEL: 3767 /* enable Vcc */ 3768 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3769 default: 3770 return (BAD_VCC); 3771 } 3772 } 3773 } 3774 3775 3776 /* 3777 * pcic_set_socket() 3778 * Socket Services SetSocket call 3779 * sets basic socket configuration 3780 */ 3781 static int 3782 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3783 { 3784 anp_t *anp = ddi_get_driver_private(dip); 3785 pcicdev_t *pcic = anp->an_private; 3786 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3787 int irq, interrupt, mirq; 3788 int powerlevel = 0; 3789 int ind, value, orig_pwrctl; 3790 3791 #if defined(PCIC_DEBUG) 3792 if (pcic_debug) { 3793 cmn_err(CE_CONT, 3794 "pcic_set_socket(dip=%p, socket=%d)" 3795 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3796 socket->socket, socket->VccLevel, socket->Vpp1Level, 3797 socket->Vpp2Level); 3798 } 3799 #endif 3800 /* 3801 * check VccLevel, etc. before setting mutex 3802 * if this is zero, power is being turned off 3803 * if it is non-zero, power is being turned on. 3804 * the default case is to assume Vcc only. 3805 */ 3806 3807 /* this appears to be very implementation specific */ 3808 3809 if (socket->Vpp1Level != socket->Vpp2Level) 3810 return (BAD_VPP); 3811 3812 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3813 powerlevel = 0; 3814 sockp->pcs_vcc = 0; 3815 sockp->pcs_vpp1 = 0; 3816 sockp->pcs_vpp2 = 0; 3817 } else { 3818 #if defined(PCIC_DEBUG) 3819 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3820 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3821 #endif 3822 /* valid Vcc power level? */ 3823 if (socket->VccLevel >= pcic->pc_numpower) 3824 return (BAD_VCC); 3825 3826 switch (pcic_power[socket->VccLevel].PowerLevel) { 3827 case 33: /* 3.3V */ 3828 case 60: /* for bad CIS in Option GPRS card */ 3829 if (!(pcic->pc_flags & PCF_33VCAP)) { 3830 cmn_err(CE_WARN, 3831 "%s%d: Bad Request for 3.3V " 3832 "(Controller incapable)\n", 3833 ddi_get_name(pcic->dip), 3834 ddi_get_instance(pcic->dip)); 3835 return (BAD_VCC); 3836 } 3837 /* FALLTHROUGH */ 3838 case 50: /* 5V */ 3839 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3840 pcic_getcb(pcic, CB_PRESENT_STATE) & 3841 CB_PS_33VCARD) { 3842 /* 3843 * This is actually a 3.3V card. 3844 * Solaris Card Services 3845 * doesn't understand 3.3V 3846 * so we cheat and change 3847 * the setting to the one appropriate to 3.3V. 3848 * Note that this is the entry number 3849 * in the pcic_power[] array. 3850 */ 3851 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3852 } else 3853 sockp->pcs_vcc = socket->VccLevel; 3854 break; 3855 default: 3856 return (BAD_VCC); 3857 } 3858 3859 /* enable Vcc */ 3860 powerlevel = POWER_CARD_ENABLE; 3861 3862 #if defined(PCIC_DEBUG) 3863 if (pcic_debug) { 3864 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3865 socket->VccLevel, powerlevel); 3866 } 3867 #endif 3868 ind = 0; /* default index to 0 power */ 3869 if ((int)socket->Vpp1Level >= 0 && 3870 socket->Vpp1Level < pcic->pc_numpower) { 3871 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3872 & VPP1)) { 3873 return (BAD_VPP); 3874 } 3875 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3876 powerlevel |= pcic_vpp_levels[ind]; 3877 sockp->pcs_vpp1 = socket->Vpp1Level; 3878 } 3879 if ((int)socket->Vpp2Level >= 0 && 3880 socket->Vpp2Level < pcic->pc_numpower) { 3881 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3882 & VPP2)) { 3883 return (BAD_VPP); 3884 } 3885 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3886 powerlevel |= (pcic_vpp_levels[ind] << 2); 3887 sockp->pcs_vpp2 = socket->Vpp2Level; 3888 } 3889 3890 if (pcic->pc_flags & PCF_VPPX) { 3891 /* 3892 * this adapter doesn't allow separate Vpp1/Vpp2 3893 * if one is turned on, both are turned on and only 3894 * the Vpp1 bits should be set 3895 */ 3896 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3897 /* must be the same if one not zero */ 3898 if (sockp->pcs_vpp1 != 0 && 3899 sockp->pcs_vpp2 != 0) { 3900 cmn_err(CE_WARN, 3901 "%s%d: Bad Power Request " 3902 "(Vpp1/2 not the same)\n", 3903 ddi_get_name(pcic->dip), 3904 ddi_get_instance(pcic->dip)); 3905 return (BAD_VPP); 3906 } 3907 } 3908 powerlevel &= ~(3<<2); 3909 } 3910 3911 #if defined(PCIC_DEBUG) 3912 if (pcic_debug) { 3913 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3914 powerlevel, ind); 3915 } 3916 #endif 3917 } 3918 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3919 3920 /* turn socket->IREQRouting off while programming */ 3921 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3922 interrupt &= ~PCIC_INTR_MASK; 3923 if (pcic->pc_flags & PCF_USE_SMI) 3924 interrupt |= PCIC_INTR_ENABLE; 3925 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3926 3927 switch (pcic->pc_type) { 3928 case PCIC_INTEL_i82092: 3929 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3930 PCIC_82092_INT_DISABLE); 3931 break; 3932 default: 3933 break; 3934 } /* switch */ 3935 3936 /* the SCIntMask specifies events to detect */ 3937 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3938 3939 #if defined(PCIC_DEBUG) 3940 if (pcic_debug) 3941 cmn_err(CE_CONT, 3942 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3943 socket->SCIntMask, interrupt, mirq); 3944 #endif 3945 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3946 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3947 mirq & ~PCIC_CHANGE_MASK); 3948 3949 /* save the mask we want to use */ 3950 sockp->pcs_intmask = socket->SCIntMask; 3951 3952 /* 3953 * Until there is a card present it's not worth enabling 3954 * any interrupts except "Card detect". This is done 3955 * elsewhere in the driver so don't change things if 3956 * there is no card! 3957 */ 3958 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3959 3960 /* now update the hardware to reflect events desired */ 3961 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3962 mirq |= PCIC_BD_DETECT; 3963 3964 if (sockp->pcs_intmask & SBM_BVD2) 3965 mirq |= PCIC_BW_DETECT; 3966 3967 if (sockp->pcs_intmask & SBM_RDYBSY) 3968 mirq |= PCIC_RD_DETECT; 3969 3970 if (sockp->pcs_intmask & SBM_CD) 3971 mirq |= PCIC_CD_DETECT; 3972 } 3973 3974 if (sockp->pcs_flags & PCS_READY) { 3975 /* 3976 * card just came ready. 3977 * make sure enough time elapses 3978 * before touching it. 3979 */ 3980 sockp->pcs_flags &= ~PCS_READY; 3981 pcic_mswait(pcic, socket->socket, 10); 3982 } 3983 3984 #if defined(PCIC_DEBUG) 3985 if (pcic_debug) { 3986 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3987 } 3988 #endif 3989 3990 switch (pcic->pc_type) { 3991 case PCIC_I82365SL: 3992 case PCIC_VADEM: 3993 case PCIC_VADEM_VG469: 3994 /* 3995 * The Intel version has different options. This is a 3996 * special case of GPI which might be used for eject 3997 */ 3998 3999 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 4000 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 4001 pcic->pc_flags & PCF_GPI_EJECT) { 4002 irq |= PCIC_GPI_ENABLE; 4003 } else { 4004 irq &= ~PCIC_GPI_ENABLE; 4005 } 4006 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 4007 break; 4008 case PCIC_CL_PD6710: 4009 case PCIC_CL_PD6722: 4010 if (socket->IFType == IF_IO) { 4011 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 4012 value = pcic_getb(pcic, socket->socket, 4013 PCIC_MISC_CTL_1); 4014 if (pcic->pc_flags & PCF_AUDIO) 4015 value |= PCIC_MC_SPEAKER_ENB; 4016 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4017 value); 4018 } else { 4019 value = pcic_getb(pcic, socket->socket, 4020 PCIC_MISC_CTL_1); 4021 value &= ~PCIC_MC_SPEAKER_ENB; 4022 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4023 value); 4024 } 4025 break; 4026 case PCIC_CL_PD6729: 4027 case PCIC_CL_PD6730: 4028 case PCIC_CL_PD6832: 4029 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4030 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4031 value |= PCIC_MC_SPEAKER_ENB; 4032 } else { 4033 value &= ~PCIC_MC_SPEAKER_ENB; 4034 } 4035 4036 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4037 value |= PCIC_MC_3VCC; 4038 else 4039 value &= ~PCIC_MC_3VCC; 4040 4041 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4042 break; 4043 4044 case PCIC_O2_OZ6912: 4045 value = pcic_getcb(pcic, CB_MISCCTRL); 4046 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4047 value |= (1<<25); 4048 else 4049 value &= ~(1<<25); 4050 pcic_putcb(pcic, CB_MISCCTRL, value); 4051 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4052 powerlevel |= 0x08; 4053 break; 4054 4055 case PCIC_TI_PCI1250: 4056 case PCIC_TI_PCI1221: 4057 case PCIC_TI_PCI1225: 4058 case PCIC_TI_PCI1410: 4059 case PCIC_ENE_1410: 4060 case PCIC_TI_PCI1510: 4061 case PCIC_TI_PCI1520: 4062 case PCIC_TI_PCI1420: 4063 case PCIC_ENE_1420: 4064 value = ddi_get8(pcic->cfg_handle, 4065 pcic->cfgaddr + PCIC_CRDCTL_REG); 4066 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4067 value |= PCIC_CRDCTL_SPKR_ENBL; 4068 } else { 4069 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4070 } 4071 ddi_put8(pcic->cfg_handle, 4072 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4073 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4074 powerlevel |= 0x08; 4075 break; 4076 } 4077 4078 /* 4079 * ctlind processing -- we can ignore this 4080 * there aren't any outputs on the chip for this and 4081 * the GUI will display what it thinks is correct 4082 */ 4083 4084 /* 4085 * If outputs are enabled and the power is going off 4086 * turn off outputs first. 4087 */ 4088 4089 /* power setup -- if necessary */ 4090 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4091 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4092 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4093 pcic_putb(pcic, socket->socket, 4094 PCIC_POWER_CONTROL, orig_pwrctl); 4095 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4096 } 4097 4098 if (pcic->pc_flags & PCF_CBPWRCTL) { 4099 value = pcic_cbus_powerctl(pcic, socket->socket); 4100 powerlevel = 0; 4101 } else 4102 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4103 4104 if (value != SUCCESS) { 4105 mutex_exit(&pcic->pc_lock); 4106 return (value); 4107 } 4108 4109 /* 4110 * If outputs were disabled and the power is going on 4111 * turn on outputs afterwards. 4112 */ 4113 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4114 orig_pwrctl = pcic_getb(pcic, socket->socket, 4115 PCIC_POWER_CONTROL); 4116 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4117 pcic_putb(pcic, socket->socket, 4118 PCIC_POWER_CONTROL, orig_pwrctl); 4119 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4120 } 4121 4122 /* 4123 * Once we have done the power stuff can re-enable management 4124 * interrupts. 4125 */ 4126 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4127 4128 #if defined(PCIC_DEBUG) 4129 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4130 "cbctl 0x%x\n", 4131 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4132 pcic_getcb(pcic, CB_CONTROL)); 4133 #endif 4134 4135 /* irq processing */ 4136 if (socket->IFType == IF_IO) { 4137 /* IRQ only for I/O */ 4138 irq = socket->IREQRouting & PCIC_INTR_MASK; 4139 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4140 value &= ~PCIC_INTR_MASK; 4141 4142 /* to enable I/O operation */ 4143 value |= PCIC_IO_CARD | PCIC_RESET; 4144 sockp->pcs_flags |= PCS_CARD_IO; 4145 if (irq != sockp->pcs_irq) { 4146 if (sockp->pcs_irq != 0) 4147 cmn_err(CE_CONT, 4148 "SetSocket: IRQ mismatch %x != %x!\n", 4149 irq, sockp->pcs_irq); 4150 else 4151 sockp->pcs_irq = irq; 4152 } 4153 irq = sockp->pcs_irq; 4154 4155 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4156 if (socket->IREQRouting & IRQ_ENABLE) { 4157 pcic_enable_io_intr(pcic, socket->socket, irq); 4158 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4159 } else { 4160 pcic_disable_io_intr(pcic, socket->socket); 4161 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4162 } 4163 #if defined(PCIC_DEBUG) 4164 if (pcic_debug) { 4165 cmn_err(CE_CONT, 4166 "\tsocket type is I/O and irq %x is %s\n", irq, 4167 (socket->IREQRouting & IRQ_ENABLE) ? 4168 "enabled" : "not enabled"); 4169 xxdmp_all_regs(pcic, socket->socket, 20); 4170 } 4171 #endif 4172 } else { 4173 /* make sure I/O mode is off */ 4174 4175 sockp->pcs_irq = 0; 4176 4177 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4178 value &= ~PCIC_IO_CARD; 4179 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4180 pcic_disable_io_intr(pcic, socket->socket); 4181 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4182 } 4183 4184 sockp->pcs_state &= ~socket->State; 4185 4186 mutex_exit(&pcic->pc_lock); 4187 return (SUCCESS); 4188 } 4189 4190 /* 4191 * pcic_inquire_socket() 4192 * SocketServices InquireSocket function 4193 * returns basic characteristics of the socket 4194 */ 4195 /*ARGSUSED*/ 4196 static int 4197 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4198 { 4199 anp_t *anp = ddi_get_driver_private(dip); 4200 pcicdev_t *pcic = anp->an_private; 4201 int value; 4202 4203 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4204 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4205 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4206 value = pcic->pc_sockets[socket->socket].pcs_flags; 4207 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4208 socket->ActiveHigh = 0; 4209 /* these are the usable IRQs */ 4210 socket->ActiveLow = 0xfff0; 4211 return (SUCCESS); 4212 } 4213 4214 /* 4215 * pcic_inquire_window() 4216 * SocketServices InquireWindow function 4217 * returns detailed characteristics of the window 4218 * this is where windows get tied to sockets 4219 */ 4220 /*ARGSUSED*/ 4221 static int 4222 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4223 { 4224 int type, socket; 4225 4226 type = window->window % PCIC_NUMWINSOCK; 4227 socket = window->window / PCIC_NUMWINSOCK; 4228 4229 #if defined(PCIC_DEBUG) 4230 if (pcic_debug >= 8) 4231 cmn_err(CE_CONT, 4232 "pcic_inquire_window: window = %d/%d socket=%d\n", 4233 window->window, type, socket); 4234 #endif 4235 if (type < PCIC_IOWINDOWS) { 4236 window->WndCaps = WC_IO|WC_WAIT; 4237 type = IF_IO; 4238 } else { 4239 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4240 type = IF_MEMORY; 4241 } 4242 4243 /* initialize the socket map - one socket per window */ 4244 PR_ZERO(window->Sockets); 4245 PR_SET(window->Sockets, socket); 4246 4247 if (type == IF_IO) { 4248 iowin_char_t *io; 4249 io = &window->iowin_char; 4250 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4251 WC_16BIT; 4252 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4253 io->LastByte = (baseaddr_t)IOMEM_LAST; 4254 io->MinSize = IOMEM_MIN; 4255 io->MaxSize = IOMEM_MAX; 4256 io->ReqGran = IOMEM_GRAN; 4257 io->AddrLines = IOMEM_DECODE; 4258 io->EISASlot = 0; 4259 } else { 4260 mem_win_char_t *mem; 4261 mem = &window->mem_win_char; 4262 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4263 WC_16BIT|WC_WP; 4264 4265 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4266 mem->LastByte = (baseaddr_t)MEM_LAST; 4267 4268 mem->MinSize = MEM_MIN; 4269 mem->MaxSize = MEM_MAX; 4270 mem->ReqGran = PCIC_PAGE; 4271 mem->ReqBase = 0; 4272 mem->ReqOffset = PCIC_PAGE; 4273 mem->Slowest = MEM_SPEED_MAX; 4274 mem->Fastest = MEM_SPEED_MIN; 4275 } 4276 return (SUCCESS); 4277 } 4278 4279 /* 4280 * pcic_get_adapter() 4281 * SocketServices GetAdapter function 4282 * this is nearly a no-op. 4283 */ 4284 /*ARGSUSED*/ 4285 static int 4286 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4287 { 4288 anp_t *anp = ddi_get_driver_private(dip); 4289 pcicdev_t *pcic = anp->an_private; 4290 4291 if (pcic->pc_flags & PCF_INTRENAB) 4292 adapt->SCRouting = IRQ_ENABLE; 4293 adapt->state = 0; 4294 return (SUCCESS); 4295 } 4296 4297 /* 4298 * pcic_get_page() 4299 * SocketServices GetPage function 4300 * returns info about the window 4301 */ 4302 /*ARGSUSED*/ 4303 static int 4304 pcic_get_page(dev_info_t *dip, get_page_t *page) 4305 { 4306 anp_t *anp = ddi_get_driver_private(dip); 4307 pcicdev_t *pcic = anp->an_private; 4308 int socket, window; 4309 pcs_memwin_t *winp; 4310 4311 socket = page->window / PCIC_NUMWINSOCK; 4312 window = page->window % PCIC_NUMWINSOCK; 4313 4314 /* I/O windows are the first two */ 4315 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4316 return (BAD_WINDOW); 4317 } 4318 4319 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4320 4321 if (page->page != 0) 4322 return (BAD_PAGE); 4323 4324 page->state = 0; 4325 if (winp->pcw_status & PCW_ENABLED) 4326 page->state |= PS_ENABLED; 4327 if (winp->pcw_status & PCW_ATTRIBUTE) 4328 page->state |= PS_ATTRIBUTE; 4329 if (winp->pcw_status & PCW_WP) 4330 page->state |= PS_WP; 4331 4332 page->offset = (off_t)winp->pcw_offset; 4333 4334 return (SUCCESS); 4335 } 4336 4337 /* 4338 * pcic_get_socket() 4339 * SocketServices GetSocket 4340 * returns information about the current socket setting 4341 */ 4342 /*ARGSUSED*/ 4343 static int 4344 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4345 { 4346 anp_t *anp = ddi_get_driver_private(dip); 4347 pcicdev_t *pcic = anp->an_private; 4348 int socknum, irq_enabled; 4349 pcic_socket_t *sockp; 4350 4351 socknum = socket->socket; 4352 sockp = &pcic->pc_sockets[socknum]; 4353 4354 socket->SCIntMask = sockp->pcs_intmask; 4355 sockp->pcs_state = pcic_card_state(pcic, sockp); 4356 4357 socket->state = sockp->pcs_state; 4358 if (socket->state & SBM_CD) { 4359 socket->VccLevel = sockp->pcs_vcc; 4360 socket->Vpp1Level = sockp->pcs_vpp1; 4361 socket->Vpp2Level = sockp->pcs_vpp2; 4362 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4363 IRQ_ENABLE : 0; 4364 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4365 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4366 IF_IO : IF_MEMORY; 4367 } else { 4368 socket->VccLevel = 0; 4369 socket->Vpp1Level = 0; 4370 socket->Vpp2Level = 0; 4371 socket->IRQRouting = 0; 4372 socket->IFType = IF_MEMORY; 4373 } 4374 socket->CtlInd = 0; /* no indicators */ 4375 4376 return (SUCCESS); 4377 } 4378 4379 /* 4380 * pcic_get_status() 4381 * SocketServices GetStatus 4382 * returns status information about the PC Card in 4383 * the selected socket 4384 */ 4385 /*ARGSUSED*/ 4386 static int 4387 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4388 { 4389 anp_t *anp = ddi_get_driver_private(dip); 4390 pcicdev_t *pcic = anp->an_private; 4391 int socknum, irq_enabled; 4392 pcic_socket_t *sockp; 4393 4394 socknum = status->socket; 4395 sockp = &pcic->pc_sockets[socknum]; 4396 4397 status->CardState = pcic_card_state(pcic, sockp); 4398 status->SocketState = sockp->pcs_state; 4399 status->CtlInd = 0; /* no indicators */ 4400 4401 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4402 status->SocketState |= SBM_CD; 4403 if (status->CardState & SBM_CD) { 4404 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4405 IRQ_ENABLE : 0; 4406 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4407 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4408 IF_IO : IF_MEMORY; 4409 } else { 4410 status->IRQRouting = 0; 4411 status->IFType = IF_MEMORY; 4412 } 4413 4414 #if defined(PCIC_DEBUG) 4415 if (pcic_debug >= 8) 4416 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4417 "SocketState=%x\n", 4418 socknum, status->CardState, status->SocketState); 4419 #endif 4420 switch (pcic->pc_type) { 4421 uint32_t present_state; 4422 case PCIC_TI_PCI1410: 4423 case PCIC_TI_PCI1520: 4424 case PCIC_TI_PCI1420: 4425 case PCIC_ENE_1420: 4426 case PCIC_TOSHIBA_TOPIC100: 4427 case PCIC_TOSHIBA_TOPIC95: 4428 case PCIC_TOSHIBA_VENDOR: 4429 case PCIC_O2MICRO_VENDOR: 4430 case PCIC_TI_VENDOR: 4431 case PCIC_RICOH_VENDOR: 4432 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4433 if (present_state & PCIC_CB_CARD) 4434 status->IFType = IF_CARDBUS; 4435 #if defined(PCIC_DEBUG) 4436 if (pcic_debug >= 8) 4437 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4438 present_state); 4439 #endif 4440 break; 4441 default: 4442 break; 4443 } 4444 4445 return (SUCCESS); 4446 } 4447 4448 /* 4449 * pcic_get_window() 4450 * SocketServices GetWindow function 4451 * returns state information about the specified window 4452 */ 4453 /*ARGSUSED*/ 4454 static int 4455 pcic_get_window(dev_info_t *dip, get_window_t *window) 4456 { 4457 anp_t *anp = ddi_get_driver_private(dip); 4458 pcicdev_t *pcic = anp->an_private; 4459 int socket, win; 4460 pcic_socket_t *sockp; 4461 pcs_memwin_t *winp; 4462 4463 socket = window->window / PCIC_NUMWINSOCK; 4464 win = window->window % PCIC_NUMWINSOCK; 4465 #if defined(PCIC_DEBUG) 4466 if (pcic_debug) { 4467 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4468 socket, win); 4469 } 4470 #endif 4471 4472 if (socket > pcic->pc_numsockets) 4473 return (BAD_WINDOW); 4474 4475 sockp = &pcic->pc_sockets[socket]; 4476 winp = &sockp->pcs_windows[win].mem; 4477 4478 window->socket = socket; 4479 window->size = winp->pcw_len; 4480 window->speed = winp->pcw_speed; 4481 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4482 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4483 4484 if (win >= PCIC_IOWINDOWS) { 4485 window->state = 0; 4486 } else { 4487 window->state = WS_IO; 4488 } 4489 if (winp->pcw_status & PCW_ENABLED) 4490 window->state |= WS_ENABLED; 4491 4492 if (winp->pcw_status & PCS_CARD_16BIT) 4493 window->state |= WS_16BIT; 4494 #if defined(PCIC_DEBUG) 4495 if (pcic_debug) 4496 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4497 window->size, (unsigned)window->speed, 4498 (void *)window->handle, window->state); 4499 #endif 4500 4501 return (SUCCESS); 4502 } 4503 4504 /* 4505 * pcic_ll_reset 4506 * low level reset 4507 * separated out so it can be called when already locked 4508 * 4509 * There are two variables that control the RESET timing: 4510 * pcic_prereset_time - time in mS before asserting RESET 4511 * pcic_reset_time - time in mS to assert RESET 4512 * 4513 */ 4514 int pcic_prereset_time = 1; 4515 int pcic_reset_time = 10; 4516 int pcic_postreset_time = 20; 4517 int pcic_vpp_is_vcc_during_reset = 0; 4518 4519 static int 4520 pcic_ll_reset(pcicdev_t *pcic, int socket) 4521 { 4522 int windowbits, iobits; 4523 uint32_t pwr; 4524 4525 /* save windows that were on */ 4526 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4527 if (pcic_reset_time == 0) 4528 return (windowbits); 4529 /* turn all windows off */ 4530 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4531 4532 #if defined(PCIC_DEBUG) 4533 pcic_err(pcic->dip, 6, 4534 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4535 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4536 pcic_getcb(pcic, CB_CONTROL), 4537 pcic_getcb(pcic, CB_PRESENT_STATE)); 4538 #endif 4539 4540 if (pcic_vpp_is_vcc_during_reset) { 4541 4542 /* 4543 * Set VPP to VCC for the duration of the reset - for aironet 4544 * card. 4545 */ 4546 if (pcic->pc_flags & PCF_CBPWRCTL) { 4547 pwr = pcic_getcb(pcic, CB_CONTROL); 4548 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4549 (void) pcic_getcb(pcic, CB_CONTROL); 4550 } else { 4551 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4552 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4553 pwr | 1); 4554 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4555 } 4556 } 4557 4558 if (pcic_prereset_time > 0) { 4559 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4560 pcic_prereset_time); 4561 pcic_mswait(pcic, socket, pcic_prereset_time); 4562 } 4563 4564 /* turn interrupts off and start a reset */ 4565 pcic_err(pcic->dip, 8, 4566 "pcic_ll_reset turn interrupts off and start a reset\n"); 4567 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4568 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4569 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4570 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4571 4572 switch (pcic->pc_type) { 4573 case PCIC_INTEL_i82092: 4574 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4575 PCIC_82092_INT_DISABLE); 4576 break; 4577 default: 4578 break; 4579 } /* switch */ 4580 4581 pcic->pc_sockets[socket].pcs_state = 0; 4582 4583 if (pcic_reset_time > 0) { 4584 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4585 pcic_reset_time); 4586 pcic_mswait(pcic, socket, pcic_reset_time); 4587 } 4588 4589 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4590 4591 /* take it out of RESET now */ 4592 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4593 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4594 4595 /* 4596 * can't access the card for 20ms, but we really don't 4597 * want to sit around that long. The pcic is still usable. 4598 * memory accesses must wait for RDY to come up. 4599 */ 4600 if (pcic_postreset_time > 0) { 4601 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4602 pcic_postreset_time); 4603 pcic_mswait(pcic, socket, pcic_postreset_time); 4604 } 4605 4606 if (pcic_vpp_is_vcc_during_reset > 1) { 4607 4608 /* 4609 * Return VPP power to whatever it was before. 4610 */ 4611 if (pcic->pc_flags & PCF_CBPWRCTL) { 4612 pcic_putcb(pcic, CB_CONTROL, pwr); 4613 (void) pcic_getcb(pcic, CB_CONTROL); 4614 } else { 4615 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4616 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4617 } 4618 } 4619 4620 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4621 4622 return (windowbits); 4623 } 4624 4625 /* 4626 * pcic_reset_socket() 4627 * SocketServices ResetSocket function 4628 * puts the PC Card in the socket into the RESET state 4629 * and then takes it out after the the cycle time 4630 * The socket is back to initial state when done 4631 */ 4632 static int 4633 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4634 { 4635 anp_t *anp = ddi_get_driver_private(dip); 4636 pcicdev_t *pcic = anp->an_private; 4637 int value; 4638 int i, mint; 4639 pcic_socket_t *sockp; 4640 4641 #if defined(PCIC_DEBUG) 4642 if (pcic_debug >= 8) 4643 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4644 (void *)dip, socket, mode, 4645 mode == RESET_MODE_FULL ? "full" : "partial"); 4646 #endif 4647 4648 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4649 4650 /* Turn off management interupts. */ 4651 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4652 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4653 4654 sockp = &pcic->pc_sockets[socket]; 4655 4656 value = pcic_ll_reset(pcic, socket); 4657 if (mode == RESET_MODE_FULL) { 4658 /* disable and unmap all mapped windows */ 4659 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4660 if (i < PCIC_IOWINDOWS) { 4661 if (sockp->pcs_windows[i].io.pcw_status & 4662 PCW_MAPPED) { 4663 pcs_iowin_t *io; 4664 io = &sockp->pcs_windows[i].io; 4665 io->pcw_status &= ~PCW_ENABLED; 4666 } 4667 } else { 4668 if (sockp->pcs_windows[i].mem.pcw_status & 4669 PCW_MAPPED) { 4670 pcs_memwin_t *mem; 4671 mem = &sockp->pcs_windows[i].mem; 4672 mem->pcw_status &= ~PCW_ENABLED; 4673 } 4674 } 4675 } 4676 } else { 4677 /* turn windows back on */ 4678 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4679 /* wait the rest of the time here */ 4680 pcic_mswait(pcic, socket, 10); 4681 } 4682 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4683 mutex_exit(&pcic->pc_lock); 4684 return (SUCCESS); 4685 } 4686 4687 /* 4688 * pcic_set_interrupt() 4689 * SocketServices SetInterrupt function 4690 */ 4691 static int 4692 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4693 { 4694 anp_t *anp = ddi_get_driver_private(dip); 4695 pcicdev_t *pcic = anp->an_private; 4696 int value = DDI_SUCCESS; 4697 inthandler_t *intr; 4698 4699 #if defined(PCIC_DEBUG) 4700 if (pcic_debug) { 4701 cmn_err(CE_CONT, 4702 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4703 pcic->pc_intr_mode); 4704 cmn_err(CE_CONT, 4705 "\t irq_top=%p handler=%p handler_id=%x\n", 4706 (void *)pcic->irq_top, (void *)handler->handler, 4707 handler->handler_id); 4708 } 4709 #endif 4710 4711 /* 4712 * If we're on a PCI bus, we route all IO IRQs through a single 4713 * PCI interrupt (typically INT A#) so we don't have to do 4714 * much other than add the caller to general interrupt handler 4715 * and set some state. 4716 */ 4717 4718 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4719 if (intr == NULL) 4720 return (NO_RESOURCE); 4721 4722 switch (pcic->pc_intr_mode) { 4723 case PCIC_INTR_MODE_PCI_1: 4724 /* 4725 * We only allow above-lock-level IO IRQ handlers 4726 * in the PCI bus case. 4727 */ 4728 4729 mutex_enter(&pcic->intr_lock); 4730 4731 if (pcic->irq_top == NULL) { 4732 pcic->irq_top = intr; 4733 pcic->irq_current = pcic->irq_top; 4734 } else { 4735 while (pcic->irq_current->next != NULL) 4736 pcic->irq_current = pcic->irq_current->next; 4737 pcic->irq_current->next = intr; 4738 pcic->irq_current = pcic->irq_current->next; 4739 } 4740 4741 pcic->irq_current->intr = 4742 (ddi_intr_handler_t *)handler->handler; 4743 pcic->irq_current->handler_id = handler->handler_id; 4744 pcic->irq_current->arg1 = handler->arg1; 4745 pcic->irq_current->arg2 = handler->arg2; 4746 pcic->irq_current->socket = handler->socket; 4747 4748 mutex_exit(&pcic->intr_lock); 4749 4750 handler->iblk_cookie = &pcic->pc_pri; 4751 handler->idev_cookie = &pcic->pc_dcookie; 4752 break; 4753 4754 default: 4755 intr->intr = (ddi_intr_handler_t *)handler->handler; 4756 intr->handler_id = handler->handler_id; 4757 intr->arg1 = handler->arg1; 4758 intr->arg2 = handler->arg2; 4759 intr->socket = handler->socket; 4760 intr->irq = handler->irq; 4761 4762 /* 4763 * need to revisit this to see if interrupts can be 4764 * shared someday. Note that IRQ is set in the common 4765 * code. 4766 */ 4767 mutex_enter(&pcic->pc_lock); 4768 if (pcic->pc_handlers == NULL) { 4769 pcic->pc_handlers = intr; 4770 intr->next = intr->prev = intr; 4771 } else { 4772 insque(intr, pcic->pc_handlers); 4773 } 4774 mutex_exit(&pcic->pc_lock); 4775 4776 break; 4777 } 4778 4779 /* 4780 * need to fill in cookies in event of multiple high priority 4781 * interrupt handlers on same IRQ 4782 */ 4783 4784 #if defined(PCIC_DEBUG) 4785 if (pcic_debug) { 4786 cmn_err(CE_CONT, 4787 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4788 (void *)pcic->irq_top, value); 4789 } 4790 #endif 4791 4792 if (value == DDI_SUCCESS) { 4793 return (SUCCESS); 4794 } else { 4795 return (BAD_IRQ); 4796 } 4797 } 4798 4799 /* 4800 * pcic_clear_interrupt() 4801 * SocketServices ClearInterrupt function 4802 * 4803 * Interrupts for PCIC are complicated by the fact that we must 4804 * follow several different models for interrupts. 4805 * ISA: there is an interrupt per adapter and per socket and 4806 * they can't be shared. 4807 * PCI: some adapters have one PCI interrupt available while others 4808 * have up to 4. Solaris may or may not allow us to use more 4809 * than 1 so we essentially share them all at this point. 4810 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4811 * This is like ISA but we have to fudge and create an intrspec 4812 * that PCI's parent understands and bypass the PCI nexus. 4813 * multifunction: this requires sharing the interrupts on a per-socket 4814 * basis. 4815 */ 4816 static int 4817 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4818 { 4819 anp_t *anp = ddi_get_driver_private(dip); 4820 pcicdev_t *pcic = anp->an_private; 4821 inthandler_t *intr, *prev, *current; 4822 int i; 4823 4824 /* 4825 * If we're on a PCI bus, we route all IO IRQs through a single 4826 * PCI interrupt (typically INT A#) so we don't have to do 4827 * much other than remove the caller from the general 4828 * interrupt handler callout list. 4829 */ 4830 4831 #if defined(PCIC_DEBUG) 4832 if (pcic_debug) { 4833 cmn_err(CE_CONT, 4834 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4835 pcic->pc_intr_mode); 4836 cmn_err(CE_CONT, 4837 "\t irq_top=%p handler=%p handler_id=%x\n", 4838 (void *)pcic->irq_top, (void *)handler->handler, 4839 handler->handler_id); 4840 } 4841 #endif 4842 4843 switch (pcic->pc_intr_mode) { 4844 case PCIC_INTR_MODE_PCI_1: 4845 4846 mutex_enter(&pcic->intr_lock); 4847 if (pcic->irq_top == NULL) { 4848 mutex_exit(&pcic->intr_lock); 4849 return (BAD_IRQ); 4850 } 4851 4852 intr = NULL; 4853 pcic->irq_current = pcic->irq_top; 4854 4855 while ((pcic->irq_current != NULL) && 4856 (pcic->irq_current->handler_id != 4857 handler->handler_id)) { 4858 intr = pcic->irq_current; 4859 pcic->irq_current = pcic->irq_current->next; 4860 } 4861 4862 if (pcic->irq_current == NULL) { 4863 mutex_exit(&pcic->intr_lock); 4864 return (BAD_IRQ); 4865 } 4866 4867 if (intr != NULL) { 4868 intr->next = pcic->irq_current->next; 4869 } else { 4870 pcic->irq_top = pcic->irq_current->next; 4871 } 4872 4873 current = pcic->irq_current; 4874 pcic->irq_current = pcic->irq_top; 4875 mutex_exit(&pcic->intr_lock); 4876 kmem_free(current, sizeof (inthandler_t)); 4877 4878 break; 4879 4880 default: 4881 4882 mutex_enter(&pcic->pc_lock); 4883 intr = pcic_handlers; 4884 prev = (inthandler_t *)&pcic_handlers; 4885 4886 while (intr != NULL) { 4887 if (intr->handler_id == handler->handler_id) { 4888 i = intr->irq & PCIC_INTR_MASK; 4889 if (--pcic_irq_map[i].count == 0) { 4890 /* multi-handler form */ 4891 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4892 (void) ddi_intr_remove_handler( 4893 pcic->pc_intr_htblp[i]); 4894 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4895 (void) pcmcia_return_intr(pcic->dip, i); 4896 #if defined(PCIC_DEBUG) 4897 if (pcic_debug) { 4898 cmn_err(CE_CONT, 4899 "removing interrupt %d at %s " 4900 "priority\n", i, "high"); 4901 cmn_err(CE_CONT, 4902 "ddi_remove_intr(%p, %x, %p)\n", 4903 (void *)dip, 4904 0, 4905 (void *)intr->iblk_cookie); 4906 } 4907 #endif 4908 } 4909 prev->next = intr->next; 4910 kmem_free(intr, sizeof (inthandler_t)); 4911 intr = prev->next; 4912 } else { 4913 prev = intr; 4914 intr = intr->next; 4915 } /* if (handler_id) */ 4916 } /* while */ 4917 4918 mutex_exit(&pcic->pc_lock); 4919 } 4920 4921 #if defined(PCIC_DEBUG) 4922 if (pcic_debug) { 4923 cmn_err(CE_CONT, 4924 "pcic_clear_interrupt: exit irq_top=%p\n", 4925 (void *)pcic->irq_top); 4926 } 4927 #endif 4928 4929 4930 return (SUCCESS); 4931 } 4932 4933 struct intel_regs { 4934 char *name; 4935 int off; 4936 char *fmt; 4937 } iregs[] = { 4938 {"ident ", 0}, 4939 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4940 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4941 "\7DRD\10OE"}, 4942 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4943 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4944 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4945 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4946 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4947 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4948 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4949 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4950 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4951 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4952 {"io0-slow ", 8}, 4953 {"io0-shi ", 9}, 4954 {"io0-elow ", 0xa}, 4955 {"io0-ehi ", 0xb}, 4956 {"io1-slow ", 0xc}, 4957 {"io1-shi ", 0xd}, 4958 {"io1-elow ", 0xe}, 4959 {"io1-ehi ", 0xf}, 4960 {"mem0-slow ", 0x10}, 4961 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4962 {"mem0-elow ", 0x12}, 4963 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4964 {"card0-low ", 0x14}, 4965 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4966 {"mem1-slow ", 0x18}, 4967 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4968 {"mem1-elow ", 0x1a}, 4969 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4970 {"card1-low ", 0x1c}, 4971 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4972 {"mem2-slow ", 0x20}, 4973 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4974 {"mem2-elow ", 0x22}, 4975 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4976 {"card2-low ", 0x24}, 4977 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4978 {"mem3-slow ", 0x28}, 4979 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4980 {"mem3-elow ", 0x2a}, 4981 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4982 {"card3-low ", 0x2c}, 4983 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4984 4985 {"mem4-slow ", 0x30}, 4986 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4987 {"mem4-elow ", 0x32}, 4988 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4989 {"card4-low ", 0x34}, 4990 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4991 {"mpage0 ", 0x40}, 4992 {"mpage1 ", 0x41}, 4993 {"mpage2 ", 0x42}, 4994 {"mpage3 ", 0x43}, 4995 {"mpage4 ", 0x44}, 4996 {NULL}, 4997 }; 4998 4999 static struct intel_regs cregs[] = { 5000 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 5001 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 5002 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 5003 {"chip-info ", 0x1f, "\20\6DUAL"}, 5004 {"IO-offlow0", 0x36}, 5005 {"IO-offhi0 ", 0x37}, 5006 {"IO-offlow1", 0x38}, 5007 {"IO-offhi1 ", 0x39}, 5008 NULL, 5009 }; 5010 5011 static struct intel_regs cxregs[] = { 5012 {"ext-ctl-1 ", 0x03, 5013 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 5014 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 5015 {"mem0-up ", 0x05}, 5016 {"mem1-up ", 0x06}, 5017 {"mem2-up ", 0x07}, 5018 {"mem3-up ", 0x08}, 5019 {"mem4-up ", 0x09}, 5020 {NULL} 5021 }; 5022 5023 void 5024 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 5025 { 5026 int i, value, j; 5027 char buff[256]; 5028 char *fmt; 5029 5030 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5031 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5032 int sval; 5033 if (cregs[i].off == PCIC_MISC_CTL_2) 5034 sval = 0; 5035 else 5036 sval = socket; 5037 value = pcic_getb(pcic, sval, cregs[i].off); 5038 if (i & 1) { 5039 if (cregs[i].fmt) 5040 fmt = "%s\t%s\t%b\n"; 5041 else 5042 fmt = "%s\t%s\t%x\n"; 5043 cmn_err(CE_CONT, fmt, buff, 5044 cregs[i].name, value, cregs[i].fmt); 5045 buff[0] = '\0'; 5046 } else { 5047 if (cregs[i].fmt) 5048 fmt = "\t%s\t%b"; 5049 else 5050 fmt = "\t%s\t%x"; 5051 (void) sprintf(buff, fmt, 5052 cregs[i].name, value, cregs[i].fmt); 5053 for (j = strlen(buff); j < 40; j++) 5054 buff[j] = ' '; 5055 buff[40] = '\0'; 5056 } 5057 } 5058 cmn_err(CE_CONT, "%s\n", buff); 5059 5060 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5061 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5062 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5063 5064 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5065 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5066 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5067 5068 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5069 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5070 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5071 5072 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5073 5074 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5075 value = clext_reg_read(pcic, socket, cxregs[i].off); 5076 if (i & 1) { 5077 if (cxregs[i].fmt) 5078 fmt = "%s\t%s\t%b\n"; 5079 else 5080 fmt = "%s\t%s\t%x\n"; 5081 cmn_err(CE_CONT, fmt, buff, 5082 cxregs[i].name, value, cxregs[i].fmt); 5083 buff[0] = '\0'; 5084 } else { 5085 if (cxregs[i].fmt) 5086 fmt = "\t%s\t%b"; 5087 else 5088 fmt = "\t%s\t%x"; 5089 (void) sprintf(buff, fmt, 5090 cxregs[i].name, value, cxregs[i].fmt); 5091 for (j = strlen(buff); j < 40; j++) 5092 buff[j] = ' '; 5093 buff[40] = '\0'; 5094 } 5095 } 5096 } 5097 5098 #if defined(PCIC_DEBUG) 5099 static void 5100 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5101 { 5102 int i, value, j; 5103 char buff[256]; 5104 char *fmt; 5105 5106 #if defined(PCIC_DEBUG) 5107 if (pcic_debug < 2) 5108 return; 5109 #endif 5110 cmn_err(CE_CONT, 5111 "----------- PCIC Registers for socket %d---------\n", 5112 socket); 5113 cmn_err(CE_CONT, 5114 "\tname value name value\n"); 5115 5116 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5117 value = pcic_getb(pcic, socket, iregs[i].off); 5118 if (i & 1) { 5119 if (iregs[i].fmt) 5120 fmt = "%s\t%s\t%b\n"; 5121 else 5122 fmt = "%s\t%s\t%x\n"; 5123 cmn_err(CE_CONT, fmt, buff, 5124 iregs[i].name, value, iregs[i].fmt); 5125 buff[0] = '\0'; 5126 } else { 5127 if (iregs[i].fmt) 5128 fmt = "\t%s\t%b"; 5129 else 5130 fmt = "\t%s\t%x"; 5131 (void) sprintf(buff, fmt, 5132 iregs[i].name, value, iregs[i].fmt); 5133 for (j = strlen(buff); j < 40; j++) 5134 buff[j] = ' '; 5135 buff[40] = '\0'; 5136 } 5137 } 5138 switch (pcic->pc_type) { 5139 case PCIC_CL_PD6710: 5140 case PCIC_CL_PD6722: 5141 case PCIC_CL_PD6729: 5142 case PCIC_CL_PD6832: 5143 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5144 break; 5145 } 5146 cmn_err(CE_CONT, "%s\n", buff); 5147 } 5148 #endif 5149 5150 /* 5151 * pcic_mswait(ms) 5152 * sleep ms milliseconds 5153 * call drv_usecwait once for each ms 5154 */ 5155 static void 5156 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5157 { 5158 if (ms) { 5159 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5160 pcic_mutex_exit(&pcic->pc_lock); 5161 delay(drv_usectohz(ms*1000)); 5162 pcic_mutex_enter(&pcic->pc_lock); 5163 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5164 } 5165 } 5166 5167 /* 5168 * pcic_check_ready(pcic, index, off) 5169 * Wait for card to come ready 5170 * We only wait if the card is NOT in RESET 5171 * and power is on. 5172 */ 5173 static boolean_t 5174 pcic_check_ready(pcicdev_t *pcic, int socket) 5175 { 5176 int ifstate, intstate; 5177 5178 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5179 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5180 5181 if ((intstate & PCIC_RESET) && 5182 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5183 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5184 return (B_TRUE); 5185 5186 #ifdef PCIC_DEBUG 5187 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5188 "ifstate = 0x%x\n", intstate, ifstate); 5189 if (pcic_debug) { 5190 pcic_debug += 4; 5191 xxdmp_all_regs(pcic, socket, -1); 5192 pcic_debug -= 4; 5193 } 5194 #endif 5195 return (B_FALSE); 5196 } 5197 5198 /* 5199 * Cirrus Logic extended register read/write routines 5200 */ 5201 static int 5202 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5203 { 5204 int val; 5205 5206 switch (pcic->pc_io_type) { 5207 case PCIC_IO_TYPE_YENTA: 5208 val = ddi_get8(pcic->handle, 5209 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5210 break; 5211 default: 5212 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5213 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5214 break; 5215 } 5216 5217 return (val); 5218 } 5219 5220 static void 5221 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5222 { 5223 switch (pcic->pc_io_type) { 5224 case PCIC_IO_TYPE_YENTA: 5225 ddi_put8(pcic->handle, 5226 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5227 break; 5228 default: 5229 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5230 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5231 break; 5232 } 5233 } 5234 5235 /* 5236 * Misc PCI functions 5237 */ 5238 static void 5239 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5240 { 5241 unsigned cmd; 5242 5243 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5244 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5245 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5246 (PCI_COMM_IO|PCI_COMM_MAE)) 5247 return; 5248 5249 if (flags & PCIC_ENABLE_IO) 5250 cmd |= PCI_COMM_IO; 5251 5252 if (flags & PCIC_ENABLE_MEM) 5253 cmd |= PCI_COMM_MAE; 5254 5255 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5256 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5257 } 5258 5259 /* 5260 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5261 */ 5262 static int 5263 pcic_find_pci_type(pcicdev_t *pcic) 5264 { 5265 uint32_t vend, device; 5266 5267 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5268 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5269 "vendor-id", -1); 5270 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5271 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5272 "device-id", -1); 5273 5274 device = PCI_ID(vend, device); 5275 pcic->pc_type = device; 5276 pcic->pc_chipname = "PCI:unknown"; 5277 5278 switch (device) { 5279 case PCIC_INTEL_i82092: 5280 pcic->pc_chipname = PCIC_TYPE_i82092; 5281 break; 5282 case PCIC_CL_PD6729: 5283 pcic->pc_chipname = PCIC_TYPE_PD6729; 5284 /* 5285 * Some 6730's incorrectly identify themselves 5286 * as a 6729, so we need to do some more tests 5287 * here to see if the device that's claiming 5288 * to be a 6729 is really a 6730. 5289 */ 5290 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5291 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5292 0) { 5293 pcic->pc_chipname = PCIC_TYPE_PD6730; 5294 pcic->pc_type = PCIC_CL_PD6730; 5295 } 5296 break; 5297 case PCIC_CL_PD6730: 5298 pcic->pc_chipname = PCIC_TYPE_PD6730; 5299 break; 5300 case PCIC_CL_PD6832: 5301 pcic->pc_chipname = PCIC_TYPE_PD6832; 5302 break; 5303 case PCIC_SMC_34C90: 5304 pcic->pc_chipname = PCIC_TYPE_34C90; 5305 break; 5306 case PCIC_TOSHIBA_TOPIC95: 5307 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5308 break; 5309 case PCIC_TOSHIBA_TOPIC100: 5310 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5311 break; 5312 case PCIC_TI_PCI1031: 5313 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5314 break; 5315 case PCIC_TI_PCI1130: 5316 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5317 break; 5318 case PCIC_TI_PCI1131: 5319 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5320 break; 5321 case PCIC_TI_PCI1250: 5322 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5323 break; 5324 case PCIC_TI_PCI1225: 5325 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5326 break; 5327 case PCIC_TI_PCI1410: 5328 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5329 break; 5330 case PCIC_TI_PCI1510: 5331 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5332 break; 5333 case PCIC_TI_PCI1520: 5334 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5335 break; 5336 case PCIC_TI_PCI1221: 5337 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5338 break; 5339 case PCIC_TI_PCI1050: 5340 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5341 break; 5342 case PCIC_ENE_1410: 5343 pcic->pc_chipname = PCIC_TYPE_1410; 5344 break; 5345 case PCIC_O2_OZ6912: 5346 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5347 break; 5348 case PCIC_RICOH_RL5C466: 5349 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5350 break; 5351 case PCIC_TI_PCI1420: 5352 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5353 break; 5354 case PCIC_ENE_1420: 5355 pcic->pc_chipname = PCIC_TYPE_1420; 5356 break; 5357 default: 5358 switch (PCI_ID(vend, (uint32_t)0)) { 5359 case PCIC_TOSHIBA_VENDOR: 5360 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5361 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5362 break; 5363 case PCIC_TI_VENDOR: 5364 pcic->pc_chipname = PCIC_TYPE_TI; 5365 pcic->pc_type = PCIC_TI_VENDOR; 5366 break; 5367 case PCIC_O2MICRO_VENDOR: 5368 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5369 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5370 break; 5371 case PCIC_RICOH_VENDOR: 5372 pcic->pc_chipname = PCIC_TYPE_RICOH; 5373 pcic->pc_type = PCIC_RICOH_VENDOR; 5374 break; 5375 default: 5376 if (!(pcic->pc_flags & PCF_CARDBUS)) 5377 return (DDI_FAILURE); 5378 pcic->pc_chipname = PCIC_TYPE_YENTA; 5379 break; 5380 } 5381 } 5382 return (DDI_SUCCESS); 5383 } 5384 5385 static void 5386 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5387 { 5388 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5389 pcic->cfgaddr + PCIC_82092_PPIRR); 5390 uchar_t val; 5391 5392 if (intr == PCIC_82092_CTL_SMI) { 5393 val = PCIC_82092_SMI_CTL(socket, 5394 PCIC_82092_INT_DISABLE); 5395 ppirr &= ~val; 5396 val = PCIC_82092_SMI_CTL(socket, state); 5397 ppirr |= val; 5398 } else { 5399 val = PCIC_82092_IRQ_CTL(socket, 5400 PCIC_82092_INT_DISABLE); 5401 ppirr &= ~val; 5402 val = PCIC_82092_IRQ_CTL(socket, state); 5403 ppirr |= val; 5404 } 5405 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5406 ppirr); 5407 } 5408 5409 static uint_t 5410 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5411 { 5412 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5413 uint_t rc = DDI_INTR_UNCLAIMED; 5414 5415 _NOTE(ARGUNUSED(arg2)) 5416 5417 mutex_enter(&sockp->pcs_pcic->pc_lock); 5418 if (sockp->pcs_cd_softint_flg) { 5419 uint8_t status; 5420 sockp->pcs_cd_softint_flg = 0; 5421 rc = DDI_INTR_CLAIMED; 5422 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5423 PCIC_INTERFACE_STATUS); 5424 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5425 } 5426 mutex_exit(&sockp->pcs_pcic->pc_lock); 5427 return (rc); 5428 } 5429 5430 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5431 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5432 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5433 5434 #ifdef CARDBUS 5435 static uint32_t pcic_cbps_on = 0; 5436 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5437 CB_PS_XVCARD | CB_PS_YVCARD; 5438 #else 5439 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5440 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5441 CB_PS_CBCARD | 5442 CB_PS_XVCARD | CB_PS_YVCARD; 5443 #endif 5444 static void 5445 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5446 { 5447 boolean_t do_debounce = B_FALSE; 5448 int debounce_time = drv_usectohz(pcic_debounce_time); 5449 uint8_t irq; 5450 timeout_id_t debounce; 5451 5452 /* 5453 * Always reset debounce but may need to check original state later. 5454 */ 5455 debounce = sockp->pcs_debounce_id; 5456 sockp->pcs_debounce_id = 0; 5457 5458 /* 5459 * Check to see whether a card is present or not. There are 5460 * only two states that we are concerned with - the state 5461 * where both CD pins are asserted, which means that the 5462 * card is fully seated, and the state where neither CD 5463 * pin is asserted, which means that the card is not 5464 * present. 5465 * The CD signals are generally very noisy and cause a lot of 5466 * contact bounce as the card is being inserted and 5467 * removed, so we need to do some software debouncing. 5468 */ 5469 5470 #ifdef PCIC_DEBUG 5471 pcic_err(pcic->dip, 6, 5472 "pcic%d handle_cd_change: socket %d card status 0x%x" 5473 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5474 sockp->pcs_socket, status, debounce); 5475 #endif 5476 switch (status & PCIC_ISTAT_CD_MASK) { 5477 case PCIC_CD_PRESENT_OK: 5478 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5479 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5480 uint32_t cbps; 5481 #ifdef PCIC_DEBUG 5482 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5483 #endif 5484 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5485 #ifdef PCIC_DEBUG 5486 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5487 #endif 5488 /* 5489 * Check the CB bits are sane. 5490 */ 5491 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5492 cbps & pcic_cbps_off) { 5493 cmn_err(CE_WARN, 5494 "%s%d: Odd Cardbus Present State 0x%x\n", 5495 ddi_get_name(pcic->dip), 5496 ddi_get_instance(pcic->dip), 5497 cbps); 5498 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5499 debounce = 0; 5500 debounce_time = drv_usectohz(1000000); 5501 } 5502 if (debounce) { 5503 sockp->pcs_flags |= PCS_CARD_PRESENT; 5504 if (pcic_do_insertion) { 5505 5506 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5507 5508 if (cbps & CB_PS_16BITCARD) { 5509 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5510 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5511 /* calls pcm_adapter_callback() */ 5512 if (pcic->pc_callback) { 5513 5514 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5515 pcic->dip, PCM_DEVICETYPE, 5516 "pccard"); 5517 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5518 PCE_CARD_INSERT, 5519 sockp->pcs_socket); 5520 } 5521 } else if (cbps & CB_PS_CBCARD) { 5522 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5523 5524 if (pcic->pc_flags & PCF_CARDBUS) { 5525 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5526 #ifdef CARDBUS 5527 if (!pcic_load_cardbus(pcic, sockp)) { 5528 pcic_unload_cardbus(pcic, sockp); 5529 } 5530 5531 #else 5532 cmn_err(CE_NOTE, 5533 "32 bit Cardbus not supported in" 5534 " this device driver\n"); 5535 #endif 5536 } else { 5537 /* 5538 * Ignore the card 5539 */ 5540 cmn_err(CE_NOTE, 5541 "32 bit Cardbus not supported on this" 5542 " device\n"); 5543 } 5544 } else { 5545 cmn_err(CE_NOTE, 5546 "Unsupported PCMCIA card inserted\n"); 5547 } 5548 } 5549 syshw_send_signal(sockp->pcs_syshwsig); 5550 } else { 5551 do_debounce = B_TRUE; 5552 } 5553 } else { 5554 /* 5555 * It is possible to come through here if the system 5556 * starts up with cards already inserted. Do nothing 5557 * and don't worry about it. 5558 */ 5559 #ifdef PCIC_DEBUG 5560 pcic_err(pcic->dip, 5, 5561 "pcic%d: Odd card insertion indication on socket %d\n", 5562 ddi_get_instance(pcic->dip), 5563 sockp->pcs_socket); 5564 #endif 5565 } 5566 break; 5567 5568 default: 5569 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5570 /* 5571 * Someone has started to insert a card so delay a while. 5572 */ 5573 do_debounce = B_TRUE; 5574 break; 5575 } 5576 /* 5577 * Otherwise this is basically the same as not present 5578 * so fall through. 5579 */ 5580 5581 /* FALLTHRU */ 5582 case 0: 5583 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5584 if (pcic->pc_flags & PCF_CBPWRCTL) { 5585 pcic_putcb(pcic, CB_CONTROL, 0); 5586 } else { 5587 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5588 (void) pcic_getb(pcic, sockp->pcs_socket, 5589 PCIC_POWER_CONTROL); 5590 } 5591 #ifdef PCIC_DEBUG 5592 pcic_err(pcic->dip, 8, "Card removed\n"); 5593 #endif 5594 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5595 5596 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5597 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5598 if (pcic_do_removal && pcic->pc_callback) { 5599 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5600 PCE_CARD_REMOVAL, sockp->pcs_socket); 5601 } 5602 } 5603 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5604 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5605 sockp->pcs_flags |= PCS_CARD_CBREM; 5606 } 5607 sockp->pcs_flags |= PCS_CARD_REMOVED; 5608 5609 do_debounce = B_TRUE; 5610 } 5611 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5612 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5613 /* 5614 * Ensure that we do the unloading in the 5615 * debounce handler, that way we're not doing 5616 * nasty things in an interrupt handler. e.g. 5617 * a USB device will wait for data which will 5618 * obviously never come because we've 5619 * unplugged the device, but the wait will 5620 * wait forever because no interrupts can 5621 * come in... 5622 */ 5623 #ifdef CARDBUS 5624 pcic_unload_cardbus(pcic, sockp); 5625 /* pcic_dump_all(pcic); */ 5626 #endif 5627 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5628 } 5629 syshw_send_signal(sockp->pcs_syshwsig); 5630 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5631 } 5632 break; 5633 } /* switch */ 5634 5635 if (do_debounce) { 5636 /* 5637 * Delay doing 5638 * anything for a while so that things can settle 5639 * down a little. Interrupts are already disabled. 5640 * Reset the state and we'll reevaluate the 5641 * whole kit 'n kaboodle when the timeout fires 5642 */ 5643 #ifdef PCIC_DEBUG 5644 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5645 "socket %d.%d\n", 5646 ddi_get_instance(pcic->dip), 5647 sockp->pcs_socket); 5648 #endif 5649 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5650 5651 /* 5652 * We bug out here without re-enabling interrupts. They will 5653 * be re-enabled when the debounce timeout swings through 5654 * here. 5655 */ 5656 return; 5657 } 5658 5659 /* 5660 * Turn on Card detect interrupts. Other interrupts will be 5661 * enabled during set_socket calls. 5662 * 5663 * Note that set_socket only changes interrupt settings when there 5664 * is a card present. 5665 */ 5666 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5667 irq |= PCIC_CD_DETECT; 5668 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5669 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5670 5671 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5672 } 5673 5674 /* 5675 * pcic_getb() 5676 * get an I/O byte based on the yardware decode method 5677 */ 5678 static uint8_t 5679 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5680 { 5681 int work; 5682 5683 #if defined(PCIC_DEBUG) 5684 if (pcic_debug == 0x7fff) { 5685 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5686 (void *)pcic, socket, reg); 5687 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5688 pcic->pc_io_type, (void *)pcic->handle, 5689 (void *)pcic->ioaddr); 5690 } 5691 #endif 5692 5693 switch (pcic->pc_io_type) { 5694 case PCIC_IO_TYPE_YENTA: 5695 return (ddi_get8(pcic->handle, 5696 pcic->ioaddr + CB_R2_OFFSET + reg)); 5697 default: 5698 work = (socket * PCIC_SOCKET_1) | reg; 5699 ddi_put8(pcic->handle, pcic->ioaddr, work); 5700 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5701 } 5702 } 5703 5704 static void 5705 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5706 { 5707 int work; 5708 5709 #if defined(PCIC_DEBUG) 5710 if (pcic_debug == 0x7fff) { 5711 cmn_err(CE_CONT, 5712 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5713 (void *)pcic, socket, reg, value); 5714 cmn_err(CE_CONT, 5715 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5716 pcic->pc_io_type, (void *)pcic->handle, 5717 (void *)pcic->ioaddr); 5718 } 5719 #endif 5720 5721 5722 switch (pcic->pc_io_type) { 5723 case PCIC_IO_TYPE_YENTA: 5724 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5725 value); 5726 break; 5727 default: 5728 work = (socket * PCIC_SOCKET_1) | reg; 5729 ddi_put8(pcic->handle, pcic->ioaddr, work); 5730 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5731 break; 5732 } 5733 } 5734 5735 /* 5736 * chip identification functions 5737 */ 5738 5739 /* 5740 * chip identification: Cirrus Logic PD6710/6720/6722 5741 */ 5742 static int 5743 pcic_ci_cirrus(pcicdev_t *pcic) 5744 { 5745 int value1, value2; 5746 5747 /* Init the CL id mode */ 5748 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5749 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5750 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5751 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5752 5753 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5754 (value2 & PCIC_CI_ID) == 0) { 5755 /* chip is a Cirrus Logic and not Intel */ 5756 pcic->pc_type = PCIC_CL_PD6710; 5757 if (value1 & PCIC_CI_SLOTS) 5758 pcic->pc_chipname = PCIC_TYPE_PD6720; 5759 else 5760 pcic->pc_chipname = PCIC_TYPE_PD6710; 5761 /* now fine tune things just in case a 6722 */ 5762 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5763 if (value1 == 0) { 5764 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5765 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5766 if (value1 == 0x55) { 5767 pcic->pc_chipname = PCIC_TYPE_PD6722; 5768 pcic->pc_type = PCIC_CL_PD6722; 5769 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5770 } 5771 } 5772 return (1); 5773 } 5774 return (0); 5775 } 5776 5777 /* 5778 * chip identification: Vadem (VG365/465/468/469) 5779 */ 5780 5781 static void 5782 pcic_vadem_enable(pcicdev_t *pcic) 5783 { 5784 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5785 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5786 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5787 } 5788 5789 static int 5790 pcic_ci_vadem(pcicdev_t *pcic) 5791 { 5792 int value; 5793 5794 pcic_vadem_enable(pcic); 5795 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5796 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5797 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5798 (value | PCIC_VADEM_D3) || 5799 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5800 PCIC_VADEM_469) { 5801 int vadem, new; 5802 pcic_vadem_enable(pcic); 5803 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5804 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5805 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5806 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5807 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5808 5809 /* want to lock but leave mouse or other on */ 5810 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5811 switch (value & PCIC_REV_MASK) { 5812 case PCIC_VADEM_365: 5813 pcic->pc_chipname = PCIC_VG_365; 5814 pcic->pc_type = PCIC_VADEM; 5815 break; 5816 case PCIC_VADEM_465: 5817 pcic->pc_chipname = PCIC_VG_465; 5818 pcic->pc_type = PCIC_VADEM; 5819 pcic->pc_flags |= PCF_1SOCKET; 5820 break; 5821 case PCIC_VADEM_468: 5822 pcic->pc_chipname = PCIC_VG_468; 5823 pcic->pc_type = PCIC_VADEM; 5824 break; 5825 case PCIC_VADEM_469: 5826 pcic->pc_chipname = PCIC_VG_469; 5827 pcic->pc_type = PCIC_VADEM_VG469; 5828 break; 5829 } 5830 return (1); 5831 } 5832 return (0); 5833 } 5834 5835 /* 5836 * chip identification: Ricoh 5837 */ 5838 static int 5839 pcic_ci_ricoh(pcicdev_t *pcic) 5840 { 5841 int value; 5842 5843 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5844 switch (value) { 5845 case PCIC_RF_296: 5846 pcic->pc_type = PCIC_RICOH; 5847 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5848 return (1); 5849 case PCIC_RF_396: 5850 pcic->pc_type = PCIC_RICOH; 5851 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5852 return (1); 5853 } 5854 return (0); 5855 } 5856 5857 5858 /* 5859 * set up available address spaces in busra 5860 */ 5861 static void 5862 pcic_init_assigned(dev_info_t *dip) 5863 { 5864 pcm_regs_t *pcic_avail_p; 5865 pci_regspec_t *pci_avail_p, *regs; 5866 int len, entries, rlen; 5867 dev_info_t *pdip; 5868 5869 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5870 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5871 /* 5872 * found "available" property at the cardbus/pcmcia node 5873 * need to translate address space entries from pcmcia 5874 * format to pci format 5875 */ 5876 entries = len / sizeof (pcm_regs_t); 5877 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5878 KM_SLEEP); 5879 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5880 entries) == DDI_SUCCESS) 5881 (void) pci_resource_setup_avail(dip, pci_avail_p, 5882 entries); 5883 kmem_free(pcic_avail_p, len); 5884 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5885 return; 5886 } 5887 5888 /* 5889 * "legacy" platforms will have "available" property in pci node 5890 */ 5891 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5892 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5893 "available", (caddr_t)&pci_avail_p, &len) == 5894 DDI_PROP_SUCCESS) { 5895 /* (void) pci_resource_setup(pdip); */ 5896 kmem_free(pci_avail_p, len); 5897 break; 5898 } 5899 } 5900 5901 if (pdip == NULL) { 5902 int len; 5903 char bus_type[16] = "(unknown)"; 5904 dev_info_t *par; 5905 5906 cmn_err(CE_CONT, 5907 "?pcic_init_assigned: no available property for pcmcia\n"); 5908 5909 /* 5910 * This code is taken from pci_resource_setup() but does 5911 * not attempt to use the "available" property to populate 5912 * the ndi maps that are created. 5913 * The fact that we will actually 5914 * free some resource below (that was allocated by OBP) 5915 * should be enough to be going on with. 5916 */ 5917 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5918 len = sizeof (bus_type); 5919 5920 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5921 PROP_LEN_AND_VAL_BUF, 5922 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5923 "device_type", 5924 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5925 (strcmp(bus_type, "pci") == 0)) 5926 break; 5927 } 5928 if (par != NULL && 5929 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5930 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5931 par = NULL; 5932 } else { 5933 #ifdef CARDBUS 5934 cardbus_bus_range_t *bus_range; 5935 int k; 5936 5937 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5938 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5939 if (bus_range->lo != bus_range->hi) 5940 pcic_err(pdip, 9, "allowable bus range is " 5941 "%u->%u\n", bus_range->lo, bus_range->hi); 5942 else { 5943 pcic_err(pdip, 0, 5944 "!No spare PCI bus numbers, range is " 5945 "%u->%u, cardbus isn't usable\n", 5946 bus_range->lo, bus_range->hi); 5947 } 5948 kmem_free(bus_range, k); 5949 } else 5950 pcic_err(pdip, 0, "!No bus-range property seems to " 5951 "have been set up\n"); 5952 #endif 5953 /* 5954 * Have a valid parent with the "available" property 5955 */ 5956 (void) pci_resource_setup(pdip); 5957 } 5958 5959 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5960 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5961 "assigned-addresses", 5962 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5963 ra_return_t ra; 5964 5965 /* 5966 * On the UltraBook IIi the ranges are assigned under 5967 * openboot. If we don't free them here the first I/O 5968 * space that can be used is up above 0x10000 which 5969 * doesn't work for this driver due to restrictions 5970 * on the PCI I/O addresses the controllers can cope with. 5971 * They are never going to be used by anything else 5972 * so free them up to the general pool. AG. 5973 */ 5974 pcic_err(dip, 1, "Free assigned addresses\n"); 5975 5976 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5977 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5978 regs[0].pci_size_low == 0x1000000) { 5979 ra.ra_addr_lo = regs[0].pci_phys_low; 5980 ra.ra_len = regs[0].pci_size_low; 5981 (void) pcmcia_free_mem(dip, &ra); 5982 } 5983 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5984 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5985 (regs[1].pci_size_low == 0x8000 || 5986 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5987 { 5988 ra.ra_addr_lo = regs[1].pci_phys_low; 5989 ra.ra_len = regs[1].pci_size_low; 5990 (void) pcmcia_free_io(dip, &ra); 5991 } 5992 kmem_free((caddr_t)regs, rlen); 5993 } 5994 } 5995 5996 /* 5997 * translate "available" from pcmcia format to pci format 5998 */ 5999 static int 6000 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 6001 pci_regspec_t *pci_p, int entries) 6002 { 6003 int i, range_len, range_entries; 6004 pcic_ranges_t *pcic_range_p; 6005 6006 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 6007 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 6008 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 6009 "no ranges property for pcmcia\n"); 6010 return (DDI_FAILURE); 6011 } 6012 6013 range_entries = range_len / sizeof (pcic_ranges_t); 6014 6015 /* for each "available" entry to be translated */ 6016 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6017 int j; 6018 pcic_ranges_t *range_p = pcic_range_p; 6019 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6020 6021 /* for each "ranges" entry to be searched */ 6022 for (j = 0; j < range_entries; j++, range_p++) { 6023 uint64_t range_end = range_p->pcic_range_caddrlo + 6024 range_p->pcic_range_size; 6025 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6026 6027 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6028 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6029 (range_end < avail_end)) 6030 continue; 6031 6032 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6033 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6034 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6035 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6036 pci_p->pci_size_hi = 0; 6037 pci_p->pci_size_low = pcic_p->phys_len; 6038 } 6039 } 6040 kmem_free(pcic_range_p, range_len); 6041 return (DDI_SUCCESS); 6042 } 6043 6044 static int 6045 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6046 { 6047 if (getminor(*dev) == SYSHW_MINOR) 6048 return (syshw_open(dev, flag, otyp, cred)); 6049 #ifdef CARDBUS 6050 if (cardbus_is_cb_minor(*dev)) 6051 return (cardbus_open(dev, flag, otyp, cred)); 6052 #endif 6053 return (EINVAL); 6054 } 6055 6056 static int 6057 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6058 { 6059 if (getminor(dev) == SYSHW_MINOR) 6060 return (syshw_close(dev, flag, otyp, cred)); 6061 #ifdef CARDBUS 6062 if (cardbus_is_cb_minor(dev)) 6063 return (cardbus_close(dev, flag, otyp, cred)); 6064 #endif 6065 return (EINVAL); 6066 } 6067 6068 static int 6069 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6070 int *rval) 6071 { 6072 if (getminor(dev) == SYSHW_MINOR) 6073 return (syshw_ioctl(dev, cmd, arg, mode, cred, rval)); 6074 #ifdef CARDBUS 6075 if (cardbus_is_cb_minor(dev)) 6076 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6077 #endif 6078 return (EINVAL); 6079 } 6080 6081 6082 static boolean_t 6083 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6084 { 6085 uint32_t present_state; 6086 dev_info_t *dip = pcic->dip; 6087 set_socket_t s; 6088 get_socket_t g; 6089 boolean_t retval; 6090 unsigned vccLevel; 6091 6092 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6093 6094 pcic_mutex_exit(&pcic->pc_lock); 6095 6096 bzero(&s, sizeof (set_socket_t)); 6097 s.socket = sockp->pcs_socket; 6098 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6099 s.IFType = IF_CARDBUS; 6100 s.State = (unsigned)~0; 6101 6102 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6103 if (present_state & PCIC_VCC_3VCARD) 6104 s.VccLevel = PCIC_VCC_3VLEVEL; 6105 else if (present_state & PCIC_VCC_5VCARD) 6106 s.VccLevel = PCIC_VCC_5VLEVEL; 6107 else { 6108 cmn_err(CE_CONT, 6109 "pcic_load_cardbus: unsupported card voltage\n"); 6110 goto failure; 6111 } 6112 vccLevel = s.VccLevel; 6113 s.Vpp1Level = s.Vpp2Level = 0; 6114 6115 if (pcic_set_socket(dip, &s) != SUCCESS) 6116 goto failure; 6117 6118 if (pcic_reset_socket(dip, sockp->pcs_socket, 6119 RESET_MODE_CARD_ONLY) != SUCCESS) 6120 goto failure; 6121 6122 bzero(&g, sizeof (get_socket_t)); 6123 g.socket = sockp->pcs_socket; 6124 if (pcic_get_socket(dip, &g) != SUCCESS) 6125 goto failure; 6126 6127 bzero(&s, sizeof (set_socket_t)); 6128 s.socket = sockp->pcs_socket; 6129 s.SCIntMask = SBM_CD; 6130 s.IREQRouting = g.IRQRouting; 6131 s.IFType = g.IFType; 6132 s.CtlInd = g.CtlInd; 6133 s.State = (unsigned)~0; 6134 s.VccLevel = vccLevel; 6135 s.Vpp1Level = s.Vpp2Level = 0; 6136 6137 if (pcic_set_socket(dip, &s) != SUCCESS) 6138 goto failure; 6139 6140 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6141 goto exit; 6142 6143 failure: 6144 retval = B_FALSE; 6145 6146 exit: 6147 pcic_mutex_enter(&pcic->pc_lock); 6148 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6149 retval ? "success" : "failure"); 6150 return (retval); 6151 } 6152 6153 static void 6154 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6155 { 6156 dev_info_t *dip = pcic->dip; 6157 set_socket_t s; 6158 6159 pcic_mutex_exit(&pcic->pc_lock); 6160 6161 cardbus_unload_cardbus(dip); 6162 6163 bzero(&s, sizeof (set_socket_t)); 6164 s.socket = sockp->pcs_socket; 6165 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6166 s.IREQRouting = 0; 6167 s.IFType = IF_MEMORY; 6168 s.CtlInd = 0; 6169 s.State = 0; 6170 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6171 6172 (void) pcic_set_socket(dip, &s); 6173 6174 pcic_mutex_enter(&pcic->pc_lock); 6175 } 6176 6177 static uint32_t 6178 pcic_getcb(pcicdev_t *pcic, int reg) 6179 { 6180 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6181 6182 return (ddi_get32(pcic->handle, 6183 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6184 } 6185 6186 static void 6187 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6188 { 6189 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6190 6191 ddi_put32(pcic->handle, 6192 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6193 } 6194 6195 static void 6196 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6197 { 6198 uint8_t value; 6199 uint16_t brdgctl; 6200 6201 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6202 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6203 6204 switch (pcic->pc_type) { 6205 case PCIC_INTEL_i82092: 6206 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6207 PCIC_82092_INT_ENABLE); 6208 break; 6209 case PCIC_O2_OZ6912: 6210 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6211 value |= 0x8; 6212 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6213 break; 6214 case PCIC_CL_PD6832: 6215 case PCIC_TI_PCI1250: 6216 case PCIC_TI_PCI1221: 6217 case PCIC_TI_PCI1225: 6218 case PCIC_TI_PCI1410: 6219 case PCIC_ENE_1410: 6220 case PCIC_TI_PCI1510: 6221 case PCIC_TI_PCI1520: 6222 case PCIC_TI_PCI1420: 6223 case PCIC_ENE_1420: 6224 /* route card functional interrupts to PCI interrupts */ 6225 brdgctl = ddi_get16(pcic->cfg_handle, 6226 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6227 pcic_err(NULL, 1, 6228 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6229 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6230 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6231 ddi_put16(pcic->cfg_handle, 6232 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6233 brdgctl); 6234 /* Flush the write */ 6235 (void) ddi_get16(pcic->cfg_handle, 6236 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6237 break; 6238 default: 6239 break; 6240 } 6241 } 6242 6243 static void 6244 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6245 { 6246 uint8_t value; 6247 uint16_t brdgctl; 6248 6249 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6250 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6251 6252 switch (pcic->pc_type) { 6253 case PCIC_INTEL_i82092: 6254 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6255 PCIC_82092_INT_DISABLE); 6256 break; 6257 case PCIC_O2_OZ6912: 6258 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6259 value &= ~0x8; 6260 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6261 /* Flush the write */ 6262 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6263 break; 6264 case PCIC_CL_PD6832: 6265 case PCIC_TI_PCI1250: 6266 case PCIC_TI_PCI1221: 6267 case PCIC_TI_PCI1225: 6268 case PCIC_TI_PCI1410: 6269 case PCIC_ENE_1410: 6270 case PCIC_TI_PCI1510: 6271 case PCIC_TI_PCI1520: 6272 case PCIC_TI_PCI1420: 6273 case PCIC_ENE_1420: 6274 /* 6275 * This maps I/O interrupts to ExCA which 6276 * have been turned off by the write to 6277 * PCIC_INTERRUPT above. It would appear to 6278 * be the only way to actually turn I/O Ints off 6279 * while retaining CS Ints. 6280 */ 6281 brdgctl = ddi_get16(pcic->cfg_handle, 6282 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6283 pcic_err(NULL, 1, 6284 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6285 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6286 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6287 ddi_put16(pcic->cfg_handle, 6288 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6289 brdgctl); 6290 /* Flush the write */ 6291 (void) ddi_get16(pcic->cfg_handle, 6292 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6293 break; 6294 default: 6295 break; 6296 } 6297 } 6298 6299 static void 6300 pcic_cb_enable_intr(dev_info_t *dip) 6301 { 6302 anp_t *anp = ddi_get_driver_private(dip); 6303 pcicdev_t *pcic = anp->an_private; 6304 6305 mutex_enter(&pcic->pc_lock); 6306 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6307 mutex_exit(&pcic->pc_lock); 6308 } 6309 6310 static void 6311 pcic_cb_disable_intr(dev_info_t *dip) 6312 { 6313 anp_t *anp = ddi_get_driver_private(dip); 6314 pcicdev_t *pcic = anp->an_private; 6315 6316 mutex_enter(&pcic->pc_lock); 6317 pcic_disable_io_intr(pcic, 0); 6318 mutex_exit(&pcic->pc_lock); 6319 } 6320 6321 static int 6322 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6323 { 6324 int nerr = 0; 6325 if (e & PCI_STAT_PERROR) { 6326 nerr++; 6327 cmn_err(CE_CONT, "detected parity error.\n"); 6328 } 6329 if (e & PCI_STAT_S_SYSERR) { 6330 nerr++; 6331 if (bridge_secondary) 6332 cmn_err(CE_CONT, "received system error.\n"); 6333 else 6334 cmn_err(CE_CONT, "signalled system error.\n"); 6335 } 6336 if (e & PCI_STAT_R_MAST_AB) { 6337 nerr++; 6338 cmn_err(CE_CONT, "received master abort.\n"); 6339 } 6340 if (e & PCI_STAT_R_TARG_AB) 6341 cmn_err(CE_CONT, "received target abort.\n"); 6342 if (e & PCI_STAT_S_TARG_AB) 6343 cmn_err(CE_CONT, "signalled target abort\n"); 6344 if (e & PCI_STAT_S_PERROR) { 6345 nerr++; 6346 cmn_err(CE_CONT, "signalled parity error\n"); 6347 } 6348 return (nerr); 6349 } 6350 6351 #if defined(__sparc) 6352 static int 6353 pcic_fault(enum pci_fault_ops op, void *arg) 6354 { 6355 pcicdev_t *pcic = (pcicdev_t *)arg; 6356 ushort_t pci_cfg_stat = 6357 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6358 ushort_t pci_cfg_sec_stat = 6359 pci_config_get16(pcic->cfg_handle, 0x16); 6360 char nm[24]; 6361 int nerr = 0; 6362 6363 cardbus_dump_pci_config(pcic->dip); 6364 6365 switch (op) { 6366 case FAULT_LOG: 6367 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6368 ddi_get_instance(pcic->dip)); 6369 6370 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6371 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6372 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6373 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6374 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6375 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6376 return (nerr); 6377 case FAULT_POKEFINI: 6378 case FAULT_RESET: 6379 pci_config_put16(pcic->cfg_handle, 6380 PCI_CONF_STAT, pci_cfg_stat); 6381 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6382 break; 6383 case FAULT_POKEFLT: 6384 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6385 return (1); 6386 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6387 return (1); 6388 break; 6389 default: 6390 break; 6391 } 6392 return (DDI_SUCCESS); 6393 } 6394 #endif 6395 6396 static void 6397 pcic_delayed_resume(void *arg) 6398 { 6399 int i, j, interrupt; 6400 anp_t *pcic_nexus; 6401 pcicdev_t *pcic; 6402 6403 _NOTE(ARGUNUSED(arg)) 6404 6405 #if defined(PCIC_DEBUG) 6406 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6407 #endif 6408 for (j = 0; j <= pcic_maxinst; j++) { 6409 6410 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6411 if (!pcic_nexus) 6412 continue; 6413 pcic = (pcicdev_t *)pcic_nexus->an_private; 6414 if (!pcic) 6415 continue; 6416 6417 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6418 for (i = 0; i < pcic->pc_numsockets; i++) { 6419 /* Enable interrupts on PCI if needs be */ 6420 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6421 if (pcic->pc_flags & PCF_USE_SMI) 6422 interrupt |= PCIC_INTR_ENABLE; 6423 pcic_putb(pcic, i, PCIC_INTERRUPT, 6424 PCIC_RESET | interrupt); 6425 pcic->pc_sockets[i].pcs_debounce_id = 6426 pcic_add_debqueue(&pcic->pc_sockets[i], 6427 drv_usectohz(pcic_debounce_time)); 6428 } 6429 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6430 if (pcic_do_pcmcia_sr) 6431 (void) pcmcia_wait_insert(pcic->dip); 6432 } 6433 } 6434 6435 static void 6436 pcic_debounce(pcic_socket_t *pcs) 6437 { 6438 uint8_t status, stschng; 6439 6440 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6441 pcs->pcs_flags &= ~PCS_STARTING; 6442 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6443 PCIC_CARD_STATUS_CHANGE); 6444 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6445 PCIC_INTERFACE_STATUS); 6446 #ifdef PCIC_DEBUG 6447 pcic_err(pcs->pcs_pcic->dip, 8, 6448 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6449 "chg 0x%x flg 0x%x\n", 6450 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6451 status, stschng, pcs->pcs_flags); 6452 #endif 6453 6454 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6455 PCIC_CD_DETECT); 6456 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6457 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6458 } 6459 6460 static void 6461 pcic_deb_thread() 6462 { 6463 callb_cpr_t cprinfo; 6464 struct debounce *debp; 6465 clock_t lastt; 6466 6467 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6468 callb_generic_cpr, "pcic debounce thread"); 6469 mutex_enter(&pcic_deb_mtx); 6470 while (pcic_deb_threadid) { 6471 while (pcic_deb_queue) { 6472 #ifdef PCIC_DEBUG 6473 pcic_dump_debqueue("Thread"); 6474 #endif 6475 debp = pcic_deb_queue; 6476 (void) drv_getparm(LBOLT, &lastt); 6477 if (lastt >= debp->expire) { 6478 pcic_deb_queue = debp->next; 6479 mutex_exit(&pcic_deb_mtx); 6480 pcic_debounce(debp->pcs); 6481 mutex_enter(&pcic_deb_mtx); 6482 kmem_free(debp, sizeof (*debp)); 6483 } else { 6484 (void) cv_timedwait(&pcic_deb_cv, 6485 &pcic_deb_mtx, debp->expire); 6486 } 6487 } 6488 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6489 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6490 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6491 } 6492 pcic_deb_threadid = (kthread_t *)1; 6493 cv_signal(&pcic_deb_cv); 6494 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6495 thread_exit(); 6496 } 6497 6498 static void * 6499 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6500 { 6501 clock_t lbolt; 6502 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6503 6504 (void) drv_getparm(LBOLT, &lbolt); 6505 dbp = kmem_alloc(sizeof (struct debounce), KM_NOSLEEP); 6506 6507 dbp->expire = lbolt + clocks; 6508 dbp->pcs = pcs; 6509 mutex_enter(&pcic_deb_mtx); 6510 while (*dbpp) { 6511 if (dbp->expire > (*dbpp)->expire) 6512 dbpp = &((*dbpp)->next); 6513 else 6514 break; 6515 } 6516 dbp->next = *dbpp; 6517 *dbpp = dbp; 6518 #ifdef PCIC_DEBUG 6519 pcic_dump_debqueue("Add"); 6520 #endif 6521 cv_signal(&pcic_deb_cv); 6522 mutex_exit(&pcic_deb_mtx); 6523 return (dbp); 6524 } 6525 6526 static void 6527 pcic_rm_debqueue(void *id) 6528 { 6529 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6530 6531 dbp = (struct debounce *)id; 6532 mutex_enter(&pcic_deb_mtx); 6533 while (*dbpp) { 6534 if (*dbpp == dbp) { 6535 *dbpp = dbp->next; 6536 kmem_free(dbp, sizeof (*dbp)); 6537 #ifdef PCIC_DEBUG 6538 pcic_dump_debqueue("Remove"); 6539 #endif 6540 cv_signal(&pcic_deb_cv); 6541 mutex_exit(&pcic_deb_mtx); 6542 return; 6543 } 6544 dbpp = &((*dbpp)->next); 6545 } 6546 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6547 mutex_exit(&pcic_deb_mtx); 6548 } 6549 6550 6551 static int pcic_powerdelay = 0; 6552 6553 static int 6554 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6555 { 6556 int ind, value, orig_pwrctl; 6557 6558 /* power setup -- if necessary */ 6559 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6560 6561 #if defined(PCIC_DEBUG) 6562 pcic_err(pcic->dip, 6, 6563 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6564 socket, powerlevel, orig_pwrctl); 6565 #endif 6566 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6567 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6568 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6569 if (powerlevel != orig_pwrctl) { 6570 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6571 int ifs; 6572 /* 6573 * set power to socket 6574 * note that the powerlevel was calculated earlier 6575 */ 6576 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6577 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6578 6579 /* 6580 * this second write to the power control register 6581 * is needed to resolve a problem on 6582 * the IBM ThinkPad 750 6583 * where the first write doesn't latch. 6584 * The second write appears to always work and 6585 * doesn't hurt the operation of other chips 6586 * so we can just use it -- this is good since we can't 6587 * determine what chip the 750 actually uses 6588 * (I suspect an early Ricoh). 6589 */ 6590 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6591 6592 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6593 pcic_mswait(pcic, socket, pcic_powerdelay); 6594 #if defined(PCIC_DEBUG) 6595 pcic_err(pcic->dip, 8, 6596 "\tpowerlevel reg = %x (ifs %x)\n", 6597 value, pcic_getb(pcic, socket, 6598 PCIC_INTERFACE_STATUS)); 6599 pcic_err(pcic->dip, 8, 6600 "CBus regs: PS 0x%x, Control 0x%x\n", 6601 pcic_getcb(pcic, CB_PRESENT_STATE), 6602 pcic_getcb(pcic, CB_CONTROL)); 6603 #endif 6604 /* 6605 * since power was touched, make sure it says it 6606 * is on. This lets it become stable. 6607 */ 6608 for (ind = 0; ind < 20; ind++) { 6609 ifs = pcic_getb(pcic, socket, 6610 PCIC_INTERFACE_STATUS); 6611 if (ifs & PCIC_POWER_ON) 6612 break; 6613 else { 6614 pcic_putb(pcic, socket, 6615 PCIC_POWER_CONTROL, 0); 6616 (void) pcic_getb(pcic, socket, 6617 PCIC_POWER_CONTROL); 6618 pcic_mswait(pcic, socket, 40); 6619 if (ind == 10) { 6620 pcic_putcb(pcic, CB_EVENT_FORCE, 6621 CB_EF_CVTEST); 6622 pcic_mswait(pcic, socket, 100); 6623 } 6624 pcic_putb(pcic, socket, 6625 PCIC_POWER_CONTROL, 6626 powerlevel & ~POWER_OUTPUT_ENABLE); 6627 (void) pcic_getb(pcic, socket, 6628 PCIC_POWER_CONTROL); 6629 pcic_mswait(pcic, socket, 6630 pcic_powerdelay); 6631 pcic_putb(pcic, socket, 6632 PCIC_POWER_CONTROL, powerlevel); 6633 (void) pcic_getb(pcic, socket, 6634 PCIC_POWER_CONTROL); 6635 pcic_mswait(pcic, socket, 6636 pcic_powerdelay); 6637 } 6638 } 6639 6640 if (!(ifs & PCIC_POWER_ON)) { 6641 cmn_err(CE_WARN, 6642 "pcic socket %d: Power didn't get turned" 6643 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6644 "misc1 0x%x igc 0x%x ind %d\n", 6645 socket, ifs, 6646 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6647 orig_pwrctl, 6648 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6649 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6650 ind); 6651 return (BAD_VCC); 6652 } 6653 #if defined(PCIC_DEBUG) 6654 pcic_err(pcic->dip, 8, 6655 "\tind = %d, if status %x pwrc 0x%x " 6656 "misc1 0x%x igc 0x%x\n", 6657 ind, ifs, 6658 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6659 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6660 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6661 #endif 6662 } else { 6663 /* explicitly turned off the power */ 6664 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6665 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6666 } 6667 } 6668 return (SUCCESS); 6669 } 6670 6671 static int pcic_cbdoreset_during_poweron = 1; 6672 static int 6673 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6674 { 6675 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6676 int ind, iobits; 6677 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6678 6679 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6680 6681 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6682 cbctl |= pcic_cbv_levels[ind]; 6683 6684 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6685 cbctl |= (pcic_cbv_levels[ind]<<4); 6686 6687 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6688 6689 #if defined(PCIC_DEBUG) 6690 pcic_err(pcic->dip, 6, 6691 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6692 "cbctl 0x%x->0x%x\n", 6693 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6694 #endif 6695 if (cbctl != orig_cbctl) { 6696 if (pcic_cbdoreset_during_poweron && 6697 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6698 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6699 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6700 } 6701 pcic_putcb(pcic, CB_CONTROL, cbctl); 6702 6703 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6704 pcic_mswait(pcic, socket, pcic_powerdelay); 6705 return (SUCCESS); 6706 } 6707 for (ind = 0; ind < 20; ind++) { 6708 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6709 6710 if (cbstev & CB_SE_POWER_CYCLE) { 6711 6712 /* 6713 * delay 400 ms: though the standard defines that the Vcc 6714 * set-up time is 20 ms, some PC-Card bridge requires longer 6715 * duration. 6716 * Note: We should check the status AFTER the delay to give time 6717 * for things to stabilize. 6718 */ 6719 pcic_mswait(pcic, socket, 400); 6720 6721 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6722 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6723 /* break; */ 6724 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6725 } 6726 if (cbctl & CB_PS_BADVCC) { 6727 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6728 break; 6729 } 6730 6731 #if defined(PCIC_DEBUG) 6732 pcic_err(pcic->dip, 8, 6733 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6734 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6735 cbctl, orig_cbctl); 6736 #endif 6737 if (pcic_cbdoreset_during_poweron && 6738 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6739 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6740 } 6741 return (SUCCESS); 6742 } 6743 pcic_mswait(pcic, socket, 40); 6744 } 6745 if (pcic_cbdoreset_during_poweron && 6746 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6747 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6748 } 6749 cmn_err(CE_WARN, 6750 "pcic socket %d: Power didn't get turned on/off!\n" 6751 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6752 "vcc %d vpp1 %d", socket, cbstev, 6753 pcic_getcb(pcic, CB_PRESENT_STATE), 6754 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6755 return (BAD_VCC); 6756 } 6757 return (SUCCESS); 6758 } 6759 6760 static int pcic_do_pprintf = 0; 6761 6762 static void 6763 pcic_dump_debqueue(char *msg) 6764 { 6765 struct debounce *debp = pcic_deb_queue; 6766 clock_t lbolt; 6767 6768 (void) drv_getparm(LBOLT, &lbolt); 6769 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6770 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6771 while (debp) { 6772 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6773 (void *) debp, (int)debp->expire, (void *) debp->next, 6774 debp->pcs->pcs_debounce_id); 6775 debp = debp->next; 6776 } 6777 } 6778 6779 6780 /* PRINTFLIKE3 */ 6781 static void 6782 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6783 { 6784 if (pcic_debug && (level <= pcic_debug)) { 6785 va_list adx; 6786 int instance; 6787 char buf[256]; 6788 const char *name; 6789 #if !defined(PCIC_DEBUG) 6790 int ce; 6791 char qmark = 0; 6792 6793 if (level <= 3) 6794 ce = CE_WARN; 6795 else 6796 ce = CE_CONT; 6797 if (level == 4) 6798 qmark = 1; 6799 #endif 6800 6801 if (dip) { 6802 instance = ddi_get_instance(dip); 6803 /* name = ddi_binding_name(dip); */ 6804 name = ddi_driver_name(dip); 6805 } else { 6806 instance = 0; 6807 name = ""; 6808 } 6809 6810 va_start(adx, fmt); 6811 (void) vsprintf(buf, fmt, adx); 6812 va_end(adx); 6813 6814 #if defined(PCIC_DEBUG) 6815 if (pcic_do_pprintf) { 6816 if (dip) { 6817 if (instance >= 0) 6818 prom_printf("%s(%d),0x%p: %s", name, 6819 instance, dip, buf); 6820 else 6821 prom_printf("%s,0x%p: %s", 6822 name, dip, buf); 6823 } else 6824 prom_printf(buf); 6825 } else { 6826 if (dip) { 6827 if (instance >= 0) 6828 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6829 name, instance, (void *) dip, buf); 6830 else 6831 cmn_err(CE_CONT, "%s,0x%p: %s", 6832 name, (void *) dip, buf); 6833 } else 6834 cmn_err(CE_CONT, buf); 6835 } 6836 #else 6837 if (dip) 6838 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6839 instance, buf); 6840 else 6841 cmn_err(ce, qmark ? "?%s" : buf, buf); 6842 #endif 6843 } 6844 } 6845 6846 6847 static void 6848 pcic_syshw_cardstate(syshw_t *item, void *arg) 6849 { 6850 pcic_socket_t *pcs = (pcic_socket_t *)arg; 6851 6852 if (pcs->pcs_flags & PCS_CARD_PRESENT) { 6853 item->state = B_TRUE; 6854 if (pcs->pcs_flags & PCS_CARD_IS16BIT) 6855 item->values[0] = 1; 6856 else if (pcs->pcs_flags & PCS_CARD_ISCARDBUS) 6857 item->values[0] = 2; 6858 else 6859 item->values[0] = 0; 6860 } else { 6861 item->state = B_FALSE; 6862 item->values[0] = 0; 6863 } 6864 } 6865 6866 /* 6867 * Tadpole additional for the syshw interface used to control the 6868 * start/stop switch which is physically linked to the GPIO1 pin 6869 * on the 1250a. 6870 */ 6871 6872 #define CLIENT_CALLED 0x8000000 6873 #define NCE_EVENT_MASK 0xffff 6874 6875 typedef struct _client { 6876 pid_t pid; /* set by kernel */ 6877 int flags; /* NCE_REGISTER... */ 6878 int priority; /* >100 unless root */ 6879 int events; /* pending event flags */ 6880 int event_sig; /* SIG... etc */ 6881 struct _client *next; /* set by kernel */ 6882 struct _client *prev; /* set by kernel */ 6883 } client_data; 6884 6885 static client_data *cl_data; 6886 static int n_clients; 6887 static kmutex_t client_mtx, intr_mtx; 6888 6889 static void delete_client(int); 6890 6891 #ifdef VOYAGER 6892 static uint32_t runstop_sig; 6893 static ddi_softintr_t softint_id; 6894 static uchar_t softint_flag; 6895 static int switch_debounce_time = 100; /* in milliseconds */ 6896 static timeout_id_t switch_to_id; 6897 6898 static syshw_t syshw_run_stop = { 6899 0, "Run/Stop", SH_SWITCH, 6900 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID, 6901 B_FALSE, { 0 } }; 6902 6903 static void 6904 syshw_get_run_stop(syshw_t *item, void *arg) 6905 { 6906 pcicdev_t *pcic = (pcicdev_t *)arg; 6907 6908 if (ddi_get8(pcic->cfg_handle, 6909 pcic->cfgaddr + PCIC_GPIO1_REG) & PCIC_GPIO_DIN) 6910 item->state = B_TRUE; 6911 else 6912 item->state = B_FALSE; 6913 } 6914 6915 6916 #endif 6917 6918 static void 6919 syshw_attach(pcicdev_t *pcic) 6920 { 6921 if (ddi_get_instance(pcic->dip) != 0) 6922 return; 6923 6924 #ifdef VOYAGER 6925 if (pcic->pc_type == PCIC_TI_PCI1250) { 6926 6927 /* 6928 * Only setup run/stop on a Voyager. 6929 * This is currently defined as 6930 * a TI1250 on a SPARC architecture. May have to make this a 6931 * property definition in the future. 6932 */ 6933 if (ddi_add_softintr(pcic->dip, 6934 DDI_SOFTINT_LOW, &softint_id, 6935 NULL, NULL, syshw_intr, 6936 (caddr_t)pcic) == DDI_SUCCESS) { 6937 runstop_sig = syshw_add2map(&syshw_run_stop, 6938 syshw_get_run_stop, pcic); 6939 mutex_init(&intr_mtx, NULL, MUTEX_DRIVER, 6940 pcic->pc_pri); 6941 ddi_put8(pcic->cfg_handle, 6942 pcic->cfgaddr + PCIC_GPIO1_REG, 6943 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | 6944 PCIC_GPIO_DELTA); 6945 } 6946 } 6947 #endif 6948 mutex_init(&client_mtx, "syshw client", MUTEX_DRIVER, NULL); 6949 (void) ddi_create_minor_node(pcic->dip, "syshw", S_IFCHR, 6950 SYSHW_MINOR, NULL, NULL); 6951 } 6952 6953 static void 6954 syshw_detach(pcicdev_t *pcic) 6955 { 6956 #ifdef VOYAGER 6957 if (pcic->pc_type == PCIC_TI_PCI1250) { 6958 pcic_mutex_enter(&intr_mtx); 6959 6960 /* 6961 * Turn off this interrupt. 6962 */ 6963 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6964 PCIC_GPIO_FINPUT); 6965 6966 if (switch_to_id) 6967 (void) untimeout(switch_to_id); 6968 switch_to_id = 0; 6969 softint_flag = 0; 6970 6971 pcic_mutex_exit(&intr_mtx); 6972 ddi_remove_softintr(softint_id); 6973 mutex_destroy(&intr_mtx); 6974 } 6975 #endif 6976 6977 ddi_remove_minor_node(pcic->dip, NULL); 6978 mutex_destroy(&client_mtx); 6979 } 6980 6981 static void 6982 syshw_resume(pcicdev_t *pcic) 6983 { 6984 #ifdef VOYAGER 6985 if (pcic->pc_type == PCIC_TI_PCI1250) { 6986 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6987 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | PCIC_GPIO_DELTA); 6988 } 6989 #else 6990 _NOTE(ARGUNUSED(pcic)) 6991 #endif 6992 } 6993 6994 #ifdef VOYAGER 6995 static uint_t 6996 syshw_intr_hi(pcicdev_t *pcic) 6997 { 6998 uchar_t regval; 6999 7000 if (pcic->pc_type != PCIC_TI_PCI1250) 7001 return (DDI_INTR_UNCLAIMED); 7002 7003 regval = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG); 7004 if (regval & PCIC_GPIO_DELTA) { 7005 pcic_mutex_enter(&intr_mtx); 7006 if (softint_flag == 0 && switch_to_id == 0) { 7007 softint_flag = 1; 7008 ddi_trigger_softintr(softint_id); 7009 } 7010 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 7011 regval); 7012 pcic_mutex_exit(&intr_mtx); 7013 return (DDI_INTR_CLAIMED); 7014 } 7015 7016 return (DDI_INTR_UNCLAIMED); 7017 } 7018 7019 /* 7020 * Don't deliver the signal until the debounce period has expired. 7021 * Unfortuately this means it end up as a three tier interrupt just 7022 * to indicate a bit change. 7023 */ 7024 static void 7025 syshw_debounce_to(void *arg) 7026 { 7027 _NOTE(ARGUNUSED(arg)) 7028 7029 if (switch_to_id) { 7030 pcic_mutex_enter(&intr_mtx); 7031 switch_to_id = 0; 7032 pcic_mutex_exit(&intr_mtx); 7033 syshw_send_signal(runstop_sig); 7034 return; 7035 } 7036 } 7037 7038 static uint_t 7039 syshw_intr(caddr_t arg) 7040 { 7041 _NOTE(ARGUNUSED(arg)) 7042 7043 if (softint_flag) { 7044 pcic_mutex_enter(&intr_mtx); 7045 softint_flag = 0; 7046 if (!switch_to_id) 7047 switch_to_id = timeout(syshw_debounce_to, arg, 7048 drv_usectohz(switch_debounce_time * 1000)); 7049 pcic_mutex_exit(&intr_mtx); 7050 return (DDI_INTR_CLAIMED); 7051 } 7052 return (DDI_INTR_UNCLAIMED); 7053 } 7054 #endif 7055 7056 /* 7057 * Send signals to the registered clients 7058 */ 7059 static void 7060 syshw_send_signal(int events) 7061 { 7062 client_data *ptr; 7063 proc_t *pr; 7064 int done_flag; 7065 7066 ptr = cl_data; 7067 while (ptr != NULL) { 7068 done_flag = CLIENT_CALLED; 7069 7070 if ((ptr->flags & events) && 7071 (ptr->event_sig != 0) && 7072 ((ptr->flags & done_flag) == 0)) { 7073 7074 /* 7075 * only call the process if: 7076 * it has not already received the nce signal 7077 * its signal was not zero (just in case) 7078 * and it is registered to receive this signal 7079 */ 7080 pcic_mutex_enter(&pidlock); 7081 pr = prfind(ptr->pid); 7082 pcic_mutex_exit(&pidlock); 7083 if (pr == NULL) { 7084 /* 7085 * This process has died, 7086 * so we free its memory and move on 7087 * start at the begining again: 7088 * a waste of cycles but it makes things easy.. 7089 */ 7090 delete_client(ptr->pid); 7091 ptr = cl_data; 7092 } else { 7093 ptr->events |= (events & ptr->flags & 7094 NCE_EVENT_MASK); 7095 psignal(pr, ptr->event_sig); 7096 ptr->flags |= done_flag; 7097 ptr = ptr->next; 7098 } 7099 } else { 7100 ptr = ptr->next; 7101 } 7102 } 7103 7104 ptr = cl_data; 7105 while (ptr != NULL) { 7106 ptr->flags &= ~done_flag; 7107 ptr = ptr->next; 7108 } 7109 } 7110 7111 static int 7112 syshw_open(dev_t *dev, int flag, int otyp, cred_t *cred) 7113 { 7114 _NOTE(ARGUNUSED(dev, flag, cred)) 7115 7116 if (otyp != OTYP_CHR) 7117 return (EINVAL); 7118 7119 return (0); 7120 } 7121 7122 static int 7123 syshw_close(dev_t dev, int flag, int otyp, cred_t *cred) 7124 { 7125 _NOTE(ARGUNUSED(dev, flag, otyp, cred)) 7126 7127 return (0); 7128 } 7129 7130 /* 7131 * Add a client to the list of interested processes 7132 */ 7133 static void 7134 add_client(client_data *new) 7135 { 7136 client_data * ptr; 7137 7138 n_clients++; 7139 if (cl_data == NULL) { 7140 cl_data = new; 7141 return; 7142 } 7143 7144 ptr = cl_data; 7145 while ((ptr->next != NULL) && (ptr->priority <= new->priority)) 7146 ptr = ptr->next; 7147 7148 if (ptr == cl_data) { 7149 /* at head of the list */ 7150 cl_data = new; 7151 new->next = ptr; 7152 new->prev = NULL; 7153 if (ptr != NULL) 7154 ptr->prev = new; 7155 } else { 7156 /* somewhere else in the list - insert after */ 7157 new->next = ptr->next; 7158 ptr->next = new; 7159 new->prev = ptr; 7160 if (new->next != NULL) 7161 (new->next)->prev = new; 7162 } 7163 } 7164 7165 /* 7166 * Locate a client data structure in the client list by looking for a PID match. 7167 */ 7168 static client_data * 7169 locate_client(pid_t pid) 7170 { 7171 client_data * ptr = cl_data; 7172 7173 while ((ptr != NULL) && (ptr->pid != pid)) 7174 ptr = ptr->next; 7175 7176 return (ptr); 7177 } 7178 7179 /* 7180 * Remove a client record from the client list 7181 */ 7182 static void 7183 delete_client(pid_t pid) 7184 { 7185 client_data * ptr; 7186 7187 ptr = locate_client(pid); 7188 if (ptr == NULL) 7189 return; /* hmmm!! */ 7190 7191 n_clients--; 7192 7193 if (ptr == cl_data) { 7194 /* remove the head of the list */ 7195 cl_data = ptr->next; 7196 } 7197 if (ptr->prev != NULL) 7198 (ptr->prev)->next = ptr->next; 7199 if (ptr->next != NULL) 7200 (ptr->next)->prev = ptr->prev; 7201 7202 kmem_free(ptr, sizeof (client_data)); 7203 } 7204 7205 static void 7206 unregister_event_client() 7207 { 7208 pcic_mutex_enter(&client_mtx); 7209 delete_client(ddi_get_pid()); 7210 pcic_mutex_exit(&client_mtx); 7211 } 7212 7213 static int 7214 register_event_client(client_data *u_client) 7215 { 7216 int error; 7217 client_data * client; 7218 7219 pcic_mutex_enter(&client_mtx); 7220 client = locate_client(ddi_get_pid()); 7221 if (client) { 7222 /* 7223 * we are re-registering ourself 7224 * so we delete the previous entry 7225 */ 7226 delete_client(ddi_get_pid()); 7227 } 7228 7229 client = (client_data *)kmem_alloc(sizeof (client_data), KM_SLEEP); 7230 7231 if (client) { 7232 client->pid = ddi_get_pid(); 7233 client->priority = u_client->priority; 7234 client->flags = u_client->flags & NCE_EVENT_MASK; 7235 client->events = 0; 7236 client->event_sig = u_client->event_sig; 7237 client->next = NULL; 7238 client->prev = NULL; 7239 add_client(client); 7240 error = 0; 7241 } else 7242 error = EIO; 7243 7244 pcic_mutex_exit(&client_mtx); 7245 return (error); 7246 } 7247 7248 /* 7249 * Read the currently pending event flags for the process in question 7250 */ 7251 static int 7252 check_events_pending(caddr_t data) 7253 { 7254 client_data * client; 7255 int error = 0; 7256 7257 pcic_mutex_enter(&client_mtx); 7258 client = locate_client(ddi_get_pid()); 7259 if (client) { 7260 if (copyout((caddr_t)&client->events, data, sizeof (int))) 7261 error = EFAULT; 7262 else 7263 client->events = 0; 7264 } else 7265 error = EINVAL; 7266 7267 pcic_mutex_exit(&client_mtx); 7268 return (error); 7269 } 7270 7271 7272 #define MAXITEMS 8 7273 static syshw_t *syshw_map[MAXITEMS]; 7274 static void (*syshw_getfuncs[MAXITEMS])(syshw_t *, void *); 7275 static void *syshw_getfunc_args[MAXITEMS]; 7276 static int nsyshw_items = 0; 7277 #define NSYSHW_ITEMS nsyshw_items 7278 7279 static uint32_t 7280 syshw_add2map(syshw_t *item, void (*getfunc)(syshw_t *, void *), void *getarg) 7281 { 7282 uint32_t rval = (1 << nsyshw_items); 7283 if (nsyshw_items == MAXITEMS) 7284 return (0); 7285 item->hw_id = nsyshw_items; 7286 syshw_map[nsyshw_items] = item; 7287 syshw_getfuncs[nsyshw_items] = getfunc; 7288 syshw_getfunc_args[nsyshw_items] = getarg; 7289 nsyshw_items++; 7290 return (rval); 7291 } 7292 7293 static int 7294 syshw_ioctl(dev_t dev, int cmd, intptr_t ioctldata, int mode, 7295 cred_t *cred, int *rval) 7296 { 7297 caddr_t data = (caddr_t)ioctldata; 7298 syshw_t sh; 7299 hwev_t hwev; 7300 client_data dummy_client; 7301 int rc = 0, i; 7302 7303 _NOTE(ARGUNUSED(dev, mode, cred, rval)) 7304 7305 switch (cmd) { 7306 default: 7307 rc = EINVAL; 7308 break; 7309 7310 case SYSHW_GET_ITEM: 7311 case SYSHW_GET_ITEM_MAXVALUES: 7312 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7313 rc = EFAULT; 7314 break; 7315 } 7316 7317 if (sh.hw_id >= NSYSHW_ITEMS) { 7318 rc = EINVAL; 7319 break; 7320 } 7321 7322 sh = *syshw_map[sh.hw_id]; 7323 if (!sh.id_string[0]) { 7324 rc = ENOTTY; 7325 break; 7326 } 7327 if (cmd == SYSHW_GET_ITEM) { 7328 if (syshw_getfuncs[sh.hw_id]) 7329 syshw_getfuncs[sh.hw_id](&sh, 7330 syshw_getfunc_args[sh.hw_id]); 7331 else 7332 rc = ENOTTY; 7333 } 7334 7335 if (copyout((caddr_t)&sh, data, sizeof (sh))) { 7336 rc = EFAULT; 7337 break; 7338 } 7339 break; 7340 7341 case SYSHW_SET_ITEM: 7342 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7343 rc = EFAULT; 7344 break; 7345 } 7346 7347 if (sh.hw_id >= NSYSHW_ITEMS || 7348 !syshw_map[sh.hw_id]->id_string[0] || 7349 !(syshw_map[sh.hw_id]->capabilities & 7350 (SYSHW_STATE_MODIFY | SYSHW_VAL0_MODIFY | 7351 SYSHW_VAL1_MODIFY | SYSHW_VAL2_MODIFY | 7352 SYSHW_VAL3_MODIFY))) { 7353 rc = EINVAL; 7354 break; 7355 } 7356 7357 switch (sh.hw_id) { 7358 default: 7359 rc = EINVAL; 7360 break; 7361 } 7362 break; 7363 7364 case SYSHW_EVREG: 7365 if (copyin(data, (caddr_t)&hwev, sizeof (hwev))) { 7366 rc = EFAULT; 7367 break; 7368 } 7369 7370 for (i = 0; i < NSYSHW_ITEMS; i++) { 7371 if (hwev.events & (1 << i) && 7372 !(syshw_map[i]->capabilities & 7373 SYSHW_CAN_SIGNAL_CHANGE)) { 7374 rc = EINVAL; 7375 break; 7376 } 7377 } 7378 if (hwev.event_sig != SIGUSR1 && hwev.event_sig != SIGUSR2) 7379 rc = EINVAL; 7380 7381 if (!rc) { 7382 dummy_client.priority = 100; 7383 dummy_client.flags = hwev.events; 7384 dummy_client.event_sig = hwev.event_sig; 7385 rc = register_event_client(&dummy_client); 7386 } 7387 break; 7388 7389 case SYSHW_EVUNREG: 7390 unregister_event_client(); 7391 break; 7392 7393 case SYSHW_CHKEV: 7394 rc = check_events_pending(data); 7395 break; 7396 } 7397 return (rc); 7398 } 7399