1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 31 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 32 (rdcgrp + nxgep->pt_config.hw_config.start_rdc_grpid) 33 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 34 (rdc + nxgep->pt_config.hw_config.start_rdc) 35 36 /* 37 * Globals: tunable parameters (/etc/system or adb) 38 * 39 */ 40 extern uint32_t nxge_rbr_size; 41 extern uint32_t nxge_rcr_size; 42 extern uint32_t nxge_rbr_spare_size; 43 44 extern uint32_t nxge_mblks_pending; 45 46 /* 47 * Tunable to reduce the amount of time spent in the 48 * ISR doing Rx Processing. 49 */ 50 extern uint32_t nxge_max_rx_pkts; 51 boolean_t nxge_jumbo_enable; 52 53 /* 54 * Tunables to manage the receive buffer blocks. 55 * 56 * nxge_rx_threshold_hi: copy all buffers. 57 * nxge_rx_bcopy_size_type: receive buffer block size type. 58 * nxge_rx_threshold_lo: copy only up to tunable block size type. 59 */ 60 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 61 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 62 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 63 64 static nxge_status_t nxge_map_rxdma(p_nxge_t); 65 static void nxge_unmap_rxdma(p_nxge_t); 66 67 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 68 static void nxge_rxdma_hw_stop_common(p_nxge_t); 69 70 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t); 71 static void nxge_rxdma_hw_stop(p_nxge_t); 72 73 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 74 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 75 uint32_t, 76 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 77 p_rx_mbox_t *); 78 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 79 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 80 81 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 82 uint16_t, 83 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 84 p_rx_rcr_ring_t *, p_rx_mbox_t *); 85 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 86 p_rx_rcr_ring_t, p_rx_mbox_t); 87 88 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 89 uint16_t, 90 p_nxge_dma_common_t *, 91 p_rx_rbr_ring_t *, uint32_t); 92 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 93 p_rx_rbr_ring_t); 94 95 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 96 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 97 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 98 99 mblk_t * 100 nxge_rx_pkts(p_nxge_t, uint_t, p_nxge_ldv_t, 101 p_rx_rcr_ring_t *, rx_dma_ctl_stat_t); 102 103 static void nxge_receive_packet(p_nxge_t, 104 p_rx_rcr_ring_t, 105 p_rcr_entry_t, 106 boolean_t *, 107 mblk_t **, mblk_t **); 108 109 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 110 111 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 112 static void nxge_freeb(p_rx_msg_t); 113 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, 114 p_nxge_ldv_t, rx_dma_ctl_stat_t); 115 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, uint_t, 116 p_nxge_ldv_t, rx_dma_ctl_stat_t); 117 118 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 119 uint32_t, uint32_t); 120 121 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 122 p_rx_rbr_ring_t); 123 124 125 static nxge_status_t 126 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 127 128 nxge_status_t 129 nxge_rx_port_fatal_err_recover(p_nxge_t); 130 131 static uint16_t 132 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb); 133 134 nxge_status_t 135 nxge_init_rxdma_channels(p_nxge_t nxgep) 136 { 137 nxge_status_t status = NXGE_OK; 138 139 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 140 141 status = nxge_map_rxdma(nxgep); 142 if (status != NXGE_OK) { 143 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 144 "<== nxge_init_rxdma: status 0x%x", status)); 145 return (status); 146 } 147 148 status = nxge_rxdma_hw_start_common(nxgep); 149 if (status != NXGE_OK) { 150 nxge_unmap_rxdma(nxgep); 151 } 152 153 status = nxge_rxdma_hw_start(nxgep); 154 if (status != NXGE_OK) { 155 nxge_unmap_rxdma(nxgep); 156 } 157 158 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 159 "<== nxge_init_rxdma_channels: status 0x%x", status)); 160 161 return (status); 162 } 163 164 void 165 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 166 { 167 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 168 169 nxge_rxdma_hw_stop(nxgep); 170 nxge_rxdma_hw_stop_common(nxgep); 171 nxge_unmap_rxdma(nxgep); 172 173 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 174 "<== nxge_uinit_rxdma_channels")); 175 } 176 177 nxge_status_t 178 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 179 { 180 npi_handle_t handle; 181 npi_status_t rs = NPI_SUCCESS; 182 nxge_status_t status = NXGE_OK; 183 184 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 185 186 handle = NXGE_DEV_NPI_HANDLE(nxgep); 187 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 188 189 if (rs != NPI_SUCCESS) { 190 status = NXGE_ERROR | rs; 191 } 192 193 return (status); 194 } 195 196 void 197 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 198 { 199 int i, ndmas; 200 uint16_t channel; 201 p_rx_rbr_rings_t rx_rbr_rings; 202 p_rx_rbr_ring_t *rbr_rings; 203 npi_handle_t handle; 204 205 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 206 207 handle = NXGE_DEV_NPI_HANDLE(nxgep); 208 (void) npi_rxdma_dump_fzc_regs(handle); 209 210 rx_rbr_rings = nxgep->rx_rbr_rings; 211 if (rx_rbr_rings == NULL) { 212 NXGE_DEBUG_MSG((nxgep, RX_CTL, 213 "<== nxge_rxdma_regs_dump_channels: " 214 "NULL ring pointer")); 215 return; 216 } 217 if (rx_rbr_rings->rbr_rings == NULL) { 218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 219 "<== nxge_rxdma_regs_dump_channels: " 220 " NULL rbr rings pointer")); 221 return; 222 } 223 224 ndmas = rx_rbr_rings->ndmas; 225 if (!ndmas) { 226 NXGE_DEBUG_MSG((nxgep, RX_CTL, 227 "<== nxge_rxdma_regs_dump_channels: no channel")); 228 return; 229 } 230 231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 232 "==> nxge_rxdma_regs_dump_channels (ndmas %d)", ndmas)); 233 234 rbr_rings = rx_rbr_rings->rbr_rings; 235 for (i = 0; i < ndmas; i++) { 236 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 237 continue; 238 } 239 channel = rbr_rings[i]->rdc; 240 (void) nxge_dump_rxdma_channel(nxgep, channel); 241 } 242 243 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 244 245 } 246 247 nxge_status_t 248 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 249 { 250 npi_handle_t handle; 251 npi_status_t rs = NPI_SUCCESS; 252 nxge_status_t status = NXGE_OK; 253 254 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 255 256 handle = NXGE_DEV_NPI_HANDLE(nxgep); 257 rs = npi_rxdma_dump_rdc_regs(handle, channel); 258 259 if (rs != NPI_SUCCESS) { 260 status = NXGE_ERROR | rs; 261 } 262 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 263 return (status); 264 } 265 266 nxge_status_t 267 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 268 p_rx_dma_ent_msk_t mask_p) 269 { 270 npi_handle_t handle; 271 npi_status_t rs = NPI_SUCCESS; 272 nxge_status_t status = NXGE_OK; 273 274 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 275 "<== nxge_init_rxdma_channel_event_mask")); 276 277 handle = NXGE_DEV_NPI_HANDLE(nxgep); 278 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 279 if (rs != NPI_SUCCESS) { 280 status = NXGE_ERROR | rs; 281 } 282 283 return (status); 284 } 285 286 nxge_status_t 287 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 288 p_rx_dma_ctl_stat_t cs_p) 289 { 290 npi_handle_t handle; 291 npi_status_t rs = NPI_SUCCESS; 292 nxge_status_t status = NXGE_OK; 293 294 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 295 "<== nxge_init_rxdma_channel_cntl_stat")); 296 297 handle = NXGE_DEV_NPI_HANDLE(nxgep); 298 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 299 300 if (rs != NPI_SUCCESS) { 301 status = NXGE_ERROR | rs; 302 } 303 304 return (status); 305 } 306 307 nxge_status_t 308 nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep, uint8_t rdcgrp, 309 uint8_t rdc) 310 { 311 npi_handle_t handle; 312 npi_status_t rs = NPI_SUCCESS; 313 p_nxge_dma_pt_cfg_t p_dma_cfgp; 314 p_nxge_rdc_grp_t rdc_grp_p; 315 uint8_t actual_rdcgrp, actual_rdc; 316 317 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 318 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 319 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 320 321 handle = NXGE_DEV_NPI_HANDLE(nxgep); 322 323 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 324 rdc_grp_p->rdc[0] = rdc; 325 326 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 327 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 328 329 rs = npi_rxdma_cfg_rdc_table_default_rdc(handle, actual_rdcgrp, 330 actual_rdc); 331 332 if (rs != NPI_SUCCESS) { 333 return (NXGE_ERROR | rs); 334 } 335 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 336 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 337 return (NXGE_OK); 338 } 339 340 nxge_status_t 341 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 342 { 343 npi_handle_t handle; 344 345 uint8_t actual_rdc; 346 npi_status_t rs = NPI_SUCCESS; 347 348 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 349 " ==> nxge_rxdma_cfg_port_default_rdc")); 350 351 handle = NXGE_DEV_NPI_HANDLE(nxgep); 352 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 353 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 354 355 356 if (rs != NPI_SUCCESS) { 357 return (NXGE_ERROR | rs); 358 } 359 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 360 " <== nxge_rxdma_cfg_port_default_rdc")); 361 362 return (NXGE_OK); 363 } 364 365 nxge_status_t 366 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 367 uint16_t pkts) 368 { 369 npi_status_t rs = NPI_SUCCESS; 370 npi_handle_t handle; 371 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 372 " ==> nxge_rxdma_cfg_rcr_threshold")); 373 handle = NXGE_DEV_NPI_HANDLE(nxgep); 374 375 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 376 377 if (rs != NPI_SUCCESS) { 378 return (NXGE_ERROR | rs); 379 } 380 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 381 return (NXGE_OK); 382 } 383 384 nxge_status_t 385 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 386 uint16_t tout, uint8_t enable) 387 { 388 npi_status_t rs = NPI_SUCCESS; 389 npi_handle_t handle; 390 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 if (enable == 0) { 393 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 394 } else { 395 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 396 tout); 397 } 398 399 if (rs != NPI_SUCCESS) { 400 return (NXGE_ERROR | rs); 401 } 402 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 403 return (NXGE_OK); 404 } 405 406 nxge_status_t 407 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 408 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 409 { 410 npi_handle_t handle; 411 rdc_desc_cfg_t rdc_desc; 412 p_rcrcfig_b_t cfgb_p; 413 npi_status_t rs = NPI_SUCCESS; 414 415 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 416 handle = NXGE_DEV_NPI_HANDLE(nxgep); 417 /* 418 * Use configuration data composed at init time. 419 * Write to hardware the receive ring configurations. 420 */ 421 rdc_desc.mbox_enable = 1; 422 rdc_desc.mbox_addr = mbox_p->mbox_addr; 423 NXGE_DEBUG_MSG((nxgep, RX_CTL, 424 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 425 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 426 427 rdc_desc.rbr_len = rbr_p->rbb_max; 428 rdc_desc.rbr_addr = rbr_p->rbr_addr; 429 430 switch (nxgep->rx_bksize_code) { 431 case RBR_BKSIZE_4K: 432 rdc_desc.page_size = SIZE_4KB; 433 break; 434 case RBR_BKSIZE_8K: 435 rdc_desc.page_size = SIZE_8KB; 436 break; 437 case RBR_BKSIZE_16K: 438 rdc_desc.page_size = SIZE_16KB; 439 break; 440 case RBR_BKSIZE_32K: 441 rdc_desc.page_size = SIZE_32KB; 442 break; 443 } 444 445 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 446 rdc_desc.valid0 = 1; 447 448 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 449 rdc_desc.valid1 = 1; 450 451 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 452 rdc_desc.valid2 = 1; 453 454 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 455 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 456 457 rdc_desc.rcr_len = rcr_p->comp_size; 458 rdc_desc.rcr_addr = rcr_p->rcr_addr; 459 460 cfgb_p = &(rcr_p->rcr_cfgb); 461 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 462 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 463 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 464 465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 466 "rbr_len qlen %d pagesize code %d rcr_len %d", 467 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 468 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 469 "size 0 %d size 1 %d size 2 %d", 470 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 471 rbr_p->npi_pkt_buf_size2)); 472 473 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 474 if (rs != NPI_SUCCESS) { 475 return (NXGE_ERROR | rs); 476 } 477 478 /* 479 * Enable the timeout and threshold. 480 */ 481 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 482 rdc_desc.rcr_threshold); 483 if (rs != NPI_SUCCESS) { 484 return (NXGE_ERROR | rs); 485 } 486 487 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 488 rdc_desc.rcr_timeout); 489 if (rs != NPI_SUCCESS) { 490 return (NXGE_ERROR | rs); 491 } 492 493 /* Enable the DMA */ 494 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 495 if (rs != NPI_SUCCESS) { 496 return (NXGE_ERROR | rs); 497 } 498 499 /* Kick the DMA engine. */ 500 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 501 /* Clear the rbr empty bit */ 502 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 503 504 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 505 506 return (NXGE_OK); 507 } 508 509 nxge_status_t 510 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 511 { 512 npi_handle_t handle; 513 npi_status_t rs = NPI_SUCCESS; 514 515 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 516 handle = NXGE_DEV_NPI_HANDLE(nxgep); 517 518 /* disable the DMA */ 519 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 520 if (rs != NPI_SUCCESS) { 521 NXGE_DEBUG_MSG((nxgep, RX_CTL, 522 "<== nxge_disable_rxdma_channel:failed (0x%x)", 523 rs)); 524 return (NXGE_ERROR | rs); 525 } 526 527 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 528 return (NXGE_OK); 529 } 530 531 nxge_status_t 532 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 533 { 534 npi_handle_t handle; 535 nxge_status_t status = NXGE_OK; 536 537 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 538 "<== nxge_init_rxdma_channel_rcrflush")); 539 540 handle = NXGE_DEV_NPI_HANDLE(nxgep); 541 npi_rxdma_rdc_rcr_flush(handle, channel); 542 543 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 544 "<== nxge_init_rxdma_channel_rcrflsh")); 545 return (status); 546 547 } 548 549 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 550 551 #define TO_LEFT -1 552 #define TO_RIGHT 1 553 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 554 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 555 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 556 #define NO_HINT 0xffffffff 557 558 /*ARGSUSED*/ 559 nxge_status_t 560 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 561 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 562 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 563 { 564 int bufsize; 565 uint64_t pktbuf_pp; 566 uint64_t dvma_addr; 567 rxring_info_t *ring_info; 568 int base_side, end_side; 569 int r_index, l_index, anchor_index; 570 int found, search_done; 571 uint32_t offset, chunk_size, block_size, page_size_mask; 572 uint32_t chunk_index, block_index, total_index; 573 int max_iterations, iteration; 574 rxbuf_index_info_t *bufinfo; 575 576 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 577 578 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 579 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 580 pkt_buf_addr_pp, 581 pktbufsz_type)); 582 583 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 584 585 switch (pktbufsz_type) { 586 case 0: 587 bufsize = rbr_p->pkt_buf_size0; 588 break; 589 case 1: 590 bufsize = rbr_p->pkt_buf_size1; 591 break; 592 case 2: 593 bufsize = rbr_p->pkt_buf_size2; 594 break; 595 case RCR_SINGLE_BLOCK: 596 bufsize = 0; 597 anchor_index = 0; 598 break; 599 default: 600 return (NXGE_ERROR); 601 } 602 603 if (rbr_p->num_blocks == 1) { 604 anchor_index = 0; 605 ring_info = rbr_p->ring_info; 606 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 607 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 608 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 609 "buf_pp $%p btype %d anchor_index %d " 610 "bufinfo $%p", 611 pkt_buf_addr_pp, 612 pktbufsz_type, 613 anchor_index, 614 bufinfo)); 615 616 goto found_index; 617 } 618 619 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 620 "==> nxge_rxbuf_pp_to_vp: " 621 "buf_pp $%p btype %d anchor_index %d", 622 pkt_buf_addr_pp, 623 pktbufsz_type, 624 anchor_index)); 625 626 ring_info = rbr_p->ring_info; 627 found = B_FALSE; 628 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 629 iteration = 0; 630 max_iterations = ring_info->max_iterations; 631 /* 632 * First check if this block has been seen 633 * recently. This is indicated by a hint which 634 * is initialized when the first buffer of the block 635 * is seen. The hint is reset when the last buffer of 636 * the block has been processed. 637 * As three block sizes are supported, three hints 638 * are kept. The idea behind the hints is that once 639 * the hardware uses a block for a buffer of that 640 * size, it will use it exclusively for that size 641 * and will use it until it is exhausted. It is assumed 642 * that there would a single block being used for the same 643 * buffer sizes at any given time. 644 */ 645 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 646 anchor_index = ring_info->hint[pktbufsz_type]; 647 dvma_addr = bufinfo[anchor_index].dvma_addr; 648 chunk_size = bufinfo[anchor_index].buf_size; 649 if ((pktbuf_pp >= dvma_addr) && 650 (pktbuf_pp < (dvma_addr + chunk_size))) { 651 found = B_TRUE; 652 /* 653 * check if this is the last buffer in the block 654 * If so, then reset the hint for the size; 655 */ 656 657 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 658 ring_info->hint[pktbufsz_type] = NO_HINT; 659 } 660 } 661 662 if (found == B_FALSE) { 663 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 664 "==> nxge_rxbuf_pp_to_vp: (!found)" 665 "buf_pp $%p btype %d anchor_index %d", 666 pkt_buf_addr_pp, 667 pktbufsz_type, 668 anchor_index)); 669 670 /* 671 * This is the first buffer of the block of this 672 * size. Need to search the whole information 673 * array. 674 * the search algorithm uses a binary tree search 675 * algorithm. It assumes that the information is 676 * already sorted with increasing order 677 * info[0] < info[1] < info[2] .... < info[n-1] 678 * where n is the size of the information array 679 */ 680 r_index = rbr_p->num_blocks - 1; 681 l_index = 0; 682 search_done = B_FALSE; 683 anchor_index = MID_INDEX(r_index, l_index); 684 while (search_done == B_FALSE) { 685 if ((r_index == l_index) || 686 (iteration >= max_iterations)) 687 search_done = B_TRUE; 688 end_side = TO_RIGHT; /* to the right */ 689 base_side = TO_LEFT; /* to the left */ 690 /* read the DVMA address information and sort it */ 691 dvma_addr = bufinfo[anchor_index].dvma_addr; 692 chunk_size = bufinfo[anchor_index].buf_size; 693 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 694 "==> nxge_rxbuf_pp_to_vp: (searching)" 695 "buf_pp $%p btype %d " 696 "anchor_index %d chunk_size %d dvmaaddr $%p", 697 pkt_buf_addr_pp, 698 pktbufsz_type, 699 anchor_index, 700 chunk_size, 701 dvma_addr)); 702 703 if (pktbuf_pp >= dvma_addr) 704 base_side = TO_RIGHT; /* to the right */ 705 if (pktbuf_pp < (dvma_addr + chunk_size)) 706 end_side = TO_LEFT; /* to the left */ 707 708 switch (base_side + end_side) { 709 case IN_MIDDLE: 710 /* found */ 711 found = B_TRUE; 712 search_done = B_TRUE; 713 if ((pktbuf_pp + bufsize) < 714 (dvma_addr + chunk_size)) 715 ring_info->hint[pktbufsz_type] = 716 bufinfo[anchor_index].buf_index; 717 break; 718 case BOTH_RIGHT: 719 /* not found: go to the right */ 720 l_index = anchor_index + 1; 721 anchor_index = 722 MID_INDEX(r_index, l_index); 723 break; 724 725 case BOTH_LEFT: 726 /* not found: go to the left */ 727 r_index = anchor_index - 1; 728 anchor_index = MID_INDEX(r_index, 729 l_index); 730 break; 731 default: /* should not come here */ 732 return (NXGE_ERROR); 733 } 734 iteration++; 735 } 736 737 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 738 "==> nxge_rxbuf_pp_to_vp: (search done)" 739 "buf_pp $%p btype %d anchor_index %d", 740 pkt_buf_addr_pp, 741 pktbufsz_type, 742 anchor_index)); 743 } 744 745 if (found == B_FALSE) { 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (search failed)" 748 "buf_pp $%p btype %d anchor_index %d", 749 pkt_buf_addr_pp, 750 pktbufsz_type, 751 anchor_index)); 752 return (NXGE_ERROR); 753 } 754 755 found_index: 756 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 757 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 758 "buf_pp $%p btype %d bufsize %d anchor_index %d", 759 pkt_buf_addr_pp, 760 pktbufsz_type, 761 bufsize, 762 anchor_index)); 763 764 /* index of the first block in this chunk */ 765 chunk_index = bufinfo[anchor_index].start_index; 766 dvma_addr = bufinfo[anchor_index].dvma_addr; 767 page_size_mask = ring_info->block_size_mask; 768 769 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 770 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 771 "buf_pp $%p btype %d bufsize %d " 772 "anchor_index %d chunk_index %d dvma $%p", 773 pkt_buf_addr_pp, 774 pktbufsz_type, 775 bufsize, 776 anchor_index, 777 chunk_index, 778 dvma_addr)); 779 780 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 781 block_size = rbr_p->block_size; /* System block(page) size */ 782 783 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 784 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 785 "buf_pp $%p btype %d bufsize %d " 786 "anchor_index %d chunk_index %d dvma $%p " 787 "offset %d block_size %d", 788 pkt_buf_addr_pp, 789 pktbufsz_type, 790 bufsize, 791 anchor_index, 792 chunk_index, 793 dvma_addr, 794 offset, 795 block_size)); 796 797 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 798 799 block_index = (offset / block_size); /* index within chunk */ 800 total_index = chunk_index + block_index; 801 802 803 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 804 "==> nxge_rxbuf_pp_to_vp: " 805 "total_index %d dvma_addr $%p " 806 "offset %d block_size %d " 807 "block_index %d ", 808 total_index, dvma_addr, 809 offset, block_size, 810 block_index)); 811 812 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr 813 + offset); 814 815 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 816 "==> nxge_rxbuf_pp_to_vp: " 817 "total_index %d dvma_addr $%p " 818 "offset %d block_size %d " 819 "block_index %d " 820 "*pkt_buf_addr_p $%p", 821 total_index, dvma_addr, 822 offset, block_size, 823 block_index, 824 *pkt_buf_addr_p)); 825 826 827 *msg_index = total_index; 828 *bufoffset = (offset & page_size_mask); 829 830 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 831 "==> nxge_rxbuf_pp_to_vp: get msg index: " 832 "msg_index %d bufoffset_index %d", 833 *msg_index, 834 *bufoffset)); 835 836 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 837 838 return (NXGE_OK); 839 } 840 841 /* 842 * used by quick sort (qsort) function 843 * to perform comparison 844 */ 845 static int 846 nxge_sort_compare(const void *p1, const void *p2) 847 { 848 849 rxbuf_index_info_t *a, *b; 850 851 a = (rxbuf_index_info_t *)p1; 852 b = (rxbuf_index_info_t *)p2; 853 854 if (a->dvma_addr > b->dvma_addr) 855 return (1); 856 if (a->dvma_addr < b->dvma_addr) 857 return (-1); 858 return (0); 859 } 860 861 862 863 /* 864 * grabbed this sort implementation from common/syscall/avl.c 865 * 866 */ 867 /* 868 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 869 * v = Ptr to array/vector of objs 870 * n = # objs in the array 871 * s = size of each obj (must be multiples of a word size) 872 * f = ptr to function to compare two objs 873 * returns (-1 = less than, 0 = equal, 1 = greater than 874 */ 875 void 876 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 877 { 878 int g, i, j, ii; 879 unsigned int *p1, *p2; 880 unsigned int tmp; 881 882 /* No work to do */ 883 if (v == NULL || n <= 1) 884 return; 885 /* Sanity check on arguments */ 886 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 887 ASSERT(s > 0); 888 889 for (g = n / 2; g > 0; g /= 2) { 890 for (i = g; i < n; i++) { 891 for (j = i - g; j >= 0 && 892 (*f)(v + j * s, v + (j + g) * s) == 1; 893 j -= g) { 894 p1 = (unsigned *)(v + j * s); 895 p2 = (unsigned *)(v + (j + g) * s); 896 for (ii = 0; ii < s / 4; ii++) { 897 tmp = *p1; 898 *p1++ = *p2; 899 *p2++ = tmp; 900 } 901 } 902 } 903 } 904 } 905 906 /* 907 * Initialize data structures required for rxdma 908 * buffer dvma->vmem address lookup 909 */ 910 /*ARGSUSED*/ 911 static nxge_status_t 912 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 913 { 914 915 int index; 916 rxring_info_t *ring_info; 917 int max_iteration = 0, max_index = 0; 918 919 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 920 921 ring_info = rbrp->ring_info; 922 ring_info->hint[0] = NO_HINT; 923 ring_info->hint[1] = NO_HINT; 924 ring_info->hint[2] = NO_HINT; 925 max_index = rbrp->num_blocks; 926 927 /* read the DVMA address information and sort it */ 928 /* do init of the information array */ 929 930 931 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 932 " nxge_rxbuf_index_info_init Sort ptrs")); 933 934 /* sort the array */ 935 nxge_ksort((void *)ring_info->buffer, max_index, 936 sizeof (rxbuf_index_info_t), nxge_sort_compare); 937 938 939 940 for (index = 0; index < max_index; index++) { 941 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 942 " nxge_rxbuf_index_info_init: sorted chunk %d " 943 " ioaddr $%p kaddr $%p size %x", 944 index, ring_info->buffer[index].dvma_addr, 945 ring_info->buffer[index].kaddr, 946 ring_info->buffer[index].buf_size)); 947 } 948 949 max_iteration = 0; 950 while (max_index >= (1ULL << max_iteration)) 951 max_iteration++; 952 ring_info->max_iterations = max_iteration + 1; 953 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 954 " nxge_rxbuf_index_info_init Find max iter %d", 955 ring_info->max_iterations)); 956 957 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 958 return (NXGE_OK); 959 } 960 961 /* ARGSUSED */ 962 void 963 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 964 { 965 #ifdef NXGE_DEBUG 966 967 uint32_t bptr; 968 uint64_t pp; 969 970 bptr = entry_p->bits.hdw.pkt_buf_addr; 971 972 NXGE_DEBUG_MSG((nxgep, RX_CTL, 973 "\trcr entry $%p " 974 "\trcr entry 0x%0llx " 975 "\trcr entry 0x%08x " 976 "\trcr entry 0x%08x " 977 "\tvalue 0x%0llx\n" 978 "\tmulti = %d\n" 979 "\tpkt_type = 0x%x\n" 980 "\tzero_copy = %d\n" 981 "\tnoport = %d\n" 982 "\tpromis = %d\n" 983 "\terror = 0x%04x\n" 984 "\tdcf_err = 0x%01x\n" 985 "\tl2_len = %d\n" 986 "\tpktbufsize = %d\n" 987 "\tpkt_buf_addr = $%p\n" 988 "\tpkt_buf_addr (<< 6) = $%p\n", 989 entry_p, 990 *(int64_t *)entry_p, 991 *(int32_t *)entry_p, 992 *(int32_t *)((char *)entry_p + 32), 993 entry_p->value, 994 entry_p->bits.hdw.multi, 995 entry_p->bits.hdw.pkt_type, 996 entry_p->bits.hdw.zero_copy, 997 entry_p->bits.hdw.noport, 998 entry_p->bits.hdw.promis, 999 entry_p->bits.hdw.error, 1000 entry_p->bits.hdw.dcf_err, 1001 entry_p->bits.hdw.l2_len, 1002 entry_p->bits.hdw.pktbufsz, 1003 bptr, 1004 entry_p->bits.ldw.pkt_buf_addr)); 1005 1006 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1007 RCR_PKT_BUF_ADDR_SHIFT; 1008 1009 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1010 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1011 #endif 1012 } 1013 1014 void 1015 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1016 { 1017 npi_handle_t handle; 1018 rbr_stat_t rbr_stat; 1019 addr44_t hd_addr; 1020 addr44_t tail_addr; 1021 uint16_t qlen; 1022 1023 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1024 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1025 1026 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1027 1028 /* RBR head */ 1029 hd_addr.addr = 0; 1030 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1031 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1032 (void *)hd_addr.addr); 1033 1034 /* RBR stats */ 1035 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1036 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1037 1038 /* RCR tail */ 1039 tail_addr.addr = 0; 1040 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1041 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1042 (void *)tail_addr.addr); 1043 1044 /* RCR qlen */ 1045 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1046 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1047 1048 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1049 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1050 } 1051 1052 void 1053 nxge_rxdma_stop(p_nxge_t nxgep) 1054 { 1055 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1056 1057 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1058 (void) nxge_rx_mac_disable(nxgep); 1059 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1060 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1061 } 1062 1063 void 1064 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1065 { 1066 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1067 1068 (void) nxge_rxdma_stop(nxgep); 1069 (void) nxge_uninit_rxdma_channels(nxgep); 1070 (void) nxge_init_rxdma_channels(nxgep); 1071 1072 #ifndef AXIS_DEBUG_LB 1073 (void) nxge_xcvr_init(nxgep); 1074 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1075 #endif 1076 (void) nxge_rx_mac_enable(nxgep); 1077 1078 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1079 } 1080 1081 nxge_status_t 1082 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1083 { 1084 int i, ndmas; 1085 uint16_t channel; 1086 p_rx_rbr_rings_t rx_rbr_rings; 1087 p_rx_rbr_ring_t *rbr_rings; 1088 npi_handle_t handle; 1089 npi_status_t rs = NPI_SUCCESS; 1090 nxge_status_t status = NXGE_OK; 1091 1092 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1093 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1094 1095 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1096 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1097 "<== nxge_rxdma_mode: not initialized")); 1098 return (NXGE_ERROR); 1099 } 1100 1101 rx_rbr_rings = nxgep->rx_rbr_rings; 1102 if (rx_rbr_rings == NULL) { 1103 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1104 "<== nxge_rxdma_mode: NULL ring pointer")); 1105 return (NXGE_ERROR); 1106 } 1107 if (rx_rbr_rings->rbr_rings == NULL) { 1108 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1109 "<== nxge_rxdma_mode: NULL rbr rings pointer")); 1110 return (NXGE_ERROR); 1111 } 1112 1113 ndmas = rx_rbr_rings->ndmas; 1114 if (!ndmas) { 1115 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1116 "<== nxge_rxdma_mode: no channel")); 1117 return (NXGE_ERROR); 1118 } 1119 1120 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1121 "==> nxge_rxdma_mode (ndmas %d)", ndmas)); 1122 1123 rbr_rings = rx_rbr_rings->rbr_rings; 1124 1125 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1126 for (i = 0; i < ndmas; i++) { 1127 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 1128 continue; 1129 } 1130 channel = rbr_rings[i]->rdc; 1131 if (enable) { 1132 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1133 "==> nxge_rxdma_hw_mode: channel %d (enable)", 1134 channel)); 1135 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 1136 } else { 1137 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1138 "==> nxge_rxdma_hw_mode: channel %d (disable)", 1139 channel)); 1140 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 1141 } 1142 } 1143 1144 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1145 1146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1147 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1148 1149 return (status); 1150 } 1151 1152 void 1153 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1154 { 1155 npi_handle_t handle; 1156 1157 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1158 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1159 1160 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1161 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1162 1163 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1164 } 1165 1166 void 1167 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1168 { 1169 npi_handle_t handle; 1170 1171 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1172 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1173 1174 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1175 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1176 1177 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1178 } 1179 1180 void 1181 nxge_hw_start_rx(p_nxge_t nxgep) 1182 { 1183 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1184 1185 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1186 (void) nxge_rx_mac_enable(nxgep); 1187 1188 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1189 } 1190 1191 /*ARGSUSED*/ 1192 void 1193 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1194 { 1195 int i, ndmas; 1196 uint16_t rdc; 1197 p_rx_rbr_rings_t rx_rbr_rings; 1198 p_rx_rbr_ring_t *rbr_rings; 1199 p_rx_rcr_rings_t rx_rcr_rings; 1200 1201 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1202 1203 rx_rbr_rings = nxgep->rx_rbr_rings; 1204 if (rx_rbr_rings == NULL) { 1205 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1206 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1207 return; 1208 } 1209 ndmas = rx_rbr_rings->ndmas; 1210 if (!ndmas) { 1211 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1212 "<== nxge_fixup_rxdma_rings: no channel")); 1213 return; 1214 } 1215 1216 rx_rcr_rings = nxgep->rx_rcr_rings; 1217 if (rx_rcr_rings == NULL) { 1218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1219 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1220 return; 1221 } 1222 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1223 "==> nxge_fixup_rxdma_rings (ndmas %d)", ndmas)); 1224 1225 nxge_rxdma_hw_stop(nxgep); 1226 1227 rbr_rings = rx_rbr_rings->rbr_rings; 1228 for (i = 0; i < ndmas; i++) { 1229 rdc = rbr_rings[i]->rdc; 1230 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1231 "==> nxge_fixup_rxdma_rings: channel %d " 1232 "ring $%px", rdc, rbr_rings[i])); 1233 (void) nxge_rxdma_fixup_channel(nxgep, rdc, i); 1234 } 1235 1236 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1237 } 1238 1239 void 1240 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1241 { 1242 int i; 1243 1244 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1245 i = nxge_rxdma_get_ring_index(nxgep, channel); 1246 if (i < 0) { 1247 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1248 "<== nxge_rxdma_fix_channel: no entry found")); 1249 return; 1250 } 1251 1252 nxge_rxdma_fixup_channel(nxgep, channel, i); 1253 1254 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_txdma_fix_channel")); 1255 } 1256 1257 void 1258 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1259 { 1260 int ndmas; 1261 p_rx_rbr_rings_t rx_rbr_rings; 1262 p_rx_rbr_ring_t *rbr_rings; 1263 p_rx_rcr_rings_t rx_rcr_rings; 1264 p_rx_rcr_ring_t *rcr_rings; 1265 p_rx_mbox_areas_t rx_mbox_areas_p; 1266 p_rx_mbox_t *rx_mbox_p; 1267 p_nxge_dma_pool_t dma_buf_poolp; 1268 p_nxge_dma_pool_t dma_cntl_poolp; 1269 p_rx_rbr_ring_t rbrp; 1270 p_rx_rcr_ring_t rcrp; 1271 p_rx_mbox_t mboxp; 1272 p_nxge_dma_common_t dmap; 1273 nxge_status_t status = NXGE_OK; 1274 1275 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1276 1277 (void) nxge_rxdma_stop_channel(nxgep, channel); 1278 1279 dma_buf_poolp = nxgep->rx_buf_pool_p; 1280 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1281 1282 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1283 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1284 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1285 return; 1286 } 1287 1288 ndmas = dma_buf_poolp->ndmas; 1289 if (!ndmas) { 1290 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1291 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1292 return; 1293 } 1294 1295 rx_rbr_rings = nxgep->rx_rbr_rings; 1296 rx_rcr_rings = nxgep->rx_rcr_rings; 1297 rbr_rings = rx_rbr_rings->rbr_rings; 1298 rcr_rings = rx_rcr_rings->rcr_rings; 1299 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1300 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1301 1302 /* Reinitialize the receive block and completion rings */ 1303 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1304 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1305 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1306 1307 1308 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1309 rbrp->rbr_rd_index = 0; 1310 rcrp->comp_rd_index = 0; 1311 rcrp->comp_wt_index = 0; 1312 1313 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1314 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1315 1316 status = nxge_rxdma_start_channel(nxgep, channel, 1317 rbrp, rcrp, mboxp); 1318 if (status != NXGE_OK) { 1319 goto nxge_rxdma_fixup_channel_fail; 1320 } 1321 if (status != NXGE_OK) { 1322 goto nxge_rxdma_fixup_channel_fail; 1323 } 1324 1325 nxge_rxdma_fixup_channel_fail: 1326 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1327 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1328 1329 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1330 } 1331 1332 int 1333 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1334 { 1335 int i, ndmas; 1336 uint16_t rdc; 1337 p_rx_rbr_rings_t rx_rbr_rings; 1338 p_rx_rbr_ring_t *rbr_rings; 1339 1340 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1341 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1342 1343 rx_rbr_rings = nxgep->rx_rbr_rings; 1344 if (rx_rbr_rings == NULL) { 1345 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1346 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1347 return (-1); 1348 } 1349 ndmas = rx_rbr_rings->ndmas; 1350 if (!ndmas) { 1351 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1352 "<== nxge_rxdma_get_ring_index: no channel")); 1353 return (-1); 1354 } 1355 1356 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1357 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1358 1359 rbr_rings = rx_rbr_rings->rbr_rings; 1360 for (i = 0; i < ndmas; i++) { 1361 rdc = rbr_rings[i]->rdc; 1362 if (channel == rdc) { 1363 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1364 "==> nxge_rxdma_get_rbr_ring: " 1365 "channel %d (index %d) " 1366 "ring %d", channel, i, 1367 rbr_rings[i])); 1368 return (i); 1369 } 1370 } 1371 1372 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1373 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1374 1375 return (-1); 1376 } 1377 1378 p_rx_rbr_ring_t 1379 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1380 { 1381 int i, ndmas; 1382 uint16_t rdc; 1383 p_rx_rbr_rings_t rx_rbr_rings; 1384 p_rx_rbr_ring_t *rbr_rings; 1385 1386 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1387 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1388 1389 rx_rbr_rings = nxgep->rx_rbr_rings; 1390 if (rx_rbr_rings == NULL) { 1391 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1392 "<== nxge_rxdma_get_rbr_ring: NULL ring pointer")); 1393 return (NULL); 1394 } 1395 ndmas = rx_rbr_rings->ndmas; 1396 if (!ndmas) { 1397 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1398 "<== nxge_rxdma_get_rbr_ring: no channel")); 1399 return (NULL); 1400 } 1401 1402 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1403 "==> nxge_rxdma_get_ring (ndmas %d)", ndmas)); 1404 1405 rbr_rings = rx_rbr_rings->rbr_rings; 1406 for (i = 0; i < ndmas; i++) { 1407 rdc = rbr_rings[i]->rdc; 1408 if (channel == rdc) { 1409 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1410 "==> nxge_rxdma_get_rbr_ring: channel %d " 1411 "ring $%p", channel, rbr_rings[i])); 1412 return (rbr_rings[i]); 1413 } 1414 } 1415 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "<== nxge_rxdma_get_rbr_ring: not found")); 1418 1419 return (NULL); 1420 } 1421 1422 p_rx_rcr_ring_t 1423 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1424 { 1425 int i, ndmas; 1426 uint16_t rdc; 1427 p_rx_rcr_rings_t rx_rcr_rings; 1428 p_rx_rcr_ring_t *rcr_rings; 1429 1430 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1431 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1432 1433 rx_rcr_rings = nxgep->rx_rcr_rings; 1434 if (rx_rcr_rings == NULL) { 1435 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1436 "<== nxge_rxdma_get_rcr_ring: NULL ring pointer")); 1437 return (NULL); 1438 } 1439 ndmas = rx_rcr_rings->ndmas; 1440 if (!ndmas) { 1441 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1442 "<== nxge_rxdma_get_rcr_ring: no channel")); 1443 return (NULL); 1444 } 1445 1446 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1447 "==> nxge_rxdma_get_rcr_ring (ndmas %d)", ndmas)); 1448 1449 rcr_rings = rx_rcr_rings->rcr_rings; 1450 for (i = 0; i < ndmas; i++) { 1451 rdc = rcr_rings[i]->rdc; 1452 if (channel == rdc) { 1453 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1454 "==> nxge_rxdma_get_rcr_ring: channel %d " 1455 "ring $%p", channel, rcr_rings[i])); 1456 return (rcr_rings[i]); 1457 } 1458 } 1459 1460 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1461 "<== nxge_rxdma_get_rcr_ring: not found")); 1462 1463 return (NULL); 1464 } 1465 1466 /* 1467 * Static functions start here. 1468 */ 1469 1470 static p_rx_msg_t 1471 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1472 { 1473 p_rx_msg_t nxge_mp = NULL; 1474 p_nxge_dma_common_t dmamsg_p; 1475 uchar_t *buffer; 1476 1477 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1478 if (nxge_mp == NULL) { 1479 NXGE_DEBUG_MSG((NULL, MEM_CTL, 1480 "Allocation of a rx msg failed.")); 1481 goto nxge_allocb_exit; 1482 } 1483 1484 nxge_mp->use_buf_pool = B_FALSE; 1485 if (dmabuf_p) { 1486 nxge_mp->use_buf_pool = B_TRUE; 1487 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1488 *dmamsg_p = *dmabuf_p; 1489 dmamsg_p->nblocks = 1; 1490 dmamsg_p->block_size = size; 1491 dmamsg_p->alength = size; 1492 buffer = (uchar_t *)dmabuf_p->kaddrp; 1493 1494 dmabuf_p->kaddrp = (void *) 1495 ((char *)dmabuf_p->kaddrp + size); 1496 dmabuf_p->ioaddr_pp = (void *) 1497 ((char *)dmabuf_p->ioaddr_pp + size); 1498 dmabuf_p->alength -= size; 1499 dmabuf_p->offset += size; 1500 dmabuf_p->dma_cookie.dmac_laddress += size; 1501 dmabuf_p->dma_cookie.dmac_size -= size; 1502 1503 } else { 1504 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1505 if (buffer == NULL) { 1506 NXGE_DEBUG_MSG((NULL, MEM_CTL, 1507 "Allocation of a receive page failed.")); 1508 goto nxge_allocb_fail1; 1509 } 1510 } 1511 1512 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1513 if (nxge_mp->rx_mblk_p == NULL) { 1514 NXGE_DEBUG_MSG((NULL, MEM_CTL, "desballoc failed.")); 1515 goto nxge_allocb_fail2; 1516 } 1517 1518 nxge_mp->buffer = buffer; 1519 nxge_mp->block_size = size; 1520 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1521 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1522 nxge_mp->ref_cnt = 1; 1523 nxge_mp->free = B_TRUE; 1524 nxge_mp->rx_use_bcopy = B_FALSE; 1525 1526 atomic_inc_32(&nxge_mblks_pending); 1527 1528 goto nxge_allocb_exit; 1529 1530 nxge_allocb_fail2: 1531 if (!nxge_mp->use_buf_pool) { 1532 KMEM_FREE(buffer, size); 1533 } 1534 1535 nxge_allocb_fail1: 1536 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1537 nxge_mp = NULL; 1538 1539 nxge_allocb_exit: 1540 return (nxge_mp); 1541 } 1542 1543 p_mblk_t 1544 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1545 { 1546 p_mblk_t mp; 1547 1548 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1549 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1550 "offset = 0x%08X " 1551 "size = 0x%08X", 1552 nxge_mp, offset, size)); 1553 1554 mp = desballoc(&nxge_mp->buffer[offset], size, 1555 0, &nxge_mp->freeb); 1556 if (mp == NULL) { 1557 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1558 goto nxge_dupb_exit; 1559 } 1560 atomic_inc_32(&nxge_mp->ref_cnt); 1561 atomic_inc_32(&nxge_mblks_pending); 1562 1563 1564 nxge_dupb_exit: 1565 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1566 nxge_mp)); 1567 return (mp); 1568 } 1569 1570 p_mblk_t 1571 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1572 { 1573 p_mblk_t mp; 1574 uchar_t *dp; 1575 1576 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1577 if (mp == NULL) { 1578 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1579 goto nxge_dupb_bcopy_exit; 1580 } 1581 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1582 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1583 mp->b_wptr = dp + size; 1584 1585 nxge_dupb_bcopy_exit: 1586 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1587 nxge_mp)); 1588 return (mp); 1589 } 1590 1591 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1592 p_rx_msg_t rx_msg_p); 1593 1594 void 1595 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1596 { 1597 1598 npi_handle_t handle; 1599 1600 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1601 1602 /* Reuse this buffer */ 1603 rx_msg_p->free = B_FALSE; 1604 rx_msg_p->cur_usage_cnt = 0; 1605 rx_msg_p->max_usage_cnt = 0; 1606 rx_msg_p->pkt_buf_size = 0; 1607 1608 if (rx_rbr_p->rbr_use_bcopy) { 1609 rx_msg_p->rx_use_bcopy = B_FALSE; 1610 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1611 } 1612 1613 /* 1614 * Get the rbr header pointer and its offset index. 1615 */ 1616 MUTEX_ENTER(&rx_rbr_p->post_lock); 1617 1618 1619 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1620 rx_rbr_p->rbr_wrap_mask); 1621 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1622 MUTEX_EXIT(&rx_rbr_p->post_lock); 1623 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1624 npi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, 1); 1625 1626 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1627 "<== nxge_post_page (channel %d post_next_index %d)", 1628 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1629 1630 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1631 } 1632 1633 void 1634 nxge_freeb(p_rx_msg_t rx_msg_p) 1635 { 1636 size_t size; 1637 uchar_t *buffer = NULL; 1638 int ref_cnt; 1639 1640 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1641 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1642 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1643 rx_msg_p, nxge_mblks_pending)); 1644 1645 1646 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1647 atomic_dec_32(&nxge_mblks_pending); 1648 if (!ref_cnt) { 1649 buffer = rx_msg_p->buffer; 1650 size = rx_msg_p->block_size; 1651 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1652 "will free: rx_msg_p = $%p (block pending %d)", 1653 (long long)rx_msg_p, nxge_mblks_pending)); 1654 1655 if (!rx_msg_p->use_buf_pool) { 1656 KMEM_FREE(buffer, size); 1657 } 1658 1659 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1660 return; 1661 } 1662 1663 /* 1664 * Repost buffer. 1665 */ 1666 if ((ref_cnt == 1) && (rx_msg_p->free == B_TRUE)) { 1667 NXGE_DEBUG_MSG((NULL, RX_CTL, 1668 "nxge_freeb: post page $%p:", rx_msg_p)); 1669 nxge_post_page(rx_msg_p->nxgep, rx_msg_p->rx_rbr_p, 1670 rx_msg_p); 1671 } 1672 1673 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1674 } 1675 1676 uint_t 1677 nxge_rx_intr(void *arg1, void *arg2) 1678 { 1679 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1680 p_nxge_t nxgep = (p_nxge_t)arg2; 1681 p_nxge_ldg_t ldgp; 1682 uint8_t channel; 1683 npi_handle_t handle; 1684 rx_dma_ctl_stat_t cs; 1685 1686 #ifdef NXGE_DEBUG 1687 rxdma_cfig1_t cfg; 1688 #endif 1689 uint_t serviced = DDI_INTR_UNCLAIMED; 1690 1691 if (ldvp == NULL) { 1692 NXGE_DEBUG_MSG((NULL, INT_CTL, 1693 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1694 nxgep, ldvp)); 1695 1696 return (DDI_INTR_CLAIMED); 1697 } 1698 1699 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1700 nxgep = ldvp->nxgep; 1701 } 1702 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1703 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1704 nxgep, ldvp)); 1705 1706 /* 1707 * This interrupt handler is for a specific 1708 * receive dma channel. 1709 */ 1710 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1711 /* 1712 * Get the control and status for this channel. 1713 */ 1714 channel = ldvp->channel; 1715 ldgp = ldvp->ldgp; 1716 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1717 1718 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1719 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1720 channel, 1721 cs.value, 1722 cs.bits.hdw.rcrto, 1723 cs.bits.hdw.rcrthres)); 1724 1725 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, ldvp, cs); 1726 serviced = DDI_INTR_CLAIMED; 1727 1728 /* error events. */ 1729 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1730 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, ldvp, cs); 1731 } 1732 1733 nxge_intr_exit: 1734 1735 1736 /* 1737 * Enable the mailbox update interrupt if we want 1738 * to use mailbox. We probably don't need to use 1739 * mailbox as it only saves us one pio read. 1740 * Also write 1 to rcrthres and rcrto to clear 1741 * these two edge triggered bits. 1742 */ 1743 1744 cs.value &= RX_DMA_CTL_STAT_WR1C; 1745 cs.bits.hdw.mex = 1; 1746 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1747 cs.value); 1748 1749 /* 1750 * Rearm this logical group if this is a single device 1751 * group. 1752 */ 1753 if (ldgp->nldvs == 1) { 1754 ldgimgm_t mgm; 1755 mgm.value = 0; 1756 mgm.bits.ldw.arm = 1; 1757 mgm.bits.ldw.timer = ldgp->ldg_timer; 1758 NXGE_REG_WR64(handle, 1759 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1760 mgm.value); 1761 } 1762 1763 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1764 serviced)); 1765 return (serviced); 1766 } 1767 1768 /* 1769 * Process the packets received in the specified logical device 1770 * and pass up a chain of message blocks to the upper layer. 1771 */ 1772 static void 1773 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1774 rx_dma_ctl_stat_t cs) 1775 { 1776 p_mblk_t mp; 1777 p_rx_rcr_ring_t rcrp; 1778 1779 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1780 if ((mp = nxge_rx_pkts(nxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1781 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1782 "<== nxge_rx_pkts_vring: no mp")); 1783 return; 1784 } 1785 1786 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1787 mp)); 1788 1789 #ifdef NXGE_DEBUG 1790 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1791 "==> nxge_rx_pkts_vring:calling mac_rx " 1792 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1793 "mac_handle $%p", 1794 mp->b_wptr - mp->b_rptr, 1795 mp, mp->b_cont, mp->b_next, 1796 rcrp, rcrp->rcr_mac_handle)); 1797 1798 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1799 "==> nxge_rx_pkts_vring: dump packets " 1800 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1801 mp, 1802 mp->b_rptr, 1803 mp->b_wptr, 1804 nxge_dump_packet((char *)mp->b_rptr, 1805 mp->b_wptr - mp->b_rptr))); 1806 if (mp->b_cont) { 1807 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1808 "==> nxge_rx_pkts_vring: dump b_cont packets " 1809 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1810 mp->b_cont, 1811 mp->b_cont->b_rptr, 1812 mp->b_cont->b_wptr, 1813 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1814 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1815 } 1816 if (mp->b_next) { 1817 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1818 "==> nxge_rx_pkts_vring: dump next packets " 1819 "(b_rptr $%p): %s", 1820 mp->b_next->b_rptr, 1821 nxge_dump_packet((char *)mp->b_next->b_rptr, 1822 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1823 } 1824 #endif 1825 1826 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1827 } 1828 1829 1830 /* 1831 * This routine is the main packet receive processing function. 1832 * It gets the packet type, error code, and buffer related 1833 * information from the receive completion entry. 1834 * How many completion entries to process is based on the number of packets 1835 * queued by the hardware, a hardware maintained tail pointer 1836 * and a configurable receive packet count. 1837 * 1838 * A chain of message blocks will be created as result of processing 1839 * the completion entries. This chain of message blocks will be returned and 1840 * a hardware control status register will be updated with the number of 1841 * packets were removed from the hardware queue. 1842 * 1843 */ 1844 mblk_t * 1845 nxge_rx_pkts(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1846 p_rx_rcr_ring_t *rcrp, rx_dma_ctl_stat_t cs) 1847 { 1848 npi_handle_t handle; 1849 uint8_t channel; 1850 p_rx_rcr_rings_t rx_rcr_rings; 1851 p_rx_rcr_ring_t rcr_p; 1852 uint32_t comp_rd_index; 1853 p_rcr_entry_t rcr_desc_rd_head_p; 1854 p_rcr_entry_t rcr_desc_rd_head_pp; 1855 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1856 uint16_t qlen, nrcr_read, npkt_read; 1857 uint32_t qlen_hw; 1858 boolean_t multi; 1859 rcrcfig_b_t rcr_cfg_b; 1860 #if defined(_BIG_ENDIAN) 1861 npi_status_t rs = NPI_SUCCESS; 1862 #endif 1863 1864 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:vindex %d " 1865 "channel %d", vindex, ldvp->channel)); 1866 1867 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1868 return (NULL); 1869 } 1870 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1871 rx_rcr_rings = nxgep->rx_rcr_rings; 1872 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1873 channel = rcr_p->rdc; 1874 if (channel != ldvp->channel) { 1875 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1876 "channel %d, and rcr channel %d not matched.", 1877 vindex, ldvp->channel, channel)); 1878 return (NULL); 1879 } 1880 1881 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1882 "==> nxge_rx_pkts: START: rcr channel %d " 1883 "head_p $%p head_pp $%p index %d ", 1884 channel, rcr_p->rcr_desc_rd_head_p, 1885 rcr_p->rcr_desc_rd_head_pp, 1886 rcr_p->comp_rd_index)); 1887 1888 1889 #if !defined(_BIG_ENDIAN) 1890 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1891 #else 1892 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1893 if (rs != NPI_SUCCESS) { 1894 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1895 "channel %d, get qlen failed 0x%08x", 1896 vindex, ldvp->channel, rs)); 1897 return (NULL); 1898 } 1899 #endif 1900 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 1901 "qlen %d", channel, qlen)); 1902 1903 1904 1905 if (!qlen) { 1906 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1907 "==> nxge_rx_pkts:rcr channel %d " 1908 "qlen %d (no pkts)", channel, qlen)); 1909 1910 return (NULL); 1911 } 1912 1913 comp_rd_index = rcr_p->comp_rd_index; 1914 1915 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1916 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1917 nrcr_read = npkt_read = 0; 1918 1919 /* 1920 * Number of packets queued 1921 * (The jumbo or multi packet will be counted as only one 1922 * packets and it may take up more than one completion entry). 1923 */ 1924 qlen_hw = (qlen < nxge_max_rx_pkts) ? 1925 qlen : nxge_max_rx_pkts; 1926 head_mp = NULL; 1927 tail_mp = &head_mp; 1928 nmp = mp_cont = NULL; 1929 multi = B_FALSE; 1930 1931 while (qlen_hw) { 1932 1933 #ifdef NXGE_DEBUG 1934 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 1935 #endif 1936 /* 1937 * Process one completion ring entry. 1938 */ 1939 nxge_receive_packet(nxgep, 1940 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 1941 1942 /* 1943 * message chaining modes 1944 */ 1945 if (nmp) { 1946 nmp->b_next = NULL; 1947 if (!multi && !mp_cont) { /* frame fits a partition */ 1948 *tail_mp = nmp; 1949 tail_mp = &nmp->b_next; 1950 nmp = NULL; 1951 } else if (multi && !mp_cont) { /* first segment */ 1952 *tail_mp = nmp; 1953 tail_mp = &nmp->b_cont; 1954 } else if (multi && mp_cont) { /* mid of multi segs */ 1955 *tail_mp = mp_cont; 1956 tail_mp = &mp_cont->b_cont; 1957 } else if (!multi && mp_cont) { /* last segment */ 1958 *tail_mp = mp_cont; 1959 tail_mp = &nmp->b_next; 1960 nmp = NULL; 1961 } 1962 } 1963 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1964 "==> nxge_rx_pkts: loop: rcr channel %d " 1965 "before updating: multi %d " 1966 "nrcr_read %d " 1967 "npk read %d " 1968 "head_pp $%p index %d ", 1969 channel, 1970 multi, 1971 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1972 comp_rd_index)); 1973 1974 if (!multi) { 1975 qlen_hw--; 1976 npkt_read++; 1977 } 1978 1979 /* 1980 * Update the next read entry. 1981 */ 1982 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1983 rcr_p->comp_wrap_mask); 1984 1985 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1986 rcr_p->rcr_desc_first_p, 1987 rcr_p->rcr_desc_last_p); 1988 1989 nrcr_read++; 1990 1991 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1992 "<== nxge_rx_pkts: (SAM, process one packet) " 1993 "nrcr_read %d", 1994 nrcr_read)); 1995 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1996 "==> nxge_rx_pkts: loop: rcr channel %d " 1997 "multi %d " 1998 "nrcr_read %d " 1999 "npk read %d " 2000 "head_pp $%p index %d ", 2001 channel, 2002 multi, 2003 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2004 comp_rd_index)); 2005 2006 } 2007 2008 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2009 rcr_p->comp_rd_index = comp_rd_index; 2010 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2011 2012 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2013 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2014 rcr_p->intr_timeout = nxgep->intr_timeout; 2015 rcr_p->intr_threshold = nxgep->intr_threshold; 2016 rcr_cfg_b.value = 0x0ULL; 2017 if (rcr_p->intr_timeout) 2018 rcr_cfg_b.bits.ldw.entout = 1; 2019 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2020 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2021 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2022 channel, rcr_cfg_b.value); 2023 } 2024 2025 cs.bits.ldw.pktread = npkt_read; 2026 cs.bits.ldw.ptrread = nrcr_read; 2027 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2028 channel, cs.value); 2029 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2030 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2031 "head_pp $%p index %016llx ", 2032 channel, 2033 rcr_p->rcr_desc_rd_head_pp, 2034 rcr_p->comp_rd_index)); 2035 /* 2036 * Update RCR buffer pointer read and number of packets 2037 * read. 2038 */ 2039 2040 *rcrp = rcr_p; 2041 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2042 return (head_mp); 2043 } 2044 2045 void 2046 nxge_receive_packet(p_nxge_t nxgep, 2047 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2048 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2049 { 2050 p_mblk_t nmp = NULL; 2051 uint64_t multi; 2052 uint64_t dcf_err; 2053 uint8_t channel; 2054 2055 boolean_t first_entry = B_TRUE; 2056 boolean_t is_tcp_udp = B_FALSE; 2057 boolean_t buffer_free = B_FALSE; 2058 boolean_t error_send_up = B_FALSE; 2059 uint8_t error_type; 2060 uint16_t l2_len; 2061 uint16_t skip_len; 2062 uint8_t pktbufsz_type; 2063 uint16_t pktbufsz; 2064 uint64_t rcr_entry; 2065 uint64_t *pkt_buf_addr_pp; 2066 uint64_t *pkt_buf_addr_p; 2067 uint32_t buf_offset; 2068 uint32_t bsize; 2069 uint32_t error_disp_cnt; 2070 uint32_t msg_index; 2071 p_rx_rbr_ring_t rx_rbr_p; 2072 p_rx_msg_t *rx_msg_ring_p; 2073 p_rx_msg_t rx_msg_p; 2074 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2075 nxge_status_t status = NXGE_OK; 2076 boolean_t is_valid = B_FALSE; 2077 p_nxge_rx_ring_stats_t rdc_stats; 2078 uint32_t bytes_read; 2079 uint64_t pkt_type; 2080 uint64_t frag; 2081 #ifdef NXGE_DEBUG 2082 int dump_len; 2083 #endif 2084 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2085 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2086 2087 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2088 2089 multi = (rcr_entry & RCR_MULTI_MASK); 2090 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2091 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2092 2093 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2094 frag = (rcr_entry & RCR_FRAG_MASK); 2095 2096 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2097 2098 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2099 RCR_PKTBUFSZ_SHIFT); 2100 2101 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2102 RCR_PKT_BUF_ADDR_SHIFT); 2103 2104 channel = rcr_p->rdc; 2105 2106 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2107 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2108 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2109 "error_type 0x%x pkt_type 0x%x " 2110 "pktbufsz_type %d ", 2111 rcr_desc_rd_head_p, 2112 rcr_entry, pkt_buf_addr_pp, l2_len, 2113 multi, 2114 error_type, 2115 pkt_type, 2116 pktbufsz_type)); 2117 2118 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2119 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2120 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2121 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2122 rcr_entry, pkt_buf_addr_pp, l2_len, 2123 multi, 2124 error_type, 2125 pkt_type)); 2126 2127 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2128 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2129 "full pkt_buf_addr_pp $%p l2_len %d", 2130 rcr_entry, pkt_buf_addr_pp, l2_len)); 2131 2132 /* get the stats ptr */ 2133 rdc_stats = rcr_p->rdc_stats; 2134 2135 if (!l2_len) { 2136 2137 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2138 "<== nxge_receive_packet: failed: l2 length is 0.")); 2139 return; 2140 } 2141 2142 /* shift 6 bits to get the full io address */ 2143 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2144 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2145 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2146 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2147 "full pkt_buf_addr_pp $%p l2_len %d", 2148 rcr_entry, pkt_buf_addr_pp, l2_len)); 2149 2150 rx_rbr_p = rcr_p->rx_rbr_p; 2151 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2152 2153 if (first_entry) { 2154 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2155 RXDMA_HDR_SIZE_DEFAULT); 2156 2157 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2158 "==> nxge_receive_packet: first entry 0x%016llx " 2159 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2160 rcr_entry, pkt_buf_addr_pp, l2_len, 2161 hdr_size)); 2162 } 2163 2164 MUTEX_ENTER(&rcr_p->lock); 2165 MUTEX_ENTER(&rx_rbr_p->lock); 2166 2167 bytes_read = rcr_p->rcvd_pkt_bytes; 2168 2169 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2170 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2171 "full pkt_buf_addr_pp $%p l2_len %d", 2172 rcr_entry, pkt_buf_addr_pp, l2_len)); 2173 2174 /* 2175 * Packet buffer address in the completion entry points 2176 * to the starting buffer address (offset 0). 2177 * Use the starting buffer address to locate the corresponding 2178 * kernel address. 2179 */ 2180 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2181 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2182 &buf_offset, 2183 &msg_index); 2184 2185 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2186 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2187 "full pkt_buf_addr_pp $%p l2_len %d", 2188 rcr_entry, pkt_buf_addr_pp, l2_len)); 2189 2190 if (status != NXGE_OK) { 2191 MUTEX_EXIT(&rx_rbr_p->lock); 2192 MUTEX_EXIT(&rcr_p->lock); 2193 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2194 "<== nxge_receive_packet: found vaddr failed %d", 2195 status)); 2196 return; 2197 } 2198 2199 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2200 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2201 "full pkt_buf_addr_pp $%p l2_len %d", 2202 rcr_entry, pkt_buf_addr_pp, l2_len)); 2203 2204 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2205 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2206 "full pkt_buf_addr_pp $%p l2_len %d", 2207 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2208 2209 rx_msg_p = rx_msg_ring_p[msg_index]; 2210 2211 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2212 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2213 "full pkt_buf_addr_pp $%p l2_len %d", 2214 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2215 2216 switch (pktbufsz_type) { 2217 case RCR_PKTBUFSZ_0: 2218 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2219 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2220 "==> nxge_receive_packet: 0 buf %d", bsize)); 2221 break; 2222 case RCR_PKTBUFSZ_1: 2223 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2224 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2225 "==> nxge_receive_packet: 1 buf %d", bsize)); 2226 break; 2227 case RCR_PKTBUFSZ_2: 2228 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2229 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2230 "==> nxge_receive_packet: 2 buf %d", bsize)); 2231 break; 2232 case RCR_SINGLE_BLOCK: 2233 bsize = rx_msg_p->block_size; 2234 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2235 "==> nxge_receive_packet: single %d", bsize)); 2236 2237 break; 2238 default: 2239 MUTEX_EXIT(&rx_rbr_p->lock); 2240 MUTEX_EXIT(&rcr_p->lock); 2241 return; 2242 } 2243 2244 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2245 (buf_offset + sw_offset_bytes), 2246 (hdr_size + l2_len), 2247 DDI_DMA_SYNC_FORCPU); 2248 2249 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2250 "==> nxge_receive_packet: after first dump:usage count")); 2251 2252 if (rx_msg_p->cur_usage_cnt == 0) { 2253 if (rx_rbr_p->rbr_use_bcopy) { 2254 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2255 if (rx_rbr_p->rbr_consumed < 2256 rx_rbr_p->rbr_threshold_hi) { 2257 if (rx_rbr_p->rbr_threshold_lo == 0 || 2258 ((rx_rbr_p->rbr_consumed >= 2259 rx_rbr_p->rbr_threshold_lo) && 2260 (rx_rbr_p->rbr_bufsize_type >= 2261 pktbufsz_type))) { 2262 rx_msg_p->rx_use_bcopy = B_TRUE; 2263 } 2264 } else { 2265 rx_msg_p->rx_use_bcopy = B_TRUE; 2266 } 2267 } 2268 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2269 "==> nxge_receive_packet: buf %d (new block) ", 2270 bsize)); 2271 2272 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2273 rx_msg_p->pkt_buf_size = bsize; 2274 rx_msg_p->cur_usage_cnt = 1; 2275 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2276 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2277 "==> nxge_receive_packet: buf %d " 2278 "(single block) ", 2279 bsize)); 2280 /* 2281 * Buffer can be reused once the free function 2282 * is called. 2283 */ 2284 rx_msg_p->max_usage_cnt = 1; 2285 buffer_free = B_TRUE; 2286 } else { 2287 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2288 if (rx_msg_p->max_usage_cnt == 1) { 2289 buffer_free = B_TRUE; 2290 } 2291 } 2292 } else { 2293 rx_msg_p->cur_usage_cnt++; 2294 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2295 buffer_free = B_TRUE; 2296 } 2297 } 2298 2299 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2300 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2301 msg_index, l2_len, 2302 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2303 2304 if ((error_type) || (dcf_err)) { 2305 rdc_stats->ierrors++; 2306 if (dcf_err) { 2307 rdc_stats->dcf_err++; 2308 #ifdef NXGE_DEBUG 2309 if (!rdc_stats->dcf_err) { 2310 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2311 "nxge_receive_packet: channel %d dcf_err rcr" 2312 " 0x%llx", channel, rcr_entry)); 2313 } 2314 #endif 2315 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2316 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2317 } else { 2318 /* Update error stats */ 2319 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2320 rdc_stats->errlog.compl_err_type = error_type; 2321 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2322 NXGE_FM_EREPORT_RDMC_COMPLETION_ERR); 2323 2324 switch (error_type) { 2325 case RCR_L2_ERROR: 2326 rdc_stats->l2_err++; 2327 if (rdc_stats->l2_err < 2328 error_disp_cnt) 2329 NXGE_ERROR_MSG((nxgep, 2330 NXGE_ERR_CTL, 2331 " nxge_receive_packet:" 2332 " channel %d RCR L2_ERROR", 2333 channel)); 2334 break; 2335 case RCR_L4_CSUM_ERROR: 2336 error_send_up = B_TRUE; 2337 rdc_stats->l4_cksum_err++; 2338 if (rdc_stats->l4_cksum_err < 2339 error_disp_cnt) 2340 NXGE_ERROR_MSG((nxgep, 2341 NXGE_ERR_CTL, 2342 " nxge_receive_packet:" 2343 " channel %d" 2344 " RCR L4_CSUM_ERROR", 2345 channel)); 2346 break; 2347 case RCR_FFLP_SOFT_ERROR: 2348 error_send_up = B_TRUE; 2349 rdc_stats->fflp_soft_err++; 2350 if (rdc_stats->fflp_soft_err < 2351 error_disp_cnt) 2352 NXGE_ERROR_MSG((nxgep, 2353 NXGE_ERR_CTL, 2354 " nxge_receive_packet:" 2355 " channel %d" 2356 " RCR FFLP_SOFT_ERROR", 2357 channel)); 2358 break; 2359 case RCR_ZCP_SOFT_ERROR: 2360 error_send_up = B_TRUE; 2361 rdc_stats->fflp_soft_err++; 2362 if (rdc_stats->zcp_soft_err < 2363 error_disp_cnt) 2364 NXGE_ERROR_MSG((nxgep, 2365 NXGE_ERR_CTL, 2366 " nxge_receive_packet:" 2367 " Channel %d" 2368 " RCR ZCP_SOFT_ERROR", 2369 channel)); 2370 break; 2371 default: 2372 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2373 " nxge_receive_packet:" 2374 " Channel %d" 2375 " RCR entry 0x%llx" 2376 " error 0x%x", 2377 rcr_entry, channel, 2378 error_type)); 2379 break; 2380 } 2381 } 2382 2383 /* 2384 * Update and repost buffer block if max usage 2385 * count is reached. 2386 */ 2387 if (error_send_up == B_FALSE) { 2388 if (buffer_free == B_TRUE) { 2389 rx_msg_p->free = B_TRUE; 2390 } 2391 2392 atomic_inc_32(&rx_msg_p->ref_cnt); 2393 MUTEX_EXIT(&rx_rbr_p->lock); 2394 MUTEX_EXIT(&rcr_p->lock); 2395 nxge_freeb(rx_msg_p); 2396 return; 2397 } 2398 } 2399 2400 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2401 "==> nxge_receive_packet: DMA sync second ")); 2402 2403 skip_len = sw_offset_bytes + hdr_size; 2404 if (!rx_msg_p->rx_use_bcopy) { 2405 nmp = nxge_dupb(rx_msg_p, buf_offset, bsize); 2406 } else { 2407 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, l2_len); 2408 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2409 "==> nxge_receive_packet: use bcopy " 2410 "rbr consumed %d " 2411 "pktbufsz_type %d " 2412 "offset %d " 2413 "hdr_size %d l2_len %d " 2414 "nmp->b_rptr $%p", 2415 rx_rbr_p->rbr_consumed, 2416 pktbufsz_type, 2417 buf_offset, hdr_size, l2_len, 2418 nmp->b_rptr)); 2419 } 2420 if (nmp != NULL) { 2421 pktbufsz = nxge_get_pktbuf_size(nxgep, pktbufsz_type, 2422 rx_rbr_p->rbr_cfgb); 2423 if (!rx_msg_p->rx_use_bcopy) { 2424 if (first_entry) { 2425 bytes_read = 0; 2426 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2427 if (l2_len > pktbufsz - skip_len) 2428 nmp->b_wptr = &nmp->b_rptr[pktbufsz 2429 - skip_len]; 2430 else 2431 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2432 } else { 2433 if (l2_len - bytes_read > pktbufsz) 2434 nmp->b_wptr = &nmp->b_rptr[pktbufsz]; 2435 else 2436 nmp->b_wptr = 2437 &nmp->b_rptr[l2_len - bytes_read]; 2438 } 2439 bytes_read += nmp->b_wptr - nmp->b_rptr; 2440 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2441 "==> nxge_receive_packet after dupb: " 2442 "rbr consumed %d " 2443 "pktbufsz_type %d " 2444 "nmp $%p rptr $%p wptr $%p " 2445 "buf_offset %d bzise %d l2_len %d skip_len %d", 2446 rx_rbr_p->rbr_consumed, 2447 pktbufsz_type, 2448 nmp, nmp->b_rptr, nmp->b_wptr, 2449 buf_offset, bsize, l2_len, skip_len)); 2450 } 2451 } else { 2452 cmn_err(CE_WARN, "!nxge_receive_packet: " 2453 "update stats (error)"); 2454 } 2455 if (buffer_free == B_TRUE) { 2456 rx_msg_p->free = B_TRUE; 2457 } 2458 2459 /* 2460 * ERROR, FRAG and PKT_TYPE are only reported 2461 * in the first entry. 2462 * If a packet is not fragmented and no error bit is set, then 2463 * L4 checksum is OK. 2464 */ 2465 is_valid = (nmp != NULL); 2466 rdc_stats->ibytes += l2_len; 2467 rdc_stats->ipackets++; 2468 MUTEX_EXIT(&rx_rbr_p->lock); 2469 MUTEX_EXIT(&rcr_p->lock); 2470 2471 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2472 atomic_inc_32(&rx_msg_p->ref_cnt); 2473 nxge_freeb(rx_msg_p); 2474 } 2475 2476 if (is_valid) { 2477 nmp->b_cont = NULL; 2478 if (first_entry) { 2479 *mp = nmp; 2480 *mp_cont = NULL; 2481 } else 2482 *mp_cont = nmp; 2483 } 2484 2485 /* 2486 * Update stats and hardware checksuming. 2487 */ 2488 if (is_valid && !multi) { 2489 2490 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2491 pkt_type == RCR_PKT_IS_UDP) ? 2492 B_TRUE: B_FALSE); 2493 2494 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2495 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2496 is_valid, multi, is_tcp_udp, frag, error_type)); 2497 2498 if (is_tcp_udp && !frag && !error_type) { 2499 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2500 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2501 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2502 "==> nxge_receive_packet: Full tcp/udp cksum " 2503 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2504 "error %d", 2505 is_valid, multi, is_tcp_udp, frag, error_type)); 2506 } 2507 } 2508 2509 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2510 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2511 2512 *multi_p = (multi == RCR_MULTI_MASK); 2513 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2514 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2515 *multi_p, nmp, *mp, *mp_cont)); 2516 } 2517 2518 /*ARGSUSED*/ 2519 static nxge_status_t 2520 nxge_rx_err_evnts(p_nxge_t nxgep, uint_t index, p_nxge_ldv_t ldvp, 2521 rx_dma_ctl_stat_t cs) 2522 { 2523 p_nxge_rx_ring_stats_t rdc_stats; 2524 npi_handle_t handle; 2525 npi_status_t rs; 2526 boolean_t rxchan_fatal = B_FALSE; 2527 boolean_t rxport_fatal = B_FALSE; 2528 uint8_t channel; 2529 uint8_t portn; 2530 nxge_status_t status = NXGE_OK; 2531 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2532 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2533 2534 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2535 channel = ldvp->channel; 2536 portn = nxgep->mac.portnum; 2537 rdc_stats = &nxgep->statsp->rdc_stats[ldvp->vdma_index]; 2538 2539 if (cs.bits.hdw.rbr_tmout) { 2540 rdc_stats->rx_rbr_tmout++; 2541 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2542 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2543 rxchan_fatal = B_TRUE; 2544 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2545 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2546 } 2547 if (cs.bits.hdw.rsp_cnt_err) { 2548 rdc_stats->rsp_cnt_err++; 2549 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2550 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2551 rxchan_fatal = B_TRUE; 2552 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2553 "==> nxge_rx_err_evnts(channel %d): " 2554 "rsp_cnt_err", channel)); 2555 } 2556 if (cs.bits.hdw.byte_en_bus) { 2557 rdc_stats->byte_en_bus++; 2558 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2559 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2560 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2561 "==> nxge_rx_err_evnts(channel %d): " 2562 "fatal error: byte_en_bus", channel)); 2563 rxchan_fatal = B_TRUE; 2564 } 2565 if (cs.bits.hdw.rsp_dat_err) { 2566 rdc_stats->rsp_dat_err++; 2567 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2568 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2569 rxchan_fatal = B_TRUE; 2570 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2571 "==> nxge_rx_err_evnts(channel %d): " 2572 "fatal error: rsp_dat_err", channel)); 2573 } 2574 if (cs.bits.hdw.rcr_ack_err) { 2575 rdc_stats->rcr_ack_err++; 2576 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2577 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2578 rxchan_fatal = B_TRUE; 2579 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2580 "==> nxge_rx_err_evnts(channel %d): " 2581 "fatal error: rcr_ack_err", channel)); 2582 } 2583 if (cs.bits.hdw.dc_fifo_err) { 2584 rdc_stats->dc_fifo_err++; 2585 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2586 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2587 /* This is not a fatal error! */ 2588 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2589 "==> nxge_rx_err_evnts(channel %d): " 2590 "dc_fifo_err", channel)); 2591 rxport_fatal = B_TRUE; 2592 } 2593 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2594 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2595 &rdc_stats->errlog.pre_par, 2596 &rdc_stats->errlog.sha_par)) 2597 != NPI_SUCCESS) { 2598 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2599 "==> nxge_rx_err_evnts(channel %d): " 2600 "rcr_sha_par: get perr", channel)); 2601 return (NXGE_ERROR | rs); 2602 } 2603 if (cs.bits.hdw.rcr_sha_par) { 2604 rdc_stats->rcr_sha_par++; 2605 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2606 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2607 rxchan_fatal = B_TRUE; 2608 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2609 "==> nxge_rx_err_evnts(channel %d): " 2610 "fatal error: rcr_sha_par", channel)); 2611 } 2612 if (cs.bits.hdw.rbr_pre_par) { 2613 rdc_stats->rbr_pre_par++; 2614 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2615 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2616 rxchan_fatal = B_TRUE; 2617 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2618 "==> nxge_rx_err_evnts(channel %d): " 2619 "fatal error: rbr_pre_par", channel)); 2620 } 2621 } 2622 if (cs.bits.hdw.port_drop_pkt) { 2623 rdc_stats->port_drop_pkt++; 2624 if (rdc_stats->port_drop_pkt < error_disp_cnt) 2625 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2626 "==> nxge_rx_err_evnts (channel %d): " 2627 "port_drop_pkt", channel)); 2628 } 2629 if (cs.bits.hdw.wred_drop) { 2630 rdc_stats->wred_drop++; 2631 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2632 "==> nxge_rx_err_evnts(channel %d): " 2633 "wred_drop", channel)); 2634 } 2635 if (cs.bits.hdw.rbr_pre_empty) { 2636 rdc_stats->rbr_pre_empty++; 2637 if (rdc_stats->rbr_pre_empty < error_disp_cnt) 2638 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2639 "==> nxge_rx_err_evnts(channel %d): " 2640 "rbr_pre_empty", channel)); 2641 } 2642 if (cs.bits.hdw.rcr_shadow_full) { 2643 rdc_stats->rcr_shadow_full++; 2644 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2645 "==> nxge_rx_err_evnts(channel %d): " 2646 "rcr_shadow_full", channel)); 2647 } 2648 if (cs.bits.hdw.config_err) { 2649 rdc_stats->config_err++; 2650 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2651 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2652 rxchan_fatal = B_TRUE; 2653 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2654 "==> nxge_rx_err_evnts(channel %d): " 2655 "config error", channel)); 2656 } 2657 if (cs.bits.hdw.rcrincon) { 2658 rdc_stats->rcrincon++; 2659 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2660 NXGE_FM_EREPORT_RDMC_RCRINCON); 2661 rxchan_fatal = B_TRUE; 2662 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2663 "==> nxge_rx_err_evnts(channel %d): " 2664 "fatal error: rcrincon error", channel)); 2665 } 2666 if (cs.bits.hdw.rcrfull) { 2667 rdc_stats->rcrfull++; 2668 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2669 NXGE_FM_EREPORT_RDMC_RCRFULL); 2670 rxchan_fatal = B_TRUE; 2671 if (rdc_stats->rcrfull < error_disp_cnt) 2672 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2673 "==> nxge_rx_err_evnts(channel %d): " 2674 "fatal error: rcrfull error", channel)); 2675 } 2676 if (cs.bits.hdw.rbr_empty) { 2677 rdc_stats->rbr_empty++; 2678 if (rdc_stats->rbr_empty < error_disp_cnt) 2679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2680 "==> nxge_rx_err_evnts(channel %d): " 2681 "rbr empty error", channel)); 2682 } 2683 if (cs.bits.hdw.rbrfull) { 2684 rdc_stats->rbrfull++; 2685 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2686 NXGE_FM_EREPORT_RDMC_RBRFULL); 2687 rxchan_fatal = B_TRUE; 2688 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2689 "==> nxge_rx_err_evnts(channel %d): " 2690 "fatal error: rbr_full error", channel)); 2691 } 2692 if (cs.bits.hdw.rbrlogpage) { 2693 rdc_stats->rbrlogpage++; 2694 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2695 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2696 rxchan_fatal = B_TRUE; 2697 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2698 "==> nxge_rx_err_evnts(channel %d): " 2699 "fatal error: rbr logical page error", channel)); 2700 } 2701 if (cs.bits.hdw.cfiglogpage) { 2702 rdc_stats->cfiglogpage++; 2703 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2704 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2705 rxchan_fatal = B_TRUE; 2706 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2707 "==> nxge_rx_err_evnts(channel %d): " 2708 "fatal error: cfig logical page error", channel)); 2709 } 2710 2711 if (rxport_fatal) { 2712 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2713 " nxge_rx_err_evnts: " 2714 " fatal error on Port #%d\n", 2715 portn)); 2716 status = nxge_ipp_fatal_err_recover(nxgep); 2717 if (status == NXGE_OK) { 2718 FM_SERVICE_RESTORED(nxgep); 2719 } 2720 } 2721 2722 if (rxchan_fatal) { 2723 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2724 " nxge_rx_err_evnts: " 2725 " fatal error on Channel #%d\n", 2726 channel)); 2727 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2728 if (status == NXGE_OK) { 2729 FM_SERVICE_RESTORED(nxgep); 2730 } 2731 } 2732 2733 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2734 2735 return (status); 2736 } 2737 2738 static nxge_status_t 2739 nxge_map_rxdma(p_nxge_t nxgep) 2740 { 2741 int i, ndmas; 2742 uint16_t channel; 2743 p_rx_rbr_rings_t rx_rbr_rings; 2744 p_rx_rbr_ring_t *rbr_rings; 2745 p_rx_rcr_rings_t rx_rcr_rings; 2746 p_rx_rcr_ring_t *rcr_rings; 2747 p_rx_mbox_areas_t rx_mbox_areas_p; 2748 p_rx_mbox_t *rx_mbox_p; 2749 p_nxge_dma_pool_t dma_buf_poolp; 2750 p_nxge_dma_pool_t dma_cntl_poolp; 2751 p_nxge_dma_common_t *dma_buf_p; 2752 p_nxge_dma_common_t *dma_cntl_p; 2753 uint32_t *num_chunks; 2754 nxge_status_t status = NXGE_OK; 2755 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2756 p_nxge_dma_common_t t_dma_buf_p; 2757 p_nxge_dma_common_t t_dma_cntl_p; 2758 #endif 2759 2760 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 2761 2762 dma_buf_poolp = nxgep->rx_buf_pool_p; 2763 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2764 2765 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2766 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2767 "<== nxge_map_rxdma: buf not allocated")); 2768 return (NXGE_ERROR); 2769 } 2770 2771 ndmas = dma_buf_poolp->ndmas; 2772 if (!ndmas) { 2773 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2774 "<== nxge_map_rxdma: no dma allocated")); 2775 return (NXGE_ERROR); 2776 } 2777 2778 num_chunks = dma_buf_poolp->num_chunks; 2779 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2780 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2781 2782 rx_rbr_rings = (p_rx_rbr_rings_t) 2783 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2784 rbr_rings = (p_rx_rbr_ring_t *) 2785 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2786 rx_rcr_rings = (p_rx_rcr_rings_t) 2787 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2788 rcr_rings = (p_rx_rcr_ring_t *) 2789 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2790 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2791 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2792 rx_mbox_p = (p_rx_mbox_t *) 2793 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2794 2795 /* 2796 * Timeout should be set based on the system clock divider. 2797 * The following timeout value of 1 assumes that the 2798 * granularity (1000) is 3 microseconds running at 300MHz. 2799 */ 2800 2801 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2802 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2803 2804 /* 2805 * Map descriptors from the buffer polls for each dam channel. 2806 */ 2807 for (i = 0; i < ndmas; i++) { 2808 /* 2809 * Set up and prepare buffer blocks, descriptors 2810 * and mailbox. 2811 */ 2812 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2813 status = nxge_map_rxdma_channel(nxgep, channel, 2814 (p_nxge_dma_common_t *)&dma_buf_p[i], 2815 (p_rx_rbr_ring_t *)&rbr_rings[i], 2816 num_chunks[i], 2817 (p_nxge_dma_common_t *)&dma_cntl_p[i], 2818 (p_rx_rcr_ring_t *)&rcr_rings[i], 2819 (p_rx_mbox_t *)&rx_mbox_p[i]); 2820 if (status != NXGE_OK) { 2821 goto nxge_map_rxdma_fail1; 2822 } 2823 rbr_rings[i]->index = (uint16_t)i; 2824 rcr_rings[i]->index = (uint16_t)i; 2825 rcr_rings[i]->rdc_stats = &nxgep->statsp->rdc_stats[i]; 2826 2827 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2828 if (nxgep->niu_type == N2_NIU && NXGE_DMA_BLOCK == 1) { 2829 rbr_rings[i]->hv_set = B_FALSE; 2830 t_dma_buf_p = (p_nxge_dma_common_t)dma_buf_p[i]; 2831 t_dma_cntl_p = 2832 (p_nxge_dma_common_t)dma_cntl_p[i]; 2833 2834 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp = 2835 (uint64_t)t_dma_buf_p->orig_ioaddr_pp; 2836 rbr_rings[i]->hv_rx_buf_ioaddr_size = 2837 (uint64_t)t_dma_buf_p->orig_alength; 2838 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2839 "==> nxge_map_rxdma_channel: " 2840 "channel %d " 2841 "data buf base io $%p ($%p) " 2842 "size 0x%llx (%d 0x%x)", 2843 channel, 2844 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp, 2845 t_dma_cntl_p->ioaddr_pp, 2846 rbr_rings[i]->hv_rx_buf_ioaddr_size, 2847 t_dma_buf_p->orig_alength, 2848 t_dma_buf_p->orig_alength)); 2849 2850 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp = 2851 (uint64_t)t_dma_cntl_p->orig_ioaddr_pp; 2852 rbr_rings[i]->hv_rx_cntl_ioaddr_size = 2853 (uint64_t)t_dma_cntl_p->orig_alength; 2854 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2855 "==> nxge_map_rxdma_channel: " 2856 "channel %d " 2857 "cntl base io $%p ($%p) " 2858 "size 0x%llx (%d 0x%x)", 2859 channel, 2860 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp, 2861 t_dma_cntl_p->ioaddr_pp, 2862 rbr_rings[i]->hv_rx_cntl_ioaddr_size, 2863 t_dma_cntl_p->orig_alength, 2864 t_dma_cntl_p->orig_alength)); 2865 } 2866 2867 #endif /* sun4v and NIU_LP_WORKAROUND */ 2868 } 2869 2870 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2871 rx_rbr_rings->rbr_rings = rbr_rings; 2872 nxgep->rx_rbr_rings = rx_rbr_rings; 2873 rx_rcr_rings->rcr_rings = rcr_rings; 2874 nxgep->rx_rcr_rings = rx_rcr_rings; 2875 2876 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2877 nxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2878 2879 goto nxge_map_rxdma_exit; 2880 2881 nxge_map_rxdma_fail1: 2882 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2883 "==> nxge_map_rxdma: unmap rbr,rcr " 2884 "(status 0x%x channel %d i %d)", 2885 status, channel, i)); 2886 for (; i >= 0; i--) { 2887 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2888 nxge_unmap_rxdma_channel(nxgep, channel, 2889 rbr_rings[i], 2890 rcr_rings[i], 2891 rx_mbox_p[i]); 2892 } 2893 2894 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2895 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2896 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2897 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2898 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2899 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2900 2901 nxge_map_rxdma_exit: 2902 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2903 "<== nxge_map_rxdma: " 2904 "(status 0x%x channel %d)", 2905 status, channel)); 2906 2907 return (status); 2908 } 2909 2910 static void 2911 nxge_unmap_rxdma(p_nxge_t nxgep) 2912 { 2913 int i, ndmas; 2914 uint16_t channel; 2915 p_rx_rbr_rings_t rx_rbr_rings; 2916 p_rx_rbr_ring_t *rbr_rings; 2917 p_rx_rcr_rings_t rx_rcr_rings; 2918 p_rx_rcr_ring_t *rcr_rings; 2919 p_rx_mbox_areas_t rx_mbox_areas_p; 2920 p_rx_mbox_t *rx_mbox_p; 2921 p_nxge_dma_pool_t dma_buf_poolp; 2922 p_nxge_dma_pool_t dma_cntl_poolp; 2923 p_nxge_dma_common_t *dma_buf_p; 2924 2925 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma")); 2926 2927 dma_buf_poolp = nxgep->rx_buf_pool_p; 2928 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2929 2930 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2931 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2932 "<== nxge_unmap_rxdma: NULL buf pointers")); 2933 return; 2934 } 2935 2936 rx_rbr_rings = nxgep->rx_rbr_rings; 2937 rx_rcr_rings = nxgep->rx_rcr_rings; 2938 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2939 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2940 "<== nxge_unmap_rxdma: NULL ring pointers")); 2941 return; 2942 } 2943 ndmas = rx_rbr_rings->ndmas; 2944 if (!ndmas) { 2945 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2946 "<== nxge_unmap_rxdma: no channel")); 2947 return; 2948 } 2949 2950 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2951 "==> nxge_unmap_rxdma (ndmas %d)", ndmas)); 2952 rbr_rings = rx_rbr_rings->rbr_rings; 2953 rcr_rings = rx_rcr_rings->rcr_rings; 2954 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 2955 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2956 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2957 2958 for (i = 0; i < ndmas; i++) { 2959 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2960 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2961 "==> nxge_unmap_rxdma (ndmas %d) channel %d", 2962 ndmas, channel)); 2963 (void) nxge_unmap_rxdma_channel(nxgep, channel, 2964 (p_rx_rbr_ring_t)rbr_rings[i], 2965 (p_rx_rcr_ring_t)rcr_rings[i], 2966 (p_rx_mbox_t)rx_mbox_p[i]); 2967 } 2968 2969 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2970 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2971 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2972 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2973 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2974 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2975 2976 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2977 "<== nxge_unmap_rxdma")); 2978 } 2979 2980 nxge_status_t 2981 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 2982 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2983 uint32_t num_chunks, 2984 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 2985 p_rx_mbox_t *rx_mbox_p) 2986 { 2987 int status = NXGE_OK; 2988 2989 /* 2990 * Set up and prepare buffer blocks, descriptors 2991 * and mailbox. 2992 */ 2993 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2994 "==> nxge_map_rxdma_channel (channel %d)", channel)); 2995 /* 2996 * Receive buffer blocks 2997 */ 2998 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 2999 dma_buf_p, rbr_p, num_chunks); 3000 if (status != NXGE_OK) { 3001 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3002 "==> nxge_map_rxdma_channel (channel %d): " 3003 "map buffer failed 0x%x", channel, status)); 3004 goto nxge_map_rxdma_channel_exit; 3005 } 3006 3007 /* 3008 * Receive block ring, completion ring and mailbox. 3009 */ 3010 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3011 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3012 if (status != NXGE_OK) { 3013 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3014 "==> nxge_map_rxdma_channel (channel %d): " 3015 "map config failed 0x%x", channel, status)); 3016 goto nxge_map_rxdma_channel_fail2; 3017 } 3018 3019 goto nxge_map_rxdma_channel_exit; 3020 3021 nxge_map_rxdma_channel_fail3: 3022 /* Free rbr, rcr */ 3023 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3024 "==> nxge_map_rxdma_channel: free rbr/rcr " 3025 "(status 0x%x channel %d)", 3026 status, channel)); 3027 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3028 *rcr_p, *rx_mbox_p); 3029 3030 nxge_map_rxdma_channel_fail2: 3031 /* Free buffer blocks */ 3032 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3033 "==> nxge_map_rxdma_channel: free rx buffers" 3034 "(nxgep 0x%x status 0x%x channel %d)", 3035 nxgep, status, channel)); 3036 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3037 3038 nxge_map_rxdma_channel_exit: 3039 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3040 "<== nxge_map_rxdma_channel: " 3041 "(nxgep 0x%x status 0x%x channel %d)", 3042 nxgep, status, channel)); 3043 3044 return (status); 3045 } 3046 3047 /*ARGSUSED*/ 3048 static void 3049 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3050 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3051 { 3052 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3053 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3054 3055 /* 3056 * unmap receive block ring, completion ring and mailbox. 3057 */ 3058 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3059 rcr_p, rx_mbox_p); 3060 3061 /* unmap buffer blocks */ 3062 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3063 3064 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3065 } 3066 3067 /*ARGSUSED*/ 3068 static nxge_status_t 3069 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3070 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3071 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3072 { 3073 p_rx_rbr_ring_t rbrp; 3074 p_rx_rcr_ring_t rcrp; 3075 p_rx_mbox_t mboxp; 3076 p_nxge_dma_common_t cntl_dmap; 3077 p_nxge_dma_common_t dmap; 3078 p_rx_msg_t *rx_msg_ring; 3079 p_rx_msg_t rx_msg_p; 3080 p_rbr_cfig_a_t rcfga_p; 3081 p_rbr_cfig_b_t rcfgb_p; 3082 p_rcrcfig_a_t cfga_p; 3083 p_rcrcfig_b_t cfgb_p; 3084 p_rxdma_cfig1_t cfig1_p; 3085 p_rxdma_cfig2_t cfig2_p; 3086 p_rbr_kick_t kick_p; 3087 uint32_t dmaaddrp; 3088 uint32_t *rbr_vaddrp; 3089 uint32_t bkaddr; 3090 nxge_status_t status = NXGE_OK; 3091 int i; 3092 uint32_t nxge_port_rcr_size; 3093 3094 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3095 "==> nxge_map_rxdma_channel_cfg_ring")); 3096 3097 cntl_dmap = *dma_cntl_p; 3098 3099 /* Map in the receive block ring */ 3100 rbrp = *rbr_p; 3101 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3102 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3103 /* 3104 * Zero out buffer block ring descriptors. 3105 */ 3106 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3107 3108 rcfga_p = &(rbrp->rbr_cfga); 3109 rcfgb_p = &(rbrp->rbr_cfgb); 3110 kick_p = &(rbrp->rbr_kick); 3111 rcfga_p->value = 0; 3112 rcfgb_p->value = 0; 3113 kick_p->value = 0; 3114 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3115 rcfga_p->value = (rbrp->rbr_addr & 3116 (RBR_CFIG_A_STDADDR_MASK | 3117 RBR_CFIG_A_STDADDR_BASE_MASK)); 3118 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3119 3120 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3121 rcfgb_p->bits.ldw.vld0 = 1; 3122 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3123 rcfgb_p->bits.ldw.vld1 = 1; 3124 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3125 rcfgb_p->bits.ldw.vld2 = 1; 3126 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3127 3128 /* 3129 * For each buffer block, enter receive block address to the ring. 3130 */ 3131 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3132 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3133 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3134 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3135 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3136 3137 rx_msg_ring = rbrp->rx_msg_ring; 3138 for (i = 0; i < rbrp->tnblocks; i++) { 3139 rx_msg_p = rx_msg_ring[i]; 3140 rx_msg_p->nxgep = nxgep; 3141 rx_msg_p->rx_rbr_p = rbrp; 3142 bkaddr = (uint32_t) 3143 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3144 >> RBR_BKADDR_SHIFT)); 3145 rx_msg_p->free = B_FALSE; 3146 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3147 3148 *rbr_vaddrp++ = bkaddr; 3149 } 3150 3151 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3152 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3153 3154 rbrp->rbr_rd_index = 0; 3155 3156 rbrp->rbr_consumed = 0; 3157 rbrp->rbr_use_bcopy = B_TRUE; 3158 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3159 /* 3160 * Do bcopy on packets greater than bcopy size once 3161 * the lo threshold is reached. 3162 * This lo threshold should be less than the hi threshold. 3163 * 3164 * Do bcopy on every packet once the hi threshold is reached. 3165 */ 3166 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3167 /* default it to use hi */ 3168 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3169 } 3170 3171 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3172 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3173 } 3174 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3175 3176 switch (nxge_rx_threshold_hi) { 3177 default: 3178 case NXGE_RX_COPY_NONE: 3179 /* Do not do bcopy at all */ 3180 rbrp->rbr_use_bcopy = B_FALSE; 3181 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3182 break; 3183 3184 case NXGE_RX_COPY_1: 3185 case NXGE_RX_COPY_2: 3186 case NXGE_RX_COPY_3: 3187 case NXGE_RX_COPY_4: 3188 case NXGE_RX_COPY_5: 3189 case NXGE_RX_COPY_6: 3190 case NXGE_RX_COPY_7: 3191 rbrp->rbr_threshold_hi = 3192 rbrp->rbb_max * 3193 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3194 break; 3195 3196 case NXGE_RX_COPY_ALL: 3197 rbrp->rbr_threshold_hi = 0; 3198 break; 3199 } 3200 3201 switch (nxge_rx_threshold_lo) { 3202 default: 3203 case NXGE_RX_COPY_NONE: 3204 /* Do not do bcopy at all */ 3205 if (rbrp->rbr_use_bcopy) { 3206 rbrp->rbr_use_bcopy = B_FALSE; 3207 } 3208 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3209 break; 3210 3211 case NXGE_RX_COPY_1: 3212 case NXGE_RX_COPY_2: 3213 case NXGE_RX_COPY_3: 3214 case NXGE_RX_COPY_4: 3215 case NXGE_RX_COPY_5: 3216 case NXGE_RX_COPY_6: 3217 case NXGE_RX_COPY_7: 3218 rbrp->rbr_threshold_lo = 3219 rbrp->rbb_max * 3220 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3221 break; 3222 3223 case NXGE_RX_COPY_ALL: 3224 rbrp->rbr_threshold_lo = 0; 3225 break; 3226 } 3227 3228 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3229 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3230 "rbb_max %d " 3231 "rbrp->rbr_bufsize_type %d " 3232 "rbb_threshold_hi %d " 3233 "rbb_threshold_lo %d", 3234 dma_channel, 3235 rbrp->rbb_max, 3236 rbrp->rbr_bufsize_type, 3237 rbrp->rbr_threshold_hi, 3238 rbrp->rbr_threshold_lo)); 3239 3240 rbrp->page_valid.value = 0; 3241 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3242 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3243 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3244 rbrp->page_hdl.value = 0; 3245 3246 rbrp->page_valid.bits.ldw.page0 = 1; 3247 rbrp->page_valid.bits.ldw.page1 = 1; 3248 3249 /* Map in the receive completion ring */ 3250 rcrp = (p_rx_rcr_ring_t) 3251 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3252 rcrp->rdc = dma_channel; 3253 3254 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3255 rcrp->comp_size = nxge_port_rcr_size; 3256 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3257 3258 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3259 3260 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3261 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3262 sizeof (rcr_entry_t)); 3263 rcrp->comp_rd_index = 0; 3264 rcrp->comp_wt_index = 0; 3265 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3266 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3267 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3268 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3269 3270 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3271 (nxge_port_rcr_size - 1); 3272 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3273 (nxge_port_rcr_size - 1); 3274 3275 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3276 "==> nxge_map_rxdma_channel_cfg_ring: " 3277 "channel %d " 3278 "rbr_vaddrp $%p " 3279 "rcr_desc_rd_head_p $%p " 3280 "rcr_desc_rd_head_pp $%p " 3281 "rcr_desc_rd_last_p $%p " 3282 "rcr_desc_rd_last_pp $%p ", 3283 dma_channel, 3284 rbr_vaddrp, 3285 rcrp->rcr_desc_rd_head_p, 3286 rcrp->rcr_desc_rd_head_pp, 3287 rcrp->rcr_desc_last_p, 3288 rcrp->rcr_desc_last_pp)); 3289 3290 /* 3291 * Zero out buffer block ring descriptors. 3292 */ 3293 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3294 rcrp->intr_timeout = nxgep->intr_timeout; 3295 rcrp->intr_threshold = nxgep->intr_threshold; 3296 rcrp->full_hdr_flag = B_FALSE; 3297 rcrp->sw_priv_hdr_len = 0; 3298 3299 cfga_p = &(rcrp->rcr_cfga); 3300 cfgb_p = &(rcrp->rcr_cfgb); 3301 cfga_p->value = 0; 3302 cfgb_p->value = 0; 3303 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3304 cfga_p->value = (rcrp->rcr_addr & 3305 (RCRCFIG_A_STADDR_MASK | 3306 RCRCFIG_A_STADDR_BASE_MASK)); 3307 3308 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3309 RCRCFIG_A_LEN_SHIF); 3310 3311 /* 3312 * Timeout should be set based on the system clock divider. 3313 * The following timeout value of 1 assumes that the 3314 * granularity (1000) is 3 microseconds running at 300MHz. 3315 */ 3316 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3317 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3318 cfgb_p->bits.ldw.entout = 1; 3319 3320 /* Map in the mailbox */ 3321 mboxp = (p_rx_mbox_t) 3322 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3323 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3324 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3325 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3326 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3327 cfig1_p->value = cfig2_p->value = 0; 3328 3329 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3330 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3331 "==> nxge_map_rxdma_channel_cfg_ring: " 3332 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3333 dma_channel, cfig1_p->value, cfig2_p->value, 3334 mboxp->mbox_addr)); 3335 3336 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3337 & 0xfff); 3338 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3339 3340 3341 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3342 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3343 RXDMA_CFIG2_MBADDR_L_MASK); 3344 3345 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3346 3347 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3348 "==> nxge_map_rxdma_channel_cfg_ring: " 3349 "channel %d damaddrp $%p " 3350 "cfg1 0x%016llx cfig2 0x%016llx", 3351 dma_channel, dmaaddrp, 3352 cfig1_p->value, cfig2_p->value)); 3353 3354 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3355 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3356 3357 rbrp->rx_rcr_p = rcrp; 3358 rcrp->rx_rbr_p = rbrp; 3359 *rcr_p = rcrp; 3360 *rx_mbox_p = mboxp; 3361 3362 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3363 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3364 3365 return (status); 3366 } 3367 3368 /*ARGSUSED*/ 3369 static void 3370 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3371 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3372 { 3373 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3374 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3375 rcr_p->rdc)); 3376 3377 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3378 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3379 3380 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3381 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3382 } 3383 3384 static nxge_status_t 3385 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3386 p_nxge_dma_common_t *dma_buf_p, 3387 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3388 { 3389 p_rx_rbr_ring_t rbrp; 3390 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3391 p_rx_msg_t *rx_msg_ring; 3392 p_rx_msg_t rx_msg_p; 3393 p_mblk_t mblk_p; 3394 3395 rxring_info_t *ring_info; 3396 nxge_status_t status = NXGE_OK; 3397 int i, j, index; 3398 uint32_t size, bsize, nblocks, nmsgs; 3399 3400 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3401 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3402 channel)); 3403 3404 dma_bufp = tmp_bufp = *dma_buf_p; 3405 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3406 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3407 "chunks bufp 0x%016llx", 3408 channel, num_chunks, dma_bufp)); 3409 3410 nmsgs = 0; 3411 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3412 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3413 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3414 "bufp 0x%016llx nblocks %d nmsgs %d", 3415 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3416 nmsgs += tmp_bufp->nblocks; 3417 } 3418 if (!nmsgs) { 3419 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3420 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3421 "no msg blocks", 3422 channel)); 3423 status = NXGE_ERROR; 3424 goto nxge_map_rxdma_channel_buf_ring_exit; 3425 } 3426 3427 rbrp = (p_rx_rbr_ring_t) 3428 KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 3429 3430 size = nmsgs * sizeof (p_rx_msg_t); 3431 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3432 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3433 KM_SLEEP); 3434 3435 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3436 (void *)nxgep->interrupt_cookie); 3437 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3438 (void *)nxgep->interrupt_cookie); 3439 rbrp->rdc = channel; 3440 rbrp->num_blocks = num_chunks; 3441 rbrp->tnblocks = nmsgs; 3442 rbrp->rbb_max = nmsgs; 3443 rbrp->rbr_max_size = nmsgs; 3444 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3445 3446 /* 3447 * Buffer sizes suggested by NIU architect. 3448 * 256, 512 and 2K. 3449 */ 3450 3451 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3452 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3453 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3454 3455 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3456 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3457 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3458 3459 rbrp->block_size = nxgep->rx_default_block_size; 3460 3461 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3462 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3463 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3464 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3465 } else { 3466 if (rbrp->block_size >= 0x2000) { 3467 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3468 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3469 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3470 } else { 3471 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3472 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3473 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3474 } 3475 } 3476 3477 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3478 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3479 "actual rbr max %d rbb_max %d nmsgs %d " 3480 "rbrp->block_size %d default_block_size %d " 3481 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3482 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3483 rbrp->block_size, nxgep->rx_default_block_size, 3484 nxge_rbr_size, nxge_rbr_spare_size)); 3485 3486 /* Map in buffers from the buffer pool. */ 3487 index = 0; 3488 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3489 bsize = dma_bufp->block_size; 3490 nblocks = dma_bufp->nblocks; 3491 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3492 ring_info->buffer[i].buf_index = i; 3493 ring_info->buffer[i].buf_size = dma_bufp->alength; 3494 ring_info->buffer[i].start_index = index; 3495 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3496 3497 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3498 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3499 "chunk %d" 3500 " nblocks %d chunk_size %x block_size 0x%x " 3501 "dma_bufp $%p", channel, i, 3502 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3503 dma_bufp)); 3504 3505 for (j = 0; j < nblocks; j++) { 3506 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3507 dma_bufp)) == NULL) { 3508 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3509 "allocb failed")); 3510 break; 3511 } 3512 rx_msg_ring[index] = rx_msg_p; 3513 rx_msg_p->block_index = index; 3514 rx_msg_p->shifted_addr = (uint32_t) 3515 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3516 RBR_BKADDR_SHIFT)); 3517 3518 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3519 "index %d j %d rx_msg_p $%p", 3520 index, j, rx_msg_p)); 3521 3522 mblk_p = rx_msg_p->rx_mblk_p; 3523 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3524 index++; 3525 rx_msg_p->buf_dma.dma_channel = channel; 3526 } 3527 } 3528 if (i < rbrp->num_blocks) { 3529 goto nxge_map_rxdma_channel_buf_ring_fail1; 3530 } 3531 3532 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3533 "nxge_map_rxdma_channel_buf_ring: done buf init " 3534 "channel %d msg block entries %d", 3535 channel, index)); 3536 ring_info->block_size_mask = bsize - 1; 3537 rbrp->rx_msg_ring = rx_msg_ring; 3538 rbrp->dma_bufp = dma_buf_p; 3539 rbrp->ring_info = ring_info; 3540 3541 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3542 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3543 " nxge_map_rxdma_channel_buf_ring: " 3544 "channel %d done buf info init", channel)); 3545 3546 *rbr_p = rbrp; 3547 goto nxge_map_rxdma_channel_buf_ring_exit; 3548 3549 nxge_map_rxdma_channel_buf_ring_fail1: 3550 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3551 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3552 channel, status)); 3553 3554 index--; 3555 for (; index >= 0; index--) { 3556 rx_msg_p = rx_msg_ring[index]; 3557 if (rx_msg_p != NULL) { 3558 freeb(rx_msg_p->rx_mblk_p); 3559 rx_msg_ring[index] = NULL; 3560 } 3561 } 3562 nxge_map_rxdma_channel_buf_ring_fail: 3563 MUTEX_DESTROY(&rbrp->post_lock); 3564 MUTEX_DESTROY(&rbrp->lock); 3565 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3566 KMEM_FREE(rx_msg_ring, size); 3567 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3568 3569 nxge_map_rxdma_channel_buf_ring_exit: 3570 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3571 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3572 3573 return (status); 3574 } 3575 3576 /*ARGSUSED*/ 3577 static void 3578 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3579 p_rx_rbr_ring_t rbr_p) 3580 { 3581 p_rx_msg_t *rx_msg_ring; 3582 p_rx_msg_t rx_msg_p; 3583 rxring_info_t *ring_info; 3584 int i; 3585 uint32_t size; 3586 #ifdef NXGE_DEBUG 3587 int num_chunks; 3588 #endif 3589 3590 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3591 "==> nxge_unmap_rxdma_channel_buf_ring")); 3592 if (rbr_p == NULL) { 3593 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3594 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3595 return; 3596 } 3597 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3598 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3599 rbr_p->rdc)); 3600 3601 rx_msg_ring = rbr_p->rx_msg_ring; 3602 ring_info = rbr_p->ring_info; 3603 3604 if (rx_msg_ring == NULL || ring_info == NULL) { 3605 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3606 "<== nxge_unmap_rxdma_channel_buf_ring: " 3607 "rx_msg_ring $%p ring_info $%p", 3608 rx_msg_p, ring_info)); 3609 return; 3610 } 3611 3612 #ifdef NXGE_DEBUG 3613 num_chunks = rbr_p->num_blocks; 3614 #endif 3615 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3616 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3617 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3618 "tnblocks %d (max %d) size ptrs %d ", 3619 rbr_p->rdc, num_chunks, 3620 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3621 3622 for (i = 0; i < rbr_p->tnblocks; i++) { 3623 rx_msg_p = rx_msg_ring[i]; 3624 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3625 " nxge_unmap_rxdma_channel_buf_ring: " 3626 "rx_msg_p $%p", 3627 rx_msg_p)); 3628 if (rx_msg_p != NULL) { 3629 freeb(rx_msg_p->rx_mblk_p); 3630 rx_msg_ring[i] = NULL; 3631 } 3632 } 3633 3634 MUTEX_DESTROY(&rbr_p->post_lock); 3635 MUTEX_DESTROY(&rbr_p->lock); 3636 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3637 KMEM_FREE(rx_msg_ring, size); 3638 KMEM_FREE(rbr_p, sizeof (rx_rbr_ring_t)); 3639 3640 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3641 "<== nxge_unmap_rxdma_channel_buf_ring")); 3642 } 3643 3644 static nxge_status_t 3645 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3646 { 3647 nxge_status_t status = NXGE_OK; 3648 3649 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3650 3651 /* 3652 * Load the sharable parameters by writing to the 3653 * function zero control registers. These FZC registers 3654 * should be initialized only once for the entire chip. 3655 */ 3656 (void) nxge_init_fzc_rx_common(nxgep); 3657 3658 /* 3659 * Initialize the RXDMA port specific FZC control configurations. 3660 * These FZC registers are pertaining to each port. 3661 */ 3662 (void) nxge_init_fzc_rxdma_port(nxgep); 3663 3664 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3665 3666 return (status); 3667 } 3668 3669 /*ARGSUSED*/ 3670 static void 3671 nxge_rxdma_hw_stop_common(p_nxge_t nxgep) 3672 { 3673 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3674 3675 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3676 } 3677 3678 static nxge_status_t 3679 nxge_rxdma_hw_start(p_nxge_t nxgep) 3680 { 3681 int i, ndmas; 3682 uint16_t channel; 3683 p_rx_rbr_rings_t rx_rbr_rings; 3684 p_rx_rbr_ring_t *rbr_rings; 3685 p_rx_rcr_rings_t rx_rcr_rings; 3686 p_rx_rcr_ring_t *rcr_rings; 3687 p_rx_mbox_areas_t rx_mbox_areas_p; 3688 p_rx_mbox_t *rx_mbox_p; 3689 nxge_status_t status = NXGE_OK; 3690 3691 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3692 3693 rx_rbr_rings = nxgep->rx_rbr_rings; 3694 rx_rcr_rings = nxgep->rx_rcr_rings; 3695 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3696 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3697 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3698 return (NXGE_ERROR); 3699 } 3700 ndmas = rx_rbr_rings->ndmas; 3701 if (ndmas == 0) { 3702 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3703 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3704 return (NXGE_ERROR); 3705 } 3706 3707 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3708 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3709 3710 rbr_rings = rx_rbr_rings->rbr_rings; 3711 rcr_rings = rx_rcr_rings->rcr_rings; 3712 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3713 if (rx_mbox_areas_p) { 3714 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3715 } 3716 3717 for (i = 0; i < ndmas; i++) { 3718 channel = rbr_rings[i]->rdc; 3719 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3720 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3721 ndmas, channel)); 3722 status = nxge_rxdma_start_channel(nxgep, channel, 3723 (p_rx_rbr_ring_t)rbr_rings[i], 3724 (p_rx_rcr_ring_t)rcr_rings[i], 3725 (p_rx_mbox_t)rx_mbox_p[i]); 3726 if (status != NXGE_OK) { 3727 goto nxge_rxdma_hw_start_fail1; 3728 } 3729 } 3730 3731 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3732 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3733 rx_rbr_rings, rx_rcr_rings)); 3734 3735 goto nxge_rxdma_hw_start_exit; 3736 3737 nxge_rxdma_hw_start_fail1: 3738 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3739 "==> nxge_rxdma_hw_start: disable " 3740 "(status 0x%x channel %d i %d)", status, channel, i)); 3741 for (; i >= 0; i--) { 3742 channel = rbr_rings[i]->rdc; 3743 (void) nxge_rxdma_stop_channel(nxgep, channel); 3744 } 3745 3746 nxge_rxdma_hw_start_exit: 3747 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3748 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3749 3750 return (status); 3751 } 3752 3753 static void 3754 nxge_rxdma_hw_stop(p_nxge_t nxgep) 3755 { 3756 int i, ndmas; 3757 uint16_t channel; 3758 p_rx_rbr_rings_t rx_rbr_rings; 3759 p_rx_rbr_ring_t *rbr_rings; 3760 p_rx_rcr_rings_t rx_rcr_rings; 3761 3762 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3763 3764 rx_rbr_rings = nxgep->rx_rbr_rings; 3765 rx_rcr_rings = nxgep->rx_rcr_rings; 3766 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3767 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3768 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3769 return; 3770 } 3771 ndmas = rx_rbr_rings->ndmas; 3772 if (!ndmas) { 3773 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3774 "<== nxge_rxdma_hw_stop: no dma channel allocated")); 3775 return; 3776 } 3777 3778 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3779 "==> nxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3780 3781 rbr_rings = rx_rbr_rings->rbr_rings; 3782 3783 for (i = 0; i < ndmas; i++) { 3784 channel = rbr_rings[i]->rdc; 3785 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3786 "==> nxge_rxdma_hw_stop (ndmas %d) channel %d", 3787 ndmas, channel)); 3788 (void) nxge_rxdma_stop_channel(nxgep, channel); 3789 } 3790 3791 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3792 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3793 rx_rbr_rings, rx_rcr_rings)); 3794 3795 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3796 } 3797 3798 3799 static nxge_status_t 3800 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3801 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3802 3803 { 3804 npi_handle_t handle; 3805 npi_status_t rs = NPI_SUCCESS; 3806 rx_dma_ctl_stat_t cs; 3807 rx_dma_ent_msk_t ent_mask; 3808 nxge_status_t status = NXGE_OK; 3809 3810 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3811 3812 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3813 3814 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3815 "npi handle addr $%p acc $%p", 3816 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3817 3818 /* Reset RXDMA channel */ 3819 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3820 if (rs != NPI_SUCCESS) { 3821 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3822 "==> nxge_rxdma_start_channel: " 3823 "reset rxdma failed (0x%08x channel %d)", 3824 status, channel)); 3825 return (NXGE_ERROR | rs); 3826 } 3827 3828 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3829 "==> nxge_rxdma_start_channel: reset done: channel %d", 3830 channel)); 3831 3832 /* 3833 * Initialize the RXDMA channel specific FZC control 3834 * configurations. These FZC registers are pertaining 3835 * to each RX channel (logical pages). 3836 */ 3837 status = nxge_init_fzc_rxdma_channel(nxgep, 3838 channel, rbr_p, rcr_p, mbox_p); 3839 if (status != NXGE_OK) { 3840 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3841 "==> nxge_rxdma_start_channel: " 3842 "init fzc rxdma failed (0x%08x channel %d)", 3843 status, channel)); 3844 return (status); 3845 } 3846 3847 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3848 "==> nxge_rxdma_start_channel: fzc done")); 3849 3850 /* 3851 * Zero out the shadow and prefetch ram. 3852 */ 3853 3854 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3855 "ram done")); 3856 3857 /* Set up the interrupt event masks. */ 3858 ent_mask.value = 0; 3859 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 3860 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3861 &ent_mask); 3862 if (rs != NPI_SUCCESS) { 3863 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3864 "==> nxge_rxdma_start_channel: " 3865 "init rxdma event masks failed (0x%08x channel %d)", 3866 status, channel)); 3867 return (NXGE_ERROR | rs); 3868 } 3869 3870 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3871 "event done: channel %d (mask 0x%016llx)", 3872 channel, ent_mask.value)); 3873 3874 /* Initialize the receive DMA control and status register */ 3875 cs.value = 0; 3876 cs.bits.hdw.mex = 1; 3877 cs.bits.hdw.rcrthres = 1; 3878 cs.bits.hdw.rcrto = 1; 3879 cs.bits.hdw.rbr_empty = 1; 3880 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 3881 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3882 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3883 if (status != NXGE_OK) { 3884 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3885 "==> nxge_rxdma_start_channel: " 3886 "init rxdma control register failed (0x%08x channel %d", 3887 status, channel)); 3888 return (status); 3889 } 3890 3891 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3892 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3893 3894 /* 3895 * Load RXDMA descriptors, buffers, mailbox, 3896 * initialise the receive DMA channels and 3897 * enable each DMA channel. 3898 */ 3899 status = nxge_enable_rxdma_channel(nxgep, 3900 channel, rbr_p, rcr_p, mbox_p); 3901 3902 if (status != NXGE_OK) { 3903 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3904 " nxge_rxdma_start_channel: " 3905 " init enable rxdma failed (0x%08x channel %d)", 3906 status, channel)); 3907 return (status); 3908 } 3909 3910 ent_mask.value = 0; 3911 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 3912 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 3913 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3914 &ent_mask); 3915 if (rs != NPI_SUCCESS) { 3916 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3917 "==> nxge_rxdma_start_channel: " 3918 "init rxdma event masks failed (0x%08x channel %d)", 3919 status, channel)); 3920 return (NXGE_ERROR | rs); 3921 } 3922 3923 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3924 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3925 3926 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3927 "==> nxge_rxdma_start_channel: enable done")); 3928 3929 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 3930 3931 return (NXGE_OK); 3932 } 3933 3934 static nxge_status_t 3935 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 3936 { 3937 npi_handle_t handle; 3938 npi_status_t rs = NPI_SUCCESS; 3939 rx_dma_ctl_stat_t cs; 3940 rx_dma_ent_msk_t ent_mask; 3941 nxge_status_t status = NXGE_OK; 3942 3943 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 3944 3945 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3946 3947 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 3948 "npi handle addr $%p acc $%p", 3949 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3950 3951 /* Reset RXDMA channel */ 3952 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3953 if (rs != NPI_SUCCESS) { 3954 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3955 " nxge_rxdma_stop_channel: " 3956 " reset rxdma failed (0x%08x channel %d)", 3957 rs, channel)); 3958 return (NXGE_ERROR | rs); 3959 } 3960 3961 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3962 "==> nxge_rxdma_stop_channel: reset done")); 3963 3964 /* Set up the interrupt event masks. */ 3965 ent_mask.value = RX_DMA_ENT_MSK_ALL; 3966 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3967 &ent_mask); 3968 if (rs != NPI_SUCCESS) { 3969 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3970 "==> nxge_rxdma_stop_channel: " 3971 "set rxdma event masks failed (0x%08x channel %d)", 3972 rs, channel)); 3973 return (NXGE_ERROR | rs); 3974 } 3975 3976 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3977 "==> nxge_rxdma_stop_channel: event done")); 3978 3979 /* Initialize the receive DMA control and status register */ 3980 cs.value = 0; 3981 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 3982 &cs); 3983 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 3984 " to default (all 0s) 0x%08x", cs.value)); 3985 if (status != NXGE_OK) { 3986 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3987 " nxge_rxdma_stop_channel: init rxdma" 3988 " control register failed (0x%08x channel %d", 3989 status, channel)); 3990 return (status); 3991 } 3992 3993 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3994 "==> nxge_rxdma_stop_channel: control done")); 3995 3996 /* disable dma channel */ 3997 status = nxge_disable_rxdma_channel(nxgep, channel); 3998 3999 if (status != NXGE_OK) { 4000 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4001 " nxge_rxdma_stop_channel: " 4002 " init enable rxdma failed (0x%08x channel %d)", 4003 status, channel)); 4004 return (status); 4005 } 4006 4007 NXGE_DEBUG_MSG((nxgep, 4008 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4009 4010 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4011 4012 return (NXGE_OK); 4013 } 4014 4015 nxge_status_t 4016 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4017 { 4018 npi_handle_t handle; 4019 p_nxge_rdc_sys_stats_t statsp; 4020 rx_ctl_dat_fifo_stat_t stat; 4021 uint32_t zcp_err_status; 4022 uint32_t ipp_err_status; 4023 nxge_status_t status = NXGE_OK; 4024 npi_status_t rs = NPI_SUCCESS; 4025 boolean_t my_err = B_FALSE; 4026 4027 handle = nxgep->npi_handle; 4028 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4029 4030 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4031 4032 if (rs != NPI_SUCCESS) 4033 return (NXGE_ERROR | rs); 4034 4035 if (stat.bits.ldw.id_mismatch) { 4036 statsp->id_mismatch++; 4037 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4038 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4039 /* Global fatal error encountered */ 4040 } 4041 4042 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4043 switch (nxgep->mac.portnum) { 4044 case 0: 4045 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4046 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4047 my_err = B_TRUE; 4048 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4049 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4050 } 4051 break; 4052 case 1: 4053 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4054 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4055 my_err = B_TRUE; 4056 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4057 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4058 } 4059 break; 4060 case 2: 4061 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4062 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4063 my_err = B_TRUE; 4064 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4065 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4066 } 4067 break; 4068 case 3: 4069 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4070 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4071 my_err = B_TRUE; 4072 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4073 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4074 } 4075 break; 4076 default: 4077 return (NXGE_ERROR); 4078 } 4079 } 4080 4081 if (my_err) { 4082 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4083 zcp_err_status); 4084 if (status != NXGE_OK) 4085 return (status); 4086 } 4087 4088 return (NXGE_OK); 4089 } 4090 4091 static nxge_status_t 4092 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4093 uint32_t zcp_status) 4094 { 4095 boolean_t rxport_fatal = B_FALSE; 4096 p_nxge_rdc_sys_stats_t statsp; 4097 nxge_status_t status = NXGE_OK; 4098 uint8_t portn; 4099 4100 portn = nxgep->mac.portnum; 4101 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4102 4103 if (ipp_status & (0x1 << portn)) { 4104 statsp->ipp_eop_err++; 4105 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4106 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4107 rxport_fatal = B_TRUE; 4108 } 4109 4110 if (zcp_status & (0x1 << portn)) { 4111 statsp->zcp_eop_err++; 4112 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4113 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4114 rxport_fatal = B_TRUE; 4115 } 4116 4117 if (rxport_fatal) { 4118 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4119 " nxge_rxdma_handle_port_error: " 4120 " fatal error on Port #%d\n", 4121 portn)); 4122 status = nxge_rx_port_fatal_err_recover(nxgep); 4123 if (status == NXGE_OK) { 4124 FM_SERVICE_RESTORED(nxgep); 4125 } 4126 } 4127 4128 return (status); 4129 } 4130 4131 static nxge_status_t 4132 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4133 { 4134 npi_handle_t handle; 4135 npi_status_t rs = NPI_SUCCESS; 4136 nxge_status_t status = NXGE_OK; 4137 p_rx_rbr_ring_t rbrp; 4138 p_rx_rcr_ring_t rcrp; 4139 p_rx_mbox_t mboxp; 4140 rx_dma_ent_msk_t ent_mask; 4141 p_nxge_dma_common_t dmap; 4142 int ring_idx; 4143 uint32_t ref_cnt; 4144 p_rx_msg_t rx_msg_p; 4145 int i; 4146 uint32_t nxge_port_rcr_size; 4147 4148 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4149 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4150 "Recovering from RxDMAChannel#%d error...", channel)); 4151 4152 /* 4153 * Stop the dma channel waits for the stop done. 4154 * If the stop done bit is not set, then create 4155 * an error. 4156 */ 4157 4158 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4159 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4160 4161 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4162 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4163 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4164 4165 MUTEX_ENTER(&rcrp->lock); 4166 MUTEX_ENTER(&rbrp->lock); 4167 MUTEX_ENTER(&rbrp->post_lock); 4168 4169 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4170 4171 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4172 if (rs != NPI_SUCCESS) { 4173 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4174 "nxge_disable_rxdma_channel:failed")); 4175 goto fail; 4176 } 4177 4178 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4179 4180 /* Disable interrupt */ 4181 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4182 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4183 if (rs != NPI_SUCCESS) { 4184 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4185 "nxge_rxdma_stop_channel: " 4186 "set rxdma event masks failed (channel %d)", 4187 channel)); 4188 } 4189 4190 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4191 4192 /* Reset RXDMA channel */ 4193 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4194 if (rs != NPI_SUCCESS) { 4195 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4196 "nxge_rxdma_fatal_err_recover: " 4197 " reset rxdma failed (channel %d)", channel)); 4198 goto fail; 4199 } 4200 4201 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4202 4203 mboxp = 4204 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4205 4206 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4207 rbrp->rbr_rd_index = 0; 4208 4209 rcrp->comp_rd_index = 0; 4210 rcrp->comp_wt_index = 0; 4211 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4212 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4213 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4214 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4215 4216 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4217 (nxge_port_rcr_size - 1); 4218 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4219 (nxge_port_rcr_size - 1); 4220 4221 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4222 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4223 4224 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4225 4226 for (i = 0; i < rbrp->rbr_max_size; i++) { 4227 rx_msg_p = rbrp->rx_msg_ring[i]; 4228 ref_cnt = rx_msg_p->ref_cnt; 4229 if (ref_cnt != 1) { 4230 if (rx_msg_p->cur_usage_cnt != 4231 rx_msg_p->max_usage_cnt) { 4232 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4233 "buf[%d]: cur_usage_cnt = %d " 4234 "max_usage_cnt = %d\n", i, 4235 rx_msg_p->cur_usage_cnt, 4236 rx_msg_p->max_usage_cnt)); 4237 } else { 4238 /* Buffer can be re-posted */ 4239 rx_msg_p->free = B_TRUE; 4240 rx_msg_p->cur_usage_cnt = 0; 4241 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4242 rx_msg_p->pkt_buf_size = 0; 4243 } 4244 } 4245 } 4246 4247 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4248 4249 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4250 if (status != NXGE_OK) { 4251 goto fail; 4252 } 4253 4254 MUTEX_EXIT(&rbrp->post_lock); 4255 MUTEX_EXIT(&rbrp->lock); 4256 MUTEX_EXIT(&rcrp->lock); 4257 4258 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4259 "Recovery Successful, RxDMAChannel#%d Restored", 4260 channel)); 4261 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4262 4263 return (NXGE_OK); 4264 fail: 4265 MUTEX_EXIT(&rbrp->post_lock); 4266 MUTEX_EXIT(&rbrp->lock); 4267 MUTEX_EXIT(&rcrp->lock); 4268 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4269 4270 return (NXGE_ERROR | rs); 4271 } 4272 4273 nxge_status_t 4274 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4275 { 4276 nxge_status_t status = NXGE_OK; 4277 p_nxge_dma_common_t *dma_buf_p; 4278 uint16_t channel; 4279 int ndmas; 4280 int i; 4281 4282 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4283 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4284 "Recovering from RxPort error...")); 4285 /* Disable RxMAC */ 4286 4287 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxMAC...\n")); 4288 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4289 goto fail; 4290 4291 NXGE_DELAY(1000); 4292 4293 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stop all RxDMA channels...")); 4294 4295 ndmas = nxgep->rx_buf_pool_p->ndmas; 4296 dma_buf_p = nxgep->rx_buf_pool_p->dma_buf_pool_p; 4297 4298 for (i = 0; i < ndmas; i++) { 4299 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 4300 if (nxge_rxdma_fatal_err_recover(nxgep, channel) != NXGE_OK) { 4301 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4302 "Could not recover channel %d", 4303 channel)); 4304 } 4305 } 4306 4307 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset IPP...")); 4308 4309 /* Reset IPP */ 4310 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4311 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4312 "nxge_rx_port_fatal_err_recover: " 4313 "Failed to reset IPP")); 4314 goto fail; 4315 } 4316 4317 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4318 4319 /* Reset RxMAC */ 4320 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4322 "nxge_rx_port_fatal_err_recover: " 4323 "Failed to reset RxMAC")); 4324 goto fail; 4325 } 4326 4327 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4328 4329 /* Re-Initialize IPP */ 4330 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4331 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4332 "nxge_rx_port_fatal_err_recover: " 4333 "Failed to init IPP")); 4334 goto fail; 4335 } 4336 4337 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4338 4339 /* Re-Initialize RxMAC */ 4340 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4341 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4342 "nxge_rx_port_fatal_err_recover: " 4343 "Failed to reset RxMAC")); 4344 goto fail; 4345 } 4346 4347 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4348 4349 /* Re-enable RxMAC */ 4350 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4351 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4352 "nxge_rx_port_fatal_err_recover: " 4353 "Failed to enable RxMAC")); 4354 goto fail; 4355 } 4356 4357 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4358 "Recovery Successful, RxPort Restored")); 4359 4360 return (NXGE_OK); 4361 fail: 4362 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4363 return (status); 4364 } 4365 4366 void 4367 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4368 { 4369 rx_dma_ctl_stat_t cs; 4370 rx_ctl_dat_fifo_stat_t cdfs; 4371 4372 switch (err_id) { 4373 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4374 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4375 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4376 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4377 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4378 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4379 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4380 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4381 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4382 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4383 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4384 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4385 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4386 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4387 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4388 chan, &cs.value); 4389 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4390 cs.bits.hdw.rcr_ack_err = 1; 4391 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4392 cs.bits.hdw.dc_fifo_err = 1; 4393 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4394 cs.bits.hdw.rcr_sha_par = 1; 4395 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4396 cs.bits.hdw.rbr_pre_par = 1; 4397 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4398 cs.bits.hdw.rbr_tmout = 1; 4399 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4400 cs.bits.hdw.rsp_cnt_err = 1; 4401 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4402 cs.bits.hdw.byte_en_bus = 1; 4403 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4404 cs.bits.hdw.rsp_dat_err = 1; 4405 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4406 cs.bits.hdw.config_err = 1; 4407 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4408 cs.bits.hdw.rcrincon = 1; 4409 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4410 cs.bits.hdw.rcrfull = 1; 4411 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4412 cs.bits.hdw.rbrfull = 1; 4413 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4414 cs.bits.hdw.rbrlogpage = 1; 4415 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4416 cs.bits.hdw.cfiglogpage = 1; 4417 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4418 cs.value); 4419 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4420 chan, cs.value); 4421 break; 4422 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4423 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4424 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4425 cdfs.value = 0; 4426 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4427 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4428 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4429 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4430 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4431 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4432 cmn_err(CE_NOTE, 4433 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4434 cdfs.value); 4435 RXDMA_REG_WRITE64(nxgep->npi_handle, 4436 RX_CTL_DAT_FIFO_STAT_DBG_REG, chan, cdfs.value); 4437 break; 4438 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4439 break; 4440 case NXGE_FM_EREPORT_RDMC_COMPLETION_ERR: 4441 break; 4442 } 4443 } 4444 4445 4446 static uint16_t 4447 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb) 4448 { 4449 uint16_t sz = RBR_BKSIZE_8K_BYTES; 4450 4451 switch (bufsz_type) { 4452 case RCR_PKTBUFSZ_0: 4453 switch (rbr_cfgb.bits.ldw.bufsz0) { 4454 case RBR_BUFSZ0_256B: 4455 sz = RBR_BUFSZ0_256_BYTES; 4456 break; 4457 case RBR_BUFSZ0_512B: 4458 sz = RBR_BUFSZ0_512B_BYTES; 4459 break; 4460 case RBR_BUFSZ0_1K: 4461 sz = RBR_BUFSZ0_1K_BYTES; 4462 break; 4463 case RBR_BUFSZ0_2K: 4464 sz = RBR_BUFSZ0_2K_BYTES; 4465 break; 4466 default: 4467 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4468 "nxge_get_pktbug_size: bad bufsz0")); 4469 break; 4470 } 4471 break; 4472 case RCR_PKTBUFSZ_1: 4473 switch (rbr_cfgb.bits.ldw.bufsz1) { 4474 case RBR_BUFSZ1_1K: 4475 sz = RBR_BUFSZ1_1K_BYTES; 4476 break; 4477 case RBR_BUFSZ1_2K: 4478 sz = RBR_BUFSZ1_2K_BYTES; 4479 break; 4480 case RBR_BUFSZ1_4K: 4481 sz = RBR_BUFSZ1_4K_BYTES; 4482 break; 4483 case RBR_BUFSZ1_8K: 4484 sz = RBR_BUFSZ1_8K_BYTES; 4485 break; 4486 default: 4487 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4488 "nxge_get_pktbug_size: bad bufsz1")); 4489 break; 4490 } 4491 break; 4492 case RCR_PKTBUFSZ_2: 4493 switch (rbr_cfgb.bits.ldw.bufsz2) { 4494 case RBR_BUFSZ2_2K: 4495 sz = RBR_BUFSZ2_2K_BYTES; 4496 break; 4497 case RBR_BUFSZ2_4K: 4498 sz = RBR_BUFSZ2_4K_BYTES; 4499 break; 4500 case RBR_BUFSZ2_8K: 4501 sz = RBR_BUFSZ2_8K_BYTES; 4502 break; 4503 case RBR_BUFSZ2_16K: 4504 sz = RBR_BUFSZ2_16K_BYTES; 4505 break; 4506 default: 4507 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4508 "nxge_get_pktbug_size: bad bufsz2")); 4509 break; 4510 } 4511 break; 4512 case RCR_SINGLE_BLOCK: 4513 switch (rbr_cfgb.bits.ldw.bksize) { 4514 case BKSIZE_4K: 4515 sz = RBR_BKSIZE_4K_BYTES; 4516 break; 4517 case BKSIZE_8K: 4518 sz = RBR_BKSIZE_8K_BYTES; 4519 break; 4520 case BKSIZE_16K: 4521 sz = RBR_BKSIZE_16K_BYTES; 4522 break; 4523 case BKSIZE_32K: 4524 sz = RBR_BKSIZE_32K_BYTES; 4525 break; 4526 default: 4527 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4528 "nxge_get_pktbug_size: bad bksize")); 4529 break; 4530 } 4531 break; 4532 default: 4533 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4534 "nxge_get_pktbug_size: bad bufsz_type")); 4535 break; 4536 } 4537 return (sz); 4538 } 4539