1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 112 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 113 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 120 p_mblk_t, caddr_t); 121 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 122 p_mblk_t, caddr_t); 123 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 124 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 125 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 126 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 127 char *, caddr_t); 128 static int nxge_param_set_npi_debug_flag(p_nxge_t, 129 queue_t *, mblk_t *, char *, caddr_t); 130 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 131 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 132 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 137 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 138 static boolean_t nxge_param_link_update(p_nxge_t); 139 140 /* 141 * Global array of Neptune changable parameters. 142 * This array is initialized to correspond to the default 143 * Neptune 4 port configuration. This array would be copied 144 * into each port's parameter structure and modifed per 145 * fcode and nxge.conf configuration. Later, the parameters are 146 * exported to ndd to display and run-time configuration (at least 147 * some of them). 148 * 149 */ 150 151 static nxge_param_t nxge_param_arr[] = { 152 /* 153 * min max value old hw-name conf-name 154 */ 155 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 156 0, 999, 1000, 0, "instance", "instance"}, 157 158 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 159 0, 999, 1000, 0, "main-instance", "main_instance"}, 160 161 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 162 0, 3, 0, 0, "function-number", "function_number"}, 163 164 /* Partition Id */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 8, 0, 0, "partition-id", "partition_id"}, 167 168 /* Read Write Permission Mode */ 169 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 170 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 171 172 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 173 0, 32, 0, 0, "version", "fw_version"}, 174 175 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 176 0, 32, 0, 0, "port-mode", "port_mode"}, 177 178 /* hw cfg types */ 179 /* control the DMA config of Neptune/NIU */ 180 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 181 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 182 "niu-cfg-type", "niu_cfg_type"}, 183 184 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 185 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 186 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 187 "tx-qcfg-type", "tx_qcfg_type"}, 188 189 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 190 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 191 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 192 "rx-qcfg-type", "rx_qcfg_type"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, 199 NXGE_PARAM_DONT_SHOW, 200 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 201 202 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 203 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 204 205 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 206 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 207 208 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 209 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 210 211 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 212 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 213 214 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 215 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 216 217 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 218 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 219 220 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 221 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 222 223 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 224 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 225 226 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 227 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 228 229 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 230 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 231 232 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 233 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 234 235 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 236 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 237 238 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 239 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 240 241 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 242 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 243 244 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 245 0, 255, 8, 8, "ipg0", "ipg0"}, 246 247 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 248 0, 255, 8, 8, "ipg1", "ipg1"}, 249 250 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 251 0, 255, 4, 4, "ipg2", "ipg2"}, 252 253 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 254 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 255 256 /* Transmit DMA channels */ 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 264 265 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 266 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 267 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 268 { nxge_param_get_txdma_info, NULL, 269 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 270 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 271 272 /* Receive DMA channels */ 273 { nxge_param_get_generic, NULL, 274 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 280 281 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 282 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 283 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 284 "rx-drr-weight", "rx_drr_weight"}, 285 286 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 288 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 289 290 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 291 NXGE_PARAM_DONT_SHOW, 292 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 293 294 { nxge_param_get_rxdma_info, NULL, 295 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 296 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 297 "rx-rbr-size", "rx_rbr_size"}, 298 299 { nxge_param_get_rxdma_info, NULL, 300 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 301 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 302 "rx-rcr-size", "rx_rcr_size"}, 303 304 { nxge_param_get_generic, nxge_param_set_port_rdc, 305 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 306 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 310 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 311 312 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 313 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 314 RXDMA_RCR_PTHRES_DEFAULT, 0, 315 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 320 321 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 322 NXGE_PARAM_DONT_SHOW, 323 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 352 353 { nxge_param_get_generic, nxge_param_set_grp_rdc, 354 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 355 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 356 357 { nxge_param_get_rxdma_rdcgrp_info, NULL, 358 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 359 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 360 361 /* Logical device groups */ 362 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363 0, 63, 0, 0, "start-ldg", "start_ldg"}, 364 365 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 366 0, 64, 0, 0, "max-ldg", "max_ldg" }, 367 368 /* MAC table information */ 369 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 370 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 371 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 372 373 /* VLAN table information */ 374 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 375 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 376 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 377 378 { nxge_param_get_generic, NULL, 379 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 380 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 381 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 386 387 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 388 NXGE_PARAM_DONT_SHOW, 389 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 390 391 { nxge_param_get_generic, nxge_param_tcam_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 394 395 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 398 399 { nxge_param_get_generic, nxge_param_llc_snap_enable, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_fflp_hash_init, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 410 411 { nxge_param_get_generic, nxge_param_set_ether_usr, 412 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413 0, ALL_FF_32, 0x0, 0, 414 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 415 416 { nxge_param_get_generic, nxge_param_set_ether_usr, 417 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418 0, ALL_FF_32, 0x0, 0, 419 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 420 421 { nxge_param_get_generic, nxge_param_set_ip_usr, 422 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423 0, ALL_FF_32, 0x0, 0, 424 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 425 426 { nxge_param_get_generic, nxge_param_set_ip_usr, 427 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428 0, ALL_FF_32, 0x0, 0, 429 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 430 431 { nxge_param_get_generic, nxge_param_set_ip_usr, 432 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433 0, ALL_FF_32, 0x0, 0, 434 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 435 436 { nxge_param_get_generic, nxge_param_set_ip_usr, 437 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 438 0, ALL_FF_32, 0x0, 0, 439 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 440 441 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 443 0, ALL_FF_32, 0x0, 0, 444 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 445 446 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 448 0, ALL_FF_32, 0x0, 0, 449 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 450 451 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 453 0, ALL_FF_32, 0x0, 0, 454 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 455 456 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 457 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 458 0, ALL_FF_32, 0x0, 0, 459 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 460 461 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 462 NXGE_PARAM_CLASS_RWS, 463 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 464 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 465 466 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 467 NXGE_PARAM_CLASS_RWS, 468 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 469 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 470 471 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 472 NXGE_PARAM_CLASS_RWS, 473 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 474 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 475 476 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 477 NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 492 493 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 494 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 495 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 496 497 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 498 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 499 0ULL, ALL_FF_64, 0ULL, 0ULL, 500 "nxge-debug-flag", "nxge_debug_flag"}, 501 502 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 503 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 504 0ULL, ALL_FF_64, 0ULL, 0ULL, 505 "npi-debug-flag", "npi_debug_flag"}, 506 507 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 509 510 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 512 513 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 516 517 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 520 521 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 522 NXGE_PARAM_DONT_SHOW, 523 0, 0x0fffffff, 0x0fffffff, 0, 524 "dump-fflp-regs", "dump_fflp_regs"}, 525 526 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 527 NXGE_PARAM_DONT_SHOW, 528 0, 0x0fffffff, 0x0fffffff, 0, 529 "dump-vlan-table", "dump_vlan_table"}, 530 531 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 532 NXGE_PARAM_DONT_SHOW, 533 0, 0x0fffffff, 0x0fffffff, 0, 534 "dump-rdc-table", "dump_rdc_table"}, 535 536 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 537 NXGE_PARAM_DONT_SHOW, 538 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 539 540 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 541 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 542 }; 543 544 extern void *nxge_list; 545 546 void 547 nxge_get_param_soft_properties(p_nxge_t nxgep) 548 { 549 550 p_nxge_param_t param_arr; 551 uint_t prop_len; 552 int i, j; 553 uint32_t param_count; 554 uint32_t *int_prop_val; 555 556 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 557 558 param_arr = nxgep->param_arr; 559 param_count = nxgep->param_count; 560 for (i = 0; i < param_count; i++) { 561 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 562 continue; 563 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 564 continue; 565 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 566 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 567 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 568 nxgep->dip, 0, param_arr[i].fcode_name, 569 (int **)&int_prop_val, 570 (uint_t *)&prop_len) 571 == DDI_PROP_SUCCESS) { 572 uint32_t *cfg_value; 573 uint64_t prop_count; 574 575 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 576 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 577 #if defined(__i386) 578 cfg_value = 579 (uint32_t *)(int32_t)param_arr[i].value; 580 #else 581 cfg_value = (uint32_t *)param_arr[i].value; 582 #endif 583 for (j = 0; j < prop_len; j++) { 584 cfg_value[j] = int_prop_val[j]; 585 } 586 prop_count = prop_len; 587 param_arr[i].type |= 588 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 589 ddi_prop_free(int_prop_val); 590 } 591 continue; 592 } 593 594 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 595 param_arr[i].fcode_name, 596 (int **)&int_prop_val, 597 &prop_len) == DDI_PROP_SUCCESS) { 598 if ((*int_prop_val >= param_arr[i].minimum) && 599 (*int_prop_val <= param_arr[i].maximum)) 600 param_arr[i].value = *int_prop_val; 601 #ifdef NXGE_DEBUG_ERROR 602 else { 603 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 604 "nxge%d: 'prom' file parameter error\n", 605 nxgep->instance)); 606 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 607 "Parameter keyword '%s'" 608 " is outside valid range\n", 609 param_arr[i].name)); 610 } 611 #endif 612 ddi_prop_free(int_prop_val); 613 } 614 615 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 616 param_arr[i].name, 617 (int **)&int_prop_val, 618 &prop_len) == DDI_PROP_SUCCESS) { 619 if ((*int_prop_val >= param_arr[i].minimum) && 620 (*int_prop_val <= param_arr[i].maximum)) 621 param_arr[i].value = *int_prop_val; 622 #ifdef NXGE_DEBUG_ERROR 623 else { 624 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 625 "nxge%d: 'conf' file parameter error\n", 626 nxgep->instance)); 627 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 628 "Parameter keyword '%s'" 629 "is outside valid range\n", 630 param_arr[i].name)); 631 } 632 #endif 633 ddi_prop_free(int_prop_val); 634 } 635 } 636 } 637 638 static int 639 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 640 { 641 int status = B_TRUE; 642 int channel; 643 uint8_t grp; 644 char *prop_name; 645 char *end; 646 uint32_t name_chars; 647 648 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 649 "nxge_private_param_register %s", param_arr->name)); 650 651 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 652 return (B_TRUE); 653 654 prop_name = param_arr->name; 655 if (param_arr->type & NXGE_PARAM_RXDMA) { 656 if (strncmp("rxdma_intr", prop_name, 10) == 0) 657 return (B_TRUE); 658 name_chars = strlen("default_grp"); 659 if (strncmp("default_grp", prop_name, name_chars) == 0) { 660 prop_name += name_chars; 661 grp = mi_strtol(prop_name, &end, 10); 662 /* now check if this rdcgrp is in config */ 663 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 664 } 665 name_chars = strlen(prop_name); 666 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 667 return (B_TRUE); 668 } 669 return (B_FALSE); 670 } 671 672 if (param_arr->type & NXGE_PARAM_TXDMA) { 673 name_chars = strlen("txdma"); 674 if (strncmp("txdma", prop_name, name_chars) == 0) { 675 prop_name += name_chars; 676 channel = mi_strtol(prop_name, &end, 10); 677 /* now check if this rdc is in config */ 678 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 679 " nxge_private_param_register: %d", 680 channel)); 681 return (nxge_check_txdma_port_member(nxgep, channel)); 682 } 683 return (B_FALSE); 684 } 685 686 status = B_FALSE; 687 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 688 689 return (status); 690 } 691 692 void 693 nxge_setup_param(p_nxge_t nxgep) 694 { 695 p_nxge_param_t param_arr; 696 int i; 697 pfi_t set_pfi; 698 699 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 700 701 /* 702 * Make sure the param_instance is set to a valid device instance. 703 */ 704 if (nxge_param_arr[param_instance].value == 1000) 705 nxge_param_arr[param_instance].value = nxgep->instance; 706 707 param_arr = nxgep->param_arr; 708 param_arr[param_instance].value = nxgep->instance; 709 param_arr[param_function_number].value = nxgep->function_num; 710 711 for (i = 0; i < nxgep->param_count; i++) { 712 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 713 (nxge_private_param_register(nxgep, 714 ¶m_arr[i]) == B_FALSE)) { 715 param_arr[i].setf = NULL; 716 param_arr[i].getf = NULL; 717 } 718 719 if (param_arr[i].type & NXGE_PARAM_CMPLX) 720 param_arr[i].setf = NULL; 721 722 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 723 param_arr[i].setf = NULL; 724 param_arr[i].getf = NULL; 725 } 726 727 set_pfi = (pfi_t)param_arr[i].setf; 728 729 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 730 set_pfi = NULL; 731 } 732 733 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 734 (pfi_t)param_arr[i].getf, set_pfi, 735 (caddr_t)¶m_arr[i])) { 736 (void) nxge_nd_free(&nxgep->param_list); 737 break; 738 } 739 } 740 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 741 } 742 743 void 744 nxge_init_param(p_nxge_t nxgep) 745 { 746 p_nxge_param_t param_arr; 747 int i, alloc_size; 748 uint64_t alloc_count; 749 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 750 /* 751 * Make sure the param_instance is set to a valid device instance. 752 */ 753 if (nxge_param_arr[param_instance].value == 1000) 754 nxge_param_arr[param_instance].value = nxgep->instance; 755 756 param_arr = nxgep->param_arr; 757 if (param_arr == NULL) { 758 param_arr = (p_nxge_param_t) 759 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 760 } 761 762 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 763 param_arr[i] = nxge_param_arr[i]; 764 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 765 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 766 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 767 alloc_size = alloc_count * sizeof (uint64_t); 768 param_arr[i].value = 769 #if defined(__i386) 770 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 771 KM_SLEEP); 772 #else 773 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 774 #endif 775 param_arr[i].old_value = 776 #if defined(__i386) 777 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 778 KM_SLEEP); 779 #else 780 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 781 #endif 782 param_arr[i].type |= 783 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 784 } 785 } 786 787 nxgep->param_arr = param_arr; 788 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 789 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 790 nxgep->param_count)); 791 } 792 793 void 794 nxge_destroy_param(p_nxge_t nxgep) 795 { 796 int i; 797 uint64_t free_size, free_count; 798 799 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 800 801 if (nxgep->param_arr == NULL) 802 return; 803 /* 804 * Make sure the param_instance is set to a valid device instance. 805 */ 806 if (nxge_param_arr[param_instance].value == nxgep->instance) { 807 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 808 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 809 (i != nxgep->instance)) 810 break; 811 } 812 nxge_param_arr[param_instance].value = i; 813 } 814 815 if (nxgep->param_list) 816 nxge_nd_free(&nxgep->param_list); 817 for (i = 0; i < nxgep->param_count; i++) 818 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 819 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 820 free_count = ((nxgep->param_arr[i].type & 821 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 822 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 823 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 824 free_size = sizeof (uint64_t) * free_count; 825 #if defined(__i386) 826 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 827 free_size); 828 #else 829 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 830 #endif 831 #if defined(__i386) 832 KMEM_FREE((void *)(uint32_t) 833 nxgep->param_arr[i].old_value, free_size); 834 #else 835 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 836 free_size); 837 #endif 838 } 839 840 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 841 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 842 } 843 844 /* 845 * Extracts the value from the 'nxge' parameter array and prints the 846 * parameter value. cp points to the required parameter. 847 */ 848 849 /* ARGSUSED */ 850 int 851 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 852 { 853 p_nxge_param_t pa = (p_nxge_param_t)cp; 854 855 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 856 "==> nxge_param_get_generic name %s ", pa->name)); 857 858 if (pa->value > 0xffffffff) 859 (void) mi_mpprintf(mp, "%x%x", 860 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 861 else 862 (void) mi_mpprintf(mp, "%x", (int)pa->value); 863 864 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 865 return (0); 866 } 867 868 /* ARGSUSED */ 869 static int 870 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 871 { 872 p_nxge_param_t pa = (p_nxge_param_t)cp; 873 874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 875 876 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 877 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 878 return (0); 879 } 880 881 /* ARGSUSED */ 882 static int 883 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 884 { 885 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 886 887 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 888 nxgep->instance, nxgep->vpd_info.ver); 889 890 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 891 return (0); 892 } 893 894 /* ARGSUSED */ 895 static int 896 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 897 { 898 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 899 900 switch (nxgep->mac.portmode) { 901 case PORT_1G_COPPER: 902 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 903 nxgep->instance, 904 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 905 break; 906 case PORT_1G_FIBER: 907 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 908 nxgep->instance, 909 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 910 break; 911 case PORT_10G_COPPER: 912 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 913 "%s\n", nxgep->instance, 914 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 915 break; 916 case PORT_10G_FIBER: 917 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 918 nxgep->instance, 919 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 920 break; 921 case PORT_10G_SERDES: 922 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 923 "%s\n", nxgep->instance, 924 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 925 break; 926 case PORT_1G_SERDES: 927 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 928 nxgep->instance, 929 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 930 break; 931 case PORT_1G_RGMII_FIBER: 932 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 933 "Fiber %s\n", nxgep->instance, 934 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 935 break; 936 case PORT_HSP_MODE: 937 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 938 "PHY, Currently NOT present\n", nxgep->instance); 939 break; 940 default: 941 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 942 nxgep->instance, 943 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 944 break; 945 } 946 947 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 948 return (0); 949 } 950 951 /* ARGSUSED */ 952 int 953 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 954 { 955 956 uint_t print_len, buf_len; 957 p_mblk_t np; 958 int tdc; 959 960 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 961 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 962 963 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 964 nxgep->function_num); 965 966 967 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 968 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 969 return (0); 970 } 971 972 buf_len = buff_alloc_size; 973 mp->b_cont = np; 974 975 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 976 "Total TDCs\t %d\n", nxgep->ntdc); 977 978 ((mblk_t *)np)->b_wptr += print_len; 979 buf_len -= print_len; 980 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 981 "TDC\t HW TDC\t\n"); 982 ((mblk_t *)np)->b_wptr += print_len; 983 984 buf_len -= print_len; 985 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 986 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 987 buf_len, "%d\t %d\n", 988 tdc, nxgep->tdc[tdc]); 989 ((mblk_t *)np)->b_wptr += print_len; 990 buf_len -= print_len; 991 } 992 993 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 994 return (0); 995 } 996 997 /* ARGSUSED */ 998 int 999 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1000 { 1001 uint_t print_len, buf_len; 1002 p_mblk_t np; 1003 int rdc; 1004 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1005 p_nxge_hw_pt_cfg_t p_cfgp; 1006 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1007 p_rx_rcr_rings_t rx_rcr_rings; 1008 p_rx_rcr_ring_t *rcr_rings; 1009 p_rx_rbr_rings_t rx_rbr_rings; 1010 p_rx_rbr_ring_t *rbr_rings; 1011 1012 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1013 1014 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1015 nxgep->function_num); 1016 1017 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1018 /* The following may work even if we cannot get a large buf. */ 1019 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1020 return (0); 1021 } 1022 1023 buf_len = buff_alloc_size; 1024 mp->b_cont = np; 1025 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1026 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1027 1028 rx_rcr_rings = nxgep->rx_rcr_rings; 1029 rcr_rings = rx_rcr_rings->rcr_rings; 1030 rx_rbr_rings = nxgep->rx_rbr_rings; 1031 rbr_rings = rx_rbr_rings->rbr_rings; 1032 1033 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1034 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1035 1036 ((mblk_t *)np)->b_wptr += print_len; 1037 buf_len -= print_len; 1038 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1039 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1040 "chunks\t RCR ptr\n"); 1041 1042 ((mblk_t *)np)->b_wptr += print_len; 1043 buf_len -= print_len; 1044 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 1045 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1046 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1047 rdc, nxgep->rdc[rdc], 1048 p_dma_cfgp->rcr_timeout[rdc], 1049 p_dma_cfgp->rcr_threshold[rdc], 1050 rbr_rings[rdc], 1051 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1052 ((mblk_t *)np)->b_wptr += print_len; 1053 buf_len -= print_len; 1054 } 1055 1056 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1057 return (0); 1058 } 1059 1060 /* ARGSUSED */ 1061 int 1062 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1063 p_mblk_t mp, caddr_t cp) 1064 { 1065 uint_t print_len, buf_len; 1066 p_mblk_t np; 1067 int offset, rdc, i, rdc_grp; 1068 p_nxge_rdc_grp_t rdc_grp_p; 1069 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1070 p_nxge_hw_pt_cfg_t p_cfgp; 1071 1072 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1073 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1074 "==> nxge_param_get_rxdma_rdcgrp_info")); 1075 1076 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1077 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1078 1079 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1080 nxgep->function_num); 1081 1082 rdc_grp = p_cfgp->start_rdc_grpid; 1083 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1084 /* The following may work even if we cannot get a large buf. */ 1085 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1086 return (0); 1087 } 1088 1089 buf_len = buff_alloc_size; 1090 mp->b_cont = np; 1091 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1092 "Total RDC Groups\t %d \n" 1093 "start RDC group\t %d\n", 1094 p_cfgp->max_rdc_grpids, 1095 p_cfgp->start_rdc_grpid); 1096 1097 ((mblk_t *)np)->b_wptr += print_len; 1098 buf_len -= print_len; 1099 1100 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 1101 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 1102 rdc_grp++, i++) { 1103 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1104 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1105 "\nRDC Group Info for Group [%d] %d\n" 1106 "RDC Count %d\tstart RDC %d\n" 1107 "RDC Group Population Information" 1108 " (offsets 0 - 15)\n", 1109 i, rdc_grp, rdc_grp_p->max_rdcs, 1110 rdc_grp_p->start_rdc); 1111 1112 ((mblk_t *)np)->b_wptr += print_len; 1113 buf_len -= print_len; 1114 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1115 buf_len, "\n"); 1116 ((mblk_t *)np)->b_wptr += print_len; 1117 buf_len -= print_len; 1118 1119 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1120 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1121 buf_len, "[%d]=%d ", rdc, 1122 rdc_grp_p->start_rdc + rdc); 1123 ((mblk_t *)np)->b_wptr += print_len; 1124 buf_len -= print_len; 1125 } 1126 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1127 buf_len, "\n"); 1128 ((mblk_t *)np)->b_wptr += print_len; 1129 buf_len -= print_len; 1130 1131 for (offset = 0; offset < 16; offset++) { 1132 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1133 buf_len, " %2d ", 1134 rdc_grp_p->rdc[offset]); 1135 ((mblk_t *)np)->b_wptr += print_len; 1136 buf_len -= print_len; 1137 } 1138 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1139 buf_len, "\n"); 1140 ((mblk_t *)np)->b_wptr += print_len; 1141 buf_len -= print_len; 1142 } 1143 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1144 "<== nxge_param_get_rxdma_rdcgrp_info")); 1145 return (0); 1146 } 1147 1148 int 1149 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1150 { 1151 p_mblk_t tmp; 1152 1153 tmp = mp; 1154 while (tmp->b_cont) 1155 tmp = tmp->b_cont; 1156 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1157 tmp->b_cont = allocb(1024, BPRI_HI); 1158 tmp = tmp->b_cont; 1159 if (!tmp) 1160 return (ENOMEM); 1161 } 1162 1163 *nmp = tmp; 1164 return (0); 1165 } 1166 1167 /* 1168 * Sets the ge parameter to the value in the nxge_param_register using 1169 * nxge_nd_load(). 1170 */ 1171 1172 /* ARGSUSED */ 1173 int 1174 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1175 char *value, caddr_t cp) 1176 { 1177 char *end; 1178 uint32_t new_value; 1179 p_nxge_param_t pa = (p_nxge_param_t)cp; 1180 1181 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1182 new_value = (uint32_t)mi_strtol(value, &end, 10); 1183 if (end == value || new_value < pa->minimum || 1184 new_value > pa->maximum) { 1185 return (EINVAL); 1186 } 1187 pa->value = new_value; 1188 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1189 return (0); 1190 } 1191 1192 /* 1193 * Sets the ge parameter to the value in the nxge_param_register using 1194 * nxge_nd_load(). 1195 */ 1196 1197 /* ARGSUSED */ 1198 int 1199 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1200 char *value, caddr_t cp) 1201 { 1202 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1203 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1204 return (0); 1205 } 1206 1207 /* 1208 * Sets the ge parameter to the value in the nxge_param_register using 1209 * nxge_nd_load(). 1210 */ 1211 1212 /* ARGSUSED */ 1213 int 1214 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1215 char *value, caddr_t cp) 1216 { 1217 char *end; 1218 uint32_t new_value; 1219 int status = 0; 1220 p_nxge_param_t pa = (p_nxge_param_t)cp; 1221 1222 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1223 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1224 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1225 return (EINVAL); 1226 } 1227 1228 if (pa->value != new_value) { 1229 pa->old_value = pa->value; 1230 pa->value = new_value; 1231 } 1232 1233 if (!nxge_param_link_update(nxgep)) { 1234 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1235 " false ret from nxge_param_link_update")); 1236 status = EINVAL; 1237 } 1238 1239 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1240 return (status); 1241 } 1242 1243 /* ARGSUSED */ 1244 static int 1245 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1246 char *value, caddr_t cp) 1247 { 1248 char *end; 1249 uint32_t cfg_value; 1250 p_nxge_param_t pa = (p_nxge_param_t)cp; 1251 1252 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1253 1254 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1255 1256 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1257 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1258 return (EINVAL); 1259 } 1260 1261 if ((pa->value != cfg_value)) { 1262 pa->old_value = pa->value; 1263 pa->value = cfg_value; 1264 nxgep->intr_threshold = pa->value; 1265 } 1266 1267 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1268 return (0); 1269 } 1270 1271 /* ARGSUSED */ 1272 static int 1273 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1274 char *value, caddr_t cp) 1275 { 1276 char *end; 1277 uint32_t cfg_value; 1278 p_nxge_param_t pa = (p_nxge_param_t)cp; 1279 1280 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1281 1282 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1283 1284 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1285 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1286 return (EINVAL); 1287 } 1288 1289 if ((pa->value != cfg_value)) { 1290 pa->old_value = pa->value; 1291 pa->value = cfg_value; 1292 nxgep->intr_timeout = pa->value; 1293 } 1294 1295 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1296 return (0); 1297 } 1298 1299 /* ARGSUSED */ 1300 static int 1301 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1302 mblk_t *mp, char *value, caddr_t cp) 1303 { 1304 char *end; 1305 uint32_t status = 0, cfg_value; 1306 p_nxge_param_t pa = (p_nxge_param_t)cp; 1307 uint32_t cfg_it = B_FALSE; 1308 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1309 p_nxge_hw_pt_cfg_t p_cfgp; 1310 uint32_t *val_ptr, *old_val_ptr; 1311 nxge_param_map_t *mac_map; 1312 p_nxge_class_pt_cfg_t p_class_cfgp; 1313 nxge_mv_cfg_t *mac_host_info; 1314 1315 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1316 1317 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1318 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1319 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1320 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1321 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1322 1323 /* 1324 * now do decoding 1325 */ 1326 mac_map = (nxge_param_map_t *)&cfg_value; 1327 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1328 cfg_value, mac_map->param_id, mac_map->map_to)); 1329 1330 if ((mac_map->param_id < p_cfgp->max_macs) && 1331 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1332 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1333 p_cfgp->start_rdc_grpid)) { 1334 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1335 " nxge_param_set_mac_rdcgrp mapping" 1336 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1337 #if defined(__i386) 1338 val_ptr = (uint32_t *)(uint32_t)pa->value; 1339 #else 1340 val_ptr = (uint32_t *)pa->value; 1341 #endif 1342 #if defined(__i386) 1343 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1344 #else 1345 old_val_ptr = (uint32_t *)pa->old_value; 1346 #endif 1347 if (val_ptr[mac_map->param_id] != cfg_value) { 1348 old_val_ptr[mac_map->param_id] = 1349 val_ptr[mac_map->param_id]; 1350 val_ptr[mac_map->param_id] = cfg_value; 1351 mac_host_info[mac_map->param_id].mpr_npr = 1352 mac_map->pref; 1353 mac_host_info[mac_map->param_id].flag = 1; 1354 mac_host_info[mac_map->param_id].rdctbl = 1355 mac_map->map_to; 1356 cfg_it = B_TRUE; 1357 } 1358 } else { 1359 return (EINVAL); 1360 } 1361 1362 if (cfg_it == B_TRUE) { 1363 status = nxge_logical_mac_assign_rdc_table(nxgep, 1364 (uint8_t)mac_map->param_id); 1365 if (status != NXGE_OK) 1366 return (EINVAL); 1367 } 1368 1369 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1370 return (0); 1371 } 1372 1373 /* ARGSUSED */ 1374 static int 1375 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1376 mblk_t *mp, char *value, caddr_t cp) 1377 { 1378 char *end; 1379 uint32_t status = 0, cfg_value; 1380 p_nxge_param_t pa = (p_nxge_param_t)cp; 1381 uint32_t cfg_it = B_FALSE; 1382 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1383 p_nxge_hw_pt_cfg_t p_cfgp; 1384 uint32_t *val_ptr, *old_val_ptr; 1385 nxge_param_map_t *vmap, *old_map; 1386 p_nxge_class_pt_cfg_t p_class_cfgp; 1387 uint64_t cfgd_vlans; 1388 int i, inc = 0, cfg_position; 1389 nxge_mv_cfg_t *vlan_tbl; 1390 1391 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1392 1393 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1394 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1395 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1396 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1397 1398 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1399 1400 /* now do decoding */ 1401 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1402 NXGE_PARAM_ARRAY_CNT_SHIFT); 1403 1404 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1405 /* 1406 * for now, we process only upto max 1407 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1408 * In the future, we may want to expand 1409 * the storage array and continue 1410 */ 1411 return (EINVAL); 1412 } 1413 1414 vmap = (nxge_param_map_t *)&cfg_value; 1415 if ((vmap->param_id) && 1416 (vmap->param_id < NXGE_MAX_VLANS) && 1417 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1418 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1419 "nxge_param_set_vlan_rdcgrp mapping" 1420 " id %d grp %d", 1421 vmap->param_id, vmap->map_to)); 1422 #if defined(__i386) 1423 val_ptr = (uint32_t *)(uint32_t)pa->value; 1424 #else 1425 val_ptr = (uint32_t *)pa->value; 1426 #endif 1427 #if defined(__i386) 1428 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1429 #else 1430 old_val_ptr = (uint32_t *)pa->old_value; 1431 #endif 1432 1433 /* search to see if this vlan id is already configured */ 1434 for (i = 0; i < cfgd_vlans; i++) { 1435 old_map = (nxge_param_map_t *)&val_ptr[i]; 1436 if ((old_map->param_id == 0) || 1437 (vmap->param_id == old_map->param_id) || 1438 (vlan_tbl[vmap->param_id].flag)) { 1439 cfg_position = i; 1440 break; 1441 } 1442 } 1443 1444 if (cfgd_vlans == 0) { 1445 cfg_position = 0; 1446 inc++; 1447 } 1448 1449 if (i == cfgd_vlans) { 1450 cfg_position = i; 1451 inc++; 1452 } 1453 1454 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1455 "set_vlan_rdcgrp mapping" 1456 " i %d cfgd_vlans %llx position %d ", 1457 i, cfgd_vlans, cfg_position)); 1458 if (val_ptr[cfg_position] != cfg_value) { 1459 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1460 val_ptr[cfg_position] = cfg_value; 1461 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1462 vlan_tbl[vmap->param_id].flag = 1; 1463 vlan_tbl[vmap->param_id].rdctbl = 1464 vmap->map_to + p_cfgp->start_rdc_grpid; 1465 cfg_it = B_TRUE; 1466 if (inc) { 1467 cfgd_vlans++; 1468 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1469 pa->type |= (cfgd_vlans << 1470 NXGE_PARAM_ARRAY_CNT_SHIFT); 1471 1472 } 1473 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1474 "after: param_set_vlan_rdcgrp " 1475 " cfg_vlans %llx position %d \n", 1476 cfgd_vlans, cfg_position)); 1477 } 1478 } else { 1479 return (EINVAL); 1480 } 1481 1482 if (cfg_it == B_TRUE) { 1483 status = nxge_fflp_config_vlan_table(nxgep, 1484 (uint16_t)vmap->param_id); 1485 if (status != NXGE_OK) 1486 return (EINVAL); 1487 } 1488 1489 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1490 return (0); 1491 } 1492 1493 /* ARGSUSED */ 1494 static int 1495 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1496 mblk_t *mp, caddr_t cp) 1497 { 1498 1499 uint_t print_len, buf_len; 1500 p_mblk_t np; 1501 int i; 1502 uint32_t *val_ptr; 1503 nxge_param_map_t *vmap; 1504 p_nxge_param_t pa = (p_nxge_param_t)cp; 1505 p_nxge_class_pt_cfg_t p_class_cfgp; 1506 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1507 p_nxge_hw_pt_cfg_t p_cfgp; 1508 uint64_t cfgd_vlans = 0; 1509 nxge_mv_cfg_t *vlan_tbl; 1510 int buff_alloc_size = 1511 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1512 1513 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1514 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1515 nxgep->function_num); 1516 1517 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1518 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1519 return (0); 1520 } 1521 1522 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1523 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1524 1525 buf_len = buff_alloc_size; 1526 mp->b_cont = np; 1527 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1528 NXGE_PARAM_ARRAY_CNT_SHIFT; 1529 1530 i = (int)cfgd_vlans; 1531 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1532 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1533 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1534 "Configured VLANs %d\n" 1535 "VLAN ID\t RDC GRP (Actual/Port)\t" 1536 " Prefernce\n", i); 1537 ((mblk_t *)np)->b_wptr += print_len; 1538 buf_len -= print_len; 1539 #if defined(__i386) 1540 val_ptr = (uint32_t *)(uint32_t)pa->value; 1541 #else 1542 val_ptr = (uint32_t *)pa->value; 1543 #endif 1544 1545 for (i = 0; i < cfgd_vlans; i++) { 1546 vmap = (nxge_param_map_t *)&val_ptr[i]; 1547 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1548 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1549 buf_len, 1550 " %d\t\t %d/%d\t\t %d\n", 1551 vmap->param_id, 1552 vlan_tbl[vmap->param_id].rdctbl, 1553 vlan_tbl[vmap->param_id].rdctbl - 1554 p_cfgp->start_rdc_grpid, 1555 vlan_tbl[vmap->param_id].mpr_npr); 1556 ((mblk_t *)np)->b_wptr += print_len; 1557 buf_len -= print_len; 1558 } 1559 } 1560 1561 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1562 return (0); 1563 } 1564 1565 /* ARGSUSED */ 1566 static int 1567 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1568 mblk_t *mp, caddr_t cp) 1569 { 1570 uint_t print_len, buf_len; 1571 p_mblk_t np; 1572 int i; 1573 p_nxge_class_pt_cfg_t p_class_cfgp; 1574 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1575 p_nxge_hw_pt_cfg_t p_cfgp; 1576 nxge_mv_cfg_t *mac_host_info; 1577 1578 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1579 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1580 (void) mi_mpprintf(mp, 1581 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1582 nxgep->function_num); 1583 1584 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1585 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1586 return (0); 1587 } 1588 1589 buf_len = buff_alloc_size; 1590 mp->b_cont = np; 1591 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1592 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1593 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1594 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1595 print_len = snprintf((char *)np->b_wptr, buf_len, 1596 "MAC ID\t RDC GRP (Actual/Port)\t" 1597 " Prefernce\n"); 1598 ((mblk_t *)np)->b_wptr += print_len; 1599 buf_len -= print_len; 1600 for (i = 0; i < p_cfgp->max_macs; i++) { 1601 if (mac_host_info[i].flag) { 1602 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1603 buf_len, 1604 " %d\t %d/%d\t\t %d\n", 1605 i, mac_host_info[i].rdctbl, 1606 mac_host_info[i].rdctbl - 1607 p_cfgp->start_rdc_grpid, 1608 mac_host_info[i].mpr_npr); 1609 ((mblk_t *)np)->b_wptr += print_len; 1610 buf_len -= print_len; 1611 } 1612 } 1613 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1614 "Done Info Dumping \n"); 1615 ((mblk_t *)np)->b_wptr += print_len; 1616 buf_len -= print_len; 1617 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1618 return (0); 1619 } 1620 1621 /* ARGSUSED */ 1622 static int 1623 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1624 mblk_t *mp, char *value, caddr_t cp) 1625 { 1626 uint32_t status = 0, cfg_value; 1627 p_nxge_param_t pa = (p_nxge_param_t)cp; 1628 uint32_t cfg_it = B_FALSE; 1629 char *end; 1630 1631 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1632 1633 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1634 if (pa->value != cfg_value) { 1635 pa->old_value = pa->value; 1636 pa->value = cfg_value; 1637 cfg_it = B_TRUE; 1638 } 1639 1640 if (cfg_it == B_TRUE) { 1641 if (pa->value) 1642 status = nxge_fflp_config_tcam_enable(nxgep); 1643 else 1644 status = nxge_fflp_config_tcam_disable(nxgep); 1645 if (status != NXGE_OK) 1646 return (EINVAL); 1647 } 1648 1649 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1650 return (0); 1651 } 1652 1653 /* ARGSUSED */ 1654 static int 1655 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1656 mblk_t *mp, char *value, caddr_t cp) 1657 { 1658 uint32_t status = 0, cfg_value; 1659 p_nxge_param_t pa = (p_nxge_param_t)cp; 1660 uint32_t cfg_it = B_FALSE; 1661 char *end; 1662 1663 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1664 1665 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1666 if (pa->value != cfg_value) { 1667 pa->old_value = pa->value; 1668 pa->value = cfg_value; 1669 cfg_it = B_TRUE; 1670 } 1671 1672 if (cfg_it == B_TRUE) { 1673 if (pa->value) 1674 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1675 else 1676 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1677 if (status != NXGE_OK) 1678 return (EINVAL); 1679 } 1680 1681 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1682 return (0); 1683 } 1684 1685 /* ARGSUSED */ 1686 static int 1687 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1688 mblk_t *mp, char *value, caddr_t cp) 1689 { 1690 char *end; 1691 uint32_t status = 0, cfg_value; 1692 p_nxge_param_t pa = (p_nxge_param_t)cp; 1693 uint32_t cfg_it = B_FALSE; 1694 1695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1696 1697 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1698 if (pa->value != cfg_value) { 1699 pa->old_value = pa->value; 1700 pa->value = cfg_value; 1701 cfg_it = B_TRUE; 1702 } 1703 1704 if (cfg_it == B_TRUE) { 1705 if (pa->value) 1706 status = nxge_fflp_config_tcam_enable(nxgep); 1707 else 1708 status = nxge_fflp_config_tcam_disable(nxgep); 1709 if (status != NXGE_OK) 1710 return (EINVAL); 1711 } 1712 1713 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1714 return (0); 1715 } 1716 1717 /* ARGSUSED */ 1718 static int 1719 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1720 mblk_t *mp, char *value, caddr_t cp) 1721 { 1722 char *end; 1723 uint8_t ether_class; 1724 uint32_t status = 0, cfg_value; 1725 p_nxge_param_t pa = (p_nxge_param_t)cp; 1726 uint8_t cfg_it = B_FALSE; 1727 1728 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1729 1730 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1731 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1732 return (EINVAL); 1733 } 1734 1735 if (pa->value != cfg_value) { 1736 pa->old_value = pa->value; 1737 pa->value = cfg_value; 1738 cfg_it = B_TRUE; 1739 } 1740 1741 /* do the actual hw setup */ 1742 if (cfg_it == B_TRUE) { 1743 ether_class = mi_strtol(pa->name, &end, 10); 1744 #ifdef lint 1745 ether_class = ether_class; 1746 #endif 1747 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1748 } 1749 1750 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1751 return (status); 1752 } 1753 1754 /* ARGSUSED */ 1755 static int 1756 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1757 mblk_t *mp, char *value, caddr_t cp) 1758 { 1759 char *end; 1760 tcam_class_t class; 1761 uint32_t status, cfg_value; 1762 p_nxge_param_t pa = (p_nxge_param_t)cp; 1763 uint32_t cfg_it = B_FALSE; 1764 1765 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1766 1767 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1768 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1769 return (EINVAL); 1770 } 1771 1772 if (pa->value != cfg_value) { 1773 pa->old_value = pa->value; 1774 pa->value = cfg_value; 1775 cfg_it = B_TRUE; 1776 } 1777 1778 /* do the actual hw setup with cfg_value. */ 1779 if (cfg_it == B_TRUE) { 1780 class = mi_strtol(pa->name, &end, 10); 1781 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1782 } 1783 1784 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1785 return (status); 1786 } 1787 1788 /* ARGSUSED */ 1789 static int 1790 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1791 { 1792 int i; 1793 int class_instance = param_class_opt_ip_usr4; 1794 p_nxge_param_t param_arr; 1795 1796 param_arr = nxgep->param_arr; 1797 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1798 if (strcmp(param_arr[class_instance].name, name) == 0) 1799 return (i); 1800 class_instance++; 1801 } 1802 return (-1); 1803 } 1804 1805 /* ARGSUSED */ 1806 static int 1807 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1808 mblk_t *mp, char *value, caddr_t cp) 1809 { 1810 char *end; 1811 uint32_t status, cfg_value; 1812 p_nxge_param_t pa = (p_nxge_param_t)cp; 1813 tcam_class_t class; 1814 uint32_t cfg_it = B_FALSE; 1815 1816 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1817 1818 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1819 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1820 return (EINVAL); 1821 } 1822 1823 if (pa->value != cfg_value) { 1824 pa->old_value = pa->value; 1825 pa->value = cfg_value; 1826 cfg_it = B_TRUE; 1827 } 1828 1829 if (cfg_it == B_TRUE) { 1830 /* do the actual hw setup */ 1831 class = nxge_class_name_2value(nxgep, pa->name); 1832 if (class == -1) 1833 return (EINVAL); 1834 1835 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1836 if (status != NXGE_OK) 1837 return (EINVAL); 1838 } 1839 1840 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1841 return (0); 1842 } 1843 1844 /* ARGSUSED */ 1845 static int 1846 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1847 mblk_t *mp, caddr_t cp) 1848 { 1849 uint32_t status, cfg_value; 1850 p_nxge_param_t pa = (p_nxge_param_t)cp; 1851 tcam_class_t class; 1852 1853 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1854 1855 /* do the actual hw setup */ 1856 class = nxge_class_name_2value(nxgep, pa->name); 1857 if (class == -1) 1858 return (EINVAL); 1859 1860 cfg_value = 0; 1861 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1862 if (status != NXGE_OK) 1863 return (EINVAL); 1864 1865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1866 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1867 1868 pa->value = cfg_value; 1869 (void) mi_mpprintf(mp, "%x", cfg_value); 1870 1871 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1872 return (0); 1873 } 1874 1875 /* ARGSUSED */ 1876 static int 1877 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1878 mblk_t *mp, char *value, caddr_t cp) 1879 { 1880 char *end; 1881 uint32_t status, cfg_value; 1882 p_nxge_param_t pa = (p_nxge_param_t)cp; 1883 tcam_class_t class; 1884 uint32_t cfg_it = B_FALSE; 1885 1886 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1887 1888 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1889 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1890 return (EINVAL); 1891 } 1892 1893 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1894 "nxge_param_fflp_hash_init value %x", cfg_value)); 1895 1896 if (pa->value != cfg_value) { 1897 pa->old_value = pa->value; 1898 pa->value = cfg_value; 1899 cfg_it = B_TRUE; 1900 } 1901 1902 if (cfg_it == B_TRUE) { 1903 char *h_name; 1904 1905 /* do the actual hw setup */ 1906 h_name = pa->name; 1907 h_name++; 1908 class = mi_strtol(h_name, &end, 10); 1909 switch (class) { 1910 case 1: 1911 status = nxge_fflp_set_hash1(nxgep, 1912 (uint32_t)pa->value); 1913 break; 1914 case 2: 1915 status = nxge_fflp_set_hash2(nxgep, 1916 (uint16_t)pa->value); 1917 break; 1918 1919 default: 1920 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1921 " nxge_param_fflp_hash_init" 1922 " %s Wrong hash var %d", 1923 pa->name, class)); 1924 return (EINVAL); 1925 } 1926 if (status != NXGE_OK) 1927 return (EINVAL); 1928 } 1929 1930 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1931 return (0); 1932 } 1933 1934 /* ARGSUSED */ 1935 static int 1936 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1937 mblk_t *mp, char *value, caddr_t cp) 1938 { 1939 char *end; 1940 uint32_t status = 0, cfg_value; 1941 p_nxge_param_t pa = (p_nxge_param_t)cp; 1942 uint32_t cfg_it = B_FALSE; 1943 int rdc_grp; 1944 uint8_t real_rdc; 1945 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1946 p_nxge_hw_pt_cfg_t p_cfgp; 1947 p_nxge_rdc_grp_t rdc_grp_p; 1948 1949 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1950 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1951 1952 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1953 1954 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1955 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1956 return (EINVAL); 1957 } 1958 1959 if (cfg_value >= p_cfgp->max_rdcs) { 1960 return (EINVAL); 1961 } 1962 1963 if (pa->value != cfg_value) { 1964 pa->old_value = pa->value; 1965 pa->value = cfg_value; 1966 cfg_it = B_TRUE; 1967 } 1968 1969 if (cfg_it == B_TRUE) { 1970 char *grp_name; 1971 grp_name = pa->name; 1972 grp_name += strlen("default-grp"); 1973 rdc_grp = mi_strtol(grp_name, &end, 10); 1974 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1975 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1976 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1977 cfg_value) == B_FALSE) { 1978 pa->value = pa->old_value; 1979 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1980 " nxge_param_set_grp_rdc" 1981 " %d read %d actual %d outof range", 1982 rdc_grp, cfg_value, real_rdc)); 1983 return (EINVAL); 1984 } 1985 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1986 real_rdc); 1987 if (status != NXGE_OK) 1988 return (EINVAL); 1989 } 1990 1991 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1992 return (0); 1993 } 1994 1995 /* ARGSUSED */ 1996 static int 1997 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1998 mblk_t *mp, char *value, caddr_t cp) 1999 { 2000 char *end; 2001 uint32_t status = B_TRUE, cfg_value; 2002 p_nxge_param_t pa = (p_nxge_param_t)cp; 2003 uint32_t cfg_it = B_FALSE; 2004 2005 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2006 p_nxge_hw_pt_cfg_t p_cfgp; 2007 2008 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2009 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2010 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2011 2012 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2013 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2014 return (EINVAL); 2015 } 2016 2017 if (pa->value != cfg_value) { 2018 if (cfg_value >= p_cfgp->max_rdcs) 2019 return (EINVAL); 2020 pa->old_value = pa->value; 2021 pa->value = cfg_value; 2022 cfg_it = B_TRUE; 2023 } 2024 2025 if (cfg_it == B_TRUE) { 2026 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2027 nxgep->function_num, 2028 nxgep->rdc[cfg_value]); 2029 if (status != NXGE_OK) 2030 return (EINVAL); 2031 } 2032 2033 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2034 return (0); 2035 } 2036 2037 /* ARGSUSED */ 2038 static int 2039 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2040 mblk_t *mp, char *value, caddr_t cp) 2041 { 2042 char *end; 2043 uint32_t status = 0; 2044 uint64_t cfg_value = 0; 2045 p_nxge_param_t pa = (p_nxge_param_t)cp; 2046 uint32_t cfg_it = B_FALSE; 2047 2048 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2049 cfg_value = mi_strtol(value, &end, BASE_HEX); 2050 2051 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2052 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2053 " nxge_param_set_nxge_debug_flag" 2054 " outof range %llx", cfg_value)); 2055 return (EINVAL); 2056 } 2057 if (pa->value != cfg_value) { 2058 pa->old_value = pa->value; 2059 pa->value = cfg_value; 2060 cfg_it = B_TRUE; 2061 } 2062 2063 if (cfg_it == B_TRUE) { 2064 nxgep->nxge_debug_level = pa->value; 2065 } 2066 2067 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2068 return (status); 2069 } 2070 2071 /* ARGSUSED */ 2072 static int 2073 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2074 { 2075 int status = 0; 2076 p_nxge_param_t pa = (p_nxge_param_t)cp; 2077 2078 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2079 2080 if (pa->value > 0xffffffff) 2081 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2082 (int)(pa->value & 0xffffffff)); 2083 else 2084 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2085 2086 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2087 return (status); 2088 } 2089 2090 /* ARGSUSED */ 2091 static int 2092 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2093 mblk_t *mp, char *value, caddr_t cp) 2094 { 2095 char *end; 2096 uint32_t status = 0; 2097 uint64_t cfg_value = 0; 2098 p_nxge_param_t pa; 2099 uint32_t cfg_it = B_FALSE; 2100 2101 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2102 cfg_value = mi_strtol(value, &end, BASE_HEX); 2103 pa = (p_nxge_param_t)cp; 2104 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2105 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2106 " outof range %llx", cfg_value)); 2107 return (EINVAL); 2108 } 2109 if (pa->value != cfg_value) { 2110 pa->old_value = pa->value; 2111 pa->value = cfg_value; 2112 cfg_it = B_TRUE; 2113 } 2114 2115 if (cfg_it == B_TRUE) { 2116 npi_debug_level = pa->value; 2117 } 2118 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2119 return (status); 2120 } 2121 2122 /* ARGSUSED */ 2123 static int 2124 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2125 { 2126 uint_t rdc; 2127 2128 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2129 2130 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2131 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 2132 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 2133 2134 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2135 return (0); 2136 } 2137 2138 /* ARGSUSED */ 2139 static int 2140 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2141 { 2142 uint_t tdc; 2143 2144 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2145 2146 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2147 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2148 2149 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2150 return (0); 2151 } 2152 2153 /* ARGSUSED */ 2154 static int 2155 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2156 { 2157 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2158 2159 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2160 2161 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2162 return (0); 2163 } 2164 2165 /* ARGSUSED */ 2166 static int 2167 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2168 { 2169 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2170 2171 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2172 nxgep->function_num); 2173 2174 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2175 return (0); 2176 } 2177 2178 /* ARGSUSED */ 2179 static int 2180 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2181 { 2182 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2183 2184 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2185 nxgep->function_num); 2186 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2187 return (0); 2188 } 2189 2190 /* ARGSUSED */ 2191 static int 2192 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2193 { 2194 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2195 2196 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2197 2198 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2199 return (0); 2200 } 2201 2202 /* ARGSUSED */ 2203 static int 2204 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2205 { 2206 uint8_t table; 2207 2208 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2209 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2210 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2211 table); 2212 } 2213 2214 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2215 return (0); 2216 } 2217 2218 typedef struct block_info { 2219 char *name; 2220 uint32_t offset; 2221 } block_info_t; 2222 2223 block_info_t reg_block[] = { 2224 {"PIO", PIO}, 2225 {"FZC_PIO", FZC_PIO}, 2226 {"FZC_XMAC", FZC_MAC}, 2227 {"FZC_IPP", FZC_IPP}, 2228 {"FFLP", FFLP}, 2229 {"FZC_FFLP", FZC_FFLP}, 2230 {"PIO_VADDR", PIO_VADDR}, 2231 {"ZCP", ZCP}, 2232 {"FZC_ZCP", FZC_ZCP}, 2233 {"DMC", DMC}, 2234 {"FZC_DMC", FZC_DMC}, 2235 {"TXC", TXC}, 2236 {"FZC_TXC", FZC_TXC}, 2237 {"PIO_LDSV", PIO_LDSV}, 2238 {"PIO_LDGIM", PIO_LDGIM}, 2239 {"PIO_IMASK0", PIO_IMASK0}, 2240 {"PIO_IMASK1", PIO_IMASK1}, 2241 {"FZC_PROM", FZC_PROM}, 2242 {"END", ALL_FF_32}, 2243 }; 2244 2245 /* ARGSUSED */ 2246 static int 2247 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2248 { 2249 uint_t print_len, buf_len; 2250 p_mblk_t np; 2251 int rdc, tdc, block; 2252 uint64_t base; 2253 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2254 p_nxge_hw_pt_cfg_t p_cfgp; 2255 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2256 p_tx_ring_t *tx_rings; 2257 p_rx_rcr_rings_t rx_rcr_rings; 2258 p_rx_rcr_ring_t *rcr_rings; 2259 p_rx_rbr_rings_t rx_rbr_rings; 2260 p_rx_rbr_ring_t *rbr_rings; 2261 2262 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2263 "==> nxge_param_dump_ptrs")); 2264 2265 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2266 nxgep->function_num); 2267 2268 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2269 /* The following may work even if we cannot get a large buf. */ 2270 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2271 return (0); 2272 } 2273 2274 buf_len = buff_alloc_size; 2275 mp->b_cont = np; 2276 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2277 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2278 2279 rx_rcr_rings = nxgep->rx_rcr_rings; 2280 rcr_rings = rx_rcr_rings->rcr_rings; 2281 rx_rbr_rings = nxgep->rx_rbr_rings; 2282 rbr_rings = rx_rbr_rings->rbr_rings; 2283 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2284 "nxgep (nxge_t) $%p\n" 2285 "dev_regs (dev_regs_t) $%p\n", 2286 nxgep, nxgep->dev_regs); 2287 2288 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2289 2290 /* do register pointers */ 2291 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2292 "reg base (npi_reg_ptr_t) $%p\t " 2293 "pci reg (npi_reg_ptr_t) $%p\n", 2294 nxgep->dev_regs->nxge_regp, 2295 nxgep->dev_regs->nxge_pciregp); 2296 2297 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2298 2299 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2300 "\nBlock \t Offset \n"); 2301 2302 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2303 block = 0; 2304 #if defined(__i386) 2305 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2306 #else 2307 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2308 #endif 2309 while (reg_block[block].offset != ALL_FF_32) { 2310 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2311 "%9s\t 0x%llx\n", 2312 reg_block[block].name, 2313 (unsigned long long)(reg_block[block].offset + base)); 2314 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2315 block++; 2316 } 2317 2318 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2319 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2320 "rbrp (rx_rbr_ring_t)\n"); 2321 2322 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2323 2324 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2325 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2326 " %d\t $%p\t\t $%p\n", 2327 rdc, rcr_rings[rdc], 2328 rbr_rings[rdc]); 2329 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2330 } 2331 2332 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2333 "\nTDC\t tdcp (tx_ring_t)\n"); 2334 2335 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2336 tx_rings = nxgep->tx_rings->rings; 2337 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2338 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2339 " %d\t $%p\n", tdc, tx_rings[tdc]); 2340 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2341 } 2342 2343 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2344 2345 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2346 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2347 return (0); 2348 } 2349 2350 /* 2351 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2352 * 'ndp' should be the address of a char pointer cell. If the table 2353 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2354 * is stuffed. If there is not enough space in the table for a new 2355 * entry, more space is allocated. 2356 */ 2357 /* ARGSUSED */ 2358 boolean_t 2359 nxge_nd_load(caddr_t *pparam, char *name, 2360 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2361 { 2362 ND *nd; 2363 NDE *nde; 2364 2365 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2366 if (!pparam) 2367 return (B_FALSE); 2368 2369 if ((nd = (ND *)*pparam) == NULL) { 2370 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2371 return (B_FALSE); 2372 *pparam = (caddr_t)nd; 2373 } 2374 2375 if (nd->nd_tbl) { 2376 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2377 if (strcmp(name, nde->nde_name) == 0) 2378 goto fill_it; 2379 } 2380 } 2381 2382 if (nd->nd_free_count <= 1) { 2383 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2384 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2385 return (B_FALSE); 2386 nd->nd_free_count += NDE_ALLOC_COUNT; 2387 if (nd->nd_tbl) { 2388 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2389 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2390 } else { 2391 nd->nd_free_count--; 2392 nde->nde_name = "?"; 2393 nde->nde_get_pfi = nxge_nd_get_names; 2394 nde->nde_set_pfi = nxge_set_default; 2395 } 2396 nde->nde_data = (caddr_t)nd; 2397 nd->nd_tbl = nde; 2398 nd->nd_size += NDE_ALLOC_SIZE; 2399 } 2400 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2401 noop; 2402 nd->nd_free_count--; 2403 fill_it: 2404 nde->nde_name = name; 2405 nde->nde_get_pfi = get_pfi; 2406 nde->nde_set_pfi = set_pfi; 2407 nde->nde_data = data; 2408 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2409 2410 return (B_TRUE); 2411 } 2412 2413 /* 2414 * Free the table pointed to by 'pparam' 2415 */ 2416 void 2417 nxge_nd_free(caddr_t *pparam) 2418 { 2419 ND *nd; 2420 2421 if ((nd = (ND *)*pparam) != NULL) { 2422 if (nd->nd_tbl) 2423 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2424 KMEM_FREE((char *)nd, sizeof (ND)); 2425 *pparam = nil(caddr_t); 2426 } 2427 } 2428 2429 int 2430 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2431 { 2432 int err; 2433 IOCP iocp; 2434 p_mblk_t mp1, mp2; 2435 ND *nd; 2436 NDE *nde; 2437 char *valp; 2438 size_t avail; 2439 2440 if (!param) { 2441 return (B_FALSE); 2442 } 2443 2444 nd = (ND *)param; 2445 iocp = (IOCP)mp->b_rptr; 2446 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2447 mp->b_datap->db_type = M_IOCACK; 2448 iocp->ioc_count = 0; 2449 iocp->ioc_error = EINVAL; 2450 return (B_FALSE); 2451 } 2452 2453 /* 2454 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2455 * However, existing code sends in some big buffers. 2456 */ 2457 avail = iocp->ioc_count; 2458 if (mp1->b_cont) { 2459 freemsg(mp1->b_cont); 2460 mp1->b_cont = NULL; 2461 } 2462 2463 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2464 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2465 if (*valp == '-') 2466 *valp = '_'; 2467 } 2468 2469 valp = (char *)mp1->b_rptr; 2470 2471 for (nde = nd->nd_tbl; /* */; nde++) { 2472 if (!nde->nde_name) 2473 return (B_FALSE); 2474 if (strcmp(nde->nde_name, valp) == 0) 2475 break; 2476 } 2477 err = EINVAL; 2478 while (*valp++) 2479 noop; 2480 if (!*valp || valp >= (char *)mp1->b_wptr) 2481 valp = nilp(char); 2482 switch (iocp->ioc_cmd) { 2483 case ND_GET: 2484 /* 2485 * (temporary) hack: "*valp" is size of user buffer for 2486 * copyout. If result of action routine is too big, free 2487 * excess and return ioc_rval as buffer size needed. 2488 * Return as many mblocks as will fit, free the rest. For 2489 * backward compatibility, assume size of original ioctl 2490 * buffer if "*valp" bad or not given. 2491 */ 2492 if (valp) 2493 avail = mi_strtol(valp, (char **)0, 10); 2494 /* 2495 * We overwrite the name/value with the reply data 2496 */ 2497 mp2 = mp1; 2498 while (mp2) { 2499 mp2->b_wptr = mp2->b_rptr; 2500 mp2 = mp2->b_cont; 2501 } 2502 2503 if (nde->nde_get_pfi) { 2504 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2505 } 2506 2507 if (!err) { 2508 size_t size_out = 0; 2509 ssize_t excess; 2510 2511 iocp->ioc_rval = 0; 2512 2513 /* Tack on the null */ 2514 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2515 if (!err) { 2516 *mp2->b_wptr++ = '\0'; 2517 size_out = msgdsize(mp1); 2518 excess = size_out - avail; 2519 if (excess > 0) { 2520 iocp->ioc_rval = (int)size_out; 2521 size_out -= excess; 2522 (void) adjmsg(mp1, -(excess + 1)); 2523 err = nxge_mk_mblk_tail_space( 2524 mp1, &mp2, 1); 2525 if (!err) 2526 *mp2->b_wptr++ = '\0'; 2527 else 2528 size_out = 0; 2529 } 2530 } else 2531 size_out = 0; 2532 iocp->ioc_count = size_out; 2533 } 2534 break; 2535 2536 case ND_SET: 2537 if (valp) { 2538 if (nde->nde_set_pfi) { 2539 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2540 nde->nde_data); 2541 iocp->ioc_count = 0; 2542 freemsg(mp1); 2543 mp->b_cont = NULL; 2544 } 2545 } 2546 break; 2547 2548 default: 2549 break; 2550 } 2551 iocp->ioc_error = err; 2552 mp->b_datap->db_type = M_IOCACK; 2553 return (B_TRUE); 2554 } 2555 2556 /* ARGSUSED */ 2557 int 2558 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2559 { 2560 ND *nd; 2561 NDE *nde; 2562 char *rwtag; 2563 boolean_t get_ok, set_ok; 2564 size_t param_len; 2565 int status = 0; 2566 2567 nd = (ND *)param; 2568 if (!nd) 2569 return (ENOENT); 2570 2571 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2572 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2573 (nde->nde_get_pfi != NULL); 2574 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2575 (nde->nde_set_pfi != NULL); 2576 if (get_ok) { 2577 if (set_ok) 2578 rwtag = "read and write"; 2579 else 2580 rwtag = "read only"; 2581 } else if (set_ok) 2582 rwtag = "write only"; 2583 else { 2584 continue; 2585 } 2586 param_len = strlen(rwtag); 2587 param_len += strlen(nde->nde_name); 2588 param_len += 4; 2589 2590 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2591 } 2592 return (status); 2593 } 2594 2595 /* ARGSUSED */ 2596 int 2597 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2598 { 2599 return (EACCES); 2600 } 2601 2602 /* ARGSUSED */ 2603 int 2604 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2605 caddr_t data) 2606 { 2607 return (EACCES); 2608 } 2609 2610 void 2611 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2612 { 2613 int cmd; 2614 int status = B_FALSE; 2615 2616 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2617 cmd = iocp->ioc_cmd; 2618 2619 switch (cmd) { 2620 default: 2621 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2622 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2623 break; 2624 2625 case ND_GET: 2626 case ND_SET: 2627 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2628 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2629 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2630 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2631 "false ret from nxge_nd_getset")); 2632 break; 2633 } 2634 status = B_TRUE; 2635 break; 2636 } 2637 2638 if (status) { 2639 qreply(wq, mp); 2640 } else { 2641 miocnak(wq, mp, 0, EINVAL); 2642 } 2643 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2644 } 2645 2646 /* ARGSUSED */ 2647 static boolean_t 2648 nxge_param_link_update(p_nxge_t nxgep) 2649 { 2650 p_nxge_param_t param_arr; 2651 nxge_param_index_t i; 2652 boolean_t update_xcvr; 2653 boolean_t update_dev; 2654 int instance; 2655 boolean_t status = B_TRUE; 2656 2657 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2658 2659 param_arr = nxgep->param_arr; 2660 instance = nxgep->instance; 2661 update_xcvr = B_FALSE; 2662 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2663 update_xcvr |= param_arr[i].value; 2664 } 2665 2666 if (update_xcvr) { 2667 update_xcvr = B_FALSE; 2668 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2669 update_xcvr |= 2670 (param_arr[i].value != param_arr[i].old_value); 2671 param_arr[i].old_value = param_arr[i].value; 2672 } 2673 if (update_xcvr) { 2674 RW_ENTER_WRITER(&nxgep->filter_lock); 2675 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2676 (void) nxge_link_init(nxgep); 2677 (void) nxge_mac_init(nxgep); 2678 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2679 RW_EXIT(&nxgep->filter_lock); 2680 } 2681 } else { 2682 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2683 " no link capabilities.", instance); 2684 cmn_err(CE_WARN, " Restoring previous setting."); 2685 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2686 param_arr[i].value = param_arr[i].old_value; 2687 } 2688 2689 update_dev = B_FALSE; 2690 2691 if (update_dev) { 2692 RW_ENTER_WRITER(&nxgep->filter_lock); 2693 (void) nxge_rx_mac_disable(nxgep); 2694 (void) nxge_tx_mac_disable(nxgep); 2695 (void) nxge_tx_mac_enable(nxgep); 2696 (void) nxge_rx_mac_enable(nxgep); 2697 RW_EXIT(&nxgep->filter_lock); 2698 } 2699 2700 nxge_param_hw_update_exit: 2701 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2702 "<== nxge_param_link_update status = 0x%08x", status)); 2703 return (status); 2704 } 2705