1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 112 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 113 p_mblk_t, caddr_t); 114 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 115 p_mblk_t, caddr_t); 116 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 117 p_mblk_t, caddr_t); 118 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 119 p_mblk_t, caddr_t); 120 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 121 p_mblk_t, caddr_t); 122 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 123 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 124 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 125 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 126 char *, caddr_t); 127 static int nxge_param_set_npi_debug_flag(p_nxge_t, 128 queue_t *, mblk_t *, char *, caddr_t); 129 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 130 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 131 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 137 static boolean_t nxge_param_link_update(p_nxge_t); 138 139 /* 140 * Global array of Neptune changable parameters. 141 * This array is initialized to correspond to the default 142 * Neptune 4 port configuration. This array would be copied 143 * into each port's parameter structure and modifed per 144 * fcode and nxge.conf configuration. Later, the parameters are 145 * exported to ndd to display and run-time configuration (at least 146 * some of them). 147 * 148 */ 149 150 static nxge_param_t nxge_param_arr[] = { 151 /* 152 * min max value old hw-name conf-name 153 */ 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "instance", "instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 158 0, 999, 1000, 0, "main-instance", "main_instance"}, 159 160 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 161 0, 3, 0, 0, "function-number", "function_number"}, 162 163 /* Partition Id */ 164 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 165 0, 8, 0, 0, "partition-id", "partition_id"}, 166 167 /* Read Write Permission Mode */ 168 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 169 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 170 171 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "version", "fw_version"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 RXDMA_RCR_PTHRES_DEFAULT, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 cfg_value = (uint32_t *)param_arr[i].value; 574 for (j = 0; j < prop_len; j++) { 575 cfg_value[j] = int_prop_val[j]; 576 } 577 prop_count = prop_len; 578 param_arr[i].type |= 579 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 580 ddi_prop_free(int_prop_val); 581 } 582 continue; 583 } 584 585 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 586 param_arr[i].fcode_name, 587 (int **)&int_prop_val, 588 &prop_len) == DDI_PROP_SUCCESS) { 589 if ((*int_prop_val >= param_arr[i].minimum) && 590 (*int_prop_val <= param_arr[i].maximum)) 591 param_arr[i].value = *int_prop_val; 592 #ifdef NXGE_DEBUG_ERROR 593 else { 594 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 595 "nxge%d: 'prom' file parameter error\n", 596 nxgep->instance)); 597 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 598 "Parameter keyword '%s'" 599 " is outside valid range\n", 600 param_arr[i].name)); 601 } 602 #endif 603 ddi_prop_free(int_prop_val); 604 } 605 606 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 607 param_arr[i].name, 608 (int **)&int_prop_val, 609 &prop_len) == DDI_PROP_SUCCESS) { 610 if ((*int_prop_val >= param_arr[i].minimum) && 611 (*int_prop_val <= param_arr[i].maximum)) 612 param_arr[i].value = *int_prop_val; 613 #ifdef NXGE_DEBUG_ERROR 614 else { 615 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 616 "nxge%d: 'conf' file parameter error\n", 617 nxgep->instance)); 618 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 619 "Parameter keyword '%s'" 620 "is outside valid range\n", 621 param_arr[i].name)); 622 } 623 #endif 624 ddi_prop_free(int_prop_val); 625 } 626 } 627 } 628 629 static int 630 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 631 { 632 int status = B_TRUE; 633 int channel; 634 uint8_t grp; 635 char *prop_name; 636 char *end; 637 uint32_t name_chars; 638 639 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 640 "nxge_private_param_register %s", param_arr->name)); 641 642 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 643 return (B_TRUE); 644 645 prop_name = param_arr->name; 646 if (param_arr->type & NXGE_PARAM_RXDMA) { 647 if (strncmp("rxdma_intr", prop_name, 10) == 0) 648 return (B_TRUE); 649 name_chars = strlen("default_grp"); 650 if (strncmp("default_grp", prop_name, name_chars) == 0) { 651 prop_name += name_chars; 652 grp = mi_strtol(prop_name, &end, 10); 653 /* now check if this rdcgrp is in config */ 654 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 655 } 656 name_chars = strlen(prop_name); 657 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 658 return (B_TRUE); 659 } 660 return (B_FALSE); 661 } 662 663 if (param_arr->type & NXGE_PARAM_TXDMA) { 664 name_chars = strlen("txdma"); 665 if (strncmp("txdma", prop_name, name_chars) == 0) { 666 prop_name += name_chars; 667 channel = mi_strtol(prop_name, &end, 10); 668 /* now check if this rdc is in config */ 669 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 670 " nxge_private_param_register: %d", 671 channel)); 672 return (nxge_check_txdma_port_member(nxgep, channel)); 673 } 674 return (B_FALSE); 675 } 676 677 status = B_FALSE; 678 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 679 680 return (status); 681 } 682 683 void 684 nxge_setup_param(p_nxge_t nxgep) 685 { 686 p_nxge_param_t param_arr; 687 int i; 688 pfi_t set_pfi; 689 690 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 691 692 /* 693 * Make sure the param_instance is set to a valid device instance. 694 */ 695 if (nxge_param_arr[param_instance].value == 1000) 696 nxge_param_arr[param_instance].value = nxgep->instance; 697 698 param_arr = nxgep->param_arr; 699 param_arr[param_instance].value = nxgep->instance; 700 param_arr[param_function_number].value = nxgep->function_num; 701 702 for (i = 0; i < nxgep->param_count; i++) { 703 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 704 (nxge_private_param_register(nxgep, 705 ¶m_arr[i]) == B_FALSE)) { 706 param_arr[i].setf = NULL; 707 param_arr[i].getf = NULL; 708 } 709 710 if (param_arr[i].type & NXGE_PARAM_CMPLX) 711 param_arr[i].setf = NULL; 712 713 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 714 param_arr[i].setf = NULL; 715 param_arr[i].getf = NULL; 716 } 717 718 set_pfi = (pfi_t)param_arr[i].setf; 719 720 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 721 set_pfi = NULL; 722 } 723 724 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 725 (pfi_t)param_arr[i].getf, set_pfi, 726 (caddr_t)¶m_arr[i])) { 727 (void) nxge_nd_free(&nxgep->param_list); 728 break; 729 } 730 } 731 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 732 } 733 734 void 735 nxge_init_param(p_nxge_t nxgep) 736 { 737 p_nxge_param_t param_arr; 738 int i, alloc_size; 739 uint64_t alloc_count; 740 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 741 /* 742 * Make sure the param_instance is set to a valid device instance. 743 */ 744 if (nxge_param_arr[param_instance].value == 1000) 745 nxge_param_arr[param_instance].value = nxgep->instance; 746 747 param_arr = nxgep->param_arr; 748 if (param_arr == NULL) { 749 param_arr = (p_nxge_param_t) 750 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 751 } 752 753 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 754 param_arr[i] = nxge_param_arr[i]; 755 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 756 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 757 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 758 alloc_size = alloc_count * sizeof (uint64_t); 759 param_arr[i].value = 760 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 761 param_arr[i].old_value = 762 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 763 param_arr[i].type |= 764 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 765 } 766 } 767 768 nxgep->param_arr = param_arr; 769 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 770 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 771 nxgep->param_count)); 772 } 773 774 void 775 nxge_destroy_param(p_nxge_t nxgep) 776 { 777 int i; 778 uint64_t free_size, free_count; 779 780 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 781 782 /* 783 * Make sure the param_instance is set to a valid device instance. 784 */ 785 if (nxge_param_arr[param_instance].value == nxgep->instance) { 786 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 787 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 788 (i != nxgep->instance)) 789 break; 790 } 791 nxge_param_arr[param_instance].value = i; 792 } 793 794 if (nxgep->param_list) 795 nxge_nd_free(&nxgep->param_list); 796 for (i = 0; i < nxgep->param_count; i++) 797 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 798 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 799 free_count = ((nxgep->param_arr[i].type & 800 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 801 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 802 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 803 free_size = sizeof (uint64_t) * free_count; 804 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 805 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 806 free_size); 807 } 808 809 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 810 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 811 } 812 813 /* 814 * Extracts the value from the 'nxge' parameter array and prints the 815 * parameter value. cp points to the required parameter. 816 */ 817 818 /* ARGSUSED */ 819 int 820 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 821 { 822 p_nxge_param_t pa = (p_nxge_param_t)cp; 823 824 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 825 "==> nxge_param_get_generic name %s ", pa->name)); 826 827 if (pa->value > 0xffffffff) 828 (void) mi_mpprintf(mp, "%x%x", 829 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 830 else 831 (void) mi_mpprintf(mp, "%x", (int)pa->value); 832 833 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 834 return (0); 835 } 836 837 /* ARGSUSED */ 838 static int 839 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 840 { 841 p_nxge_param_t pa = (p_nxge_param_t)cp; 842 843 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 844 845 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 847 return (0); 848 } 849 850 /* ARGSUSED */ 851 static int 852 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 853 { 854 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 855 856 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 857 nxgep->instance, nxgep->vpd_info.ver); 858 859 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 860 return (0); 861 } 862 863 /* ARGSUSED */ 864 int 865 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 866 { 867 868 uint_t print_len, buf_len; 869 p_mblk_t np; 870 int tdc; 871 872 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 873 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 874 875 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 876 nxgep->function_num); 877 878 879 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 880 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 881 return (0); 882 } 883 884 buf_len = buff_alloc_size; 885 mp->b_cont = np; 886 887 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 888 "Total TDCs\t %d\n", nxgep->ntdc); 889 890 ((mblk_t *)np)->b_wptr += print_len; 891 buf_len -= print_len; 892 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 893 "TDC\t HW TDC\t\n"); 894 ((mblk_t *)np)->b_wptr += print_len; 895 896 buf_len -= print_len; 897 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 898 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 899 buf_len, "%d\t %d\n", 900 tdc, nxgep->tdc[tdc]); 901 ((mblk_t *)np)->b_wptr += print_len; 902 buf_len -= print_len; 903 } 904 905 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 906 return (0); 907 } 908 909 /* ARGSUSED */ 910 int 911 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 912 { 913 uint_t print_len, buf_len; 914 p_mblk_t np; 915 int rdc; 916 p_nxge_dma_pt_cfg_t p_dma_cfgp; 917 p_nxge_hw_pt_cfg_t p_cfgp; 918 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 919 p_rx_rcr_rings_t rx_rcr_rings; 920 p_rx_rcr_ring_t *rcr_rings; 921 p_rx_rbr_rings_t rx_rbr_rings; 922 p_rx_rbr_ring_t *rbr_rings; 923 924 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 925 926 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 927 nxgep->function_num); 928 929 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 930 /* The following may work even if we cannot get a large buf. */ 931 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 932 return (0); 933 } 934 935 buf_len = buff_alloc_size; 936 mp->b_cont = np; 937 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 938 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 939 940 rx_rcr_rings = nxgep->rx_rcr_rings; 941 rcr_rings = rx_rcr_rings->rcr_rings; 942 rx_rbr_rings = nxgep->rx_rbr_rings; 943 rbr_rings = rx_rbr_rings->rbr_rings; 944 945 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 946 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 947 948 ((mblk_t *)np)->b_wptr += print_len; 949 buf_len -= print_len; 950 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 951 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 952 "chunks\t RCR ptr\n"); 953 954 ((mblk_t *)np)->b_wptr += print_len; 955 buf_len -= print_len; 956 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 957 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 958 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 959 rdc, nxgep->rdc[rdc], 960 p_dma_cfgp->rcr_timeout[rdc], 961 p_dma_cfgp->rcr_threshold[rdc], 962 rbr_rings[rdc], 963 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 964 ((mblk_t *)np)->b_wptr += print_len; 965 buf_len -= print_len; 966 } 967 968 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 969 return (0); 970 } 971 972 /* ARGSUSED */ 973 int 974 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 975 p_mblk_t mp, caddr_t cp) 976 { 977 uint_t print_len, buf_len; 978 p_mblk_t np; 979 int offset, rdc, i, rdc_grp; 980 p_nxge_rdc_grp_t rdc_grp_p; 981 p_nxge_dma_pt_cfg_t p_dma_cfgp; 982 p_nxge_hw_pt_cfg_t p_cfgp; 983 984 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 985 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 986 "==> nxge_param_get_rxdma_rdcgrp_info")); 987 988 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 989 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 990 991 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 992 nxgep->function_num); 993 994 rdc_grp = p_cfgp->start_rdc_grpid; 995 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 996 /* The following may work even if we cannot get a large buf. */ 997 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 998 return (0); 999 } 1000 1001 buf_len = buff_alloc_size; 1002 mp->b_cont = np; 1003 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1004 "Total RDC Groups\t %d \n" 1005 "start RDC group\t %d\n", 1006 p_cfgp->max_rdc_grpids, 1007 p_cfgp->start_rdc_grpid); 1008 1009 ((mblk_t *)np)->b_wptr += print_len; 1010 buf_len -= print_len; 1011 1012 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 1013 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 1014 rdc_grp++, i++) { 1015 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1016 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1017 "\nRDC Group Info for Group [%d] %d\n" 1018 "RDC Count %d\tstart RDC %d\n" 1019 "RDC Group Population Information" 1020 " (offsets 0 - 15)\n", 1021 i, rdc_grp, rdc_grp_p->max_rdcs, 1022 rdc_grp_p->start_rdc); 1023 1024 ((mblk_t *)np)->b_wptr += print_len; 1025 buf_len -= print_len; 1026 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1027 buf_len, "\n"); 1028 ((mblk_t *)np)->b_wptr += print_len; 1029 buf_len -= print_len; 1030 1031 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1032 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1033 buf_len, "[%d]=%d ", rdc, 1034 rdc_grp_p->start_rdc + rdc); 1035 ((mblk_t *)np)->b_wptr += print_len; 1036 buf_len -= print_len; 1037 } 1038 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1039 buf_len, "\n"); 1040 ((mblk_t *)np)->b_wptr += print_len; 1041 buf_len -= print_len; 1042 1043 for (offset = 0; offset < 16; offset++) { 1044 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1045 buf_len, " %2d ", 1046 rdc_grp_p->rdc[offset]); 1047 ((mblk_t *)np)->b_wptr += print_len; 1048 buf_len -= print_len; 1049 } 1050 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1051 buf_len, "\n"); 1052 ((mblk_t *)np)->b_wptr += print_len; 1053 buf_len -= print_len; 1054 } 1055 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1056 "<== nxge_param_get_rxdma_rdcgrp_info")); 1057 return (0); 1058 } 1059 1060 int 1061 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1062 { 1063 p_mblk_t tmp; 1064 1065 tmp = mp; 1066 while (tmp->b_cont) 1067 tmp = tmp->b_cont; 1068 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1069 tmp->b_cont = allocb(1024, BPRI_HI); 1070 tmp = tmp->b_cont; 1071 if (!tmp) 1072 return (ENOMEM); 1073 } 1074 1075 *nmp = tmp; 1076 return (0); 1077 } 1078 1079 /* 1080 * Sets the ge parameter to the value in the nxge_param_register using 1081 * nxge_nd_load(). 1082 */ 1083 1084 /* ARGSUSED */ 1085 int 1086 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1087 char *value, caddr_t cp) 1088 { 1089 char *end; 1090 uint32_t new_value; 1091 p_nxge_param_t pa = (p_nxge_param_t)cp; 1092 1093 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1094 new_value = (uint32_t)mi_strtol(value, &end, 10); 1095 if (end == value || new_value < pa->minimum || 1096 new_value > pa->maximum) { 1097 return (EINVAL); 1098 } 1099 pa->value = new_value; 1100 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1101 return (0); 1102 } 1103 1104 /* 1105 * Sets the ge parameter to the value in the nxge_param_register using 1106 * nxge_nd_load(). 1107 */ 1108 1109 /* ARGSUSED */ 1110 int 1111 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1112 char *value, caddr_t cp) 1113 { 1114 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1115 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1116 return (0); 1117 } 1118 1119 /* 1120 * Sets the ge parameter to the value in the nxge_param_register using 1121 * nxge_nd_load(). 1122 */ 1123 1124 /* ARGSUSED */ 1125 int 1126 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1127 char *value, caddr_t cp) 1128 { 1129 char *end; 1130 uint32_t new_value; 1131 int status = 0; 1132 p_nxge_param_t pa = (p_nxge_param_t)cp; 1133 1134 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1135 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1136 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1137 return (EINVAL); 1138 } 1139 1140 if (pa->value != new_value) { 1141 pa->old_value = pa->value; 1142 pa->value = new_value; 1143 } 1144 1145 if (!nxge_param_link_update(nxgep)) { 1146 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1147 " false ret from nxge_param_link_update")); 1148 status = EINVAL; 1149 } 1150 1151 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1152 return (status); 1153 } 1154 1155 /* ARGSUSED */ 1156 static int 1157 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1158 char *value, caddr_t cp) 1159 { 1160 char *end; 1161 uint32_t cfg_value; 1162 p_nxge_param_t pa = (p_nxge_param_t)cp; 1163 1164 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1165 1166 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1167 1168 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1169 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1170 return (EINVAL); 1171 } 1172 1173 if ((pa->value != cfg_value)) { 1174 pa->old_value = pa->value; 1175 pa->value = cfg_value; 1176 nxgep->intr_threshold = pa->value; 1177 } 1178 1179 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1180 return (0); 1181 } 1182 1183 /* ARGSUSED */ 1184 static int 1185 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1186 char *value, caddr_t cp) 1187 { 1188 char *end; 1189 uint32_t cfg_value; 1190 p_nxge_param_t pa = (p_nxge_param_t)cp; 1191 1192 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1193 1194 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1195 1196 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1197 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1198 return (EINVAL); 1199 } 1200 1201 if ((pa->value != cfg_value)) { 1202 pa->old_value = pa->value; 1203 pa->value = cfg_value; 1204 nxgep->intr_timeout = pa->value; 1205 } 1206 1207 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1208 return (0); 1209 } 1210 1211 /* ARGSUSED */ 1212 static int 1213 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1214 mblk_t *mp, char *value, caddr_t cp) 1215 { 1216 char *end; 1217 uint32_t status = 0, cfg_value; 1218 p_nxge_param_t pa = (p_nxge_param_t)cp; 1219 uint32_t cfg_it = B_FALSE; 1220 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1221 p_nxge_hw_pt_cfg_t p_cfgp; 1222 uint32_t *val_ptr, *old_val_ptr; 1223 nxge_param_map_t *mac_map; 1224 p_nxge_class_pt_cfg_t p_class_cfgp; 1225 nxge_mv_cfg_t *mac_host_info; 1226 1227 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1228 1229 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1230 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1231 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1232 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1233 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1234 1235 /* 1236 * now do decoding 1237 */ 1238 mac_map = (nxge_param_map_t *)&cfg_value; 1239 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1240 cfg_value, mac_map->param_id, mac_map->map_to)); 1241 1242 if ((mac_map->param_id < p_cfgp->max_macs) && 1243 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1244 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1245 p_cfgp->start_rdc_grpid)) { 1246 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1247 " nxge_param_set_mac_rdcgrp mapping" 1248 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1249 val_ptr = (uint32_t *)pa->value; 1250 old_val_ptr = (uint32_t *)pa->old_value; 1251 if (val_ptr[mac_map->param_id] != cfg_value) { 1252 old_val_ptr[mac_map->param_id] = 1253 val_ptr[mac_map->param_id]; 1254 val_ptr[mac_map->param_id] = cfg_value; 1255 mac_host_info[mac_map->param_id].mpr_npr = 1256 mac_map->pref; 1257 mac_host_info[mac_map->param_id].flag = 1; 1258 mac_host_info[mac_map->param_id].rdctbl = 1259 mac_map->map_to; 1260 cfg_it = B_TRUE; 1261 } 1262 } else { 1263 return (EINVAL); 1264 } 1265 1266 if (cfg_it == B_TRUE) { 1267 status = nxge_logical_mac_assign_rdc_table(nxgep, 1268 (uint8_t)mac_map->param_id); 1269 if (status != NXGE_OK) 1270 return (EINVAL); 1271 } 1272 1273 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1274 return (0); 1275 } 1276 1277 /* ARGSUSED */ 1278 static int 1279 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1280 mblk_t *mp, char *value, caddr_t cp) 1281 { 1282 char *end; 1283 uint32_t status = 0, cfg_value; 1284 p_nxge_param_t pa = (p_nxge_param_t)cp; 1285 uint32_t cfg_it = B_FALSE; 1286 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1287 p_nxge_hw_pt_cfg_t p_cfgp; 1288 uint32_t *val_ptr, *old_val_ptr; 1289 nxge_param_map_t *vmap, *old_map; 1290 p_nxge_class_pt_cfg_t p_class_cfgp; 1291 uint64_t cfgd_vlans; 1292 int i, inc = 0, cfg_position; 1293 nxge_mv_cfg_t *vlan_tbl; 1294 1295 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1296 1297 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1298 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1299 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1300 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1301 1302 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1303 1304 /* now do decoding */ 1305 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1306 NXGE_PARAM_ARRAY_CNT_SHIFT); 1307 1308 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1309 /* 1310 * for now, we process only upto max 1311 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1312 * In the future, we may want to expand 1313 * the storage array and continue 1314 */ 1315 return (EINVAL); 1316 } 1317 1318 vmap = (nxge_param_map_t *)&cfg_value; 1319 if ((vmap->param_id) && 1320 (vmap->param_id < NXGE_MAX_VLANS) && 1321 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1322 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1323 "nxge_param_set_vlan_rdcgrp mapping" 1324 " id %d grp %d", 1325 vmap->param_id, vmap->map_to)); 1326 val_ptr = (uint32_t *)pa->value; 1327 old_val_ptr = (uint32_t *)pa->old_value; 1328 1329 /* search to see if this vlan id is already configured */ 1330 for (i = 0; i < cfgd_vlans; i++) { 1331 old_map = (nxge_param_map_t *)&val_ptr[i]; 1332 if ((old_map->param_id == 0) || 1333 (vmap->param_id == old_map->param_id) || 1334 (vlan_tbl[vmap->param_id].flag)) { 1335 cfg_position = i; 1336 break; 1337 } 1338 } 1339 1340 if (cfgd_vlans == 0) { 1341 cfg_position = 0; 1342 inc++; 1343 } 1344 1345 if (i == cfgd_vlans) { 1346 cfg_position = i; 1347 inc++; 1348 } 1349 1350 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1351 "set_vlan_rdcgrp mapping" 1352 " i %d cfgd_vlans %llx position %d ", 1353 i, cfgd_vlans, cfg_position)); 1354 if (val_ptr[cfg_position] != cfg_value) { 1355 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1356 val_ptr[cfg_position] = cfg_value; 1357 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1358 vlan_tbl[vmap->param_id].flag = 1; 1359 vlan_tbl[vmap->param_id].rdctbl = 1360 vmap->map_to + p_cfgp->start_rdc_grpid; 1361 cfg_it = B_TRUE; 1362 if (inc) { 1363 cfgd_vlans++; 1364 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1365 pa->type |= (cfgd_vlans << 1366 NXGE_PARAM_ARRAY_CNT_SHIFT); 1367 1368 } 1369 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1370 "after: param_set_vlan_rdcgrp " 1371 " cfg_vlans %llx position %d \n", 1372 cfgd_vlans, cfg_position)); 1373 } 1374 } else { 1375 return (EINVAL); 1376 } 1377 1378 if (cfg_it == B_TRUE) { 1379 status = nxge_fflp_config_vlan_table(nxgep, 1380 (uint16_t)vmap->param_id); 1381 if (status != NXGE_OK) 1382 return (EINVAL); 1383 } 1384 1385 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1386 return (0); 1387 } 1388 1389 /* ARGSUSED */ 1390 static int 1391 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1392 mblk_t *mp, caddr_t cp) 1393 { 1394 1395 uint_t print_len, buf_len; 1396 p_mblk_t np; 1397 int i; 1398 uint32_t *val_ptr; 1399 nxge_param_map_t *vmap; 1400 p_nxge_param_t pa = (p_nxge_param_t)cp; 1401 p_nxge_class_pt_cfg_t p_class_cfgp; 1402 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1403 p_nxge_hw_pt_cfg_t p_cfgp; 1404 uint64_t cfgd_vlans = 0; 1405 nxge_mv_cfg_t *vlan_tbl; 1406 int buff_alloc_size = 1407 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1408 1409 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1410 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1411 nxgep->function_num); 1412 1413 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1414 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1415 return (0); 1416 } 1417 1418 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1419 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1420 1421 buf_len = buff_alloc_size; 1422 mp->b_cont = np; 1423 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1424 NXGE_PARAM_ARRAY_CNT_SHIFT; 1425 1426 i = (int)cfgd_vlans; 1427 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1428 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1429 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1430 "Configured VLANs %d\n" 1431 "VLAN ID\t RDC GRP (Actual/Port)\t" 1432 " Prefernce\n", i); 1433 ((mblk_t *)np)->b_wptr += print_len; 1434 buf_len -= print_len; 1435 1436 val_ptr = (uint32_t *)pa->value; 1437 1438 for (i = 0; i < cfgd_vlans; i++) { 1439 vmap = (nxge_param_map_t *)&val_ptr[i]; 1440 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1441 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1442 buf_len, 1443 " %d\t\t %d/%d\t\t %d\n", 1444 vmap->param_id, 1445 vlan_tbl[vmap->param_id].rdctbl, 1446 vlan_tbl[vmap->param_id].rdctbl - 1447 p_cfgp->start_rdc_grpid, 1448 vlan_tbl[vmap->param_id].mpr_npr); 1449 ((mblk_t *)np)->b_wptr += print_len; 1450 buf_len -= print_len; 1451 } 1452 } 1453 1454 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1455 return (0); 1456 } 1457 1458 /* ARGSUSED */ 1459 static int 1460 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1461 mblk_t *mp, caddr_t cp) 1462 { 1463 uint_t print_len, buf_len; 1464 p_mblk_t np; 1465 int i; 1466 p_nxge_class_pt_cfg_t p_class_cfgp; 1467 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1468 p_nxge_hw_pt_cfg_t p_cfgp; 1469 nxge_mv_cfg_t *mac_host_info; 1470 1471 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1472 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1473 (void) mi_mpprintf(mp, 1474 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1475 nxgep->function_num); 1476 1477 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1478 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1479 return (0); 1480 } 1481 1482 buf_len = buff_alloc_size; 1483 mp->b_cont = np; 1484 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1485 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1486 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1487 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1488 print_len = snprintf((char *)np->b_wptr, buf_len, 1489 "MAC ID\t RDC GRP (Actual/Port)\t" 1490 " Prefernce\n"); 1491 ((mblk_t *)np)->b_wptr += print_len; 1492 buf_len -= print_len; 1493 for (i = 0; i < p_cfgp->max_macs; i++) { 1494 if (mac_host_info[i].flag) { 1495 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1496 buf_len, 1497 " %d\t %d/%d\t\t %d\n", 1498 i, mac_host_info[i].rdctbl, 1499 mac_host_info[i].rdctbl - 1500 p_cfgp->start_rdc_grpid, 1501 mac_host_info[i].mpr_npr); 1502 ((mblk_t *)np)->b_wptr += print_len; 1503 buf_len -= print_len; 1504 } 1505 } 1506 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1507 "Done Info Dumping \n"); 1508 ((mblk_t *)np)->b_wptr += print_len; 1509 buf_len -= print_len; 1510 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1511 return (0); 1512 } 1513 1514 /* ARGSUSED */ 1515 static int 1516 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1517 mblk_t *mp, char *value, caddr_t cp) 1518 { 1519 uint32_t status = 0, cfg_value; 1520 p_nxge_param_t pa = (p_nxge_param_t)cp; 1521 uint32_t cfg_it = B_FALSE; 1522 char *end; 1523 1524 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1525 1526 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1527 if (pa->value != cfg_value) { 1528 pa->old_value = pa->value; 1529 pa->value = cfg_value; 1530 cfg_it = B_TRUE; 1531 } 1532 1533 if (cfg_it == B_TRUE) { 1534 if (pa->value) 1535 status = nxge_fflp_config_tcam_enable(nxgep); 1536 else 1537 status = nxge_fflp_config_tcam_disable(nxgep); 1538 if (status != NXGE_OK) 1539 return (EINVAL); 1540 } 1541 1542 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1543 return (0); 1544 } 1545 1546 /* ARGSUSED */ 1547 static int 1548 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1549 mblk_t *mp, char *value, caddr_t cp) 1550 { 1551 uint32_t status = 0, cfg_value; 1552 p_nxge_param_t pa = (p_nxge_param_t)cp; 1553 uint32_t cfg_it = B_FALSE; 1554 char *end; 1555 1556 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1557 1558 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1559 if (pa->value != cfg_value) { 1560 pa->old_value = pa->value; 1561 pa->value = cfg_value; 1562 cfg_it = B_TRUE; 1563 } 1564 1565 if (cfg_it == B_TRUE) { 1566 if (pa->value) 1567 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1568 else 1569 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1570 if (status != NXGE_OK) 1571 return (EINVAL); 1572 } 1573 1574 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1575 return (0); 1576 } 1577 1578 /* ARGSUSED */ 1579 static int 1580 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1581 mblk_t *mp, char *value, caddr_t cp) 1582 { 1583 char *end; 1584 uint32_t status = 0, cfg_value; 1585 p_nxge_param_t pa = (p_nxge_param_t)cp; 1586 uint32_t cfg_it = B_FALSE; 1587 1588 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1589 1590 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1591 if (pa->value != cfg_value) { 1592 pa->old_value = pa->value; 1593 pa->value = cfg_value; 1594 cfg_it = B_TRUE; 1595 } 1596 1597 if (cfg_it == B_TRUE) { 1598 if (pa->value) 1599 status = nxge_fflp_config_tcam_enable(nxgep); 1600 else 1601 status = nxge_fflp_config_tcam_disable(nxgep); 1602 if (status != NXGE_OK) 1603 return (EINVAL); 1604 } 1605 1606 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1607 return (0); 1608 } 1609 1610 /* ARGSUSED */ 1611 static int 1612 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1613 mblk_t *mp, char *value, caddr_t cp) 1614 { 1615 char *end; 1616 uint8_t ether_class; 1617 uint32_t status = 0, cfg_value; 1618 p_nxge_param_t pa = (p_nxge_param_t)cp; 1619 uint8_t cfg_it = B_FALSE; 1620 1621 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1622 1623 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1624 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1625 return (EINVAL); 1626 } 1627 1628 if (pa->value != cfg_value) { 1629 pa->old_value = pa->value; 1630 pa->value = cfg_value; 1631 cfg_it = B_TRUE; 1632 } 1633 1634 /* do the actual hw setup */ 1635 if (cfg_it == B_TRUE) { 1636 ether_class = mi_strtol(pa->name, &end, 10); 1637 #ifdef lint 1638 ether_class = ether_class; 1639 #endif 1640 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1641 } 1642 1643 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1644 return (status); 1645 } 1646 1647 /* ARGSUSED */ 1648 static int 1649 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1650 mblk_t *mp, char *value, caddr_t cp) 1651 { 1652 char *end; 1653 tcam_class_t class; 1654 uint32_t status, cfg_value; 1655 p_nxge_param_t pa = (p_nxge_param_t)cp; 1656 uint32_t cfg_it = B_FALSE; 1657 1658 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1659 1660 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1661 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1662 return (EINVAL); 1663 } 1664 1665 if (pa->value != cfg_value) { 1666 pa->old_value = pa->value; 1667 pa->value = cfg_value; 1668 cfg_it = B_TRUE; 1669 } 1670 1671 /* do the actual hw setup with cfg_value. */ 1672 if (cfg_it == B_TRUE) { 1673 class = mi_strtol(pa->name, &end, 10); 1674 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1675 } 1676 1677 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1678 return (status); 1679 } 1680 1681 /* ARGSUSED */ 1682 static int 1683 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1684 { 1685 int i; 1686 int class_instance = param_class_opt_ip_usr4; 1687 p_nxge_param_t param_arr; 1688 1689 param_arr = nxgep->param_arr; 1690 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1691 if (strcmp(param_arr[class_instance].name, name) == 0) 1692 return (i); 1693 class_instance++; 1694 } 1695 return (-1); 1696 } 1697 1698 /* ARGSUSED */ 1699 static int 1700 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1701 mblk_t *mp, char *value, caddr_t cp) 1702 { 1703 char *end; 1704 uint32_t status, cfg_value; 1705 p_nxge_param_t pa = (p_nxge_param_t)cp; 1706 tcam_class_t class; 1707 uint32_t cfg_it = B_FALSE; 1708 1709 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1710 1711 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1712 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1713 return (EINVAL); 1714 } 1715 1716 if (pa->value != cfg_value) { 1717 pa->old_value = pa->value; 1718 pa->value = cfg_value; 1719 cfg_it = B_TRUE; 1720 } 1721 1722 if (cfg_it == B_TRUE) { 1723 /* do the actual hw setup */ 1724 class = nxge_class_name_2value(nxgep, pa->name); 1725 if (class == -1) 1726 return (EINVAL); 1727 1728 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1729 if (status != NXGE_OK) 1730 return (EINVAL); 1731 } 1732 1733 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1734 return (0); 1735 } 1736 1737 /* ARGSUSED */ 1738 static int 1739 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1740 mblk_t *mp, caddr_t cp) 1741 { 1742 uint32_t status, cfg_value; 1743 p_nxge_param_t pa = (p_nxge_param_t)cp; 1744 tcam_class_t class; 1745 1746 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1747 1748 /* do the actual hw setup */ 1749 class = nxge_class_name_2value(nxgep, pa->name); 1750 if (class == -1) 1751 return (EINVAL); 1752 1753 cfg_value = 0; 1754 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1755 if (status != NXGE_OK) 1756 return (EINVAL); 1757 1758 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1759 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1760 1761 pa->value = cfg_value; 1762 (void) mi_mpprintf(mp, "%x", cfg_value); 1763 1764 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1765 return (0); 1766 } 1767 1768 /* ARGSUSED */ 1769 static int 1770 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1771 mblk_t *mp, char *value, caddr_t cp) 1772 { 1773 char *end; 1774 uint32_t status, cfg_value; 1775 p_nxge_param_t pa = (p_nxge_param_t)cp; 1776 tcam_class_t class; 1777 uint32_t cfg_it = B_FALSE; 1778 1779 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1780 1781 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1782 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1783 return (EINVAL); 1784 } 1785 1786 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1787 "nxge_param_fflp_hash_init value %x", cfg_value)); 1788 1789 if (pa->value != cfg_value) { 1790 pa->old_value = pa->value; 1791 pa->value = cfg_value; 1792 cfg_it = B_TRUE; 1793 } 1794 1795 if (cfg_it == B_TRUE) { 1796 char *h_name; 1797 1798 /* do the actual hw setup */ 1799 h_name = pa->name; 1800 h_name++; 1801 class = mi_strtol(h_name, &end, 10); 1802 switch (class) { 1803 case 1: 1804 status = nxge_fflp_set_hash1(nxgep, 1805 (uint32_t)pa->value); 1806 break; 1807 case 2: 1808 status = nxge_fflp_set_hash2(nxgep, 1809 (uint16_t)pa->value); 1810 break; 1811 1812 default: 1813 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1814 " nxge_param_fflp_hash_init" 1815 " %s Wrong hash var %d", 1816 pa->name, class)); 1817 return (EINVAL); 1818 } 1819 if (status != NXGE_OK) 1820 return (EINVAL); 1821 } 1822 1823 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1824 return (0); 1825 } 1826 1827 /* ARGSUSED */ 1828 static int 1829 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1830 mblk_t *mp, char *value, caddr_t cp) 1831 { 1832 char *end; 1833 uint32_t status = 0, cfg_value; 1834 p_nxge_param_t pa = (p_nxge_param_t)cp; 1835 uint32_t cfg_it = B_FALSE; 1836 int rdc_grp; 1837 uint8_t real_rdc; 1838 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1839 p_nxge_hw_pt_cfg_t p_cfgp; 1840 p_nxge_rdc_grp_t rdc_grp_p; 1841 1842 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1843 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1844 1845 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1846 1847 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1848 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1849 return (EINVAL); 1850 } 1851 1852 if (cfg_value >= p_cfgp->max_rdcs) { 1853 return (EINVAL); 1854 } 1855 1856 if (pa->value != cfg_value) { 1857 pa->old_value = pa->value; 1858 pa->value = cfg_value; 1859 cfg_it = B_TRUE; 1860 } 1861 1862 if (cfg_it == B_TRUE) { 1863 char *grp_name; 1864 grp_name = pa->name; 1865 grp_name += strlen("default-grp"); 1866 rdc_grp = mi_strtol(grp_name, &end, 10); 1867 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1868 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1869 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1870 cfg_value) == B_FALSE) { 1871 pa->value = pa->old_value; 1872 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1873 " nxge_param_set_grp_rdc" 1874 " %d read %d actual %d outof range", 1875 rdc_grp, cfg_value, real_rdc)); 1876 return (EINVAL); 1877 } 1878 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1879 real_rdc); 1880 if (status != NXGE_OK) 1881 return (EINVAL); 1882 } 1883 1884 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1885 return (0); 1886 } 1887 1888 /* ARGSUSED */ 1889 static int 1890 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1891 mblk_t *mp, char *value, caddr_t cp) 1892 { 1893 char *end; 1894 uint32_t status = B_TRUE, cfg_value; 1895 p_nxge_param_t pa = (p_nxge_param_t)cp; 1896 uint32_t cfg_it = B_FALSE; 1897 1898 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1899 p_nxge_hw_pt_cfg_t p_cfgp; 1900 1901 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 1902 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1903 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1904 1905 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1906 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1907 return (EINVAL); 1908 } 1909 1910 if (pa->value != cfg_value) { 1911 if (cfg_value >= p_cfgp->max_rdcs) 1912 return (EINVAL); 1913 pa->old_value = pa->value; 1914 pa->value = cfg_value; 1915 cfg_it = B_TRUE; 1916 } 1917 1918 if (cfg_it == B_TRUE) { 1919 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1920 nxgep->function_num, 1921 nxgep->rdc[cfg_value]); 1922 if (status != NXGE_OK) 1923 return (EINVAL); 1924 } 1925 1926 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 1927 return (0); 1928 } 1929 1930 /* ARGSUSED */ 1931 static int 1932 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1933 mblk_t *mp, char *value, caddr_t cp) 1934 { 1935 char *end; 1936 uint32_t status = 0; 1937 uint64_t cfg_value = 0; 1938 p_nxge_param_t pa = (p_nxge_param_t)cp; 1939 uint32_t cfg_it = B_FALSE; 1940 1941 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 1942 cfg_value = mi_strtol(value, &end, BASE_HEX); 1943 1944 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1945 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1946 " nxge_param_set_nxge_debug_flag" 1947 " outof range %llx", cfg_value)); 1948 return (EINVAL); 1949 } 1950 if (pa->value != cfg_value) { 1951 pa->old_value = pa->value; 1952 pa->value = cfg_value; 1953 cfg_it = B_TRUE; 1954 } 1955 1956 if (cfg_it == B_TRUE) { 1957 nxgep->nxge_debug_level = pa->value; 1958 } 1959 1960 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 1961 return (status); 1962 } 1963 1964 /* ARGSUSED */ 1965 static int 1966 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1967 { 1968 int status = 0; 1969 p_nxge_param_t pa = (p_nxge_param_t)cp; 1970 1971 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 1972 1973 if (pa->value > 0xffffffff) 1974 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1975 (int)(pa->value & 0xffffffff)); 1976 else 1977 (void) mi_mpprintf(mp, "%x", (int)pa->value); 1978 1979 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 1980 return (status); 1981 } 1982 1983 /* ARGSUSED */ 1984 static int 1985 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1986 mblk_t *mp, char *value, caddr_t cp) 1987 { 1988 char *end; 1989 uint32_t status = 0; 1990 uint64_t cfg_value = 0; 1991 p_nxge_param_t pa; 1992 uint32_t cfg_it = B_FALSE; 1993 1994 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 1995 cfg_value = mi_strtol(value, &end, BASE_HEX); 1996 pa = (p_nxge_param_t)cp; 1997 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1998 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 1999 " outof range %llx", cfg_value)); 2000 return (EINVAL); 2001 } 2002 if (pa->value != cfg_value) { 2003 pa->old_value = pa->value; 2004 pa->value = cfg_value; 2005 cfg_it = B_TRUE; 2006 } 2007 2008 if (cfg_it == B_TRUE) { 2009 npi_debug_level = pa->value; 2010 } 2011 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2012 return (status); 2013 } 2014 2015 /* ARGSUSED */ 2016 static int 2017 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2018 { 2019 uint_t rdc; 2020 2021 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2022 2023 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2024 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 2025 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 2026 2027 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2028 return (0); 2029 } 2030 2031 /* ARGSUSED */ 2032 static int 2033 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2034 { 2035 uint_t tdc; 2036 2037 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2038 2039 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2040 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2041 2042 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2043 return (0); 2044 } 2045 2046 /* ARGSUSED */ 2047 static int 2048 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2049 { 2050 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2051 2052 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2053 2054 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2055 return (0); 2056 } 2057 2058 /* ARGSUSED */ 2059 static int 2060 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2061 { 2062 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2063 2064 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2065 nxgep->function_num); 2066 2067 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2068 return (0); 2069 } 2070 2071 /* ARGSUSED */ 2072 static int 2073 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2074 { 2075 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2076 2077 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2078 nxgep->function_num); 2079 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2080 return (0); 2081 } 2082 2083 /* ARGSUSED */ 2084 static int 2085 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2086 { 2087 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2088 2089 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2090 2091 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2092 return (0); 2093 } 2094 2095 /* ARGSUSED */ 2096 static int 2097 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2098 { 2099 uint8_t table; 2100 2101 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2102 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2103 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2104 table); 2105 } 2106 2107 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2108 return (0); 2109 } 2110 2111 typedef struct block_info { 2112 char *name; 2113 uint32_t offset; 2114 } block_info_t; 2115 2116 block_info_t reg_block[] = { 2117 {"PIO", PIO}, 2118 {"FZC_PIO", FZC_PIO}, 2119 {"FZC_XMAC", FZC_MAC}, 2120 {"FZC_IPP", FZC_IPP}, 2121 {"FFLP", FFLP}, 2122 {"FZC_FFLP", FZC_FFLP}, 2123 {"PIO_VADDR", PIO_VADDR}, 2124 {"ZCP", ZCP}, 2125 {"FZC_ZCP", FZC_ZCP}, 2126 {"DMC", DMC}, 2127 {"FZC_DMC", FZC_DMC}, 2128 {"TXC", TXC}, 2129 {"FZC_TXC", FZC_TXC}, 2130 {"PIO_LDSV", PIO_LDSV}, 2131 {"PIO_LDGIM", PIO_LDGIM}, 2132 {"PIO_IMASK0", PIO_IMASK0}, 2133 {"PIO_IMASK1", PIO_IMASK1}, 2134 {"FZC_PROM", FZC_PROM}, 2135 {"END", ALL_FF_32}, 2136 }; 2137 2138 /* ARGSUSED */ 2139 static int 2140 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2141 { 2142 uint_t print_len, buf_len; 2143 p_mblk_t np; 2144 int rdc, tdc, block; 2145 uint64_t base; 2146 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2147 p_nxge_hw_pt_cfg_t p_cfgp; 2148 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2149 p_tx_ring_t *tx_rings; 2150 p_rx_rcr_rings_t rx_rcr_rings; 2151 p_rx_rcr_ring_t *rcr_rings; 2152 p_rx_rbr_rings_t rx_rbr_rings; 2153 p_rx_rbr_ring_t *rbr_rings; 2154 2155 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2156 "==> nxge_param_dump_ptrs")); 2157 2158 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2159 nxgep->function_num); 2160 2161 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2162 /* The following may work even if we cannot get a large buf. */ 2163 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2164 return (0); 2165 } 2166 2167 buf_len = buff_alloc_size; 2168 mp->b_cont = np; 2169 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2170 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2171 2172 rx_rcr_rings = nxgep->rx_rcr_rings; 2173 rcr_rings = rx_rcr_rings->rcr_rings; 2174 rx_rbr_rings = nxgep->rx_rbr_rings; 2175 rbr_rings = rx_rbr_rings->rbr_rings; 2176 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2177 "nxgep (nxge_t) $%p\n" 2178 "dev_regs (dev_regs_t) $%p\n", 2179 nxgep, nxgep->dev_regs); 2180 2181 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2182 2183 /* do register pointers */ 2184 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2185 "reg base (npi_reg_ptr_t) $%p\t " 2186 "pci reg (npi_reg_ptr_t) $%p\n", 2187 nxgep->dev_regs->nxge_regp, 2188 nxgep->dev_regs->nxge_pciregp); 2189 2190 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2191 2192 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2193 "\nBlock \t Offset \n"); 2194 2195 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2196 block = 0; 2197 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2198 while (reg_block[block].offset != ALL_FF_32) { 2199 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2200 "%9s\t 0x%llx\n", 2201 reg_block[block].name, 2202 (unsigned long long)(reg_block[block].offset + base)); 2203 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2204 block++; 2205 } 2206 2207 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2208 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2209 "rbrp (rx_rbr_ring_t)\n"); 2210 2211 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2212 2213 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2214 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2215 " %d\t $%p\t\t $%p\n", 2216 rdc, rcr_rings[rdc], 2217 rbr_rings[rdc]); 2218 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2219 } 2220 2221 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2222 "\nTDC\t tdcp (tx_ring_t)\n"); 2223 2224 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2225 tx_rings = nxgep->tx_rings->rings; 2226 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2227 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2228 " %d\t $%p\n", tdc, tx_rings[tdc]); 2229 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2230 } 2231 2232 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2233 2234 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2235 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2236 return (0); 2237 } 2238 2239 /* 2240 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2241 * 'ndp' should be the address of a char pointer cell. If the table 2242 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2243 * is stuffed. If there is not enough space in the table for a new 2244 * entry, more space is allocated. 2245 */ 2246 /* ARGSUSED */ 2247 boolean_t 2248 nxge_nd_load(caddr_t *pparam, char *name, 2249 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2250 { 2251 ND *nd; 2252 NDE *nde; 2253 2254 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2255 if (!pparam) 2256 return (B_FALSE); 2257 2258 if ((nd = (ND *)*pparam) == NULL) { 2259 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2260 return (B_FALSE); 2261 *pparam = (caddr_t)nd; 2262 } 2263 2264 if (nd->nd_tbl) { 2265 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2266 if (strcmp(name, nde->nde_name) == 0) 2267 goto fill_it; 2268 } 2269 } 2270 2271 if (nd->nd_free_count <= 1) { 2272 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2273 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2274 return (B_FALSE); 2275 nd->nd_free_count += NDE_ALLOC_COUNT; 2276 if (nd->nd_tbl) { 2277 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2278 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2279 } else { 2280 nd->nd_free_count--; 2281 nde->nde_name = "?"; 2282 nde->nde_get_pfi = nxge_nd_get_names; 2283 nde->nde_set_pfi = nxge_set_default; 2284 } 2285 nde->nde_data = (caddr_t)nd; 2286 nd->nd_tbl = nde; 2287 nd->nd_size += NDE_ALLOC_SIZE; 2288 } 2289 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2290 noop; 2291 nd->nd_free_count--; 2292 fill_it: 2293 nde->nde_name = name; 2294 nde->nde_get_pfi = get_pfi; 2295 nde->nde_set_pfi = set_pfi; 2296 nde->nde_data = data; 2297 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2298 2299 return (B_TRUE); 2300 } 2301 2302 /* 2303 * Free the table pointed to by 'pparam' 2304 */ 2305 void 2306 nxge_nd_free(caddr_t *pparam) 2307 { 2308 ND *nd; 2309 2310 if ((nd = (ND *)*pparam) != NULL) { 2311 if (nd->nd_tbl) 2312 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2313 KMEM_FREE((char *)nd, sizeof (ND)); 2314 *pparam = nil(caddr_t); 2315 } 2316 } 2317 2318 int 2319 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2320 { 2321 int err; 2322 IOCP iocp; 2323 p_mblk_t mp1, mp2; 2324 ND *nd; 2325 NDE *nde; 2326 char *valp; 2327 size_t avail; 2328 2329 if (!param) { 2330 return (B_FALSE); 2331 } 2332 2333 nd = (ND *)param; 2334 iocp = (IOCP)mp->b_rptr; 2335 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2336 mp->b_datap->db_type = M_IOCACK; 2337 iocp->ioc_count = 0; 2338 iocp->ioc_error = EINVAL; 2339 return (B_FALSE); 2340 } 2341 2342 /* 2343 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2344 * However, existing code sends in some big buffers. 2345 */ 2346 avail = iocp->ioc_count; 2347 if (mp1->b_cont) { 2348 freemsg(mp1->b_cont); 2349 mp1->b_cont = NULL; 2350 } 2351 2352 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2353 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2354 if (*valp == '-') 2355 *valp = '_'; 2356 } 2357 2358 valp = (char *)mp1->b_rptr; 2359 2360 for (nde = nd->nd_tbl; /* */; nde++) { 2361 if (!nde->nde_name) 2362 return (B_FALSE); 2363 if (strcmp(nde->nde_name, valp) == 0) 2364 break; 2365 } 2366 err = EINVAL; 2367 while (*valp++) 2368 noop; 2369 if (!*valp || valp >= (char *)mp1->b_wptr) 2370 valp = nilp(char); 2371 switch (iocp->ioc_cmd) { 2372 case ND_GET: 2373 /* 2374 * (temporary) hack: "*valp" is size of user buffer for 2375 * copyout. If result of action routine is too big, free 2376 * excess and return ioc_rval as buffer size needed. 2377 * Return as many mblocks as will fit, free the rest. For 2378 * backward compatibility, assume size of original ioctl 2379 * buffer if "*valp" bad or not given. 2380 */ 2381 if (valp) 2382 avail = mi_strtol(valp, (char **)0, 10); 2383 /* 2384 * We overwrite the name/value with the reply data 2385 */ 2386 mp2 = mp1; 2387 while (mp2) { 2388 mp2->b_wptr = mp2->b_rptr; 2389 mp2 = mp2->b_cont; 2390 } 2391 2392 if (nde->nde_get_pfi) { 2393 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2394 } 2395 2396 if (!err) { 2397 size_t size_out = 0; 2398 size_t excess; 2399 2400 iocp->ioc_rval = 0; 2401 2402 /* Tack on the null */ 2403 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2404 if (!err) { 2405 *mp2->b_wptr++ = '\0'; 2406 size_out = msgdsize(mp1); 2407 excess = size_out - avail; 2408 if (excess > 0) { 2409 iocp->ioc_rval = (int)size_out; 2410 size_out -= excess; 2411 (void) adjmsg(mp1, -(excess + 1)); 2412 err = nxge_mk_mblk_tail_space( 2413 mp1, &mp2, 1); 2414 if (!err) 2415 *mp2->b_wptr++ = '\0'; 2416 else 2417 size_out = 0; 2418 } 2419 } else 2420 size_out = 0; 2421 iocp->ioc_count = size_out; 2422 } 2423 break; 2424 2425 case ND_SET: 2426 if (valp) { 2427 if (nde->nde_set_pfi) { 2428 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2429 nde->nde_data); 2430 iocp->ioc_count = 0; 2431 freemsg(mp1); 2432 mp->b_cont = NULL; 2433 } 2434 } 2435 break; 2436 2437 default: 2438 break; 2439 } 2440 iocp->ioc_error = err; 2441 mp->b_datap->db_type = M_IOCACK; 2442 return (B_TRUE); 2443 } 2444 2445 /* ARGSUSED */ 2446 int 2447 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2448 { 2449 ND *nd; 2450 NDE *nde; 2451 char *rwtag; 2452 boolean_t get_ok, set_ok; 2453 size_t param_len; 2454 int status = 0; 2455 2456 nd = (ND *)param; 2457 if (!nd) 2458 return (ENOENT); 2459 2460 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2461 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2462 (nde->nde_get_pfi != NULL); 2463 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2464 (nde->nde_set_pfi != NULL); 2465 if (get_ok) { 2466 if (set_ok) 2467 rwtag = "read and write"; 2468 else 2469 rwtag = "read only"; 2470 } else if (set_ok) 2471 rwtag = "write only"; 2472 else { 2473 continue; 2474 } 2475 param_len = strlen(rwtag); 2476 param_len += strlen(nde->nde_name); 2477 param_len += 4; 2478 2479 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2480 } 2481 return (status); 2482 } 2483 2484 /* ARGSUSED */ 2485 int 2486 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2487 { 2488 return (EACCES); 2489 } 2490 2491 /* ARGSUSED */ 2492 int 2493 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2494 caddr_t data) 2495 { 2496 return (EACCES); 2497 } 2498 2499 void 2500 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2501 { 2502 int cmd; 2503 int status = B_FALSE; 2504 2505 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2506 cmd = iocp->ioc_cmd; 2507 2508 switch (cmd) { 2509 default: 2510 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2511 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2512 break; 2513 2514 case ND_GET: 2515 case ND_SET: 2516 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2517 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2518 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2519 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2520 "false ret from nxge_nd_getset")); 2521 break; 2522 } 2523 status = B_TRUE; 2524 break; 2525 } 2526 2527 if (status) { 2528 qreply(wq, mp); 2529 } else { 2530 miocnak(wq, mp, 0, EINVAL); 2531 } 2532 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2533 } 2534 2535 /* ARGSUSED */ 2536 static boolean_t 2537 nxge_param_link_update(p_nxge_t nxgep) 2538 { 2539 p_nxge_param_t param_arr; 2540 nxge_param_index_t i; 2541 boolean_t update_xcvr; 2542 boolean_t update_dev; 2543 int instance; 2544 boolean_t status = B_TRUE; 2545 2546 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2547 2548 param_arr = nxgep->param_arr; 2549 instance = nxgep->instance; 2550 update_xcvr = B_FALSE; 2551 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2552 update_xcvr |= param_arr[i].value; 2553 } 2554 2555 if (update_xcvr) { 2556 update_xcvr = B_FALSE; 2557 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2558 update_xcvr |= 2559 (param_arr[i].value != param_arr[i].old_value); 2560 param_arr[i].old_value = param_arr[i].value; 2561 } 2562 if (update_xcvr) { 2563 RW_ENTER_WRITER(&nxgep->filter_lock); 2564 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2565 (void) nxge_link_init(nxgep); 2566 (void) nxge_mac_init(nxgep); 2567 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2568 RW_EXIT(&nxgep->filter_lock); 2569 } 2570 } else { 2571 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2572 " no link capabilities.", instance); 2573 cmn_err(CE_WARN, " Restoring previous setting."); 2574 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2575 param_arr[i].value = param_arr[i].old_value; 2576 } 2577 2578 update_dev = B_FALSE; 2579 2580 if (update_dev) { 2581 RW_ENTER_WRITER(&nxgep->filter_lock); 2582 (void) nxge_rx_mac_disable(nxgep); 2583 (void) nxge_tx_mac_disable(nxgep); 2584 (void) nxge_tx_mac_enable(nxgep); 2585 (void) nxge_rx_mac_enable(nxgep); 2586 RW_EXIT(&nxgep->filter_lock); 2587 } 2588 2589 nxge_param_hw_update_exit: 2590 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2591 "<== nxge_param_link_update status = 0x%08x", status)); 2592 return (status); 2593 } 2594