1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 28 */ 29 #include <sys/nxge/nxge_impl.h> 30 #include <sys/nxge/nxge_hio.h> 31 #include <sys/nxge/nxge_rxdma.h> 32 #include <sys/pcie.h> 33 34 uint32_t nxge_use_partition = 0; /* debug partition flag */ 35 uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 36 uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 37 /* 38 * PSARC/2007/453 MSI-X interrupt limit override 39 * (This PSARC case is limited to MSI-X vectors 40 * and SPARC platforms only). 41 */ 42 #if defined(_BIG_ENDIAN) 43 uint32_t nxge_msi_enable = 2; 44 #else 45 uint32_t nxge_msi_enable = 1; 46 #endif 47 48 /* 49 * Software workaround for a Neptune (PCI-E) 50 * hardware interrupt bug which the hardware 51 * may generate spurious interrupts after the 52 * device interrupt handler was removed. If this flag 53 * is enabled, the driver will reset the 54 * hardware when devices are being detached. 55 */ 56 uint32_t nxge_peu_reset_enable = 0; 57 58 /* 59 * Software workaround for the hardware 60 * checksum bugs that affect packet transmission 61 * and receive: 62 * 63 * Usage of nxge_cksum_offload: 64 * 65 * (1) nxge_cksum_offload = 0 (default): 66 * - transmits packets: 67 * TCP: uses the hardware checksum feature. 68 * UDP: driver will compute the software checksum 69 * based on the partial checksum computed 70 * by the IP layer. 71 * - receives packets 72 * TCP: marks packets checksum flags based on hardware result. 73 * UDP: will not mark checksum flags. 74 * 75 * (2) nxge_cksum_offload = 1: 76 * - transmit packets: 77 * TCP/UDP: uses the hardware checksum feature. 78 * - receives packets 79 * TCP/UDP: marks packet checksum flags based on hardware result. 80 * 81 * (3) nxge_cksum_offload = 2: 82 * - The driver will not register its checksum capability. 83 * Checksum for both TCP and UDP will be computed 84 * by the stack. 85 * - The software LSO is not allowed in this case. 86 * 87 * (4) nxge_cksum_offload > 2: 88 * - Will be treated as it is set to 2 89 * (stack will compute the checksum). 90 * 91 * (5) If the hardware bug is fixed, this workaround 92 * needs to be updated accordingly to reflect 93 * the new hardware revision. 94 */ 95 uint32_t nxge_cksum_offload = 0; 96 97 /* 98 * Globals: tunable parameters (/etc/system or adb) 99 * 100 */ 101 uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 102 uint32_t nxge_rbr_spare_size = 0; 103 uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 104 uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 105 boolean_t nxge_no_msg = B_TRUE; /* control message display */ 106 uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 107 uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 108 uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 109 uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 110 uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 111 boolean_t nxge_jumbo_enable = B_FALSE; 112 uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 113 uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 114 nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 115 116 /* MAX LSO size */ 117 #define NXGE_LSO_MAXLEN 65535 118 uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 119 120 /* 121 * Debugging flags: 122 * nxge_no_tx_lb : transmit load balancing 123 * nxge_tx_lb_policy: 0 - TCP port (default) 124 * 3 - DEST MAC 125 */ 126 uint32_t nxge_no_tx_lb = 0; 127 uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 128 129 /* 130 * Add tunable to reduce the amount of time spent in the 131 * ISR doing Rx Processing. 132 */ 133 uint32_t nxge_max_rx_pkts = 1024; 134 135 /* 136 * Tunables to manage the receive buffer blocks. 137 * 138 * nxge_rx_threshold_hi: copy all buffers. 139 * nxge_rx_bcopy_size_type: receive buffer block size type. 140 * nxge_rx_threshold_lo: copy only up to tunable block size type. 141 */ 142 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 143 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 144 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 145 146 /* Use kmem_alloc() to allocate data buffers. */ 147 #if defined(_BIG_ENDIAN) 148 uint32_t nxge_use_kmem_alloc = 1; 149 #else 150 uint32_t nxge_use_kmem_alloc = 0; 151 #endif 152 153 rtrace_t npi_rtracebuf; 154 155 /* 156 * The hardware sometimes fails to allow enough time for the link partner 157 * to send an acknowledgement for packets that the hardware sent to it. The 158 * hardware resends the packets earlier than it should be in those instances. 159 * This behavior caused some switches to acknowledge the wrong packets 160 * and it triggered the fatal error. 161 * This software workaround is to set the replay timer to a value 162 * suggested by the hardware team. 163 * 164 * PCI config space replay timer register: 165 * The following replay timeout value is 0xc 166 * for bit 14:18. 167 */ 168 #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 169 #define PCI_REPLAY_TIMEOUT_SHIFT 14 170 171 uint32_t nxge_set_replay_timer = 1; 172 uint32_t nxge_replay_timeout = 0xc; 173 174 /* 175 * The transmit serialization sometimes causes 176 * longer sleep before calling the driver transmit 177 * function as it sleeps longer than it should. 178 * The performace group suggests that a time wait tunable 179 * can be used to set the maximum wait time when needed 180 * and the default is set to 1 tick. 181 */ 182 uint32_t nxge_tx_serial_maxsleep = 1; 183 184 #if defined(sun4v) 185 /* 186 * Hypervisor N2/NIU services information. 187 */ 188 static hsvc_info_t niu_hsvc = { 189 HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 190 NIU_MINOR_VER, "nxge" 191 }; 192 193 static int nxge_hsvc_register(p_nxge_t); 194 #endif 195 196 /* 197 * Function Prototypes 198 */ 199 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 200 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 201 static void nxge_unattach(p_nxge_t); 202 static int nxge_quiesce(dev_info_t *); 203 204 #if NXGE_PROPERTY 205 static void nxge_remove_hard_properties(p_nxge_t); 206 #endif 207 208 /* 209 * These two functions are required by nxge_hio.c 210 */ 211 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 212 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 213 214 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 215 216 static nxge_status_t nxge_setup_mutexes(p_nxge_t); 217 static void nxge_destroy_mutexes(p_nxge_t); 218 219 static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 220 static void nxge_unmap_regs(p_nxge_t nxgep); 221 #ifdef NXGE_DEBUG 222 static void nxge_test_map_regs(p_nxge_t nxgep); 223 #endif 224 225 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 226 static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 227 static void nxge_remove_intrs(p_nxge_t nxgep); 228 static void nxge_remove_soft_intrs(p_nxge_t nxgep); 229 230 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 231 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 232 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 233 static void nxge_intrs_enable(p_nxge_t nxgep); 234 static void nxge_intrs_disable(p_nxge_t nxgep); 235 236 static void nxge_suspend(p_nxge_t); 237 static nxge_status_t nxge_resume(p_nxge_t); 238 239 static nxge_status_t nxge_setup_dev(p_nxge_t); 240 static void nxge_destroy_dev(p_nxge_t); 241 242 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 243 static void nxge_free_mem_pool(p_nxge_t); 244 245 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 246 static void nxge_free_rx_mem_pool(p_nxge_t); 247 248 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 249 static void nxge_free_tx_mem_pool(p_nxge_t); 250 251 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 252 struct ddi_dma_attr *, 253 size_t, ddi_device_acc_attr_t *, uint_t, 254 p_nxge_dma_common_t); 255 256 static void nxge_dma_mem_free(p_nxge_dma_common_t); 257 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 258 259 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 260 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 261 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 262 263 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 264 p_nxge_dma_common_t *, size_t); 265 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 266 267 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 268 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 269 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 270 271 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 272 p_nxge_dma_common_t *, 273 size_t); 274 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 275 276 static int nxge_init_common_dev(p_nxge_t); 277 static void nxge_uninit_common_dev(p_nxge_t); 278 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 279 char *, caddr_t); 280 281 /* 282 * The next declarations are for the GLDv3 interface. 283 */ 284 static int nxge_m_start(void *); 285 static void nxge_m_stop(void *); 286 static int nxge_m_unicst(void *, const uint8_t *); 287 static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 288 static int nxge_m_promisc(void *, boolean_t); 289 static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 290 static void nxge_m_resources(void *); 291 mblk_t *nxge_m_tx(void *arg, mblk_t *); 292 static nxge_status_t nxge_mac_register(p_nxge_t); 293 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 294 mac_addr_slot_t slot); 295 void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 296 boolean_t factory); 297 static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 298 static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 299 static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 300 static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 301 static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 302 uint_t, const void *); 303 static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 304 uint_t, uint_t, void *); 305 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 306 const void *); 307 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 308 void *); 309 static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 310 311 static void nxge_niu_peu_reset(p_nxge_t nxgep); 312 static void nxge_set_pci_replay_timeout(nxge_t *); 313 314 mac_priv_prop_t nxge_priv_props[] = { 315 {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 316 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 317 {"_function_number", MAC_PROP_PERM_READ}, 318 {"_fw_version", MAC_PROP_PERM_READ}, 319 {"_port_mode", MAC_PROP_PERM_READ}, 320 {"_hot_swap_phy", MAC_PROP_PERM_READ}, 321 {"_accept_jumbo", MAC_PROP_PERM_RW}, 322 {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 323 {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 324 {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 325 {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 326 {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 327 {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 328 {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 329 {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 330 {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 331 {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 332 {"_soft_lso_enable", MAC_PROP_PERM_RW} 333 }; 334 335 #define NXGE_MAX_PRIV_PROPS \ 336 (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 337 338 #define NXGE_M_CALLBACK_FLAGS\ 339 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 340 341 342 #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 343 #define MAX_DUMP_SZ 256 344 345 #define NXGE_M_CALLBACK_FLAGS \ 346 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 347 348 mac_callbacks_t nxge_m_callbacks = { 349 NXGE_M_CALLBACK_FLAGS, 350 nxge_m_stat, 351 nxge_m_start, 352 nxge_m_stop, 353 nxge_m_promisc, 354 nxge_m_multicst, 355 nxge_m_unicst, 356 nxge_m_tx, 357 nxge_m_resources, 358 nxge_m_ioctl, 359 nxge_m_getcapab, 360 NULL, 361 NULL, 362 nxge_m_setprop, 363 nxge_m_getprop 364 }; 365 366 void 367 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 368 369 /* PSARC/2007/453 MSI-X interrupt limit override. */ 370 #define NXGE_MSIX_REQUEST_10G 8 371 #define NXGE_MSIX_REQUEST_1G 2 372 static int nxge_create_msi_property(p_nxge_t); 373 374 /* 375 * These global variables control the message 376 * output. 377 */ 378 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 379 uint64_t nxge_debug_level; 380 381 /* 382 * This list contains the instance structures for the Neptune 383 * devices present in the system. The lock exists to guarantee 384 * mutually exclusive access to the list. 385 */ 386 void *nxge_list = NULL; 387 388 void *nxge_hw_list = NULL; 389 nxge_os_mutex_t nxge_common_lock; 390 391 extern uint64_t npi_debug_level; 392 393 extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 394 extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 395 extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 396 extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 397 extern void nxge_fm_init(p_nxge_t, 398 ddi_device_acc_attr_t *, 399 ddi_device_acc_attr_t *, 400 ddi_dma_attr_t *); 401 extern void nxge_fm_fini(p_nxge_t); 402 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 403 404 /* 405 * Count used to maintain the number of buffers being used 406 * by Neptune instances and loaned up to the upper layers. 407 */ 408 uint32_t nxge_mblks_pending = 0; 409 410 /* 411 * Device register access attributes for PIO. 412 */ 413 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 414 DDI_DEVICE_ATTR_V0, 415 DDI_STRUCTURE_LE_ACC, 416 DDI_STRICTORDER_ACC, 417 }; 418 419 /* 420 * Device descriptor access attributes for DMA. 421 */ 422 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 423 DDI_DEVICE_ATTR_V0, 424 DDI_STRUCTURE_LE_ACC, 425 DDI_STRICTORDER_ACC 426 }; 427 428 /* 429 * Device buffer access attributes for DMA. 430 */ 431 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 432 DDI_DEVICE_ATTR_V0, 433 DDI_STRUCTURE_BE_ACC, 434 DDI_STRICTORDER_ACC 435 }; 436 437 ddi_dma_attr_t nxge_desc_dma_attr = { 438 DMA_ATTR_V0, /* version number. */ 439 0, /* low address */ 440 0xffffffffffffffff, /* high address */ 441 0xffffffffffffffff, /* address counter max */ 442 #ifndef NIU_PA_WORKAROUND 443 0x100000, /* alignment */ 444 #else 445 0x2000, 446 #endif 447 0xfc00fc, /* dlim_burstsizes */ 448 0x1, /* minimum transfer size */ 449 0xffffffffffffffff, /* maximum transfer size */ 450 0xffffffffffffffff, /* maximum segment size */ 451 1, /* scatter/gather list length */ 452 (unsigned int) 1, /* granularity */ 453 0 /* attribute flags */ 454 }; 455 456 ddi_dma_attr_t nxge_tx_dma_attr = { 457 DMA_ATTR_V0, /* version number. */ 458 0, /* low address */ 459 0xffffffffffffffff, /* high address */ 460 0xffffffffffffffff, /* address counter max */ 461 #if defined(_BIG_ENDIAN) 462 0x2000, /* alignment */ 463 #else 464 0x1000, /* alignment */ 465 #endif 466 0xfc00fc, /* dlim_burstsizes */ 467 0x1, /* minimum transfer size */ 468 0xffffffffffffffff, /* maximum transfer size */ 469 0xffffffffffffffff, /* maximum segment size */ 470 5, /* scatter/gather list length */ 471 (unsigned int) 1, /* granularity */ 472 0 /* attribute flags */ 473 }; 474 475 ddi_dma_attr_t nxge_rx_dma_attr = { 476 DMA_ATTR_V0, /* version number. */ 477 0, /* low address */ 478 0xffffffffffffffff, /* high address */ 479 0xffffffffffffffff, /* address counter max */ 480 0x2000, /* alignment */ 481 0xfc00fc, /* dlim_burstsizes */ 482 0x1, /* minimum transfer size */ 483 0xffffffffffffffff, /* maximum transfer size */ 484 0xffffffffffffffff, /* maximum segment size */ 485 1, /* scatter/gather list length */ 486 (unsigned int) 1, /* granularity */ 487 DDI_DMA_RELAXED_ORDERING /* attribute flags */ 488 }; 489 490 ddi_dma_lim_t nxge_dma_limits = { 491 (uint_t)0, /* dlim_addr_lo */ 492 (uint_t)0xffffffff, /* dlim_addr_hi */ 493 (uint_t)0xffffffff, /* dlim_cntr_max */ 494 (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 495 0x1, /* dlim_minxfer */ 496 1024 /* dlim_speed */ 497 }; 498 499 dma_method_t nxge_force_dma = DVMA; 500 501 /* 502 * dma chunk sizes. 503 * 504 * Try to allocate the largest possible size 505 * so that fewer number of dma chunks would be managed 506 */ 507 #ifdef NIU_PA_WORKAROUND 508 size_t alloc_sizes [] = {0x2000}; 509 #else 510 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 511 0x10000, 0x20000, 0x40000, 0x80000, 512 0x100000, 0x200000, 0x400000, 0x800000, 513 0x1000000, 0x2000000, 0x4000000}; 514 #endif 515 516 /* 517 * Translate "dev_t" to a pointer to the associated "dev_info_t". 518 */ 519 520 extern void nxge_get_environs(nxge_t *); 521 522 static int 523 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 524 { 525 p_nxge_t nxgep = NULL; 526 int instance; 527 int status = DDI_SUCCESS; 528 uint8_t portn; 529 nxge_mmac_t *mmac_info; 530 p_nxge_param_t param_arr; 531 532 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 533 534 /* 535 * Get the device instance since we'll need to setup 536 * or retrieve a soft state for this instance. 537 */ 538 instance = ddi_get_instance(dip); 539 540 switch (cmd) { 541 case DDI_ATTACH: 542 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 543 break; 544 545 case DDI_RESUME: 546 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 547 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 548 if (nxgep == NULL) { 549 status = DDI_FAILURE; 550 break; 551 } 552 if (nxgep->dip != dip) { 553 status = DDI_FAILURE; 554 break; 555 } 556 if (nxgep->suspended == DDI_PM_SUSPEND) { 557 status = ddi_dev_is_needed(nxgep->dip, 0, 1); 558 } else { 559 status = nxge_resume(nxgep); 560 } 561 goto nxge_attach_exit; 562 563 case DDI_PM_RESUME: 564 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 565 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 566 if (nxgep == NULL) { 567 status = DDI_FAILURE; 568 break; 569 } 570 if (nxgep->dip != dip) { 571 status = DDI_FAILURE; 572 break; 573 } 574 status = nxge_resume(nxgep); 575 goto nxge_attach_exit; 576 577 default: 578 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 579 status = DDI_FAILURE; 580 goto nxge_attach_exit; 581 } 582 583 584 if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 585 status = DDI_FAILURE; 586 goto nxge_attach_exit; 587 } 588 589 nxgep = ddi_get_soft_state(nxge_list, instance); 590 if (nxgep == NULL) { 591 status = NXGE_ERROR; 592 goto nxge_attach_fail2; 593 } 594 595 nxgep->nxge_magic = NXGE_MAGIC; 596 597 nxgep->drv_state = 0; 598 nxgep->dip = dip; 599 nxgep->instance = instance; 600 nxgep->p_dip = ddi_get_parent(dip); 601 nxgep->nxge_debug_level = nxge_debug_level; 602 npi_debug_level = nxge_debug_level; 603 604 /* Are we a guest running in a Hybrid I/O environment? */ 605 nxge_get_environs(nxgep); 606 607 status = nxge_map_regs(nxgep); 608 609 if (status != NXGE_OK) { 610 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 611 goto nxge_attach_fail3; 612 } 613 614 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 615 &nxge_dev_desc_dma_acc_attr, 616 &nxge_rx_dma_attr); 617 618 /* Create & initialize the per-Neptune data structure */ 619 /* (even if we're a guest). */ 620 status = nxge_init_common_dev(nxgep); 621 if (status != NXGE_OK) { 622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 623 "nxge_init_common_dev failed")); 624 goto nxge_attach_fail4; 625 } 626 627 /* 628 * Software workaround: set the replay timer. 629 */ 630 if (nxgep->niu_type != N2_NIU) { 631 nxge_set_pci_replay_timeout(nxgep); 632 } 633 634 #if defined(sun4v) 635 /* This is required by nxge_hio_init(), which follows. */ 636 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 637 goto nxge_attach_fail4; 638 #endif 639 640 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 641 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 642 "nxge_hio_init failed")); 643 goto nxge_attach_fail4; 644 } 645 646 if (nxgep->niu_type == NEPTUNE_2_10GF) { 647 if (nxgep->function_num > 1) { 648 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 649 " function %d. Only functions 0 and 1 are " 650 "supported for this card.", nxgep->function_num)); 651 status = NXGE_ERROR; 652 goto nxge_attach_fail4; 653 } 654 } 655 656 if (isLDOMguest(nxgep)) { 657 /* 658 * Use the function number here. 659 */ 660 nxgep->mac.portnum = nxgep->function_num; 661 nxgep->mac.porttype = PORT_TYPE_LOGICAL; 662 663 /* XXX We'll set the MAC address counts to 1 for now. */ 664 mmac_info = &nxgep->nxge_mmac_info; 665 mmac_info->num_mmac = 1; 666 mmac_info->naddrfree = 1; 667 } else { 668 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 669 nxgep->mac.portnum = portn; 670 if ((portn == 0) || (portn == 1)) 671 nxgep->mac.porttype = PORT_TYPE_XMAC; 672 else 673 nxgep->mac.porttype = PORT_TYPE_BMAC; 674 /* 675 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 676 * internally, the rest 2 ports use BMAC (1G "Big" MAC). 677 * The two types of MACs have different characterizations. 678 */ 679 mmac_info = &nxgep->nxge_mmac_info; 680 if (nxgep->function_num < 2) { 681 mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 682 mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 683 } else { 684 mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 685 mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 686 } 687 } 688 /* 689 * Setup the Ndd parameters for the this instance. 690 */ 691 nxge_init_param(nxgep); 692 693 /* 694 * Setup Register Tracing Buffer. 695 */ 696 npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 697 698 /* init stats ptr */ 699 nxge_init_statsp(nxgep); 700 701 /* 702 * Copy the vpd info from eeprom to a local data 703 * structure, and then check its validity. 704 */ 705 if (!isLDOMguest(nxgep)) { 706 int *regp; 707 uint_t reglen; 708 int rv; 709 710 nxge_vpd_info_get(nxgep); 711 712 /* Find the NIU config handle. */ 713 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 714 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 715 "reg", ®p, ®len); 716 717 if (rv != DDI_PROP_SUCCESS) { 718 goto nxge_attach_fail5; 719 } 720 /* 721 * The address_hi, that is the first int, in the reg 722 * property consists of config handle, but need to remove 723 * the bits 28-31 which are OBP specific info. 724 */ 725 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 726 ddi_prop_free(regp); 727 } 728 729 if (isLDOMguest(nxgep)) { 730 uchar_t *prop_val; 731 uint_t prop_len; 732 uint32_t max_frame_size; 733 734 extern void nxge_get_logical_props(p_nxge_t); 735 736 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 737 nxgep->mac.portmode = PORT_LOGICAL; 738 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 739 "phy-type", "virtual transceiver"); 740 741 nxgep->nports = 1; 742 nxgep->board_ver = 0; /* XXX What? */ 743 744 /* 745 * local-mac-address property gives us info on which 746 * specific MAC address the Hybrid resource is associated 747 * with. 748 */ 749 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 750 "local-mac-address", &prop_val, 751 &prop_len) != DDI_PROP_SUCCESS) { 752 goto nxge_attach_fail5; 753 } 754 if (prop_len != ETHERADDRL) { 755 ddi_prop_free(prop_val); 756 goto nxge_attach_fail5; 757 } 758 ether_copy(prop_val, nxgep->hio_mac_addr); 759 ddi_prop_free(prop_val); 760 nxge_get_logical_props(nxgep); 761 762 /* 763 * Enable Jumbo property based on the "max-frame-size" 764 * property value. 765 */ 766 max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 767 nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 768 "max-frame-size", NXGE_MTU_DEFAULT_MAX); 769 if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 770 (max_frame_size <= TX_JUMBO_MTU)) { 771 param_arr = nxgep->param_arr; 772 773 param_arr[param_accept_jumbo].value = 1; 774 nxgep->mac.is_jumbo = B_TRUE; 775 nxgep->mac.maxframesize = (uint16_t)max_frame_size; 776 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 777 NXGE_EHEADER_VLAN_CRC; 778 } 779 } else { 780 status = nxge_xcvr_find(nxgep); 781 782 if (status != NXGE_OK) { 783 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 784 " Couldn't determine card type" 785 " .... exit ")); 786 goto nxge_attach_fail5; 787 } 788 789 status = nxge_get_config_properties(nxgep); 790 791 if (status != NXGE_OK) { 792 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 793 "get_hw create failed")); 794 goto nxge_attach_fail; 795 } 796 } 797 798 /* 799 * Setup the Kstats for the driver. 800 */ 801 nxge_setup_kstats(nxgep); 802 803 if (!isLDOMguest(nxgep)) 804 nxge_setup_param(nxgep); 805 806 status = nxge_setup_system_dma_pages(nxgep); 807 if (status != NXGE_OK) { 808 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 809 goto nxge_attach_fail; 810 } 811 812 nxge_hw_id_init(nxgep); 813 814 if (!isLDOMguest(nxgep)) 815 nxge_hw_init_niu_common(nxgep); 816 817 status = nxge_setup_mutexes(nxgep); 818 if (status != NXGE_OK) { 819 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 820 goto nxge_attach_fail; 821 } 822 823 #if defined(sun4v) 824 if (isLDOMguest(nxgep)) { 825 /* Find our VR & channel sets. */ 826 status = nxge_hio_vr_add(nxgep); 827 goto nxge_attach_exit; 828 } 829 #endif 830 831 status = nxge_setup_dev(nxgep); 832 if (status != DDI_SUCCESS) { 833 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 834 goto nxge_attach_fail; 835 } 836 837 status = nxge_add_intrs(nxgep); 838 if (status != DDI_SUCCESS) { 839 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 840 goto nxge_attach_fail; 841 } 842 status = nxge_add_soft_intrs(nxgep); 843 if (status != DDI_SUCCESS) { 844 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 845 "add_soft_intr failed")); 846 goto nxge_attach_fail; 847 } 848 849 /* 850 * Enable interrupts. 851 */ 852 nxge_intrs_enable(nxgep); 853 854 /* If a guest, register with vio_net instead. */ 855 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 856 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 857 "unable to register to mac layer (%d)", status)); 858 goto nxge_attach_fail; 859 } 860 861 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 862 863 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 864 "registered to mac (instance %d)", instance)); 865 866 /* nxge_link_monitor calls xcvr.check_link recursively */ 867 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 868 869 goto nxge_attach_exit; 870 871 nxge_attach_fail: 872 nxge_unattach(nxgep); 873 goto nxge_attach_fail1; 874 875 nxge_attach_fail5: 876 /* 877 * Tear down the ndd parameters setup. 878 */ 879 nxge_destroy_param(nxgep); 880 881 /* 882 * Tear down the kstat setup. 883 */ 884 nxge_destroy_kstats(nxgep); 885 886 nxge_attach_fail4: 887 if (nxgep->nxge_hw_p) { 888 nxge_uninit_common_dev(nxgep); 889 nxgep->nxge_hw_p = NULL; 890 } 891 892 nxge_attach_fail3: 893 /* 894 * Unmap the register setup. 895 */ 896 nxge_unmap_regs(nxgep); 897 898 nxge_fm_fini(nxgep); 899 900 nxge_attach_fail2: 901 ddi_soft_state_free(nxge_list, nxgep->instance); 902 903 nxge_attach_fail1: 904 if (status != NXGE_OK) 905 status = (NXGE_ERROR | NXGE_DDI_FAILED); 906 nxgep = NULL; 907 908 nxge_attach_exit: 909 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 910 status)); 911 912 return (status); 913 } 914 915 static int 916 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 917 { 918 int status = DDI_SUCCESS; 919 int instance; 920 p_nxge_t nxgep = NULL; 921 922 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 923 instance = ddi_get_instance(dip); 924 nxgep = ddi_get_soft_state(nxge_list, instance); 925 if (nxgep == NULL) { 926 status = DDI_FAILURE; 927 goto nxge_detach_exit; 928 } 929 930 switch (cmd) { 931 case DDI_DETACH: 932 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 933 break; 934 935 case DDI_PM_SUSPEND: 936 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 937 nxgep->suspended = DDI_PM_SUSPEND; 938 nxge_suspend(nxgep); 939 break; 940 941 case DDI_SUSPEND: 942 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 943 if (nxgep->suspended != DDI_PM_SUSPEND) { 944 nxgep->suspended = DDI_SUSPEND; 945 nxge_suspend(nxgep); 946 } 947 break; 948 949 default: 950 status = DDI_FAILURE; 951 } 952 953 if (cmd != DDI_DETACH) 954 goto nxge_detach_exit; 955 956 /* 957 * Stop the xcvr polling. 958 */ 959 nxgep->suspended = cmd; 960 961 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 962 963 if (isLDOMguest(nxgep)) { 964 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 965 nxge_m_stop((void *)nxgep); 966 nxge_hio_unregister(nxgep); 967 } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 968 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 969 "<== nxge_detach status = 0x%08X", status)); 970 return (DDI_FAILURE); 971 } 972 973 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 974 "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 975 976 nxge_unattach(nxgep); 977 nxgep = NULL; 978 979 nxge_detach_exit: 980 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 981 status)); 982 983 return (status); 984 } 985 986 static void 987 nxge_unattach(p_nxge_t nxgep) 988 { 989 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 990 991 if (nxgep == NULL || nxgep->dev_regs == NULL) { 992 return; 993 } 994 995 nxgep->nxge_magic = 0; 996 997 if (nxgep->nxge_timerid) { 998 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 999 nxgep->nxge_timerid = 0; 1000 } 1001 1002 /* 1003 * If this flag is set, it will affect the Neptune 1004 * only. 1005 */ 1006 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 1007 nxge_niu_peu_reset(nxgep); 1008 } 1009 1010 #if defined(sun4v) 1011 if (isLDOMguest(nxgep)) { 1012 (void) nxge_hio_vr_release(nxgep); 1013 } 1014 #endif 1015 1016 if (nxgep->nxge_hw_p) { 1017 nxge_uninit_common_dev(nxgep); 1018 nxgep->nxge_hw_p = NULL; 1019 } 1020 1021 #if defined(sun4v) 1022 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 1023 (void) hsvc_unregister(&nxgep->niu_hsvc); 1024 nxgep->niu_hsvc_available = B_FALSE; 1025 } 1026 #endif 1027 /* 1028 * Stop any further interrupts. 1029 */ 1030 nxge_remove_intrs(nxgep); 1031 1032 /* remove soft interrups */ 1033 nxge_remove_soft_intrs(nxgep); 1034 1035 /* 1036 * Stop the device and free resources. 1037 */ 1038 if (!isLDOMguest(nxgep)) { 1039 nxge_destroy_dev(nxgep); 1040 } 1041 1042 /* 1043 * Tear down the ndd parameters setup. 1044 */ 1045 nxge_destroy_param(nxgep); 1046 1047 /* 1048 * Tear down the kstat setup. 1049 */ 1050 nxge_destroy_kstats(nxgep); 1051 1052 /* 1053 * Destroy all mutexes. 1054 */ 1055 nxge_destroy_mutexes(nxgep); 1056 1057 /* 1058 * Remove the list of ndd parameters which 1059 * were setup during attach. 1060 */ 1061 if (nxgep->dip) { 1062 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1063 " nxge_unattach: remove all properties")); 1064 1065 (void) ddi_prop_remove_all(nxgep->dip); 1066 } 1067 1068 #if NXGE_PROPERTY 1069 nxge_remove_hard_properties(nxgep); 1070 #endif 1071 1072 /* 1073 * Unmap the register setup. 1074 */ 1075 nxge_unmap_regs(nxgep); 1076 1077 nxge_fm_fini(nxgep); 1078 1079 ddi_soft_state_free(nxge_list, nxgep->instance); 1080 1081 NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 1082 } 1083 1084 #if defined(sun4v) 1085 int 1086 nxge_hsvc_register(nxge_t *nxgep) 1087 { 1088 nxge_status_t status; 1089 1090 if (nxgep->niu_type == N2_NIU) { 1091 nxgep->niu_hsvc_available = B_FALSE; 1092 bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1093 if ((status = hsvc_register(&nxgep->niu_hsvc, 1094 &nxgep->niu_min_ver)) != 0) { 1095 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1096 "nxge_attach: %s: cannot negotiate " 1097 "hypervisor services revision %d group: 0x%lx " 1098 "major: 0x%lx minor: 0x%lx errno: %d", 1099 niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1100 niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1101 niu_hsvc.hsvc_minor, status)); 1102 return (DDI_FAILURE); 1103 } 1104 nxgep->niu_hsvc_available = B_TRUE; 1105 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1106 "NIU Hypervisor service enabled")); 1107 } 1108 1109 return (DDI_SUCCESS); 1110 } 1111 #endif 1112 1113 static char n2_siu_name[] = "niu"; 1114 1115 static nxge_status_t 1116 nxge_map_regs(p_nxge_t nxgep) 1117 { 1118 int ddi_status = DDI_SUCCESS; 1119 p_dev_regs_t dev_regs; 1120 char buf[MAXPATHLEN + 1]; 1121 char *devname; 1122 #ifdef NXGE_DEBUG 1123 char *sysname; 1124 #endif 1125 off_t regsize; 1126 nxge_status_t status = NXGE_OK; 1127 #if !defined(_BIG_ENDIAN) 1128 off_t pci_offset; 1129 uint16_t pcie_devctl; 1130 #endif 1131 1132 if (isLDOMguest(nxgep)) { 1133 return (nxge_guest_regs_map(nxgep)); 1134 } 1135 1136 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 1137 nxgep->dev_regs = NULL; 1138 dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 1139 dev_regs->nxge_regh = NULL; 1140 dev_regs->nxge_pciregh = NULL; 1141 dev_regs->nxge_msix_regh = NULL; 1142 dev_regs->nxge_vir_regh = NULL; 1143 dev_regs->nxge_vir2_regh = NULL; 1144 nxgep->niu_type = NIU_TYPE_NONE; 1145 1146 devname = ddi_pathname(nxgep->dip, buf); 1147 ASSERT(strlen(devname) > 0); 1148 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1149 "nxge_map_regs: pathname devname %s", devname)); 1150 1151 /* 1152 * The driver is running on a N2-NIU system if devname is something 1153 * like "/niu@80/network@0" 1154 */ 1155 if (strstr(devname, n2_siu_name)) { 1156 /* N2/NIU */ 1157 nxgep->niu_type = N2_NIU; 1158 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1159 "nxge_map_regs: N2/NIU devname %s", devname)); 1160 /* get function number */ 1161 nxgep->function_num = 1162 (devname[strlen(devname) -1] == '1' ? 1 : 0); 1163 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1164 "nxge_map_regs: N2/NIU function number %d", 1165 nxgep->function_num)); 1166 } else { 1167 int *prop_val; 1168 uint_t prop_len; 1169 uint8_t func_num; 1170 1171 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 1172 0, "reg", 1173 &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 1174 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1175 "Reg property not found")); 1176 ddi_status = DDI_FAILURE; 1177 goto nxge_map_regs_fail0; 1178 1179 } else { 1180 func_num = (prop_val[0] >> 8) & 0x7; 1181 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1182 "Reg property found: fun # %d", 1183 func_num)); 1184 nxgep->function_num = func_num; 1185 if (isLDOMguest(nxgep)) { 1186 nxgep->function_num /= 2; 1187 return (NXGE_OK); 1188 } 1189 ddi_prop_free(prop_val); 1190 } 1191 } 1192 1193 switch (nxgep->niu_type) { 1194 default: 1195 (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 1196 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1197 "nxge_map_regs: pci config size 0x%x", regsize)); 1198 1199 ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 1200 (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 1201 &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 1202 if (ddi_status != DDI_SUCCESS) { 1203 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1204 "ddi_map_regs, nxge bus config regs failed")); 1205 goto nxge_map_regs_fail0; 1206 } 1207 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1208 "nxge_map_reg: PCI config addr 0x%0llx " 1209 " handle 0x%0llx", dev_regs->nxge_pciregp, 1210 dev_regs->nxge_pciregh)); 1211 /* 1212 * IMP IMP 1213 * workaround for bit swapping bug in HW 1214 * which ends up in no-snoop = yes 1215 * resulting, in DMA not synched properly 1216 */ 1217 #if !defined(_BIG_ENDIAN) 1218 /* workarounds for x86 systems */ 1219 pci_offset = 0x80 + PCIE_DEVCTL; 1220 pcie_devctl = 0x0; 1221 pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 1222 pcie_devctl |= PCIE_DEVCTL_RO_EN; 1223 pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 1224 pcie_devctl); 1225 #endif 1226 1227 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1228 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1229 "nxge_map_regs: pio size 0x%x", regsize)); 1230 /* set up the device mapped register */ 1231 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1232 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1233 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1234 if (ddi_status != DDI_SUCCESS) { 1235 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1236 "ddi_map_regs for Neptune global reg failed")); 1237 goto nxge_map_regs_fail1; 1238 } 1239 1240 /* set up the msi/msi-x mapped register */ 1241 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1242 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1243 "nxge_map_regs: msix size 0x%x", regsize)); 1244 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1245 (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 1246 &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 1247 if (ddi_status != DDI_SUCCESS) { 1248 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1249 "ddi_map_regs for msi reg failed")); 1250 goto nxge_map_regs_fail2; 1251 } 1252 1253 /* set up the vio region mapped register */ 1254 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1255 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1256 "nxge_map_regs: vio size 0x%x", regsize)); 1257 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1258 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1259 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1260 1261 if (ddi_status != DDI_SUCCESS) { 1262 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1263 "ddi_map_regs for nxge vio reg failed")); 1264 goto nxge_map_regs_fail3; 1265 } 1266 nxgep->dev_regs = dev_regs; 1267 1268 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 1269 NPI_PCI_ADD_HANDLE_SET(nxgep, 1270 (npi_reg_ptr_t)dev_regs->nxge_pciregp); 1271 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 1272 NPI_MSI_ADD_HANDLE_SET(nxgep, 1273 (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 1274 1275 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1276 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1277 1278 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1279 NPI_REG_ADD_HANDLE_SET(nxgep, 1280 (npi_reg_ptr_t)dev_regs->nxge_regp); 1281 1282 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1283 NPI_VREG_ADD_HANDLE_SET(nxgep, 1284 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1285 1286 break; 1287 1288 case N2_NIU: 1289 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 1290 /* 1291 * Set up the device mapped register (FWARC 2006/556) 1292 * (changed back to 1: reg starts at 1!) 1293 */ 1294 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1295 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1296 "nxge_map_regs: dev size 0x%x", regsize)); 1297 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1298 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1299 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1300 1301 if (ddi_status != DDI_SUCCESS) { 1302 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1303 "ddi_map_regs for N2/NIU, global reg failed ")); 1304 goto nxge_map_regs_fail1; 1305 } 1306 1307 /* set up the first vio region mapped register */ 1308 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1309 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1310 "nxge_map_regs: vio (1) size 0x%x", regsize)); 1311 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1312 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1313 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1314 1315 if (ddi_status != DDI_SUCCESS) { 1316 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1317 "ddi_map_regs for nxge vio reg failed")); 1318 goto nxge_map_regs_fail2; 1319 } 1320 /* set up the second vio region mapped register */ 1321 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1322 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1323 "nxge_map_regs: vio (3) size 0x%x", regsize)); 1324 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1325 (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 1326 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 1327 1328 if (ddi_status != DDI_SUCCESS) { 1329 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1330 "ddi_map_regs for nxge vio2 reg failed")); 1331 goto nxge_map_regs_fail3; 1332 } 1333 nxgep->dev_regs = dev_regs; 1334 1335 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1336 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1337 1338 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1339 NPI_REG_ADD_HANDLE_SET(nxgep, 1340 (npi_reg_ptr_t)dev_regs->nxge_regp); 1341 1342 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1343 NPI_VREG_ADD_HANDLE_SET(nxgep, 1344 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1345 1346 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 1347 NPI_V2REG_ADD_HANDLE_SET(nxgep, 1348 (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 1349 1350 break; 1351 } 1352 1353 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 1354 " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 1355 1356 goto nxge_map_regs_exit; 1357 nxge_map_regs_fail3: 1358 if (dev_regs->nxge_msix_regh) { 1359 ddi_regs_map_free(&dev_regs->nxge_msix_regh); 1360 } 1361 if (dev_regs->nxge_vir_regh) { 1362 ddi_regs_map_free(&dev_regs->nxge_regh); 1363 } 1364 nxge_map_regs_fail2: 1365 if (dev_regs->nxge_regh) { 1366 ddi_regs_map_free(&dev_regs->nxge_regh); 1367 } 1368 nxge_map_regs_fail1: 1369 if (dev_regs->nxge_pciregh) { 1370 ddi_regs_map_free(&dev_regs->nxge_pciregh); 1371 } 1372 nxge_map_regs_fail0: 1373 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 1374 kmem_free(dev_regs, sizeof (dev_regs_t)); 1375 1376 nxge_map_regs_exit: 1377 if (ddi_status != DDI_SUCCESS) 1378 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1379 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 1380 return (status); 1381 } 1382 1383 static void 1384 nxge_unmap_regs(p_nxge_t nxgep) 1385 { 1386 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1387 1388 if (isLDOMguest(nxgep)) { 1389 nxge_guest_regs_map_free(nxgep); 1390 return; 1391 } 1392 1393 if (nxgep->dev_regs) { 1394 if (nxgep->dev_regs->nxge_pciregh) { 1395 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1396 "==> nxge_unmap_regs: bus")); 1397 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 1398 nxgep->dev_regs->nxge_pciregh = NULL; 1399 } 1400 if (nxgep->dev_regs->nxge_regh) { 1401 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1402 "==> nxge_unmap_regs: device registers")); 1403 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 1404 nxgep->dev_regs->nxge_regh = NULL; 1405 } 1406 if (nxgep->dev_regs->nxge_msix_regh) { 1407 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1408 "==> nxge_unmap_regs: device interrupts")); 1409 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 1410 nxgep->dev_regs->nxge_msix_regh = NULL; 1411 } 1412 if (nxgep->dev_regs->nxge_vir_regh) { 1413 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1414 "==> nxge_unmap_regs: vio region")); 1415 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 1416 nxgep->dev_regs->nxge_vir_regh = NULL; 1417 } 1418 if (nxgep->dev_regs->nxge_vir2_regh) { 1419 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1420 "==> nxge_unmap_regs: vio2 region")); 1421 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 1422 nxgep->dev_regs->nxge_vir2_regh = NULL; 1423 } 1424 1425 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 1426 nxgep->dev_regs = NULL; 1427 } 1428 1429 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 1430 } 1431 1432 static nxge_status_t 1433 nxge_setup_mutexes(p_nxge_t nxgep) 1434 { 1435 int ddi_status = DDI_SUCCESS; 1436 nxge_status_t status = NXGE_OK; 1437 nxge_classify_t *classify_ptr; 1438 int partition; 1439 1440 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 1441 1442 /* 1443 * Get the interrupt cookie so the mutexes can be 1444 * Initialized. 1445 */ 1446 if (isLDOMguest(nxgep)) { 1447 nxgep->interrupt_cookie = 0; 1448 } else { 1449 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1450 &nxgep->interrupt_cookie); 1451 1452 if (ddi_status != DDI_SUCCESS) { 1453 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1454 "<== nxge_setup_mutexes: failed 0x%x", 1455 ddi_status)); 1456 goto nxge_setup_mutexes_exit; 1457 } 1458 } 1459 1460 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 1461 MUTEX_INIT(&nxgep->poll_lock, NULL, 1462 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1463 1464 /* 1465 * Initialize mutexes for this device. 1466 */ 1467 MUTEX_INIT(nxgep->genlock, NULL, 1468 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1469 MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 1470 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1471 MUTEX_INIT(&nxgep->mif_lock, NULL, 1472 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1473 MUTEX_INIT(&nxgep->group_lock, NULL, 1474 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1475 RW_INIT(&nxgep->filter_lock, NULL, 1476 RW_DRIVER, (void *)nxgep->interrupt_cookie); 1477 1478 classify_ptr = &nxgep->classifier; 1479 /* 1480 * FFLP Mutexes are never used in interrupt context 1481 * as fflp operation can take very long time to 1482 * complete and hence not suitable to invoke from interrupt 1483 * handlers. 1484 */ 1485 MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 1486 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1487 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1488 MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 1489 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1490 for (partition = 0; partition < MAX_PARTITION; partition++) { 1491 MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 1492 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1493 } 1494 } 1495 1496 nxge_setup_mutexes_exit: 1497 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1498 "<== nxge_setup_mutexes status = %x", status)); 1499 1500 if (ddi_status != DDI_SUCCESS) 1501 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1502 1503 return (status); 1504 } 1505 1506 static void 1507 nxge_destroy_mutexes(p_nxge_t nxgep) 1508 { 1509 int partition; 1510 nxge_classify_t *classify_ptr; 1511 1512 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 1513 RW_DESTROY(&nxgep->filter_lock); 1514 MUTEX_DESTROY(&nxgep->group_lock); 1515 MUTEX_DESTROY(&nxgep->mif_lock); 1516 MUTEX_DESTROY(&nxgep->ouraddr_lock); 1517 MUTEX_DESTROY(nxgep->genlock); 1518 1519 classify_ptr = &nxgep->classifier; 1520 MUTEX_DESTROY(&classify_ptr->tcam_lock); 1521 1522 /* Destroy all polling resources. */ 1523 MUTEX_DESTROY(&nxgep->poll_lock); 1524 cv_destroy(&nxgep->poll_cv); 1525 1526 /* free data structures, based on HW type */ 1527 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1528 MUTEX_DESTROY(&classify_ptr->fcram_lock); 1529 for (partition = 0; partition < MAX_PARTITION; partition++) { 1530 MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 1531 } 1532 } 1533 1534 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 1535 } 1536 1537 nxge_status_t 1538 nxge_init(p_nxge_t nxgep) 1539 { 1540 nxge_status_t status = NXGE_OK; 1541 1542 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 1543 1544 if (nxgep->drv_state & STATE_HW_INITIALIZED) { 1545 return (status); 1546 } 1547 1548 /* 1549 * Allocate system memory for the receive/transmit buffer blocks 1550 * and receive/transmit descriptor rings. 1551 */ 1552 status = nxge_alloc_mem_pool(nxgep); 1553 if (status != NXGE_OK) { 1554 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 1555 goto nxge_init_fail1; 1556 } 1557 1558 if (!isLDOMguest(nxgep)) { 1559 /* 1560 * Initialize and enable the TXC registers. 1561 * (Globally enable the Tx controller, 1562 * enable the port, configure the dma channel bitmap, 1563 * configure the max burst size). 1564 */ 1565 status = nxge_txc_init(nxgep); 1566 if (status != NXGE_OK) { 1567 NXGE_ERROR_MSG((nxgep, 1568 NXGE_ERR_CTL, "init txc failed\n")); 1569 goto nxge_init_fail2; 1570 } 1571 } 1572 1573 /* 1574 * Initialize and enable TXDMA channels. 1575 */ 1576 status = nxge_init_txdma_channels(nxgep); 1577 if (status != NXGE_OK) { 1578 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 1579 goto nxge_init_fail3; 1580 } 1581 1582 /* 1583 * Initialize and enable RXDMA channels. 1584 */ 1585 status = nxge_init_rxdma_channels(nxgep); 1586 if (status != NXGE_OK) { 1587 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 1588 goto nxge_init_fail4; 1589 } 1590 1591 /* 1592 * The guest domain is now done. 1593 */ 1594 if (isLDOMguest(nxgep)) { 1595 nxgep->drv_state |= STATE_HW_INITIALIZED; 1596 goto nxge_init_exit; 1597 } 1598 1599 /* 1600 * Initialize TCAM and FCRAM (Neptune). 1601 */ 1602 status = nxge_classify_init(nxgep); 1603 if (status != NXGE_OK) { 1604 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 1605 goto nxge_init_fail5; 1606 } 1607 1608 /* 1609 * Initialize ZCP 1610 */ 1611 status = nxge_zcp_init(nxgep); 1612 if (status != NXGE_OK) { 1613 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 1614 goto nxge_init_fail5; 1615 } 1616 1617 /* 1618 * Initialize IPP. 1619 */ 1620 status = nxge_ipp_init(nxgep); 1621 if (status != NXGE_OK) { 1622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 1623 goto nxge_init_fail5; 1624 } 1625 1626 /* 1627 * Initialize the MAC block. 1628 */ 1629 status = nxge_mac_init(nxgep); 1630 if (status != NXGE_OK) { 1631 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 1632 goto nxge_init_fail5; 1633 } 1634 1635 nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 1636 1637 /* 1638 * Enable hardware interrupts. 1639 */ 1640 nxge_intr_hw_enable(nxgep); 1641 nxgep->drv_state |= STATE_HW_INITIALIZED; 1642 1643 goto nxge_init_exit; 1644 1645 nxge_init_fail5: 1646 nxge_uninit_rxdma_channels(nxgep); 1647 nxge_init_fail4: 1648 nxge_uninit_txdma_channels(nxgep); 1649 nxge_init_fail3: 1650 if (!isLDOMguest(nxgep)) { 1651 (void) nxge_txc_uninit(nxgep); 1652 } 1653 nxge_init_fail2: 1654 nxge_free_mem_pool(nxgep); 1655 nxge_init_fail1: 1656 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1657 "<== nxge_init status (failed) = 0x%08x", status)); 1658 return (status); 1659 1660 nxge_init_exit: 1661 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 1662 status)); 1663 return (status); 1664 } 1665 1666 1667 timeout_id_t 1668 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 1669 { 1670 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 1671 return (timeout(func, (caddr_t)nxgep, 1672 drv_usectohz(1000 * msec))); 1673 } 1674 return (NULL); 1675 } 1676 1677 /*ARGSUSED*/ 1678 void 1679 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 1680 { 1681 if (timerid) { 1682 (void) untimeout(timerid); 1683 } 1684 } 1685 1686 void 1687 nxge_uninit(p_nxge_t nxgep) 1688 { 1689 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 1690 1691 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1692 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1693 "==> nxge_uninit: not initialized")); 1694 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1695 "<== nxge_uninit")); 1696 return; 1697 } 1698 1699 /* stop timer */ 1700 if (nxgep->nxge_timerid) { 1701 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1702 nxgep->nxge_timerid = 0; 1703 } 1704 1705 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1706 (void) nxge_intr_hw_disable(nxgep); 1707 1708 /* 1709 * Reset the receive MAC side. 1710 */ 1711 (void) nxge_rx_mac_disable(nxgep); 1712 1713 /* Disable and soft reset the IPP */ 1714 if (!isLDOMguest(nxgep)) 1715 (void) nxge_ipp_disable(nxgep); 1716 1717 /* Free classification resources */ 1718 (void) nxge_classify_uninit(nxgep); 1719 1720 /* 1721 * Reset the transmit/receive DMA side. 1722 */ 1723 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 1724 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1725 1726 nxge_uninit_txdma_channels(nxgep); 1727 nxge_uninit_rxdma_channels(nxgep); 1728 1729 /* 1730 * Reset the transmit MAC side. 1731 */ 1732 (void) nxge_tx_mac_disable(nxgep); 1733 1734 nxge_free_mem_pool(nxgep); 1735 1736 /* 1737 * Start the timer if the reset flag is not set. 1738 * If this reset flag is set, the link monitor 1739 * will not be started in order to stop furthur bus 1740 * activities coming from this interface. 1741 * The driver will start the monitor function 1742 * if the interface was initialized again later. 1743 */ 1744 if (!nxge_peu_reset_enable) { 1745 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1746 } 1747 1748 nxgep->drv_state &= ~STATE_HW_INITIALIZED; 1749 1750 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 1751 "nxge_mblks_pending %d", nxge_mblks_pending)); 1752 } 1753 1754 void 1755 nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 1756 { 1757 #if defined(__i386) 1758 size_t reg; 1759 #else 1760 uint64_t reg; 1761 #endif 1762 uint64_t regdata; 1763 int i, retry; 1764 1765 bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 1766 regdata = 0; 1767 retry = 1; 1768 1769 for (i = 0; i < retry; i++) { 1770 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 1771 } 1772 bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 1773 } 1774 1775 void 1776 nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 1777 { 1778 #if defined(__i386) 1779 size_t reg; 1780 #else 1781 uint64_t reg; 1782 #endif 1783 uint64_t buf[2]; 1784 1785 bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 1786 #if defined(__i386) 1787 reg = (size_t)buf[0]; 1788 #else 1789 reg = buf[0]; 1790 #endif 1791 1792 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 1793 } 1794 1795 1796 nxge_os_mutex_t nxgedebuglock; 1797 int nxge_debug_init = 0; 1798 1799 /*ARGSUSED*/ 1800 /*VARARGS*/ 1801 void 1802 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 1803 { 1804 char msg_buffer[1048]; 1805 char prefix_buffer[32]; 1806 int instance; 1807 uint64_t debug_level; 1808 int cmn_level = CE_CONT; 1809 va_list ap; 1810 1811 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1812 /* In case a developer has changed nxge_debug_level. */ 1813 if (nxgep->nxge_debug_level != nxge_debug_level) 1814 nxgep->nxge_debug_level = nxge_debug_level; 1815 } 1816 1817 debug_level = (nxgep == NULL) ? nxge_debug_level : 1818 nxgep->nxge_debug_level; 1819 1820 if ((level & debug_level) || 1821 (level == NXGE_NOTE) || 1822 (level == NXGE_ERR_CTL)) { 1823 /* do the msg processing */ 1824 if (nxge_debug_init == 0) { 1825 MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 1826 nxge_debug_init = 1; 1827 } 1828 1829 MUTEX_ENTER(&nxgedebuglock); 1830 1831 if ((level & NXGE_NOTE)) { 1832 cmn_level = CE_NOTE; 1833 } 1834 1835 if (level & NXGE_ERR_CTL) { 1836 cmn_level = CE_WARN; 1837 } 1838 1839 va_start(ap, fmt); 1840 (void) vsprintf(msg_buffer, fmt, ap); 1841 va_end(ap); 1842 if (nxgep == NULL) { 1843 instance = -1; 1844 (void) sprintf(prefix_buffer, "%s :", "nxge"); 1845 } else { 1846 instance = nxgep->instance; 1847 (void) sprintf(prefix_buffer, 1848 "%s%d :", "nxge", instance); 1849 } 1850 1851 MUTEX_EXIT(&nxgedebuglock); 1852 cmn_err(cmn_level, "!%s %s\n", 1853 prefix_buffer, msg_buffer); 1854 1855 } 1856 } 1857 1858 char * 1859 nxge_dump_packet(char *addr, int size) 1860 { 1861 uchar_t *ap = (uchar_t *)addr; 1862 int i; 1863 static char etherbuf[1024]; 1864 char *cp = etherbuf; 1865 char digits[] = "0123456789abcdef"; 1866 1867 if (!size) 1868 size = 60; 1869 1870 if (size > MAX_DUMP_SZ) { 1871 /* Dump the leading bytes */ 1872 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1873 if (*ap > 0x0f) 1874 *cp++ = digits[*ap >> 4]; 1875 *cp++ = digits[*ap++ & 0xf]; 1876 *cp++ = ':'; 1877 } 1878 for (i = 0; i < 20; i++) 1879 *cp++ = '.'; 1880 /* Dump the last MAX_DUMP_SZ/2 bytes */ 1881 ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 1882 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1883 if (*ap > 0x0f) 1884 *cp++ = digits[*ap >> 4]; 1885 *cp++ = digits[*ap++ & 0xf]; 1886 *cp++ = ':'; 1887 } 1888 } else { 1889 for (i = 0; i < size; i++) { 1890 if (*ap > 0x0f) 1891 *cp++ = digits[*ap >> 4]; 1892 *cp++ = digits[*ap++ & 0xf]; 1893 *cp++ = ':'; 1894 } 1895 } 1896 *--cp = 0; 1897 return (etherbuf); 1898 } 1899 1900 #ifdef NXGE_DEBUG 1901 static void 1902 nxge_test_map_regs(p_nxge_t nxgep) 1903 { 1904 ddi_acc_handle_t cfg_handle; 1905 p_pci_cfg_t cfg_ptr; 1906 ddi_acc_handle_t dev_handle; 1907 char *dev_ptr; 1908 ddi_acc_handle_t pci_config_handle; 1909 uint32_t regval; 1910 int i; 1911 1912 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 1913 1914 dev_handle = nxgep->dev_regs->nxge_regh; 1915 dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 1916 1917 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1918 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1919 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1920 1921 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1922 "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 1923 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1924 "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 1925 &cfg_ptr->vendorid)); 1926 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1927 "\tvendorid 0x%x devid 0x%x", 1928 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 1929 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 1930 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1931 "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 1932 "bar1c 0x%x", 1933 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 1934 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 1935 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 1936 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 1937 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1938 "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 1939 "base 28 0x%x bar2c 0x%x\n", 1940 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 1941 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 1942 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 1943 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 1944 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1945 "\nNeptune PCI BAR: base30 0x%x\n", 1946 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 1947 1948 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1949 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1950 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1951 "first 0x%llx second 0x%llx third 0x%llx " 1952 "last 0x%llx ", 1953 NXGE_PIO_READ64(dev_handle, 1954 (uint64_t *)(dev_ptr + 0), 0), 1955 NXGE_PIO_READ64(dev_handle, 1956 (uint64_t *)(dev_ptr + 8), 0), 1957 NXGE_PIO_READ64(dev_handle, 1958 (uint64_t *)(dev_ptr + 16), 0), 1959 NXGE_PIO_READ64(cfg_handle, 1960 (uint64_t *)(dev_ptr + 24), 0))); 1961 } 1962 } 1963 1964 #endif 1965 1966 static void 1967 nxge_suspend(p_nxge_t nxgep) 1968 { 1969 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 1970 1971 nxge_intrs_disable(nxgep); 1972 nxge_destroy_dev(nxgep); 1973 1974 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 1975 } 1976 1977 static nxge_status_t 1978 nxge_resume(p_nxge_t nxgep) 1979 { 1980 nxge_status_t status = NXGE_OK; 1981 1982 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 1983 1984 nxgep->suspended = DDI_RESUME; 1985 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1986 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1987 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 1988 (void) nxge_rx_mac_enable(nxgep); 1989 (void) nxge_tx_mac_enable(nxgep); 1990 nxge_intrs_enable(nxgep); 1991 nxgep->suspended = 0; 1992 1993 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1994 "<== nxge_resume status = 0x%x", status)); 1995 return (status); 1996 } 1997 1998 static nxge_status_t 1999 nxge_setup_dev(p_nxge_t nxgep) 2000 { 2001 nxge_status_t status = NXGE_OK; 2002 2003 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 2004 nxgep->mac.portnum)); 2005 2006 status = nxge_link_init(nxgep); 2007 2008 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 2009 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2010 "port%d Bad register acc handle", nxgep->mac.portnum)); 2011 status = NXGE_ERROR; 2012 } 2013 2014 if (status != NXGE_OK) { 2015 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2016 " nxge_setup_dev status " 2017 "(xcvr init 0x%08x)", status)); 2018 goto nxge_setup_dev_exit; 2019 } 2020 2021 nxge_setup_dev_exit: 2022 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2023 "<== nxge_setup_dev port %d status = 0x%08x", 2024 nxgep->mac.portnum, status)); 2025 2026 return (status); 2027 } 2028 2029 static void 2030 nxge_destroy_dev(p_nxge_t nxgep) 2031 { 2032 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 2033 2034 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2035 2036 (void) nxge_hw_stop(nxgep); 2037 2038 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 2039 } 2040 2041 static nxge_status_t 2042 nxge_setup_system_dma_pages(p_nxge_t nxgep) 2043 { 2044 int ddi_status = DDI_SUCCESS; 2045 uint_t count; 2046 ddi_dma_cookie_t cookie; 2047 uint_t iommu_pagesize; 2048 nxge_status_t status = NXGE_OK; 2049 2050 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 2051 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 2052 if (nxgep->niu_type != N2_NIU) { 2053 iommu_pagesize = dvma_pagesize(nxgep->dip); 2054 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2055 " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2056 " default_block_size %d iommu_pagesize %d", 2057 nxgep->sys_page_sz, 2058 ddi_ptob(nxgep->dip, (ulong_t)1), 2059 nxgep->rx_default_block_size, 2060 iommu_pagesize)); 2061 2062 if (iommu_pagesize != 0) { 2063 if (nxgep->sys_page_sz == iommu_pagesize) { 2064 if (iommu_pagesize > 0x4000) 2065 nxgep->sys_page_sz = 0x4000; 2066 } else { 2067 if (nxgep->sys_page_sz > iommu_pagesize) 2068 nxgep->sys_page_sz = iommu_pagesize; 2069 } 2070 } 2071 } 2072 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2073 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2074 "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2075 "default_block_size %d page mask %d", 2076 nxgep->sys_page_sz, 2077 ddi_ptob(nxgep->dip, (ulong_t)1), 2078 nxgep->rx_default_block_size, 2079 nxgep->sys_page_mask)); 2080 2081 2082 switch (nxgep->sys_page_sz) { 2083 default: 2084 nxgep->sys_page_sz = 0x1000; 2085 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2086 nxgep->rx_default_block_size = 0x1000; 2087 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2088 break; 2089 case 0x1000: 2090 nxgep->rx_default_block_size = 0x1000; 2091 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2092 break; 2093 case 0x2000: 2094 nxgep->rx_default_block_size = 0x2000; 2095 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2096 break; 2097 case 0x4000: 2098 nxgep->rx_default_block_size = 0x4000; 2099 nxgep->rx_bksize_code = RBR_BKSIZE_16K; 2100 break; 2101 case 0x8000: 2102 nxgep->rx_default_block_size = 0x8000; 2103 nxgep->rx_bksize_code = RBR_BKSIZE_32K; 2104 break; 2105 } 2106 2107 #ifndef USE_RX_BIG_BUF 2108 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 2109 #else 2110 nxgep->rx_default_block_size = 0x2000; 2111 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2112 #endif 2113 /* 2114 * Get the system DMA burst size. 2115 */ 2116 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 2117 DDI_DMA_DONTWAIT, 0, 2118 &nxgep->dmasparehandle); 2119 if (ddi_status != DDI_SUCCESS) { 2120 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2121 "ddi_dma_alloc_handle: failed " 2122 " status 0x%x", ddi_status)); 2123 goto nxge_get_soft_properties_exit; 2124 } 2125 2126 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 2127 (caddr_t)nxgep->dmasparehandle, 2128 sizeof (nxgep->dmasparehandle), 2129 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2130 DDI_DMA_DONTWAIT, 0, 2131 &cookie, &count); 2132 if (ddi_status != DDI_DMA_MAPPED) { 2133 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2134 "Binding spare handle to find system" 2135 " burstsize failed.")); 2136 ddi_status = DDI_FAILURE; 2137 goto nxge_get_soft_properties_fail1; 2138 } 2139 2140 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 2141 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 2142 2143 nxge_get_soft_properties_fail1: 2144 ddi_dma_free_handle(&nxgep->dmasparehandle); 2145 2146 nxge_get_soft_properties_exit: 2147 2148 if (ddi_status != DDI_SUCCESS) 2149 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2150 2151 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2152 "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 2153 return (status); 2154 } 2155 2156 static nxge_status_t 2157 nxge_alloc_mem_pool(p_nxge_t nxgep) 2158 { 2159 nxge_status_t status = NXGE_OK; 2160 2161 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 2162 2163 status = nxge_alloc_rx_mem_pool(nxgep); 2164 if (status != NXGE_OK) { 2165 return (NXGE_ERROR); 2166 } 2167 2168 status = nxge_alloc_tx_mem_pool(nxgep); 2169 if (status != NXGE_OK) { 2170 nxge_free_rx_mem_pool(nxgep); 2171 return (NXGE_ERROR); 2172 } 2173 2174 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 2175 return (NXGE_OK); 2176 } 2177 2178 static void 2179 nxge_free_mem_pool(p_nxge_t nxgep) 2180 { 2181 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 2182 2183 nxge_free_rx_mem_pool(nxgep); 2184 nxge_free_tx_mem_pool(nxgep); 2185 2186 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 2187 } 2188 2189 nxge_status_t 2190 nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 2191 { 2192 uint32_t rdc_max; 2193 p_nxge_dma_pt_cfg_t p_all_cfgp; 2194 p_nxge_hw_pt_cfg_t p_cfgp; 2195 p_nxge_dma_pool_t dma_poolp; 2196 p_nxge_dma_common_t *dma_buf_p; 2197 p_nxge_dma_pool_t dma_cntl_poolp; 2198 p_nxge_dma_common_t *dma_cntl_p; 2199 uint32_t *num_chunks; /* per dma */ 2200 nxge_status_t status = NXGE_OK; 2201 2202 uint32_t nxge_port_rbr_size; 2203 uint32_t nxge_port_rbr_spare_size; 2204 uint32_t nxge_port_rcr_size; 2205 uint32_t rx_cntl_alloc_size; 2206 2207 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 2208 2209 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2210 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2211 rdc_max = NXGE_MAX_RDCS; 2212 2213 /* 2214 * Allocate memory for the common DMA data structures. 2215 */ 2216 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2217 KM_SLEEP); 2218 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2219 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2220 2221 dma_cntl_poolp = (p_nxge_dma_pool_t) 2222 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2223 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2224 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2225 2226 num_chunks = (uint32_t *)KMEM_ZALLOC( 2227 sizeof (uint32_t) * rdc_max, KM_SLEEP); 2228 2229 /* 2230 * Assume that each DMA channel will be configured with 2231 * the default block size. 2232 * rbr block counts are modulo the batch count (16). 2233 */ 2234 nxge_port_rbr_size = p_all_cfgp->rbr_size; 2235 nxge_port_rcr_size = p_all_cfgp->rcr_size; 2236 2237 if (!nxge_port_rbr_size) { 2238 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 2239 } 2240 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 2241 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 2242 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 2243 } 2244 2245 p_all_cfgp->rbr_size = nxge_port_rbr_size; 2246 nxge_port_rbr_spare_size = nxge_rbr_spare_size; 2247 2248 if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 2249 nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 2250 (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 2251 } 2252 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 2253 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2254 "nxge_alloc_rx_mem_pool: RBR size too high %d, " 2255 "set to default %d", 2256 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 2257 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 2258 } 2259 if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 2260 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2261 "nxge_alloc_rx_mem_pool: RCR too high %d, " 2262 "set to default %d", 2263 nxge_port_rcr_size, RCR_DEFAULT_MAX)); 2264 nxge_port_rcr_size = RCR_DEFAULT_MAX; 2265 } 2266 2267 /* 2268 * N2/NIU has limitation on the descriptor sizes (contiguous 2269 * memory allocation on data buffers to 4M (contig_mem_alloc) 2270 * and little endian for control buffers (must use the ddi/dki mem alloc 2271 * function). 2272 */ 2273 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2274 if (nxgep->niu_type == N2_NIU) { 2275 nxge_port_rbr_spare_size = 0; 2276 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 2277 (!ISP2(nxge_port_rbr_size))) { 2278 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 2279 } 2280 if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 2281 (!ISP2(nxge_port_rcr_size))) { 2282 nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 2283 } 2284 } 2285 #endif 2286 2287 /* 2288 * Addresses of receive block ring, receive completion ring and the 2289 * mailbox must be all cache-aligned (64 bytes). 2290 */ 2291 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 2292 rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 2293 rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 2294 rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 2295 2296 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 2297 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 2298 "nxge_port_rcr_size = %d " 2299 "rx_cntl_alloc_size = %d", 2300 nxge_port_rbr_size, nxge_port_rbr_spare_size, 2301 nxge_port_rcr_size, 2302 rx_cntl_alloc_size)); 2303 2304 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2305 if (nxgep->niu_type == N2_NIU) { 2306 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2307 (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2308 2309 if (!ISP2(rx_buf_alloc_size)) { 2310 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2311 "==> nxge_alloc_rx_mem_pool: " 2312 " must be power of 2")); 2313 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2314 goto nxge_alloc_rx_mem_pool_exit; 2315 } 2316 2317 if (rx_buf_alloc_size > (1 << 22)) { 2318 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2319 "==> nxge_alloc_rx_mem_pool: " 2320 " limit size to 4M")); 2321 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2322 goto nxge_alloc_rx_mem_pool_exit; 2323 } 2324 2325 if (rx_cntl_alloc_size < 0x2000) { 2326 rx_cntl_alloc_size = 0x2000; 2327 } 2328 } 2329 #endif 2330 nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 2331 nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2332 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2333 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 2334 2335 dma_poolp->ndmas = p_cfgp->max_rdcs; 2336 dma_poolp->num_chunks = num_chunks; 2337 dma_poolp->buf_allocated = B_TRUE; 2338 nxgep->rx_buf_pool_p = dma_poolp; 2339 dma_poolp->dma_buf_pool_p = dma_buf_p; 2340 2341 dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 2342 dma_cntl_poolp->buf_allocated = B_TRUE; 2343 nxgep->rx_cntl_pool_p = dma_cntl_poolp; 2344 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2345 2346 /* Allocate the receive rings, too. */ 2347 nxgep->rx_rbr_rings = 2348 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2349 nxgep->rx_rbr_rings->rbr_rings = 2350 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2351 nxgep->rx_rcr_rings = 2352 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2353 nxgep->rx_rcr_rings->rcr_rings = 2354 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2355 nxgep->rx_mbox_areas_p = 2356 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2357 nxgep->rx_mbox_areas_p->rxmbox_areas = 2358 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2359 2360 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2361 p_cfgp->max_rdcs; 2362 2363 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2364 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2365 2366 nxge_alloc_rx_mem_pool_exit: 2367 return (status); 2368 } 2369 2370 /* 2371 * nxge_alloc_rxb 2372 * 2373 * Allocate buffers for an RDC. 2374 * 2375 * Arguments: 2376 * nxgep 2377 * channel The channel to map into our kernel space. 2378 * 2379 * Notes: 2380 * 2381 * NPI function calls: 2382 * 2383 * NXGE function calls: 2384 * 2385 * Registers accessed: 2386 * 2387 * Context: 2388 * 2389 * Taking apart: 2390 * 2391 * Open questions: 2392 * 2393 */ 2394 nxge_status_t 2395 nxge_alloc_rxb( 2396 p_nxge_t nxgep, 2397 int channel) 2398 { 2399 size_t rx_buf_alloc_size; 2400 nxge_status_t status = NXGE_OK; 2401 2402 nxge_dma_common_t **data; 2403 nxge_dma_common_t **control; 2404 uint32_t *num_chunks; 2405 2406 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2407 2408 /* 2409 * Allocate memory for the receive buffers and descriptor rings. 2410 * Replace these allocation functions with the interface functions 2411 * provided by the partition manager if/when they are available. 2412 */ 2413 2414 /* 2415 * Allocate memory for the receive buffer blocks. 2416 */ 2417 rx_buf_alloc_size = (nxgep->rx_default_block_size * 2418 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2419 2420 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2421 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2422 2423 if ((status = nxge_alloc_rx_buf_dma( 2424 nxgep, channel, data, rx_buf_alloc_size, 2425 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2426 return (status); 2427 } 2428 2429 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2430 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2431 2432 /* 2433 * Allocate memory for descriptor rings and mailbox. 2434 */ 2435 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2436 2437 if ((status = nxge_alloc_rx_cntl_dma( 2438 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2439 != NXGE_OK) { 2440 nxge_free_rx_cntl_dma(nxgep, *control); 2441 (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2442 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2443 return (status); 2444 } 2445 2446 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2447 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2448 2449 return (status); 2450 } 2451 2452 void 2453 nxge_free_rxb( 2454 p_nxge_t nxgep, 2455 int channel) 2456 { 2457 nxge_dma_common_t *data; 2458 nxge_dma_common_t *control; 2459 uint32_t num_chunks; 2460 2461 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2462 2463 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2464 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2465 nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2466 2467 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2468 nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2469 2470 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2471 nxge_free_rx_cntl_dma(nxgep, control); 2472 2473 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2474 2475 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2476 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2477 2478 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2479 } 2480 2481 static void 2482 nxge_free_rx_mem_pool(p_nxge_t nxgep) 2483 { 2484 int rdc_max = NXGE_MAX_RDCS; 2485 2486 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 2487 2488 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 2489 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2490 "<== nxge_free_rx_mem_pool " 2491 "(null rx buf pool or buf not allocated")); 2492 return; 2493 } 2494 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 2495 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2496 "<== nxge_free_rx_mem_pool " 2497 "(null rx cntl buf pool or cntl buf not allocated")); 2498 return; 2499 } 2500 2501 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2502 sizeof (p_nxge_dma_common_t) * rdc_max); 2503 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 2504 2505 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2506 sizeof (uint32_t) * rdc_max); 2507 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2508 sizeof (p_nxge_dma_common_t) * rdc_max); 2509 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 2510 2511 nxgep->rx_buf_pool_p = 0; 2512 nxgep->rx_cntl_pool_p = 0; 2513 2514 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2515 sizeof (p_rx_rbr_ring_t) * rdc_max); 2516 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2517 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2518 sizeof (p_rx_rcr_ring_t) * rdc_max); 2519 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2520 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2521 sizeof (p_rx_mbox_t) * rdc_max); 2522 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2523 2524 nxgep->rx_rbr_rings = 0; 2525 nxgep->rx_rcr_rings = 0; 2526 nxgep->rx_mbox_areas_p = 0; 2527 2528 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 2529 } 2530 2531 2532 static nxge_status_t 2533 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2534 p_nxge_dma_common_t *dmap, 2535 size_t alloc_size, size_t block_size, uint32_t *num_chunks) 2536 { 2537 p_nxge_dma_common_t rx_dmap; 2538 nxge_status_t status = NXGE_OK; 2539 size_t total_alloc_size; 2540 size_t allocated = 0; 2541 int i, size_index, array_size; 2542 boolean_t use_kmem_alloc = B_FALSE; 2543 2544 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 2545 2546 rx_dmap = (p_nxge_dma_common_t) 2547 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 2548 KM_SLEEP); 2549 2550 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2551 " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 2552 dma_channel, alloc_size, block_size, dmap)); 2553 2554 total_alloc_size = alloc_size; 2555 2556 #if defined(RX_USE_RECLAIM_POST) 2557 total_alloc_size = alloc_size + alloc_size/4; 2558 #endif 2559 2560 i = 0; 2561 size_index = 0; 2562 array_size = sizeof (alloc_sizes)/sizeof (size_t); 2563 while ((alloc_sizes[size_index] < alloc_size) && 2564 (size_index < array_size)) 2565 size_index++; 2566 if (size_index >= array_size) { 2567 size_index = array_size - 1; 2568 } 2569 2570 /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2571 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2572 use_kmem_alloc = B_TRUE; 2573 #if defined(__i386) || defined(__amd64) 2574 size_index = 0; 2575 #endif 2576 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2577 "==> nxge_alloc_rx_buf_dma: " 2578 "Neptune use kmem_alloc() - size_index %d", 2579 size_index)); 2580 } 2581 2582 while ((allocated < total_alloc_size) && 2583 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 2584 rx_dmap[i].dma_chunk_index = i; 2585 rx_dmap[i].block_size = block_size; 2586 rx_dmap[i].alength = alloc_sizes[size_index]; 2587 rx_dmap[i].orig_alength = rx_dmap[i].alength; 2588 rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 2589 rx_dmap[i].dma_channel = dma_channel; 2590 rx_dmap[i].contig_alloc_type = B_FALSE; 2591 rx_dmap[i].kmem_alloc_type = B_FALSE; 2592 rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 2593 2594 /* 2595 * N2/NIU: data buffers must be contiguous as the driver 2596 * needs to call Hypervisor api to set up 2597 * logical pages. 2598 */ 2599 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 2600 rx_dmap[i].contig_alloc_type = B_TRUE; 2601 rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2602 } else if (use_kmem_alloc) { 2603 /* For Neptune, use kmem_alloc */ 2604 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2605 "==> nxge_alloc_rx_buf_dma: " 2606 "Neptune use kmem_alloc()")); 2607 rx_dmap[i].kmem_alloc_type = B_TRUE; 2608 rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 2609 } 2610 2611 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2612 "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 2613 "i %d nblocks %d alength %d", 2614 dma_channel, i, &rx_dmap[i], block_size, 2615 i, rx_dmap[i].nblocks, 2616 rx_dmap[i].alength)); 2617 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2618 &nxge_rx_dma_attr, 2619 rx_dmap[i].alength, 2620 &nxge_dev_buf_dma_acc_attr, 2621 DDI_DMA_READ | DDI_DMA_STREAMING, 2622 (p_nxge_dma_common_t)(&rx_dmap[i])); 2623 if (status != NXGE_OK) { 2624 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2625 "nxge_alloc_rx_buf_dma: Alloc Failed: " 2626 "dma %d size_index %d size requested %d", 2627 dma_channel, 2628 size_index, 2629 rx_dmap[i].alength)); 2630 size_index--; 2631 } else { 2632 rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2633 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2634 " nxge_alloc_rx_buf_dma DONE alloc mem: " 2635 "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2636 "buf_alloc_state %d alloc_type %d", 2637 dma_channel, 2638 &rx_dmap[i], 2639 rx_dmap[i].kaddrp, 2640 rx_dmap[i].alength, 2641 rx_dmap[i].buf_alloc_state, 2642 rx_dmap[i].buf_alloc_type)); 2643 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2644 " alloc_rx_buf_dma allocated rdc %d " 2645 "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2646 dma_channel, i, rx_dmap[i].alength, 2647 rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2648 rx_dmap[i].kaddrp)); 2649 i++; 2650 allocated += alloc_sizes[size_index]; 2651 } 2652 } 2653 2654 if (allocated < total_alloc_size) { 2655 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2656 "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 2657 "allocated 0x%x requested 0x%x", 2658 dma_channel, 2659 allocated, total_alloc_size)); 2660 status = NXGE_ERROR; 2661 goto nxge_alloc_rx_mem_fail1; 2662 } 2663 2664 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2665 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 2666 "allocated 0x%x requested 0x%x", 2667 dma_channel, 2668 allocated, total_alloc_size)); 2669 2670 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2671 " alloc_rx_buf_dma rdc %d allocated %d chunks", 2672 dma_channel, i)); 2673 *num_chunks = i; 2674 *dmap = rx_dmap; 2675 2676 goto nxge_alloc_rx_mem_exit; 2677 2678 nxge_alloc_rx_mem_fail1: 2679 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2680 2681 nxge_alloc_rx_mem_exit: 2682 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2683 "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 2684 2685 return (status); 2686 } 2687 2688 /*ARGSUSED*/ 2689 static void 2690 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 2691 uint32_t num_chunks) 2692 { 2693 int i; 2694 2695 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2696 "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 2697 2698 if (dmap == 0) 2699 return; 2700 2701 for (i = 0; i < num_chunks; i++) { 2702 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2703 "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 2704 i, dmap)); 2705 nxge_dma_free_rx_data_buf(dmap++); 2706 } 2707 2708 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 2709 } 2710 2711 /*ARGSUSED*/ 2712 static nxge_status_t 2713 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 2714 p_nxge_dma_common_t *dmap, size_t size) 2715 { 2716 p_nxge_dma_common_t rx_dmap; 2717 nxge_status_t status = NXGE_OK; 2718 2719 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 2720 2721 rx_dmap = (p_nxge_dma_common_t) 2722 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 2723 2724 rx_dmap->contig_alloc_type = B_FALSE; 2725 rx_dmap->kmem_alloc_type = B_FALSE; 2726 2727 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2728 &nxge_desc_dma_attr, 2729 size, 2730 &nxge_dev_desc_dma_acc_attr, 2731 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2732 rx_dmap); 2733 if (status != NXGE_OK) { 2734 goto nxge_alloc_rx_cntl_dma_fail1; 2735 } 2736 2737 *dmap = rx_dmap; 2738 goto nxge_alloc_rx_cntl_dma_exit; 2739 2740 nxge_alloc_rx_cntl_dma_fail1: 2741 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 2742 2743 nxge_alloc_rx_cntl_dma_exit: 2744 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2745 "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 2746 2747 return (status); 2748 } 2749 2750 /*ARGSUSED*/ 2751 static void 2752 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2753 { 2754 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2755 2756 if (dmap == 0) 2757 return; 2758 2759 nxge_dma_mem_free(dmap); 2760 2761 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2762 } 2763 2764 typedef struct { 2765 size_t tx_size; 2766 size_t cr_size; 2767 size_t threshhold; 2768 } nxge_tdc_sizes_t; 2769 2770 static 2771 nxge_status_t 2772 nxge_tdc_sizes( 2773 nxge_t *nxgep, 2774 nxge_tdc_sizes_t *sizes) 2775 { 2776 uint32_t threshhold; /* The bcopy() threshhold */ 2777 size_t tx_size; /* Transmit buffer size */ 2778 size_t cr_size; /* Completion ring size */ 2779 2780 /* 2781 * Assume that each DMA channel will be configured with the 2782 * default transmit buffer size for copying transmit data. 2783 * (If a packet is bigger than this, it will not be copied.) 2784 */ 2785 if (nxgep->niu_type == N2_NIU) { 2786 threshhold = TX_BCOPY_SIZE; 2787 } else { 2788 threshhold = nxge_bcopy_thresh; 2789 } 2790 tx_size = nxge_tx_ring_size * threshhold; 2791 2792 cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2793 cr_size += sizeof (txdma_mailbox_t); 2794 2795 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2796 if (nxgep->niu_type == N2_NIU) { 2797 if (!ISP2(tx_size)) { 2798 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2799 "==> nxge_tdc_sizes: Tx size" 2800 " must be power of 2")); 2801 return (NXGE_ERROR); 2802 } 2803 2804 if (tx_size > (1 << 22)) { 2805 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2806 "==> nxge_tdc_sizes: Tx size" 2807 " limited to 4M")); 2808 return (NXGE_ERROR); 2809 } 2810 2811 if (cr_size < 0x2000) 2812 cr_size = 0x2000; 2813 } 2814 #endif 2815 2816 sizes->threshhold = threshhold; 2817 sizes->tx_size = tx_size; 2818 sizes->cr_size = cr_size; 2819 2820 return (NXGE_OK); 2821 } 2822 /* 2823 * nxge_alloc_txb 2824 * 2825 * Allocate buffers for an TDC. 2826 * 2827 * Arguments: 2828 * nxgep 2829 * channel The channel to map into our kernel space. 2830 * 2831 * Notes: 2832 * 2833 * NPI function calls: 2834 * 2835 * NXGE function calls: 2836 * 2837 * Registers accessed: 2838 * 2839 * Context: 2840 * 2841 * Taking apart: 2842 * 2843 * Open questions: 2844 * 2845 */ 2846 nxge_status_t 2847 nxge_alloc_txb( 2848 p_nxge_t nxgep, 2849 int channel) 2850 { 2851 nxge_dma_common_t **dma_buf_p; 2852 nxge_dma_common_t **dma_cntl_p; 2853 uint32_t *num_chunks; 2854 nxge_status_t status = NXGE_OK; 2855 2856 nxge_tdc_sizes_t sizes; 2857 2858 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2859 2860 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2861 return (NXGE_ERROR); 2862 2863 /* 2864 * Allocate memory for transmit buffers and descriptor rings. 2865 * Replace these allocation functions with the interface functions 2866 * provided by the partition manager Real Soon Now. 2867 */ 2868 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2869 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2870 2871 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2872 2873 /* 2874 * Allocate memory for transmit buffers and descriptor rings. 2875 * Replace allocation functions with interface functions provided 2876 * by the partition manager when it is available. 2877 * 2878 * Allocate memory for the transmit buffer pool. 2879 */ 2880 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2881 "sizes: tx: %ld, cr:%ld, th:%ld", 2882 sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2883 2884 *num_chunks = 0; 2885 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2886 sizes.tx_size, sizes.threshhold, num_chunks); 2887 if (status != NXGE_OK) { 2888 cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2889 return (status); 2890 } 2891 2892 /* 2893 * Allocate memory for descriptor rings and mailbox. 2894 */ 2895 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2896 sizes.cr_size); 2897 if (status != NXGE_OK) { 2898 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2899 cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2900 return (status); 2901 } 2902 2903 return (NXGE_OK); 2904 } 2905 2906 void 2907 nxge_free_txb( 2908 p_nxge_t nxgep, 2909 int channel) 2910 { 2911 nxge_dma_common_t *data; 2912 nxge_dma_common_t *control; 2913 uint32_t num_chunks; 2914 2915 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2916 2917 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2918 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2919 nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2920 2921 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2922 nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2923 2924 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2925 nxge_free_tx_cntl_dma(nxgep, control); 2926 2927 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2928 2929 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2930 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2931 2932 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 2933 } 2934 2935 /* 2936 * nxge_alloc_tx_mem_pool 2937 * 2938 * This function allocates all of the per-port TDC control data structures. 2939 * The per-channel (TDC) data structures are allocated when needed. 2940 * 2941 * Arguments: 2942 * nxgep 2943 * 2944 * Notes: 2945 * 2946 * Context: 2947 * Any domain 2948 */ 2949 nxge_status_t 2950 nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 2951 { 2952 nxge_hw_pt_cfg_t *p_cfgp; 2953 nxge_dma_pool_t *dma_poolp; 2954 nxge_dma_common_t **dma_buf_p; 2955 nxge_dma_pool_t *dma_cntl_poolp; 2956 nxge_dma_common_t **dma_cntl_p; 2957 uint32_t *num_chunks; /* per dma */ 2958 int tdc_max; 2959 2960 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 2961 2962 p_cfgp = &nxgep->pt_config.hw_config; 2963 tdc_max = NXGE_MAX_TDCS; 2964 2965 /* 2966 * Allocate memory for each transmit DMA channel. 2967 */ 2968 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2969 KM_SLEEP); 2970 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2971 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2972 2973 dma_cntl_poolp = (p_nxge_dma_pool_t) 2974 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2975 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2976 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2977 2978 if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 2979 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2980 "nxge_alloc_tx_mem_pool: TDC too high %d, " 2981 "set to default %d", 2982 nxge_tx_ring_size, TDC_DEFAULT_MAX)); 2983 nxge_tx_ring_size = TDC_DEFAULT_MAX; 2984 } 2985 2986 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2987 /* 2988 * N2/NIU has limitation on the descriptor sizes (contiguous 2989 * memory allocation on data buffers to 4M (contig_mem_alloc) 2990 * and little endian for control buffers (must use the ddi/dki mem alloc 2991 * function). The transmit ring is limited to 8K (includes the 2992 * mailbox). 2993 */ 2994 if (nxgep->niu_type == N2_NIU) { 2995 if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 2996 (!ISP2(nxge_tx_ring_size))) { 2997 nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 2998 } 2999 } 3000 #endif 3001 3002 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 3003 3004 num_chunks = (uint32_t *)KMEM_ZALLOC( 3005 sizeof (uint32_t) * tdc_max, KM_SLEEP); 3006 3007 dma_poolp->ndmas = p_cfgp->tdc.owned; 3008 dma_poolp->num_chunks = num_chunks; 3009 dma_poolp->dma_buf_pool_p = dma_buf_p; 3010 nxgep->tx_buf_pool_p = dma_poolp; 3011 3012 dma_poolp->buf_allocated = B_TRUE; 3013 3014 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 3015 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 3016 nxgep->tx_cntl_pool_p = dma_cntl_poolp; 3017 3018 dma_cntl_poolp->buf_allocated = B_TRUE; 3019 3020 nxgep->tx_rings = 3021 KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3022 nxgep->tx_rings->rings = 3023 KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3024 nxgep->tx_mbox_areas_p = 3025 KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3026 nxgep->tx_mbox_areas_p->txmbox_areas_p = 3027 KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 3028 3029 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 3030 3031 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 3032 "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 3033 tdc_max, dma_poolp->ndmas)); 3034 3035 return (NXGE_OK); 3036 } 3037 3038 nxge_status_t 3039 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 3040 p_nxge_dma_common_t *dmap, size_t alloc_size, 3041 size_t block_size, uint32_t *num_chunks) 3042 { 3043 p_nxge_dma_common_t tx_dmap; 3044 nxge_status_t status = NXGE_OK; 3045 size_t total_alloc_size; 3046 size_t allocated = 0; 3047 int i, size_index, array_size; 3048 3049 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 3050 3051 tx_dmap = (p_nxge_dma_common_t) 3052 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 3053 KM_SLEEP); 3054 3055 total_alloc_size = alloc_size; 3056 i = 0; 3057 size_index = 0; 3058 array_size = sizeof (alloc_sizes) / sizeof (size_t); 3059 while ((alloc_sizes[size_index] < alloc_size) && 3060 (size_index < array_size)) 3061 size_index++; 3062 if (size_index >= array_size) { 3063 size_index = array_size - 1; 3064 } 3065 3066 while ((allocated < total_alloc_size) && 3067 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 3068 3069 tx_dmap[i].dma_chunk_index = i; 3070 tx_dmap[i].block_size = block_size; 3071 tx_dmap[i].alength = alloc_sizes[size_index]; 3072 tx_dmap[i].orig_alength = tx_dmap[i].alength; 3073 tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 3074 tx_dmap[i].dma_channel = dma_channel; 3075 tx_dmap[i].contig_alloc_type = B_FALSE; 3076 tx_dmap[i].kmem_alloc_type = B_FALSE; 3077 3078 /* 3079 * N2/NIU: data buffers must be contiguous as the driver 3080 * needs to call Hypervisor api to set up 3081 * logical pages. 3082 */ 3083 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 3084 tx_dmap[i].contig_alloc_type = B_TRUE; 3085 } 3086 3087 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3088 &nxge_tx_dma_attr, 3089 tx_dmap[i].alength, 3090 &nxge_dev_buf_dma_acc_attr, 3091 DDI_DMA_WRITE | DDI_DMA_STREAMING, 3092 (p_nxge_dma_common_t)(&tx_dmap[i])); 3093 if (status != NXGE_OK) { 3094 size_index--; 3095 } else { 3096 i++; 3097 allocated += alloc_sizes[size_index]; 3098 } 3099 } 3100 3101 if (allocated < total_alloc_size) { 3102 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3103 "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 3104 "allocated 0x%x requested 0x%x", 3105 dma_channel, 3106 allocated, total_alloc_size)); 3107 status = NXGE_ERROR; 3108 goto nxge_alloc_tx_mem_fail1; 3109 } 3110 3111 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3112 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 3113 "allocated 0x%x requested 0x%x", 3114 dma_channel, 3115 allocated, total_alloc_size)); 3116 3117 *num_chunks = i; 3118 *dmap = tx_dmap; 3119 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3120 "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 3121 *dmap, i)); 3122 goto nxge_alloc_tx_mem_exit; 3123 3124 nxge_alloc_tx_mem_fail1: 3125 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 3126 3127 nxge_alloc_tx_mem_exit: 3128 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3129 "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 3130 3131 return (status); 3132 } 3133 3134 /*ARGSUSED*/ 3135 static void 3136 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 3137 uint32_t num_chunks) 3138 { 3139 int i; 3140 3141 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 3142 3143 if (dmap == 0) 3144 return; 3145 3146 for (i = 0; i < num_chunks; i++) { 3147 nxge_dma_mem_free(dmap++); 3148 } 3149 3150 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 3151 } 3152 3153 /*ARGSUSED*/ 3154 nxge_status_t 3155 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 3156 p_nxge_dma_common_t *dmap, size_t size) 3157 { 3158 p_nxge_dma_common_t tx_dmap; 3159 nxge_status_t status = NXGE_OK; 3160 3161 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 3162 tx_dmap = (p_nxge_dma_common_t) 3163 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 3164 3165 tx_dmap->contig_alloc_type = B_FALSE; 3166 tx_dmap->kmem_alloc_type = B_FALSE; 3167 3168 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3169 &nxge_desc_dma_attr, 3170 size, 3171 &nxge_dev_desc_dma_acc_attr, 3172 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3173 tx_dmap); 3174 if (status != NXGE_OK) { 3175 goto nxge_alloc_tx_cntl_dma_fail1; 3176 } 3177 3178 *dmap = tx_dmap; 3179 goto nxge_alloc_tx_cntl_dma_exit; 3180 3181 nxge_alloc_tx_cntl_dma_fail1: 3182 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 3183 3184 nxge_alloc_tx_cntl_dma_exit: 3185 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3186 "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 3187 3188 return (status); 3189 } 3190 3191 /*ARGSUSED*/ 3192 static void 3193 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 3194 { 3195 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 3196 3197 if (dmap == 0) 3198 return; 3199 3200 nxge_dma_mem_free(dmap); 3201 3202 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 3203 } 3204 3205 /* 3206 * nxge_free_tx_mem_pool 3207 * 3208 * This function frees all of the per-port TDC control data structures. 3209 * The per-channel (TDC) data structures are freed when the channel 3210 * is stopped. 3211 * 3212 * Arguments: 3213 * nxgep 3214 * 3215 * Notes: 3216 * 3217 * Context: 3218 * Any domain 3219 */ 3220 static void 3221 nxge_free_tx_mem_pool(p_nxge_t nxgep) 3222 { 3223 int tdc_max = NXGE_MAX_TDCS; 3224 3225 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 3226 3227 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3229 "<== nxge_free_tx_mem_pool " 3230 "(null tx buf pool or buf not allocated")); 3231 return; 3232 } 3233 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3234 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3235 "<== nxge_free_tx_mem_pool " 3236 "(null tx cntl buf pool or cntl buf not allocated")); 3237 return; 3238 } 3239 3240 /* 1. Free the mailboxes. */ 3241 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3242 sizeof (p_tx_mbox_t) * tdc_max); 3243 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 3244 3245 nxgep->tx_mbox_areas_p = 0; 3246 3247 /* 2. Free the transmit ring arrays. */ 3248 KMEM_FREE(nxgep->tx_rings->rings, 3249 sizeof (p_tx_ring_t) * tdc_max); 3250 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 3251 3252 nxgep->tx_rings = 0; 3253 3254 /* 3. Free the completion ring data structures. */ 3255 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3256 sizeof (p_nxge_dma_common_t) * tdc_max); 3257 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 3258 3259 nxgep->tx_cntl_pool_p = 0; 3260 3261 /* 4. Free the data ring data structures. */ 3262 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3263 sizeof (uint32_t) * tdc_max); 3264 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3265 sizeof (p_nxge_dma_common_t) * tdc_max); 3266 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 3267 3268 nxgep->tx_buf_pool_p = 0; 3269 3270 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 3271 } 3272 3273 /*ARGSUSED*/ 3274 static nxge_status_t 3275 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3276 struct ddi_dma_attr *dma_attrp, 3277 size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3278 p_nxge_dma_common_t dma_p) 3279 { 3280 caddr_t kaddrp; 3281 int ddi_status = DDI_SUCCESS; 3282 boolean_t contig_alloc_type; 3283 boolean_t kmem_alloc_type; 3284 3285 contig_alloc_type = dma_p->contig_alloc_type; 3286 3287 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 3288 /* 3289 * contig_alloc_type for contiguous memory only allowed 3290 * for N2/NIU. 3291 */ 3292 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3293 "nxge_dma_mem_alloc: alloc type not allowed (%d)", 3294 dma_p->contig_alloc_type)); 3295 return (NXGE_ERROR | NXGE_DDI_FAILED); 3296 } 3297 3298 dma_p->dma_handle = NULL; 3299 dma_p->acc_handle = NULL; 3300 dma_p->kaddrp = dma_p->last_kaddrp = NULL; 3301 dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 3302 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 3303 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 3304 if (ddi_status != DDI_SUCCESS) { 3305 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3306 "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 3307 return (NXGE_ERROR | NXGE_DDI_FAILED); 3308 } 3309 3310 kmem_alloc_type = dma_p->kmem_alloc_type; 3311 3312 switch (contig_alloc_type) { 3313 case B_FALSE: 3314 switch (kmem_alloc_type) { 3315 case B_FALSE: 3316 ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 3317 length, 3318 acc_attr_p, 3319 xfer_flags, 3320 DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 3321 &dma_p->acc_handle); 3322 if (ddi_status != DDI_SUCCESS) { 3323 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3324 "nxge_dma_mem_alloc: " 3325 "ddi_dma_mem_alloc failed")); 3326 ddi_dma_free_handle(&dma_p->dma_handle); 3327 dma_p->dma_handle = NULL; 3328 return (NXGE_ERROR | NXGE_DDI_FAILED); 3329 } 3330 if (dma_p->alength < length) { 3331 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3332 "nxge_dma_mem_alloc:di_dma_mem_alloc " 3333 "< length.")); 3334 ddi_dma_mem_free(&dma_p->acc_handle); 3335 ddi_dma_free_handle(&dma_p->dma_handle); 3336 dma_p->acc_handle = NULL; 3337 dma_p->dma_handle = NULL; 3338 return (NXGE_ERROR); 3339 } 3340 3341 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3342 NULL, 3343 kaddrp, dma_p->alength, xfer_flags, 3344 DDI_DMA_DONTWAIT, 3345 0, &dma_p->dma_cookie, &dma_p->ncookies); 3346 if (ddi_status != DDI_DMA_MAPPED) { 3347 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3348 "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3349 "failed " 3350 "(staus 0x%x ncookies %d.)", ddi_status, 3351 dma_p->ncookies)); 3352 if (dma_p->acc_handle) { 3353 ddi_dma_mem_free(&dma_p->acc_handle); 3354 dma_p->acc_handle = NULL; 3355 } 3356 ddi_dma_free_handle(&dma_p->dma_handle); 3357 dma_p->dma_handle = NULL; 3358 return (NXGE_ERROR | NXGE_DDI_FAILED); 3359 } 3360 3361 if (dma_p->ncookies != 1) { 3362 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3363 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3364 "> 1 cookie" 3365 "(staus 0x%x ncookies %d.)", ddi_status, 3366 dma_p->ncookies)); 3367 if (dma_p->acc_handle) { 3368 ddi_dma_mem_free(&dma_p->acc_handle); 3369 dma_p->acc_handle = NULL; 3370 } 3371 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3372 ddi_dma_free_handle(&dma_p->dma_handle); 3373 dma_p->dma_handle = NULL; 3374 return (NXGE_ERROR); 3375 } 3376 break; 3377 3378 case B_TRUE: 3379 kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3380 if (kaddrp == NULL) { 3381 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3382 "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3383 "kmem alloc failed")); 3384 return (NXGE_ERROR); 3385 } 3386 3387 dma_p->alength = length; 3388 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3389 NULL, kaddrp, dma_p->alength, xfer_flags, 3390 DDI_DMA_DONTWAIT, 0, 3391 &dma_p->dma_cookie, &dma_p->ncookies); 3392 if (ddi_status != DDI_DMA_MAPPED) { 3393 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3394 "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3395 "(kmem_alloc) failed kaddrp $%p length %d " 3396 "(staus 0x%x (%d) ncookies %d.)", 3397 kaddrp, length, 3398 ddi_status, ddi_status, dma_p->ncookies)); 3399 KMEM_FREE(kaddrp, length); 3400 dma_p->acc_handle = NULL; 3401 ddi_dma_free_handle(&dma_p->dma_handle); 3402 dma_p->dma_handle = NULL; 3403 dma_p->kaddrp = NULL; 3404 return (NXGE_ERROR | NXGE_DDI_FAILED); 3405 } 3406 3407 if (dma_p->ncookies != 1) { 3408 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3409 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3410 "(kmem_alloc) > 1 cookie" 3411 "(staus 0x%x ncookies %d.)", ddi_status, 3412 dma_p->ncookies)); 3413 KMEM_FREE(kaddrp, length); 3414 dma_p->acc_handle = NULL; 3415 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3416 ddi_dma_free_handle(&dma_p->dma_handle); 3417 dma_p->dma_handle = NULL; 3418 dma_p->kaddrp = NULL; 3419 return (NXGE_ERROR); 3420 } 3421 3422 dma_p->kaddrp = kaddrp; 3423 3424 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 3425 "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 3426 "kaddr $%p alength %d", 3427 dma_p, 3428 kaddrp, 3429 dma_p->alength)); 3430 break; 3431 } 3432 break; 3433 3434 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3435 case B_TRUE: 3436 kaddrp = (caddr_t)contig_mem_alloc(length); 3437 if (kaddrp == NULL) { 3438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3439 "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 3440 ddi_dma_free_handle(&dma_p->dma_handle); 3441 return (NXGE_ERROR | NXGE_DDI_FAILED); 3442 } 3443 3444 dma_p->alength = length; 3445 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 3446 kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 3447 &dma_p->dma_cookie, &dma_p->ncookies); 3448 if (ddi_status != DDI_DMA_MAPPED) { 3449 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3450 "nxge_dma_mem_alloc:di_dma_addr_bind failed " 3451 "(status 0x%x ncookies %d.)", ddi_status, 3452 dma_p->ncookies)); 3453 3454 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3455 "==> nxge_dma_mem_alloc: (not mapped)" 3456 "length %lu (0x%x) " 3457 "free contig kaddrp $%p " 3458 "va_to_pa $%p", 3459 length, length, 3460 kaddrp, 3461 va_to_pa(kaddrp))); 3462 3463 3464 contig_mem_free((void *)kaddrp, length); 3465 ddi_dma_free_handle(&dma_p->dma_handle); 3466 3467 dma_p->dma_handle = NULL; 3468 dma_p->acc_handle = NULL; 3469 dma_p->alength = NULL; 3470 dma_p->kaddrp = NULL; 3471 3472 return (NXGE_ERROR | NXGE_DDI_FAILED); 3473 } 3474 3475 if (dma_p->ncookies != 1 || 3476 (dma_p->dma_cookie.dmac_laddress == NULL)) { 3477 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3478 "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 3479 "cookie or " 3480 "dmac_laddress is NULL $%p size %d " 3481 " (status 0x%x ncookies %d.)", 3482 ddi_status, 3483 dma_p->dma_cookie.dmac_laddress, 3484 dma_p->dma_cookie.dmac_size, 3485 dma_p->ncookies)); 3486 3487 contig_mem_free((void *)kaddrp, length); 3488 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3489 ddi_dma_free_handle(&dma_p->dma_handle); 3490 3491 dma_p->alength = 0; 3492 dma_p->dma_handle = NULL; 3493 dma_p->acc_handle = NULL; 3494 dma_p->kaddrp = NULL; 3495 3496 return (NXGE_ERROR | NXGE_DDI_FAILED); 3497 } 3498 break; 3499 3500 #else 3501 case B_TRUE: 3502 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3503 "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 3504 return (NXGE_ERROR | NXGE_DDI_FAILED); 3505 #endif 3506 } 3507 3508 dma_p->kaddrp = kaddrp; 3509 dma_p->last_kaddrp = (unsigned char *)kaddrp + 3510 dma_p->alength - RXBUF_64B_ALIGNED; 3511 #if defined(__i386) 3512 dma_p->ioaddr_pp = 3513 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3514 #else 3515 dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3516 #endif 3517 dma_p->last_ioaddr_pp = 3518 #if defined(__i386) 3519 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3520 #else 3521 (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3522 #endif 3523 dma_p->alength - RXBUF_64B_ALIGNED; 3524 3525 NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 3526 3527 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3528 dma_p->orig_ioaddr_pp = 3529 (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3530 dma_p->orig_alength = length; 3531 dma_p->orig_kaddrp = kaddrp; 3532 dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 3533 #endif 3534 3535 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 3536 "dma buffer allocated: dma_p $%p " 3537 "return dmac_ladress from cookie $%p cookie dmac_size %d " 3538 "dma_p->ioaddr_p $%p " 3539 "dma_p->orig_ioaddr_p $%p " 3540 "orig_vatopa $%p " 3541 "alength %d (0x%x) " 3542 "kaddrp $%p " 3543 "length %d (0x%x)", 3544 dma_p, 3545 dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 3546 dma_p->ioaddr_pp, 3547 dma_p->orig_ioaddr_pp, 3548 dma_p->orig_vatopa, 3549 dma_p->alength, dma_p->alength, 3550 kaddrp, 3551 length, length)); 3552 3553 return (NXGE_OK); 3554 } 3555 3556 static void 3557 nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 3558 { 3559 if (dma_p->dma_handle != NULL) { 3560 if (dma_p->ncookies) { 3561 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3562 dma_p->ncookies = 0; 3563 } 3564 ddi_dma_free_handle(&dma_p->dma_handle); 3565 dma_p->dma_handle = NULL; 3566 } 3567 3568 if (dma_p->acc_handle != NULL) { 3569 ddi_dma_mem_free(&dma_p->acc_handle); 3570 dma_p->acc_handle = NULL; 3571 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3572 } 3573 3574 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3575 if (dma_p->contig_alloc_type && 3576 dma_p->orig_kaddrp && dma_p->orig_alength) { 3577 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 3578 "kaddrp $%p (orig_kaddrp $%p)" 3579 "mem type %d ", 3580 "orig_alength %d " 3581 "alength 0x%x (%d)", 3582 dma_p->kaddrp, 3583 dma_p->orig_kaddrp, 3584 dma_p->contig_alloc_type, 3585 dma_p->orig_alength, 3586 dma_p->alength, dma_p->alength)); 3587 3588 contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 3589 dma_p->orig_alength = NULL; 3590 dma_p->orig_kaddrp = NULL; 3591 dma_p->contig_alloc_type = B_FALSE; 3592 } 3593 #endif 3594 dma_p->kaddrp = NULL; 3595 dma_p->alength = NULL; 3596 } 3597 3598 static void 3599 nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3600 { 3601 uint64_t kaddr; 3602 uint32_t buf_size; 3603 3604 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3605 3606 if (dma_p->dma_handle != NULL) { 3607 if (dma_p->ncookies) { 3608 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3609 dma_p->ncookies = 0; 3610 } 3611 ddi_dma_free_handle(&dma_p->dma_handle); 3612 dma_p->dma_handle = NULL; 3613 } 3614 3615 if (dma_p->acc_handle != NULL) { 3616 ddi_dma_mem_free(&dma_p->acc_handle); 3617 dma_p->acc_handle = NULL; 3618 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3619 } 3620 3621 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3622 "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3623 dma_p, 3624 dma_p->buf_alloc_state)); 3625 3626 if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3627 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3628 "<== nxge_dma_free_rx_data_buf: " 3629 "outstanding data buffers")); 3630 return; 3631 } 3632 3633 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3634 if (dma_p->contig_alloc_type && 3635 dma_p->orig_kaddrp && dma_p->orig_alength) { 3636 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3637 "kaddrp $%p (orig_kaddrp $%p)" 3638 "mem type %d ", 3639 "orig_alength %d " 3640 "alength 0x%x (%d)", 3641 dma_p->kaddrp, 3642 dma_p->orig_kaddrp, 3643 dma_p->contig_alloc_type, 3644 dma_p->orig_alength, 3645 dma_p->alength, dma_p->alength)); 3646 3647 kaddr = (uint64_t)dma_p->orig_kaddrp; 3648 buf_size = dma_p->orig_alength; 3649 nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3650 dma_p->orig_alength = NULL; 3651 dma_p->orig_kaddrp = NULL; 3652 dma_p->contig_alloc_type = B_FALSE; 3653 dma_p->kaddrp = NULL; 3654 dma_p->alength = NULL; 3655 return; 3656 } 3657 #endif 3658 3659 if (dma_p->kmem_alloc_type) { 3660 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3661 "nxge_dma_free_rx_data_buf: free kmem " 3662 "kaddrp $%p (orig_kaddrp $%p)" 3663 "alloc type %d " 3664 "orig_alength %d " 3665 "alength 0x%x (%d)", 3666 dma_p->kaddrp, 3667 dma_p->orig_kaddrp, 3668 dma_p->kmem_alloc_type, 3669 dma_p->orig_alength, 3670 dma_p->alength, dma_p->alength)); 3671 #if defined(__i386) 3672 kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3673 #else 3674 kaddr = (uint64_t)dma_p->kaddrp; 3675 #endif 3676 buf_size = dma_p->orig_alength; 3677 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3678 "nxge_dma_free_rx_data_buf: free dmap $%p " 3679 "kaddr $%p buf_size %d", 3680 dma_p, 3681 kaddr, buf_size)); 3682 nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3683 dma_p->alength = 0; 3684 dma_p->orig_alength = 0; 3685 dma_p->kaddrp = NULL; 3686 dma_p->kmem_alloc_type = B_FALSE; 3687 } 3688 3689 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3690 } 3691 3692 /* 3693 * nxge_m_start() -- start transmitting and receiving. 3694 * 3695 * This function is called by the MAC layer when the first 3696 * stream is open to prepare the hardware ready for sending 3697 * and transmitting packets. 3698 */ 3699 static int 3700 nxge_m_start(void *arg) 3701 { 3702 p_nxge_t nxgep = (p_nxge_t)arg; 3703 3704 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 3705 3706 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 3707 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 3708 } 3709 3710 MUTEX_ENTER(nxgep->genlock); 3711 if (nxge_init(nxgep) != NXGE_OK) { 3712 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3713 "<== nxge_m_start: initialization failed")); 3714 MUTEX_EXIT(nxgep->genlock); 3715 return (EIO); 3716 } 3717 3718 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 3719 goto nxge_m_start_exit; 3720 /* 3721 * Start timer to check the system error and tx hangs 3722 */ 3723 if (!isLDOMguest(nxgep)) 3724 nxgep->nxge_timerid = nxge_start_timer(nxgep, 3725 nxge_check_hw_state, NXGE_CHECK_TIMER); 3726 #if defined(sun4v) 3727 else 3728 nxge_hio_start_timer(nxgep); 3729 #endif 3730 3731 nxgep->link_notify = B_TRUE; 3732 3733 nxgep->nxge_mac_state = NXGE_MAC_STARTED; 3734 3735 nxge_m_start_exit: 3736 MUTEX_EXIT(nxgep->genlock); 3737 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 3738 return (0); 3739 } 3740 3741 /* 3742 * nxge_m_stop(): stop transmitting and receiving. 3743 */ 3744 static void 3745 nxge_m_stop(void *arg) 3746 { 3747 p_nxge_t nxgep = (p_nxge_t)arg; 3748 3749 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 3750 3751 MUTEX_ENTER(nxgep->genlock); 3752 nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3753 3754 if (nxgep->nxge_timerid) { 3755 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 3756 nxgep->nxge_timerid = 0; 3757 } 3758 3759 nxge_uninit(nxgep); 3760 3761 nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 3762 3763 MUTEX_EXIT(nxgep->genlock); 3764 3765 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 3766 } 3767 3768 static int 3769 nxge_m_unicst(void *arg, const uint8_t *macaddr) 3770 { 3771 p_nxge_t nxgep = (p_nxge_t)arg; 3772 struct ether_addr addrp; 3773 3774 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 3775 3776 bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 3777 if (nxge_set_mac_addr(nxgep, &addrp)) { 3778 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3779 "<== nxge_m_unicst: set unitcast failed")); 3780 return (EINVAL); 3781 } 3782 3783 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 3784 3785 return (0); 3786 } 3787 3788 static int 3789 nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 3790 { 3791 p_nxge_t nxgep = (p_nxge_t)arg; 3792 struct ether_addr addrp; 3793 3794 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3795 "==> nxge_m_multicst: add %d", add)); 3796 3797 bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 3798 if (add) { 3799 if (nxge_add_mcast_addr(nxgep, &addrp)) { 3800 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3801 "<== nxge_m_multicst: add multicast failed")); 3802 return (EINVAL); 3803 } 3804 } else { 3805 if (nxge_del_mcast_addr(nxgep, &addrp)) { 3806 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3807 "<== nxge_m_multicst: del multicast failed")); 3808 return (EINVAL); 3809 } 3810 } 3811 3812 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 3813 3814 return (0); 3815 } 3816 3817 static int 3818 nxge_m_promisc(void *arg, boolean_t on) 3819 { 3820 p_nxge_t nxgep = (p_nxge_t)arg; 3821 3822 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3823 "==> nxge_m_promisc: on %d", on)); 3824 3825 if (nxge_set_promisc(nxgep, on)) { 3826 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3827 "<== nxge_m_promisc: set promisc failed")); 3828 return (EINVAL); 3829 } 3830 3831 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3832 "<== nxge_m_promisc: on %d", on)); 3833 3834 return (0); 3835 } 3836 3837 static void 3838 nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3839 { 3840 p_nxge_t nxgep = (p_nxge_t)arg; 3841 struct iocblk *iocp; 3842 boolean_t need_privilege; 3843 int err; 3844 int cmd; 3845 3846 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 3847 3848 iocp = (struct iocblk *)mp->b_rptr; 3849 iocp->ioc_error = 0; 3850 need_privilege = B_TRUE; 3851 cmd = iocp->ioc_cmd; 3852 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 3853 switch (cmd) { 3854 default: 3855 miocnak(wq, mp, 0, EINVAL); 3856 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 3857 return; 3858 3859 case LB_GET_INFO_SIZE: 3860 case LB_GET_INFO: 3861 case LB_GET_MODE: 3862 need_privilege = B_FALSE; 3863 break; 3864 case LB_SET_MODE: 3865 break; 3866 3867 3868 case NXGE_GET_MII: 3869 case NXGE_PUT_MII: 3870 case NXGE_GET64: 3871 case NXGE_PUT64: 3872 case NXGE_GET_TX_RING_SZ: 3873 case NXGE_GET_TX_DESC: 3874 case NXGE_TX_SIDE_RESET: 3875 case NXGE_RX_SIDE_RESET: 3876 case NXGE_GLOBAL_RESET: 3877 case NXGE_RESET_MAC: 3878 case NXGE_TX_REGS_DUMP: 3879 case NXGE_RX_REGS_DUMP: 3880 case NXGE_INT_REGS_DUMP: 3881 case NXGE_VIR_INT_REGS_DUMP: 3882 case NXGE_PUT_TCAM: 3883 case NXGE_GET_TCAM: 3884 case NXGE_RTRACE: 3885 case NXGE_RDUMP: 3886 3887 need_privilege = B_FALSE; 3888 break; 3889 case NXGE_INJECT_ERR: 3890 cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 3891 nxge_err_inject(nxgep, wq, mp); 3892 break; 3893 } 3894 3895 if (need_privilege) { 3896 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 3897 if (err != 0) { 3898 miocnak(wq, mp, 0, err); 3899 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3900 "<== nxge_m_ioctl: no priv")); 3901 return; 3902 } 3903 } 3904 3905 switch (cmd) { 3906 3907 case LB_GET_MODE: 3908 case LB_SET_MODE: 3909 case LB_GET_INFO_SIZE: 3910 case LB_GET_INFO: 3911 nxge_loopback_ioctl(nxgep, wq, mp, iocp); 3912 break; 3913 3914 case NXGE_GET_MII: 3915 case NXGE_PUT_MII: 3916 case NXGE_PUT_TCAM: 3917 case NXGE_GET_TCAM: 3918 case NXGE_GET64: 3919 case NXGE_PUT64: 3920 case NXGE_GET_TX_RING_SZ: 3921 case NXGE_GET_TX_DESC: 3922 case NXGE_TX_SIDE_RESET: 3923 case NXGE_RX_SIDE_RESET: 3924 case NXGE_GLOBAL_RESET: 3925 case NXGE_RESET_MAC: 3926 case NXGE_TX_REGS_DUMP: 3927 case NXGE_RX_REGS_DUMP: 3928 case NXGE_INT_REGS_DUMP: 3929 case NXGE_VIR_INT_REGS_DUMP: 3930 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3931 "==> nxge_m_ioctl: cmd 0x%x", cmd)); 3932 nxge_hw_ioctl(nxgep, wq, mp, iocp); 3933 break; 3934 } 3935 3936 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 3937 } 3938 3939 extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 3940 3941 static void 3942 nxge_m_resources(void *arg) 3943 { 3944 p_nxge_t nxgep = arg; 3945 mac_rx_fifo_t mrf; 3946 3947 nxge_grp_set_t *set = &nxgep->rx_set; 3948 uint8_t rdc; 3949 3950 rx_rcr_ring_t *ring; 3951 3952 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 3953 3954 MUTEX_ENTER(nxgep->genlock); 3955 3956 if (set->owned.map == 0) { 3957 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3958 "nxge_m_resources: no receive resources")); 3959 goto nxge_m_resources_exit; 3960 } 3961 3962 /* 3963 * CR 6492541 Check to see if the drv_state has been initialized, 3964 * if not * call nxge_init(). 3965 */ 3966 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3967 if (nxge_init(nxgep) != NXGE_OK) 3968 goto nxge_m_resources_exit; 3969 } 3970 3971 mrf.mrf_type = MAC_RX_FIFO; 3972 mrf.mrf_blank = nxge_rx_hw_blank; 3973 mrf.mrf_arg = (void *)nxgep; 3974 3975 mrf.mrf_normal_blank_time = 128; 3976 mrf.mrf_normal_pkt_count = 8; 3977 3978 /* 3979 * Export our receive resources to the MAC layer. 3980 */ 3981 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3982 if ((1 << rdc) & set->owned.map) { 3983 ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3984 if (ring == 0) { 3985 /* 3986 * This is a big deal only if we are 3987 * *not* in an LDOMs environment. 3988 */ 3989 if (nxgep->environs == SOLARIS_DOMAIN) { 3990 cmn_err(CE_NOTE, 3991 "==> nxge_m_resources: " 3992 "ring %d == 0", rdc); 3993 } 3994 continue; 3995 } 3996 ring->rcr_mac_handle = mac_resource_add 3997 (nxgep->mach, (mac_resource_t *)&mrf); 3998 3999 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4000 "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 4001 rdc, ring, ring->rcr_mac_handle)); 4002 } 4003 } 4004 4005 nxge_m_resources_exit: 4006 MUTEX_EXIT(nxgep->genlock); 4007 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 4008 } 4009 4010 void 4011 nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 4012 { 4013 p_nxge_mmac_stats_t mmac_stats; 4014 int i; 4015 nxge_mmac_t *mmac_info; 4016 4017 mmac_info = &nxgep->nxge_mmac_info; 4018 4019 mmac_stats = &nxgep->statsp->mmac_stats; 4020 mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 4021 mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 4022 4023 for (i = 0; i < ETHERADDRL; i++) { 4024 if (factory) { 4025 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4026 = mmac_info->factory_mac_pool[slot][ 4027 (ETHERADDRL-1) - i]; 4028 } else { 4029 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4030 = mmac_info->mac_pool[slot].addr[ 4031 (ETHERADDRL - 1) - i]; 4032 } 4033 } 4034 } 4035 4036 /* 4037 * nxge_altmac_set() -- Set an alternate MAC address 4038 */ 4039 static int 4040 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot) 4041 { 4042 uint8_t addrn; 4043 uint8_t portn; 4044 npi_mac_addr_t altmac; 4045 hostinfo_t mac_rdc; 4046 p_nxge_class_pt_cfg_t clscfgp; 4047 4048 altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 4049 altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 4050 altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 4051 4052 portn = nxgep->mac.portnum; 4053 addrn = (uint8_t)slot - 1; 4054 4055 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 4056 addrn, &altmac) != NPI_SUCCESS) 4057 return (EIO); 4058 4059 /* 4060 * Set the rdc table number for the host info entry 4061 * for this mac address slot. 4062 */ 4063 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 4064 mac_rdc.value = 0; 4065 mac_rdc.bits.w0.rdc_tbl_num = clscfgp->mac_host_info[addrn].rdctbl; 4066 mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 4067 4068 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 4069 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 4070 return (EIO); 4071 } 4072 4073 /* 4074 * Enable comparison with the alternate MAC address. 4075 * While the first alternate addr is enabled by bit 1 of register 4076 * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 4077 * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 4078 * accordingly before calling npi_mac_altaddr_entry. 4079 */ 4080 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4081 addrn = (uint8_t)slot - 1; 4082 else 4083 addrn = (uint8_t)slot; 4084 4085 if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 4086 != NPI_SUCCESS) 4087 return (EIO); 4088 4089 return (0); 4090 } 4091 4092 /* 4093 * nxeg_m_mmac_add() - find an unused address slot, set the address 4094 * value to the one specified, enable the port to start filtering on 4095 * the new MAC address. Returns 0 on success. 4096 */ 4097 int 4098 nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 4099 { 4100 p_nxge_t nxgep = arg; 4101 mac_addr_slot_t slot; 4102 nxge_mmac_t *mmac_info; 4103 int err; 4104 nxge_status_t status; 4105 4106 mutex_enter(nxgep->genlock); 4107 4108 /* 4109 * Make sure that nxge is initialized, if _start() has 4110 * not been called. 4111 */ 4112 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4113 status = nxge_init(nxgep); 4114 if (status != NXGE_OK) { 4115 mutex_exit(nxgep->genlock); 4116 return (ENXIO); 4117 } 4118 } 4119 4120 mmac_info = &nxgep->nxge_mmac_info; 4121 if (mmac_info->naddrfree == 0) { 4122 mutex_exit(nxgep->genlock); 4123 return (ENOSPC); 4124 } 4125 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4126 maddr->mma_addrlen)) { 4127 mutex_exit(nxgep->genlock); 4128 return (EINVAL); 4129 } 4130 /* 4131 * Search for the first available slot. Because naddrfree 4132 * is not zero, we are guaranteed to find one. 4133 * Slot 0 is for unique (primary) MAC. The first alternate 4134 * MAC slot is slot 1. 4135 * Each of the first two ports of Neptune has 16 alternate 4136 * MAC slots but only the first 7 (of 15) slots have assigned factory 4137 * MAC addresses. We first search among the slots without bundled 4138 * factory MACs. If we fail to find one in that range, then we 4139 * search the slots with bundled factory MACs. A factory MAC 4140 * will be wasted while the slot is used with a user MAC address. 4141 * But the slot could be used by factory MAC again after calling 4142 * nxge_m_mmac_remove and nxge_m_mmac_reserve. 4143 */ 4144 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 4145 for (slot = mmac_info->num_factory_mmac + 1; 4146 slot <= mmac_info->num_mmac; slot++) { 4147 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4148 break; 4149 } 4150 if (slot > mmac_info->num_mmac) { 4151 for (slot = 1; slot <= mmac_info->num_factory_mmac; 4152 slot++) { 4153 if (!(mmac_info->mac_pool[slot].flags 4154 & MMAC_SLOT_USED)) 4155 break; 4156 } 4157 } 4158 } else { 4159 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 4160 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4161 break; 4162 } 4163 } 4164 ASSERT(slot <= mmac_info->num_mmac); 4165 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) != 0) { 4166 mutex_exit(nxgep->genlock); 4167 return (err); 4168 } 4169 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 4170 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 4171 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4172 mmac_info->naddrfree--; 4173 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4174 4175 maddr->mma_slot = slot; 4176 4177 mutex_exit(nxgep->genlock); 4178 return (0); 4179 } 4180 4181 /* 4182 * This function reserves an unused slot and programs the slot and the HW 4183 * with a factory mac address. 4184 */ 4185 static int 4186 nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 4187 { 4188 p_nxge_t nxgep = arg; 4189 mac_addr_slot_t slot; 4190 nxge_mmac_t *mmac_info; 4191 int err; 4192 nxge_status_t status; 4193 4194 mutex_enter(nxgep->genlock); 4195 4196 /* 4197 * Make sure that nxge is initialized, if _start() has 4198 * not been called. 4199 */ 4200 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4201 status = nxge_init(nxgep); 4202 if (status != NXGE_OK) { 4203 mutex_exit(nxgep->genlock); 4204 return (ENXIO); 4205 } 4206 } 4207 4208 mmac_info = &nxgep->nxge_mmac_info; 4209 if (mmac_info->naddrfree == 0) { 4210 mutex_exit(nxgep->genlock); 4211 return (ENOSPC); 4212 } 4213 4214 slot = maddr->mma_slot; 4215 if (slot == -1) { /* -1: Take the first available slot */ 4216 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 4217 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4218 break; 4219 } 4220 if (slot > mmac_info->num_factory_mmac) { 4221 mutex_exit(nxgep->genlock); 4222 return (ENOSPC); 4223 } 4224 } 4225 if (slot < 1 || slot > mmac_info->num_factory_mmac) { 4226 /* 4227 * Do not support factory MAC at a slot greater than 4228 * num_factory_mmac even when there are available factory 4229 * MAC addresses because the alternate MACs are bundled with 4230 * slot[1] through slot[num_factory_mmac] 4231 */ 4232 mutex_exit(nxgep->genlock); 4233 return (EINVAL); 4234 } 4235 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4236 mutex_exit(nxgep->genlock); 4237 return (EBUSY); 4238 } 4239 /* Verify the address to be reserved */ 4240 if (!mac_unicst_verify(nxgep->mach, 4241 mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 4242 mutex_exit(nxgep->genlock); 4243 return (EINVAL); 4244 } 4245 if (err = nxge_altmac_set(nxgep, 4246 mmac_info->factory_mac_pool[slot], slot)) { 4247 mutex_exit(nxgep->genlock); 4248 return (err); 4249 } 4250 bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 4251 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4252 mmac_info->naddrfree--; 4253 4254 nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 4255 mutex_exit(nxgep->genlock); 4256 4257 /* Pass info back to the caller */ 4258 maddr->mma_slot = slot; 4259 maddr->mma_addrlen = ETHERADDRL; 4260 maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4261 4262 return (0); 4263 } 4264 4265 /* 4266 * Remove the specified mac address and update the HW not to filter 4267 * the mac address anymore. 4268 */ 4269 int 4270 nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 4271 { 4272 p_nxge_t nxgep = arg; 4273 nxge_mmac_t *mmac_info; 4274 uint8_t addrn; 4275 uint8_t portn; 4276 int err = 0; 4277 nxge_status_t status; 4278 4279 mutex_enter(nxgep->genlock); 4280 4281 /* 4282 * Make sure that nxge is initialized, if _start() has 4283 * not been called. 4284 */ 4285 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4286 status = nxge_init(nxgep); 4287 if (status != NXGE_OK) { 4288 mutex_exit(nxgep->genlock); 4289 return (ENXIO); 4290 } 4291 } 4292 4293 mmac_info = &nxgep->nxge_mmac_info; 4294 if (slot < 1 || slot > mmac_info->num_mmac) { 4295 mutex_exit(nxgep->genlock); 4296 return (EINVAL); 4297 } 4298 4299 portn = nxgep->mac.portnum; 4300 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4301 addrn = (uint8_t)slot - 1; 4302 else 4303 addrn = (uint8_t)slot; 4304 4305 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4306 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 4307 == NPI_SUCCESS) { 4308 mmac_info->naddrfree++; 4309 mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 4310 /* 4311 * Regardless if the MAC we just stopped filtering 4312 * is a user addr or a facory addr, we must set 4313 * the MMAC_VENDOR_ADDR flag if this slot has an 4314 * associated factory MAC to indicate that a factory 4315 * MAC is available. 4316 */ 4317 if (slot <= mmac_info->num_factory_mmac) { 4318 mmac_info->mac_pool[slot].flags 4319 |= MMAC_VENDOR_ADDR; 4320 } 4321 /* 4322 * Clear mac_pool[slot].addr so that kstat shows 0 4323 * alternate MAC address if the slot is not used. 4324 * (But nxge_m_mmac_get returns the factory MAC even 4325 * when the slot is not used!) 4326 */ 4327 bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 4328 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4329 } else { 4330 err = EIO; 4331 } 4332 } else { 4333 err = EINVAL; 4334 } 4335 4336 mutex_exit(nxgep->genlock); 4337 return (err); 4338 } 4339 4340 /* 4341 * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 4342 */ 4343 static int 4344 nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 4345 { 4346 p_nxge_t nxgep = arg; 4347 mac_addr_slot_t slot; 4348 nxge_mmac_t *mmac_info; 4349 int err = 0; 4350 nxge_status_t status; 4351 4352 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4353 maddr->mma_addrlen)) 4354 return (EINVAL); 4355 4356 slot = maddr->mma_slot; 4357 4358 mutex_enter(nxgep->genlock); 4359 4360 /* 4361 * Make sure that nxge is initialized, if _start() has 4362 * not been called. 4363 */ 4364 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4365 status = nxge_init(nxgep); 4366 if (status != NXGE_OK) { 4367 mutex_exit(nxgep->genlock); 4368 return (ENXIO); 4369 } 4370 } 4371 4372 mmac_info = &nxgep->nxge_mmac_info; 4373 if (slot < 1 || slot > mmac_info->num_mmac) { 4374 mutex_exit(nxgep->genlock); 4375 return (EINVAL); 4376 } 4377 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4378 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) 4379 != 0) { 4380 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 4381 ETHERADDRL); 4382 /* 4383 * Assume that the MAC passed down from the caller 4384 * is not a factory MAC address (The user should 4385 * call mmac_remove followed by mmac_reserve if 4386 * he wants to use the factory MAC for this slot). 4387 */ 4388 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4389 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4390 } 4391 } else { 4392 err = EINVAL; 4393 } 4394 mutex_exit(nxgep->genlock); 4395 return (err); 4396 } 4397 4398 /* 4399 * nxge_m_mmac_get() - Get the MAC address and other information 4400 * related to the slot. mma_flags should be set to 0 in the call. 4401 * Note: although kstat shows MAC address as zero when a slot is 4402 * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 4403 * to the caller as long as the slot is not using a user MAC address. 4404 * The following table shows the rules, 4405 * 4406 * USED VENDOR mma_addr 4407 * ------------------------------------------------------------ 4408 * (1) Slot uses a user MAC: yes no user MAC 4409 * (2) Slot uses a factory MAC: yes yes factory MAC 4410 * (3) Slot is not used but is 4411 * factory MAC capable: no yes factory MAC 4412 * (4) Slot is not used and is 4413 * not factory MAC capable: no no 0 4414 * ------------------------------------------------------------ 4415 */ 4416 static int 4417 nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 4418 { 4419 nxge_t *nxgep = arg; 4420 mac_addr_slot_t slot; 4421 nxge_mmac_t *mmac_info; 4422 nxge_status_t status; 4423 4424 slot = maddr->mma_slot; 4425 4426 mutex_enter(nxgep->genlock); 4427 4428 /* 4429 * Make sure that nxge is initialized, if _start() has 4430 * not been called. 4431 */ 4432 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4433 status = nxge_init(nxgep); 4434 if (status != NXGE_OK) { 4435 mutex_exit(nxgep->genlock); 4436 return (ENXIO); 4437 } 4438 } 4439 4440 mmac_info = &nxgep->nxge_mmac_info; 4441 4442 if (slot < 1 || slot > mmac_info->num_mmac) { 4443 mutex_exit(nxgep->genlock); 4444 return (EINVAL); 4445 } 4446 maddr->mma_flags = 0; 4447 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 4448 maddr->mma_flags |= MMAC_SLOT_USED; 4449 4450 if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 4451 maddr->mma_flags |= MMAC_VENDOR_ADDR; 4452 bcopy(mmac_info->factory_mac_pool[slot], 4453 maddr->mma_addr, ETHERADDRL); 4454 maddr->mma_addrlen = ETHERADDRL; 4455 } else { 4456 if (maddr->mma_flags & MMAC_SLOT_USED) { 4457 bcopy(mmac_info->mac_pool[slot].addr, 4458 maddr->mma_addr, ETHERADDRL); 4459 maddr->mma_addrlen = ETHERADDRL; 4460 } else { 4461 bzero(maddr->mma_addr, ETHERADDRL); 4462 maddr->mma_addrlen = 0; 4463 } 4464 } 4465 mutex_exit(nxgep->genlock); 4466 return (0); 4467 } 4468 4469 static boolean_t 4470 nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 4471 { 4472 nxge_t *nxgep = arg; 4473 uint32_t *txflags = cap_data; 4474 multiaddress_capab_t *mmacp = cap_data; 4475 4476 switch (cap) { 4477 case MAC_CAPAB_HCKSUM: 4478 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4479 "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4480 if (nxge_cksum_offload <= 1) { 4481 *txflags = HCKSUM_INET_PARTIAL; 4482 } 4483 break; 4484 4485 case MAC_CAPAB_POLL: 4486 /* 4487 * There's nothing for us to fill in, simply returning 4488 * B_TRUE stating that we support polling is sufficient. 4489 */ 4490 break; 4491 4492 case MAC_CAPAB_MULTIADDRESS: 4493 mmacp = (multiaddress_capab_t *)cap_data; 4494 mutex_enter(nxgep->genlock); 4495 4496 mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 4497 mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4498 mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 4499 /* 4500 * maddr_handle is driver's private data, passed back to 4501 * entry point functions as arg. 4502 */ 4503 mmacp->maddr_handle = nxgep; 4504 mmacp->maddr_add = nxge_m_mmac_add; 4505 mmacp->maddr_remove = nxge_m_mmac_remove; 4506 mmacp->maddr_modify = nxge_m_mmac_modify; 4507 mmacp->maddr_get = nxge_m_mmac_get; 4508 mmacp->maddr_reserve = nxge_m_mmac_reserve; 4509 4510 mutex_exit(nxgep->genlock); 4511 break; 4512 4513 case MAC_CAPAB_LSO: { 4514 mac_capab_lso_t *cap_lso = cap_data; 4515 4516 if (nxgep->soft_lso_enable) { 4517 if (nxge_cksum_offload <= 1) { 4518 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4519 if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4520 nxge_lso_max = NXGE_LSO_MAXLEN; 4521 } 4522 cap_lso->lso_basic_tcp_ipv4.lso_max = 4523 nxge_lso_max; 4524 } 4525 break; 4526 } else { 4527 return (B_FALSE); 4528 } 4529 } 4530 4531 #if defined(sun4v) 4532 case MAC_CAPAB_RINGS: { 4533 mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4534 4535 /* 4536 * Only the service domain driver responds to 4537 * this capability request. 4538 */ 4539 if (isLDOMservice(nxgep)) { 4540 mrings->mr_handle = (void *)nxgep; 4541 4542 /* 4543 * No dynamic allocation of groups and 4544 * rings at this time. Shares dictate the 4545 * configuration. 4546 */ 4547 mrings->mr_gadd_ring = NULL; 4548 mrings->mr_grem_ring = NULL; 4549 mrings->mr_rget = NULL; 4550 mrings->mr_gget = nxge_hio_group_get; 4551 4552 if (mrings->mr_type == MAC_RING_TYPE_RX) { 4553 mrings->mr_rnum = 8; /* XXX */ 4554 mrings->mr_gnum = 6; /* XXX */ 4555 } else { 4556 mrings->mr_rnum = 8; /* XXX */ 4557 mrings->mr_gnum = 0; /* XXX */ 4558 } 4559 } else 4560 return (B_FALSE); 4561 break; 4562 } 4563 4564 case MAC_CAPAB_SHARES: { 4565 mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4566 4567 /* 4568 * Only the service domain driver responds to 4569 * this capability request. 4570 */ 4571 if (isLDOMservice(nxgep)) { 4572 mshares->ms_snum = 3; 4573 mshares->ms_handle = (void *)nxgep; 4574 mshares->ms_salloc = nxge_hio_share_alloc; 4575 mshares->ms_sfree = nxge_hio_share_free; 4576 mshares->ms_sadd = NULL; 4577 mshares->ms_sremove = NULL; 4578 mshares->ms_squery = nxge_hio_share_query; 4579 } else 4580 return (B_FALSE); 4581 break; 4582 } 4583 #endif 4584 default: 4585 return (B_FALSE); 4586 } 4587 return (B_TRUE); 4588 } 4589 4590 static boolean_t 4591 nxge_param_locked(mac_prop_id_t pr_num) 4592 { 4593 /* 4594 * All adv_* parameters are locked (read-only) while 4595 * the device is in any sort of loopback mode ... 4596 */ 4597 switch (pr_num) { 4598 case MAC_PROP_ADV_1000FDX_CAP: 4599 case MAC_PROP_EN_1000FDX_CAP: 4600 case MAC_PROP_ADV_1000HDX_CAP: 4601 case MAC_PROP_EN_1000HDX_CAP: 4602 case MAC_PROP_ADV_100FDX_CAP: 4603 case MAC_PROP_EN_100FDX_CAP: 4604 case MAC_PROP_ADV_100HDX_CAP: 4605 case MAC_PROP_EN_100HDX_CAP: 4606 case MAC_PROP_ADV_10FDX_CAP: 4607 case MAC_PROP_EN_10FDX_CAP: 4608 case MAC_PROP_ADV_10HDX_CAP: 4609 case MAC_PROP_EN_10HDX_CAP: 4610 case MAC_PROP_AUTONEG: 4611 case MAC_PROP_FLOWCTRL: 4612 return (B_TRUE); 4613 } 4614 return (B_FALSE); 4615 } 4616 4617 /* 4618 * callback functions for set/get of properties 4619 */ 4620 static int 4621 nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4622 uint_t pr_valsize, const void *pr_val) 4623 { 4624 nxge_t *nxgep = barg; 4625 p_nxge_param_t param_arr; 4626 p_nxge_stats_t statsp; 4627 int err = 0; 4628 uint8_t val; 4629 uint32_t cur_mtu, new_mtu, old_framesize; 4630 link_flowctrl_t fl; 4631 4632 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 4633 param_arr = nxgep->param_arr; 4634 statsp = nxgep->statsp; 4635 mutex_enter(nxgep->genlock); 4636 if (statsp->port_stats.lb_mode != nxge_lb_normal && 4637 nxge_param_locked(pr_num)) { 4638 /* 4639 * All adv_* parameters are locked (read-only) 4640 * while the device is in any sort of loopback mode. 4641 */ 4642 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4643 "==> nxge_m_setprop: loopback mode: read only")); 4644 mutex_exit(nxgep->genlock); 4645 return (EBUSY); 4646 } 4647 4648 val = *(uint8_t *)pr_val; 4649 switch (pr_num) { 4650 case MAC_PROP_EN_1000FDX_CAP: 4651 nxgep->param_en_1000fdx = val; 4652 param_arr[param_anar_1000fdx].value = val; 4653 4654 goto reprogram; 4655 4656 case MAC_PROP_EN_100FDX_CAP: 4657 nxgep->param_en_100fdx = val; 4658 param_arr[param_anar_100fdx].value = val; 4659 4660 goto reprogram; 4661 4662 case MAC_PROP_EN_10FDX_CAP: 4663 nxgep->param_en_10fdx = val; 4664 param_arr[param_anar_10fdx].value = val; 4665 4666 goto reprogram; 4667 4668 case MAC_PROP_EN_1000HDX_CAP: 4669 case MAC_PROP_EN_100HDX_CAP: 4670 case MAC_PROP_EN_10HDX_CAP: 4671 case MAC_PROP_ADV_1000FDX_CAP: 4672 case MAC_PROP_ADV_1000HDX_CAP: 4673 case MAC_PROP_ADV_100FDX_CAP: 4674 case MAC_PROP_ADV_100HDX_CAP: 4675 case MAC_PROP_ADV_10FDX_CAP: 4676 case MAC_PROP_ADV_10HDX_CAP: 4677 case MAC_PROP_STATUS: 4678 case MAC_PROP_SPEED: 4679 case MAC_PROP_DUPLEX: 4680 err = EINVAL; /* cannot set read-only properties */ 4681 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4682 "==> nxge_m_setprop: read only property %d", 4683 pr_num)); 4684 break; 4685 4686 case MAC_PROP_AUTONEG: 4687 param_arr[param_autoneg].value = val; 4688 4689 goto reprogram; 4690 4691 case MAC_PROP_MTU: 4692 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4693 err = EBUSY; 4694 break; 4695 } 4696 4697 cur_mtu = nxgep->mac.default_mtu; 4698 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 4699 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4700 "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 4701 new_mtu, nxgep->mac.is_jumbo)); 4702 4703 if (new_mtu == cur_mtu) { 4704 err = 0; 4705 break; 4706 } 4707 if (new_mtu < NXGE_DEFAULT_MTU || 4708 new_mtu > NXGE_MAXIMUM_MTU) { 4709 err = EINVAL; 4710 break; 4711 } 4712 4713 if ((new_mtu > NXGE_DEFAULT_MTU) && 4714 !nxgep->mac.is_jumbo) { 4715 err = EINVAL; 4716 break; 4717 } 4718 4719 old_framesize = (uint32_t)nxgep->mac.maxframesize; 4720 nxgep->mac.maxframesize = (uint16_t) 4721 (new_mtu + NXGE_EHEADER_VLAN_CRC); 4722 if (nxge_mac_set_framesize(nxgep)) { 4723 nxgep->mac.maxframesize = 4724 (uint16_t)old_framesize; 4725 err = EINVAL; 4726 break; 4727 } 4728 4729 err = mac_maxsdu_update(nxgep->mach, new_mtu); 4730 if (err) { 4731 nxgep->mac.maxframesize = 4732 (uint16_t)old_framesize; 4733 err = EINVAL; 4734 break; 4735 } 4736 4737 nxgep->mac.default_mtu = new_mtu; 4738 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4739 "==> nxge_m_setprop: set MTU: %d maxframe %d", 4740 new_mtu, nxgep->mac.maxframesize)); 4741 break; 4742 4743 case MAC_PROP_FLOWCTRL: 4744 bcopy(pr_val, &fl, sizeof (fl)); 4745 switch (fl) { 4746 default: 4747 err = EINVAL; 4748 break; 4749 4750 case LINK_FLOWCTRL_NONE: 4751 param_arr[param_anar_pause].value = 0; 4752 break; 4753 4754 case LINK_FLOWCTRL_RX: 4755 param_arr[param_anar_pause].value = 1; 4756 break; 4757 4758 case LINK_FLOWCTRL_TX: 4759 case LINK_FLOWCTRL_BI: 4760 err = EINVAL; 4761 break; 4762 } 4763 4764 reprogram: 4765 if (err == 0) { 4766 if (!nxge_param_link_update(nxgep)) { 4767 err = EINVAL; 4768 } 4769 } 4770 break; 4771 case MAC_PROP_PRIVATE: 4772 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4773 "==> nxge_m_setprop: private property")); 4774 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 4775 pr_val); 4776 break; 4777 4778 default: 4779 err = ENOTSUP; 4780 break; 4781 } 4782 4783 mutex_exit(nxgep->genlock); 4784 4785 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4786 "<== nxge_m_setprop (return %d)", err)); 4787 return (err); 4788 } 4789 4790 static int 4791 nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4792 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 4793 { 4794 nxge_t *nxgep = barg; 4795 p_nxge_param_t param_arr = nxgep->param_arr; 4796 p_nxge_stats_t statsp = nxgep->statsp; 4797 int err = 0; 4798 link_flowctrl_t fl; 4799 uint64_t tmp = 0; 4800 link_state_t ls; 4801 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 4802 4803 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4804 "==> nxge_m_getprop: pr_num %d", pr_num)); 4805 4806 if (pr_valsize == 0) 4807 return (EINVAL); 4808 4809 if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 4810 err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 4811 return (err); 4812 } 4813 4814 bzero(pr_val, pr_valsize); 4815 switch (pr_num) { 4816 case MAC_PROP_DUPLEX: 4817 *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 4818 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4819 "==> nxge_m_getprop: duplex mode %d", 4820 *(uint8_t *)pr_val)); 4821 break; 4822 4823 case MAC_PROP_SPEED: 4824 if (pr_valsize < sizeof (uint64_t)) 4825 return (EINVAL); 4826 tmp = statsp->mac_stats.link_speed * 1000000ull; 4827 bcopy(&tmp, pr_val, sizeof (tmp)); 4828 break; 4829 4830 case MAC_PROP_STATUS: 4831 if (pr_valsize < sizeof (link_state_t)) 4832 return (EINVAL); 4833 if (!statsp->mac_stats.link_up) 4834 ls = LINK_STATE_DOWN; 4835 else 4836 ls = LINK_STATE_UP; 4837 bcopy(&ls, pr_val, sizeof (ls)); 4838 break; 4839 4840 case MAC_PROP_AUTONEG: 4841 *(uint8_t *)pr_val = 4842 param_arr[param_autoneg].value; 4843 break; 4844 4845 case MAC_PROP_FLOWCTRL: 4846 if (pr_valsize < sizeof (link_flowctrl_t)) 4847 return (EINVAL); 4848 4849 fl = LINK_FLOWCTRL_NONE; 4850 if (param_arr[param_anar_pause].value) { 4851 fl = LINK_FLOWCTRL_RX; 4852 } 4853 bcopy(&fl, pr_val, sizeof (fl)); 4854 break; 4855 4856 case MAC_PROP_ADV_1000FDX_CAP: 4857 *(uint8_t *)pr_val = 4858 param_arr[param_anar_1000fdx].value; 4859 break; 4860 4861 case MAC_PROP_EN_1000FDX_CAP: 4862 *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 4863 break; 4864 4865 case MAC_PROP_ADV_100FDX_CAP: 4866 *(uint8_t *)pr_val = 4867 param_arr[param_anar_100fdx].value; 4868 break; 4869 4870 case MAC_PROP_EN_100FDX_CAP: 4871 *(uint8_t *)pr_val = nxgep->param_en_100fdx; 4872 break; 4873 4874 case MAC_PROP_ADV_10FDX_CAP: 4875 *(uint8_t *)pr_val = 4876 param_arr[param_anar_10fdx].value; 4877 break; 4878 4879 case MAC_PROP_EN_10FDX_CAP: 4880 *(uint8_t *)pr_val = nxgep->param_en_10fdx; 4881 break; 4882 4883 case MAC_PROP_EN_1000HDX_CAP: 4884 case MAC_PROP_EN_100HDX_CAP: 4885 case MAC_PROP_EN_10HDX_CAP: 4886 case MAC_PROP_ADV_1000HDX_CAP: 4887 case MAC_PROP_ADV_100HDX_CAP: 4888 case MAC_PROP_ADV_10HDX_CAP: 4889 err = ENOTSUP; 4890 break; 4891 4892 case MAC_PROP_PRIVATE: 4893 err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4894 pr_valsize, pr_val); 4895 break; 4896 default: 4897 err = EINVAL; 4898 break; 4899 } 4900 4901 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 4902 4903 return (err); 4904 } 4905 4906 /* ARGSUSED */ 4907 static int 4908 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 4909 const void *pr_val) 4910 { 4911 p_nxge_param_t param_arr = nxgep->param_arr; 4912 int err = 0; 4913 long result; 4914 4915 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4916 "==> nxge_set_priv_prop: name %s", pr_name)); 4917 4918 if (strcmp(pr_name, "_accept_jumbo") == 0) { 4919 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4920 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4921 "<== nxge_set_priv_prop: name %s " 4922 "pr_val %s result %d " 4923 "param %d is_jumbo %d", 4924 pr_name, pr_val, result, 4925 param_arr[param_accept_jumbo].value, 4926 nxgep->mac.is_jumbo)); 4927 4928 if (result > 1 || result < 0) { 4929 err = EINVAL; 4930 } else { 4931 if (nxgep->mac.is_jumbo == 4932 (uint32_t)result) { 4933 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4934 "no change (%d %d)", 4935 nxgep->mac.is_jumbo, 4936 result)); 4937 return (0); 4938 } 4939 } 4940 4941 param_arr[param_accept_jumbo].value = result; 4942 nxgep->mac.is_jumbo = B_FALSE; 4943 if (result) { 4944 nxgep->mac.is_jumbo = B_TRUE; 4945 } 4946 4947 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4948 "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 4949 pr_name, result, nxgep->mac.is_jumbo)); 4950 4951 return (err); 4952 } 4953 4954 /* Blanking */ 4955 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 4956 err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 4957 (char *)pr_val, 4958 (caddr_t)¶m_arr[param_rxdma_intr_time]); 4959 if (err) { 4960 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4961 "<== nxge_set_priv_prop: " 4962 "unable to set (%s)", pr_name)); 4963 err = EINVAL; 4964 } else { 4965 err = 0; 4966 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4967 "<== nxge_set_priv_prop: " 4968 "set (%s)", pr_name)); 4969 } 4970 4971 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4972 "<== nxge_set_priv_prop: name %s (value %d)", 4973 pr_name, result)); 4974 4975 return (err); 4976 } 4977 4978 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 4979 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 4980 (char *)pr_val, 4981 (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 4982 if (err) { 4983 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4984 "<== nxge_set_priv_prop: " 4985 "unable to set (%s)", pr_name)); 4986 err = EINVAL; 4987 } else { 4988 err = 0; 4989 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4990 "<== nxge_set_priv_prop: " 4991 "set (%s)", pr_name)); 4992 } 4993 4994 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4995 "<== nxge_set_priv_prop: name %s (value %d)", 4996 pr_name, result)); 4997 4998 return (err); 4999 } 5000 5001 /* Classification */ 5002 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5003 if (pr_val == NULL) { 5004 err = EINVAL; 5005 return (err); 5006 } 5007 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5008 5009 err = nxge_param_set_ip_opt(nxgep, NULL, 5010 NULL, (char *)pr_val, 5011 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5012 5013 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5014 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5015 pr_name, result)); 5016 5017 return (err); 5018 } 5019 5020 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5021 if (pr_val == NULL) { 5022 err = EINVAL; 5023 return (err); 5024 } 5025 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5026 5027 err = nxge_param_set_ip_opt(nxgep, NULL, 5028 NULL, (char *)pr_val, 5029 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5030 5031 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5032 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5033 pr_name, result)); 5034 5035 return (err); 5036 } 5037 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5038 if (pr_val == NULL) { 5039 err = EINVAL; 5040 return (err); 5041 } 5042 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5043 5044 err = nxge_param_set_ip_opt(nxgep, NULL, 5045 NULL, (char *)pr_val, 5046 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5047 5048 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5049 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5050 pr_name, result)); 5051 5052 return (err); 5053 } 5054 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5055 if (pr_val == NULL) { 5056 err = EINVAL; 5057 return (err); 5058 } 5059 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5060 5061 err = nxge_param_set_ip_opt(nxgep, NULL, 5062 NULL, (char *)pr_val, 5063 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5064 5065 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5066 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5067 pr_name, result)); 5068 5069 return (err); 5070 } 5071 5072 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5073 if (pr_val == NULL) { 5074 err = EINVAL; 5075 return (err); 5076 } 5077 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5078 5079 err = nxge_param_set_ip_opt(nxgep, NULL, 5080 NULL, (char *)pr_val, 5081 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5082 5083 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5084 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5085 pr_name, result)); 5086 5087 return (err); 5088 } 5089 5090 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5091 if (pr_val == NULL) { 5092 err = EINVAL; 5093 return (err); 5094 } 5095 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5096 5097 err = nxge_param_set_ip_opt(nxgep, NULL, 5098 NULL, (char *)pr_val, 5099 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5100 5101 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5102 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5103 pr_name, result)); 5104 5105 return (err); 5106 } 5107 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5108 if (pr_val == NULL) { 5109 err = EINVAL; 5110 return (err); 5111 } 5112 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5113 5114 err = nxge_param_set_ip_opt(nxgep, NULL, 5115 NULL, (char *)pr_val, 5116 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5117 5118 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5119 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5120 pr_name, result)); 5121 5122 return (err); 5123 } 5124 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5125 if (pr_val == NULL) { 5126 err = EINVAL; 5127 return (err); 5128 } 5129 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5130 5131 err = nxge_param_set_ip_opt(nxgep, NULL, 5132 NULL, (char *)pr_val, 5133 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5134 5135 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5136 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5137 pr_name, result)); 5138 5139 return (err); 5140 } 5141 5142 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5143 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 5144 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5145 "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 5146 err = EBUSY; 5147 return (err); 5148 } 5149 if (pr_val == NULL) { 5150 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5151 "==> nxge_set_priv_prop: name %s (null)", pr_name)); 5152 err = EINVAL; 5153 return (err); 5154 } 5155 5156 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5157 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5158 "<== nxge_set_priv_prop: name %s " 5159 "(lso %d pr_val %s value %d)", 5160 pr_name, nxgep->soft_lso_enable, pr_val, result)); 5161 5162 if (result > 1 || result < 0) { 5163 err = EINVAL; 5164 } else { 5165 if (nxgep->soft_lso_enable == (uint32_t)result) { 5166 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5167 "no change (%d %d)", 5168 nxgep->soft_lso_enable, result)); 5169 return (0); 5170 } 5171 } 5172 5173 nxgep->soft_lso_enable = (int)result; 5174 5175 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5176 "<== nxge_set_priv_prop: name %s (value %d)", 5177 pr_name, result)); 5178 5179 return (err); 5180 } 5181 /* 5182 * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 5183 * following code to be executed. 5184 */ 5185 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5186 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5187 (caddr_t)¶m_arr[param_anar_10gfdx]); 5188 return (err); 5189 } 5190 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5191 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5192 (caddr_t)¶m_arr[param_anar_pause]); 5193 return (err); 5194 } 5195 5196 return (EINVAL); 5197 } 5198 5199 static int 5200 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5201 uint_t pr_valsize, void *pr_val) 5202 { 5203 p_nxge_param_t param_arr = nxgep->param_arr; 5204 char valstr[MAXNAMELEN]; 5205 int err = EINVAL; 5206 uint_t strsize; 5207 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 5208 5209 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5210 "==> nxge_get_priv_prop: property %s", pr_name)); 5211 5212 /* function number */ 5213 if (strcmp(pr_name, "_function_number") == 0) { 5214 if (is_default) 5215 return (ENOTSUP); 5216 (void) snprintf(valstr, sizeof (valstr), "%d", 5217 nxgep->function_num); 5218 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5219 "==> nxge_get_priv_prop: name %s " 5220 "(value %d valstr %s)", 5221 pr_name, nxgep->function_num, valstr)); 5222 5223 err = 0; 5224 goto done; 5225 } 5226 5227 /* Neptune firmware version */ 5228 if (strcmp(pr_name, "_fw_version") == 0) { 5229 if (is_default) 5230 return (ENOTSUP); 5231 (void) snprintf(valstr, sizeof (valstr), "%s", 5232 nxgep->vpd_info.ver); 5233 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5234 "==> nxge_get_priv_prop: name %s " 5235 "(value %d valstr %s)", 5236 pr_name, nxgep->vpd_info.ver, valstr)); 5237 5238 err = 0; 5239 goto done; 5240 } 5241 5242 /* port PHY mode */ 5243 if (strcmp(pr_name, "_port_mode") == 0) { 5244 if (is_default) 5245 return (ENOTSUP); 5246 switch (nxgep->mac.portmode) { 5247 case PORT_1G_COPPER: 5248 (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 5249 nxgep->hot_swappable_phy ? 5250 "[Hot Swappable]" : ""); 5251 break; 5252 case PORT_1G_FIBER: 5253 (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 5254 nxgep->hot_swappable_phy ? 5255 "[hot swappable]" : ""); 5256 break; 5257 case PORT_10G_COPPER: 5258 (void) snprintf(valstr, sizeof (valstr), 5259 "10G copper %s", 5260 nxgep->hot_swappable_phy ? 5261 "[hot swappable]" : ""); 5262 break; 5263 case PORT_10G_FIBER: 5264 (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 5265 nxgep->hot_swappable_phy ? 5266 "[hot swappable]" : ""); 5267 break; 5268 case PORT_10G_SERDES: 5269 (void) snprintf(valstr, sizeof (valstr), 5270 "10G serdes %s", nxgep->hot_swappable_phy ? 5271 "[hot swappable]" : ""); 5272 break; 5273 case PORT_1G_SERDES: 5274 (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 5275 nxgep->hot_swappable_phy ? 5276 "[hot swappable]" : ""); 5277 break; 5278 case PORT_1G_TN1010: 5279 (void) snprintf(valstr, sizeof (valstr), 5280 "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 5281 "[hot swappable]" : ""); 5282 break; 5283 case PORT_10G_TN1010: 5284 (void) snprintf(valstr, sizeof (valstr), 5285 "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 5286 "[hot swappable]" : ""); 5287 break; 5288 case PORT_1G_RGMII_FIBER: 5289 (void) snprintf(valstr, sizeof (valstr), 5290 "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 5291 "[hot swappable]" : ""); 5292 break; 5293 case PORT_HSP_MODE: 5294 (void) snprintf(valstr, sizeof (valstr), 5295 "phy not present[hot swappable]"); 5296 break; 5297 default: 5298 (void) snprintf(valstr, sizeof (valstr), "unknown %s", 5299 nxgep->hot_swappable_phy ? 5300 "[hot swappable]" : ""); 5301 break; 5302 } 5303 5304 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5305 "==> nxge_get_priv_prop: name %s (value %s)", 5306 pr_name, valstr)); 5307 5308 err = 0; 5309 goto done; 5310 } 5311 5312 /* Hot swappable PHY */ 5313 if (strcmp(pr_name, "_hot_swap_phy") == 0) { 5314 if (is_default) 5315 return (ENOTSUP); 5316 (void) snprintf(valstr, sizeof (valstr), "%s", 5317 nxgep->hot_swappable_phy ? 5318 "yes" : "no"); 5319 5320 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5321 "==> nxge_get_priv_prop: name %s " 5322 "(value %d valstr %s)", 5323 pr_name, nxgep->hot_swappable_phy, valstr)); 5324 5325 err = 0; 5326 goto done; 5327 } 5328 5329 5330 /* accept jumbo */ 5331 if (strcmp(pr_name, "_accept_jumbo") == 0) { 5332 if (is_default) 5333 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5334 else 5335 (void) snprintf(valstr, sizeof (valstr), 5336 "%d", nxgep->mac.is_jumbo); 5337 err = 0; 5338 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5339 "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 5340 pr_name, 5341 (uint32_t)param_arr[param_accept_jumbo].value, 5342 nxgep->mac.is_jumbo, 5343 nxge_jumbo_enable)); 5344 5345 goto done; 5346 } 5347 5348 /* Receive Interrupt Blanking Parameters */ 5349 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 5350 err = 0; 5351 if (is_default) { 5352 (void) snprintf(valstr, sizeof (valstr), 5353 "%d", RXDMA_RCR_TO_DEFAULT); 5354 goto done; 5355 } 5356 5357 (void) snprintf(valstr, sizeof (valstr), "%d", 5358 nxgep->intr_timeout); 5359 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5360 "==> nxge_get_priv_prop: name %s (value %d)", 5361 pr_name, 5362 (uint32_t)nxgep->intr_timeout)); 5363 goto done; 5364 } 5365 5366 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 5367 err = 0; 5368 if (is_default) { 5369 (void) snprintf(valstr, sizeof (valstr), 5370 "%d", RXDMA_RCR_PTHRES_DEFAULT); 5371 goto done; 5372 } 5373 (void) snprintf(valstr, sizeof (valstr), "%d", 5374 nxgep->intr_threshold); 5375 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5376 "==> nxge_get_priv_prop: name %s (value %d)", 5377 pr_name, (uint32_t)nxgep->intr_threshold)); 5378 5379 goto done; 5380 } 5381 5382 /* Classification and Load Distribution Configuration */ 5383 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5384 if (is_default) { 5385 (void) snprintf(valstr, sizeof (valstr), "%x", 5386 NXGE_CLASS_FLOW_GEN_SERVER); 5387 err = 0; 5388 goto done; 5389 } 5390 err = nxge_dld_get_ip_opt(nxgep, 5391 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5392 5393 (void) snprintf(valstr, sizeof (valstr), "%x", 5394 (int)param_arr[param_class_opt_ipv4_tcp].value); 5395 5396 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5397 "==> nxge_get_priv_prop: %s", valstr)); 5398 goto done; 5399 } 5400 5401 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5402 if (is_default) { 5403 (void) snprintf(valstr, sizeof (valstr), "%x", 5404 NXGE_CLASS_FLOW_GEN_SERVER); 5405 err = 0; 5406 goto done; 5407 } 5408 err = nxge_dld_get_ip_opt(nxgep, 5409 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5410 5411 (void) snprintf(valstr, sizeof (valstr), "%x", 5412 (int)param_arr[param_class_opt_ipv4_udp].value); 5413 5414 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5415 "==> nxge_get_priv_prop: %s", valstr)); 5416 goto done; 5417 } 5418 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5419 if (is_default) { 5420 (void) snprintf(valstr, sizeof (valstr), "%x", 5421 NXGE_CLASS_FLOW_GEN_SERVER); 5422 err = 0; 5423 goto done; 5424 } 5425 err = nxge_dld_get_ip_opt(nxgep, 5426 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5427 5428 (void) snprintf(valstr, sizeof (valstr), "%x", 5429 (int)param_arr[param_class_opt_ipv4_ah].value); 5430 5431 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5432 "==> nxge_get_priv_prop: %s", valstr)); 5433 goto done; 5434 } 5435 5436 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5437 if (is_default) { 5438 (void) snprintf(valstr, sizeof (valstr), "%x", 5439 NXGE_CLASS_FLOW_GEN_SERVER); 5440 err = 0; 5441 goto done; 5442 } 5443 err = nxge_dld_get_ip_opt(nxgep, 5444 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5445 5446 (void) snprintf(valstr, sizeof (valstr), "%x", 5447 (int)param_arr[param_class_opt_ipv4_sctp].value); 5448 5449 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5450 "==> nxge_get_priv_prop: %s", valstr)); 5451 goto done; 5452 } 5453 5454 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5455 if (is_default) { 5456 (void) snprintf(valstr, sizeof (valstr), "%x", 5457 NXGE_CLASS_FLOW_GEN_SERVER); 5458 err = 0; 5459 goto done; 5460 } 5461 err = nxge_dld_get_ip_opt(nxgep, 5462 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5463 5464 (void) snprintf(valstr, sizeof (valstr), "%x", 5465 (int)param_arr[param_class_opt_ipv6_tcp].value); 5466 5467 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5468 "==> nxge_get_priv_prop: %s", valstr)); 5469 goto done; 5470 } 5471 5472 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5473 if (is_default) { 5474 (void) snprintf(valstr, sizeof (valstr), "%x", 5475 NXGE_CLASS_FLOW_GEN_SERVER); 5476 err = 0; 5477 goto done; 5478 } 5479 err = nxge_dld_get_ip_opt(nxgep, 5480 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5481 5482 (void) snprintf(valstr, sizeof (valstr), "%x", 5483 (int)param_arr[param_class_opt_ipv6_udp].value); 5484 5485 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5486 "==> nxge_get_priv_prop: %s", valstr)); 5487 goto done; 5488 } 5489 5490 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5491 if (is_default) { 5492 (void) snprintf(valstr, sizeof (valstr), "%x", 5493 NXGE_CLASS_FLOW_GEN_SERVER); 5494 err = 0; 5495 goto done; 5496 } 5497 err = nxge_dld_get_ip_opt(nxgep, 5498 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5499 5500 (void) snprintf(valstr, sizeof (valstr), "%x", 5501 (int)param_arr[param_class_opt_ipv6_ah].value); 5502 5503 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5504 "==> nxge_get_priv_prop: %s", valstr)); 5505 goto done; 5506 } 5507 5508 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5509 if (is_default) { 5510 (void) snprintf(valstr, sizeof (valstr), "%x", 5511 NXGE_CLASS_FLOW_GEN_SERVER); 5512 err = 0; 5513 goto done; 5514 } 5515 err = nxge_dld_get_ip_opt(nxgep, 5516 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5517 5518 (void) snprintf(valstr, sizeof (valstr), "%x", 5519 (int)param_arr[param_class_opt_ipv6_sctp].value); 5520 5521 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5522 "==> nxge_get_priv_prop: %s", valstr)); 5523 goto done; 5524 } 5525 5526 /* Software LSO */ 5527 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5528 if (is_default) { 5529 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5530 err = 0; 5531 goto done; 5532 } 5533 (void) snprintf(valstr, sizeof (valstr), 5534 "%d", nxgep->soft_lso_enable); 5535 err = 0; 5536 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5537 "==> nxge_get_priv_prop: name %s (value %d)", 5538 pr_name, nxgep->soft_lso_enable)); 5539 5540 goto done; 5541 } 5542 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5543 err = 0; 5544 if (is_default || 5545 nxgep->param_arr[param_anar_10gfdx].value != 0) { 5546 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5547 goto done; 5548 } else { 5549 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5550 goto done; 5551 } 5552 } 5553 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5554 err = 0; 5555 if (is_default || 5556 nxgep->param_arr[param_anar_pause].value != 0) { 5557 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5558 goto done; 5559 } else { 5560 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5561 goto done; 5562 } 5563 } 5564 5565 done: 5566 if (err == 0) { 5567 strsize = (uint_t)strlen(valstr); 5568 if (pr_valsize < strsize) { 5569 err = ENOBUFS; 5570 } else { 5571 (void) strlcpy(pr_val, valstr, pr_valsize); 5572 } 5573 } 5574 5575 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5576 "<== nxge_get_priv_prop: return %d", err)); 5577 return (err); 5578 } 5579 5580 /* 5581 * Module loading and removing entry points. 5582 */ 5583 5584 DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5585 nodev, NULL, D_MP, NULL, nxge_quiesce); 5586 5587 #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 5588 5589 /* 5590 * Module linkage information for the kernel. 5591 */ 5592 static struct modldrv nxge_modldrv = { 5593 &mod_driverops, 5594 NXGE_DESC_VER, 5595 &nxge_dev_ops 5596 }; 5597 5598 static struct modlinkage modlinkage = { 5599 MODREV_1, (void *) &nxge_modldrv, NULL 5600 }; 5601 5602 int 5603 _init(void) 5604 { 5605 int status; 5606 5607 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 5608 mac_init_ops(&nxge_dev_ops, "nxge"); 5609 status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 5610 if (status != 0) { 5611 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5612 "failed to init device soft state")); 5613 goto _init_exit; 5614 } 5615 status = mod_install(&modlinkage); 5616 if (status != 0) { 5617 ddi_soft_state_fini(&nxge_list); 5618 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 5619 goto _init_exit; 5620 } 5621 5622 MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 5623 5624 _init_exit: 5625 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 5626 5627 return (status); 5628 } 5629 5630 int 5631 _fini(void) 5632 { 5633 int status; 5634 5635 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 5636 5637 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5638 5639 if (nxge_mblks_pending) 5640 return (EBUSY); 5641 5642 status = mod_remove(&modlinkage); 5643 if (status != DDI_SUCCESS) { 5644 NXGE_DEBUG_MSG((NULL, MOD_CTL, 5645 "Module removal failed 0x%08x", 5646 status)); 5647 goto _fini_exit; 5648 } 5649 5650 mac_fini_ops(&nxge_dev_ops); 5651 5652 ddi_soft_state_fini(&nxge_list); 5653 5654 MUTEX_DESTROY(&nxge_common_lock); 5655 _fini_exit: 5656 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 5657 5658 return (status); 5659 } 5660 5661 int 5662 _info(struct modinfo *modinfop) 5663 { 5664 int status; 5665 5666 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 5667 status = mod_info(&modlinkage, modinfop); 5668 NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 5669 5670 return (status); 5671 } 5672 5673 /*ARGSUSED*/ 5674 static nxge_status_t 5675 nxge_add_intrs(p_nxge_t nxgep) 5676 { 5677 5678 int intr_types; 5679 int type = 0; 5680 int ddi_status = DDI_SUCCESS; 5681 nxge_status_t status = NXGE_OK; 5682 5683 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 5684 5685 nxgep->nxge_intr_type.intr_registered = B_FALSE; 5686 nxgep->nxge_intr_type.intr_enabled = B_FALSE; 5687 nxgep->nxge_intr_type.msi_intx_cnt = 0; 5688 nxgep->nxge_intr_type.intr_added = 0; 5689 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 5690 nxgep->nxge_intr_type.intr_type = 0; 5691 5692 if (nxgep->niu_type == N2_NIU) { 5693 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5694 } else if (nxge_msi_enable) { 5695 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5696 } 5697 5698 /* Get the supported interrupt types */ 5699 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 5700 != DDI_SUCCESS) { 5701 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 5702 "ddi_intr_get_supported_types failed: status 0x%08x", 5703 ddi_status)); 5704 return (NXGE_ERROR | NXGE_DDI_FAILED); 5705 } 5706 nxgep->nxge_intr_type.intr_types = intr_types; 5707 5708 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5709 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5710 5711 /* 5712 * Solaris MSIX is not supported yet. use MSI for now. 5713 * nxge_msi_enable (1): 5714 * 1 - MSI 2 - MSI-X others - FIXED 5715 */ 5716 switch (nxge_msi_enable) { 5717 default: 5718 type = DDI_INTR_TYPE_FIXED; 5719 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5720 "use fixed (intx emulation) type %08x", 5721 type)); 5722 break; 5723 5724 case 2: 5725 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5726 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5727 if (intr_types & DDI_INTR_TYPE_MSIX) { 5728 type = DDI_INTR_TYPE_MSIX; 5729 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5730 "ddi_intr_get_supported_types: MSIX 0x%08x", 5731 type)); 5732 } else if (intr_types & DDI_INTR_TYPE_MSI) { 5733 type = DDI_INTR_TYPE_MSI; 5734 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5735 "ddi_intr_get_supported_types: MSI 0x%08x", 5736 type)); 5737 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5738 type = DDI_INTR_TYPE_FIXED; 5739 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5740 "ddi_intr_get_supported_types: MSXED0x%08x", 5741 type)); 5742 } 5743 break; 5744 5745 case 1: 5746 if (intr_types & DDI_INTR_TYPE_MSI) { 5747 type = DDI_INTR_TYPE_MSI; 5748 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5749 "ddi_intr_get_supported_types: MSI 0x%08x", 5750 type)); 5751 } else if (intr_types & DDI_INTR_TYPE_MSIX) { 5752 type = DDI_INTR_TYPE_MSIX; 5753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5754 "ddi_intr_get_supported_types: MSIX 0x%08x", 5755 type)); 5756 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5757 type = DDI_INTR_TYPE_FIXED; 5758 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5759 "ddi_intr_get_supported_types: MSXED0x%08x", 5760 type)); 5761 } 5762 } 5763 5764 nxgep->nxge_intr_type.intr_type = type; 5765 if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 5766 type == DDI_INTR_TYPE_FIXED) && 5767 nxgep->nxge_intr_type.niu_msi_enable) { 5768 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 5769 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5770 " nxge_add_intrs: " 5771 " nxge_add_intrs_adv failed: status 0x%08x", 5772 status)); 5773 return (status); 5774 } else { 5775 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5776 "interrupts registered : type %d", type)); 5777 nxgep->nxge_intr_type.intr_registered = B_TRUE; 5778 5779 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5780 "\nAdded advanced nxge add_intr_adv " 5781 "intr type 0x%x\n", type)); 5782 5783 return (status); 5784 } 5785 } 5786 5787 if (!nxgep->nxge_intr_type.intr_registered) { 5788 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 5789 "failed to register interrupts")); 5790 return (NXGE_ERROR | NXGE_DDI_FAILED); 5791 } 5792 5793 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 5794 return (status); 5795 } 5796 5797 /*ARGSUSED*/ 5798 static nxge_status_t 5799 nxge_add_soft_intrs(p_nxge_t nxgep) 5800 { 5801 5802 int ddi_status = DDI_SUCCESS; 5803 nxge_status_t status = NXGE_OK; 5804 5805 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 5806 5807 nxgep->resched_id = NULL; 5808 nxgep->resched_running = B_FALSE; 5809 ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 5810 &nxgep->resched_id, 5811 NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 5812 if (ddi_status != DDI_SUCCESS) { 5813 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 5814 "ddi_add_softintrs failed: status 0x%08x", 5815 ddi_status)); 5816 return (NXGE_ERROR | NXGE_DDI_FAILED); 5817 } 5818 5819 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 5820 5821 return (status); 5822 } 5823 5824 static nxge_status_t 5825 nxge_add_intrs_adv(p_nxge_t nxgep) 5826 { 5827 int intr_type; 5828 p_nxge_intr_t intrp; 5829 5830 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 5831 5832 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5833 intr_type = intrp->intr_type; 5834 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 5835 intr_type)); 5836 5837 switch (intr_type) { 5838 case DDI_INTR_TYPE_MSI: /* 0x2 */ 5839 case DDI_INTR_TYPE_MSIX: /* 0x4 */ 5840 return (nxge_add_intrs_adv_type(nxgep, intr_type)); 5841 5842 case DDI_INTR_TYPE_FIXED: /* 0x1 */ 5843 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 5844 5845 default: 5846 return (NXGE_ERROR); 5847 } 5848 } 5849 5850 5851 /*ARGSUSED*/ 5852 static nxge_status_t 5853 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 5854 { 5855 dev_info_t *dip = nxgep->dip; 5856 p_nxge_ldg_t ldgp; 5857 p_nxge_intr_t intrp; 5858 uint_t *inthandler; 5859 void *arg1, *arg2; 5860 int behavior; 5861 int nintrs, navail, nrequest; 5862 int nactual, nrequired; 5863 int inum = 0; 5864 int x, y; 5865 int ddi_status = DDI_SUCCESS; 5866 nxge_status_t status = NXGE_OK; 5867 5868 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 5869 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5870 intrp->start_inum = 0; 5871 5872 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 5873 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 5874 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5875 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 5876 "nintrs: %d", ddi_status, nintrs)); 5877 return (NXGE_ERROR | NXGE_DDI_FAILED); 5878 } 5879 5880 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 5881 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 5882 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5883 "ddi_intr_get_navail() failed, status: 0x%x%, " 5884 "nintrs: %d", ddi_status, navail)); 5885 return (NXGE_ERROR | NXGE_DDI_FAILED); 5886 } 5887 5888 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5889 "ddi_intr_get_navail() returned: nintrs %d, navail %d", 5890 nintrs, navail)); 5891 5892 /* PSARC/2007/453 MSI-X interrupt limit override */ 5893 if (int_type == DDI_INTR_TYPE_MSIX) { 5894 nrequest = nxge_create_msi_property(nxgep); 5895 if (nrequest < navail) { 5896 navail = nrequest; 5897 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5898 "nxge_add_intrs_adv_type: nintrs %d " 5899 "navail %d (nrequest %d)", 5900 nintrs, navail, nrequest)); 5901 } 5902 } 5903 5904 if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 5905 /* MSI must be power of 2 */ 5906 if ((navail & 16) == 16) { 5907 navail = 16; 5908 } else if ((navail & 8) == 8) { 5909 navail = 8; 5910 } else if ((navail & 4) == 4) { 5911 navail = 4; 5912 } else if ((navail & 2) == 2) { 5913 navail = 2; 5914 } else { 5915 navail = 1; 5916 } 5917 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5918 "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 5919 "navail %d", nintrs, navail)); 5920 } 5921 5922 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 5923 DDI_INTR_ALLOC_NORMAL); 5924 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 5925 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 5926 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 5927 navail, &nactual, behavior); 5928 if (ddi_status != DDI_SUCCESS || nactual == 0) { 5929 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5930 " ddi_intr_alloc() failed: %d", 5931 ddi_status)); 5932 kmem_free(intrp->htable, intrp->intr_size); 5933 return (NXGE_ERROR | NXGE_DDI_FAILED); 5934 } 5935 5936 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 5937 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 5938 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5939 " ddi_intr_get_pri() failed: %d", 5940 ddi_status)); 5941 /* Free already allocated interrupts */ 5942 for (y = 0; y < nactual; y++) { 5943 (void) ddi_intr_free(intrp->htable[y]); 5944 } 5945 5946 kmem_free(intrp->htable, intrp->intr_size); 5947 return (NXGE_ERROR | NXGE_DDI_FAILED); 5948 } 5949 5950 nrequired = 0; 5951 switch (nxgep->niu_type) { 5952 default: 5953 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 5954 break; 5955 5956 case N2_NIU: 5957 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 5958 break; 5959 } 5960 5961 if (status != NXGE_OK) { 5962 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5963 "nxge_add_intrs_adv_typ:nxge_ldgv_init " 5964 "failed: 0x%x", status)); 5965 /* Free already allocated interrupts */ 5966 for (y = 0; y < nactual; y++) { 5967 (void) ddi_intr_free(intrp->htable[y]); 5968 } 5969 5970 kmem_free(intrp->htable, intrp->intr_size); 5971 return (status); 5972 } 5973 5974 ldgp = nxgep->ldgvp->ldgp; 5975 for (x = 0; x < nrequired; x++, ldgp++) { 5976 ldgp->vector = (uint8_t)x; 5977 ldgp->intdata = SID_DATA(ldgp->func, x); 5978 arg1 = ldgp->ldvp; 5979 arg2 = nxgep; 5980 if (ldgp->nldvs == 1) { 5981 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 5982 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5983 "nxge_add_intrs_adv_type: " 5984 "arg1 0x%x arg2 0x%x: " 5985 "1-1 int handler (entry %d intdata 0x%x)\n", 5986 arg1, arg2, 5987 x, ldgp->intdata)); 5988 } else if (ldgp->nldvs > 1) { 5989 inthandler = (uint_t *)ldgp->sys_intr_handler; 5990 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5991 "nxge_add_intrs_adv_type: " 5992 "arg1 0x%x arg2 0x%x: " 5993 "nldevs %d int handler " 5994 "(entry %d intdata 0x%x)\n", 5995 arg1, arg2, 5996 ldgp->nldvs, x, ldgp->intdata)); 5997 } 5998 5999 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6000 "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 6001 "htable 0x%llx", x, intrp->htable[x])); 6002 6003 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6004 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6005 != DDI_SUCCESS) { 6006 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6007 "==> nxge_add_intrs_adv_type: failed #%d " 6008 "status 0x%x", x, ddi_status)); 6009 for (y = 0; y < intrp->intr_added; y++) { 6010 (void) ddi_intr_remove_handler( 6011 intrp->htable[y]); 6012 } 6013 /* Free already allocated intr */ 6014 for (y = 0; y < nactual; y++) { 6015 (void) ddi_intr_free(intrp->htable[y]); 6016 } 6017 kmem_free(intrp->htable, intrp->intr_size); 6018 6019 (void) nxge_ldgv_uninit(nxgep); 6020 6021 return (NXGE_ERROR | NXGE_DDI_FAILED); 6022 } 6023 intrp->intr_added++; 6024 } 6025 6026 intrp->msi_intx_cnt = nactual; 6027 6028 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6029 "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 6030 navail, nactual, 6031 intrp->msi_intx_cnt, 6032 intrp->intr_added)); 6033 6034 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6035 6036 (void) nxge_intr_ldgv_init(nxgep); 6037 6038 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 6039 6040 return (status); 6041 } 6042 6043 /*ARGSUSED*/ 6044 static nxge_status_t 6045 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 6046 { 6047 dev_info_t *dip = nxgep->dip; 6048 p_nxge_ldg_t ldgp; 6049 p_nxge_intr_t intrp; 6050 uint_t *inthandler; 6051 void *arg1, *arg2; 6052 int behavior; 6053 int nintrs, navail; 6054 int nactual, nrequired; 6055 int inum = 0; 6056 int x, y; 6057 int ddi_status = DDI_SUCCESS; 6058 nxge_status_t status = NXGE_OK; 6059 6060 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 6061 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6062 intrp->start_inum = 0; 6063 6064 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 6065 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 6066 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6067 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 6068 "nintrs: %d", status, nintrs)); 6069 return (NXGE_ERROR | NXGE_DDI_FAILED); 6070 } 6071 6072 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 6073 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 6074 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6075 "ddi_intr_get_navail() failed, status: 0x%x%, " 6076 "nintrs: %d", ddi_status, navail)); 6077 return (NXGE_ERROR | NXGE_DDI_FAILED); 6078 } 6079 6080 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6081 "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 6082 nintrs, navail)); 6083 6084 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 6085 DDI_INTR_ALLOC_NORMAL); 6086 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 6087 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 6088 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 6089 navail, &nactual, behavior); 6090 if (ddi_status != DDI_SUCCESS || nactual == 0) { 6091 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6092 " ddi_intr_alloc() failed: %d", 6093 ddi_status)); 6094 kmem_free(intrp->htable, intrp->intr_size); 6095 return (NXGE_ERROR | NXGE_DDI_FAILED); 6096 } 6097 6098 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 6099 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 6100 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6101 " ddi_intr_get_pri() failed: %d", 6102 ddi_status)); 6103 /* Free already allocated interrupts */ 6104 for (y = 0; y < nactual; y++) { 6105 (void) ddi_intr_free(intrp->htable[y]); 6106 } 6107 6108 kmem_free(intrp->htable, intrp->intr_size); 6109 return (NXGE_ERROR | NXGE_DDI_FAILED); 6110 } 6111 6112 nrequired = 0; 6113 switch (nxgep->niu_type) { 6114 default: 6115 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 6116 break; 6117 6118 case N2_NIU: 6119 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6120 break; 6121 } 6122 6123 if (status != NXGE_OK) { 6124 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6125 "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 6126 "failed: 0x%x", status)); 6127 /* Free already allocated interrupts */ 6128 for (y = 0; y < nactual; y++) { 6129 (void) ddi_intr_free(intrp->htable[y]); 6130 } 6131 6132 kmem_free(intrp->htable, intrp->intr_size); 6133 return (status); 6134 } 6135 6136 ldgp = nxgep->ldgvp->ldgp; 6137 for (x = 0; x < nrequired; x++, ldgp++) { 6138 ldgp->vector = (uint8_t)x; 6139 if (nxgep->niu_type != N2_NIU) { 6140 ldgp->intdata = SID_DATA(ldgp->func, x); 6141 } 6142 6143 arg1 = ldgp->ldvp; 6144 arg2 = nxgep; 6145 if (ldgp->nldvs == 1) { 6146 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6147 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6148 "nxge_add_intrs_adv_type_fix: " 6149 "1-1 int handler(%d) ldg %d ldv %d " 6150 "arg1 $%p arg2 $%p\n", 6151 x, ldgp->ldg, ldgp->ldvp->ldv, 6152 arg1, arg2)); 6153 } else if (ldgp->nldvs > 1) { 6154 inthandler = (uint_t *)ldgp->sys_intr_handler; 6155 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6156 "nxge_add_intrs_adv_type_fix: " 6157 "shared ldv %d int handler(%d) ldv %d ldg %d" 6158 "arg1 0x%016llx arg2 0x%016llx\n", 6159 x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 6160 arg1, arg2)); 6161 } 6162 6163 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6164 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6165 != DDI_SUCCESS) { 6166 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6167 "==> nxge_add_intrs_adv_type_fix: failed #%d " 6168 "status 0x%x", x, ddi_status)); 6169 for (y = 0; y < intrp->intr_added; y++) { 6170 (void) ddi_intr_remove_handler( 6171 intrp->htable[y]); 6172 } 6173 for (y = 0; y < nactual; y++) { 6174 (void) ddi_intr_free(intrp->htable[y]); 6175 } 6176 /* Free already allocated intr */ 6177 kmem_free(intrp->htable, intrp->intr_size); 6178 6179 (void) nxge_ldgv_uninit(nxgep); 6180 6181 return (NXGE_ERROR | NXGE_DDI_FAILED); 6182 } 6183 intrp->intr_added++; 6184 } 6185 6186 intrp->msi_intx_cnt = nactual; 6187 6188 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6189 6190 status = nxge_intr_ldgv_init(nxgep); 6191 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 6192 6193 return (status); 6194 } 6195 6196 static void 6197 nxge_remove_intrs(p_nxge_t nxgep) 6198 { 6199 int i, inum; 6200 p_nxge_intr_t intrp; 6201 6202 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 6203 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6204 if (!intrp->intr_registered) { 6205 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6206 "<== nxge_remove_intrs: interrupts not registered")); 6207 return; 6208 } 6209 6210 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 6211 6212 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6213 (void) ddi_intr_block_disable(intrp->htable, 6214 intrp->intr_added); 6215 } else { 6216 for (i = 0; i < intrp->intr_added; i++) { 6217 (void) ddi_intr_disable(intrp->htable[i]); 6218 } 6219 } 6220 6221 for (inum = 0; inum < intrp->intr_added; inum++) { 6222 if (intrp->htable[inum]) { 6223 (void) ddi_intr_remove_handler(intrp->htable[inum]); 6224 } 6225 } 6226 6227 for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 6228 if (intrp->htable[inum]) { 6229 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6230 "nxge_remove_intrs: ddi_intr_free inum %d " 6231 "msi_intx_cnt %d intr_added %d", 6232 inum, 6233 intrp->msi_intx_cnt, 6234 intrp->intr_added)); 6235 6236 (void) ddi_intr_free(intrp->htable[inum]); 6237 } 6238 } 6239 6240 kmem_free(intrp->htable, intrp->intr_size); 6241 intrp->intr_registered = B_FALSE; 6242 intrp->intr_enabled = B_FALSE; 6243 intrp->msi_intx_cnt = 0; 6244 intrp->intr_added = 0; 6245 6246 (void) nxge_ldgv_uninit(nxgep); 6247 6248 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6249 "#msix-request"); 6250 6251 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 6252 } 6253 6254 /*ARGSUSED*/ 6255 static void 6256 nxge_remove_soft_intrs(p_nxge_t nxgep) 6257 { 6258 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 6259 if (nxgep->resched_id) { 6260 ddi_remove_softintr(nxgep->resched_id); 6261 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6262 "==> nxge_remove_soft_intrs: removed")); 6263 nxgep->resched_id = NULL; 6264 } 6265 6266 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 6267 } 6268 6269 /*ARGSUSED*/ 6270 static void 6271 nxge_intrs_enable(p_nxge_t nxgep) 6272 { 6273 p_nxge_intr_t intrp; 6274 int i; 6275 int status; 6276 6277 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 6278 6279 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6280 6281 if (!intrp->intr_registered) { 6282 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 6283 "interrupts are not registered")); 6284 return; 6285 } 6286 6287 if (intrp->intr_enabled) { 6288 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6289 "<== nxge_intrs_enable: already enabled")); 6290 return; 6291 } 6292 6293 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6294 status = ddi_intr_block_enable(intrp->htable, 6295 intrp->intr_added); 6296 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6297 "block enable - status 0x%x total inums #%d\n", 6298 status, intrp->intr_added)); 6299 } else { 6300 for (i = 0; i < intrp->intr_added; i++) { 6301 status = ddi_intr_enable(intrp->htable[i]); 6302 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6303 "ddi_intr_enable:enable - status 0x%x " 6304 "total inums %d enable inum #%d\n", 6305 status, intrp->intr_added, i)); 6306 if (status == DDI_SUCCESS) { 6307 intrp->intr_enabled = B_TRUE; 6308 } 6309 } 6310 } 6311 6312 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 6313 } 6314 6315 /*ARGSUSED*/ 6316 static void 6317 nxge_intrs_disable(p_nxge_t nxgep) 6318 { 6319 p_nxge_intr_t intrp; 6320 int i; 6321 6322 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 6323 6324 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6325 6326 if (!intrp->intr_registered) { 6327 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 6328 "interrupts are not registered")); 6329 return; 6330 } 6331 6332 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6333 (void) ddi_intr_block_disable(intrp->htable, 6334 intrp->intr_added); 6335 } else { 6336 for (i = 0; i < intrp->intr_added; i++) { 6337 (void) ddi_intr_disable(intrp->htable[i]); 6338 } 6339 } 6340 6341 intrp->intr_enabled = B_FALSE; 6342 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 6343 } 6344 6345 static nxge_status_t 6346 nxge_mac_register(p_nxge_t nxgep) 6347 { 6348 mac_register_t *macp; 6349 int status; 6350 6351 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 6352 6353 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 6354 return (NXGE_ERROR); 6355 6356 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 6357 macp->m_driver = nxgep; 6358 macp->m_dip = nxgep->dip; 6359 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 6360 macp->m_callbacks = &nxge_m_callbacks; 6361 macp->m_min_sdu = 0; 6362 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 6363 NXGE_EHEADER_VLAN_CRC; 6364 macp->m_max_sdu = nxgep->mac.default_mtu; 6365 macp->m_margin = VLAN_TAGSZ; 6366 macp->m_priv_props = nxge_priv_props; 6367 macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6368 6369 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6370 "==> nxge_mac_register: instance %d " 6371 "max_sdu %d margin %d maxframe %d (header %d)", 6372 nxgep->instance, 6373 macp->m_max_sdu, macp->m_margin, 6374 nxgep->mac.maxframesize, 6375 NXGE_EHEADER_VLAN_CRC)); 6376 6377 status = mac_register(macp, &nxgep->mach); 6378 mac_free(macp); 6379 6380 if (status != 0) { 6381 cmn_err(CE_WARN, 6382 "!nxge_mac_register failed (status %d instance %d)", 6383 status, nxgep->instance); 6384 return (NXGE_ERROR); 6385 } 6386 6387 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 6388 "(instance %d)", nxgep->instance)); 6389 6390 return (NXGE_OK); 6391 } 6392 6393 void 6394 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 6395 { 6396 ssize_t size; 6397 mblk_t *nmp; 6398 uint8_t blk_id; 6399 uint8_t chan; 6400 uint32_t err_id; 6401 err_inject_t *eip; 6402 6403 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 6404 6405 size = 1024; 6406 nmp = mp->b_cont; 6407 eip = (err_inject_t *)nmp->b_rptr; 6408 blk_id = eip->blk_id; 6409 err_id = eip->err_id; 6410 chan = eip->chan; 6411 cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 6412 cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 6413 cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 6414 switch (blk_id) { 6415 case MAC_BLK_ID: 6416 break; 6417 case TXMAC_BLK_ID: 6418 break; 6419 case RXMAC_BLK_ID: 6420 break; 6421 case MIF_BLK_ID: 6422 break; 6423 case IPP_BLK_ID: 6424 nxge_ipp_inject_err(nxgep, err_id); 6425 break; 6426 case TXC_BLK_ID: 6427 nxge_txc_inject_err(nxgep, err_id); 6428 break; 6429 case TXDMA_BLK_ID: 6430 nxge_txdma_inject_err(nxgep, err_id, chan); 6431 break; 6432 case RXDMA_BLK_ID: 6433 nxge_rxdma_inject_err(nxgep, err_id, chan); 6434 break; 6435 case ZCP_BLK_ID: 6436 nxge_zcp_inject_err(nxgep, err_id); 6437 break; 6438 case ESPC_BLK_ID: 6439 break; 6440 case FFLP_BLK_ID: 6441 break; 6442 case PHY_BLK_ID: 6443 break; 6444 case ETHER_SERDES_BLK_ID: 6445 break; 6446 case PCIE_SERDES_BLK_ID: 6447 break; 6448 case VIR_BLK_ID: 6449 break; 6450 } 6451 6452 nmp->b_wptr = nmp->b_rptr + size; 6453 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 6454 6455 miocack(wq, mp, (int)size, 0); 6456 } 6457 6458 static int 6459 nxge_init_common_dev(p_nxge_t nxgep) 6460 { 6461 p_nxge_hw_list_t hw_p; 6462 dev_info_t *p_dip; 6463 6464 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 6465 6466 p_dip = nxgep->p_dip; 6467 MUTEX_ENTER(&nxge_common_lock); 6468 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6469 "==> nxge_init_common_dev:func # %d", 6470 nxgep->function_num)); 6471 /* 6472 * Loop through existing per neptune hardware list. 6473 */ 6474 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6475 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6476 "==> nxge_init_common_device:func # %d " 6477 "hw_p $%p parent dip $%p", 6478 nxgep->function_num, 6479 hw_p, 6480 p_dip)); 6481 if (hw_p->parent_devp == p_dip) { 6482 nxgep->nxge_hw_p = hw_p; 6483 hw_p->ndevs++; 6484 hw_p->nxge_p[nxgep->function_num] = nxgep; 6485 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6486 "==> nxge_init_common_device:func # %d " 6487 "hw_p $%p parent dip $%p " 6488 "ndevs %d (found)", 6489 nxgep->function_num, 6490 hw_p, 6491 p_dip, 6492 hw_p->ndevs)); 6493 break; 6494 } 6495 } 6496 6497 if (hw_p == NULL) { 6498 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6499 "==> nxge_init_common_device:func # %d " 6500 "parent dip $%p (new)", 6501 nxgep->function_num, 6502 p_dip)); 6503 hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 6504 hw_p->parent_devp = p_dip; 6505 hw_p->magic = NXGE_NEPTUNE_MAGIC; 6506 nxgep->nxge_hw_p = hw_p; 6507 hw_p->ndevs++; 6508 hw_p->nxge_p[nxgep->function_num] = nxgep; 6509 hw_p->next = nxge_hw_list; 6510 if (nxgep->niu_type == N2_NIU) { 6511 hw_p->niu_type = N2_NIU; 6512 hw_p->platform_type = P_NEPTUNE_NIU; 6513 } else { 6514 hw_p->niu_type = NIU_TYPE_NONE; 6515 hw_p->platform_type = P_NEPTUNE_NONE; 6516 } 6517 6518 MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 6519 MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 6520 MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 6521 MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 6522 6523 nxge_hw_list = hw_p; 6524 6525 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 6526 } 6527 6528 MUTEX_EXIT(&nxge_common_lock); 6529 6530 nxgep->platform_type = hw_p->platform_type; 6531 if (nxgep->niu_type != N2_NIU) { 6532 nxgep->niu_type = hw_p->niu_type; 6533 } 6534 6535 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6536 "==> nxge_init_common_device (nxge_hw_list) $%p", 6537 nxge_hw_list)); 6538 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 6539 6540 return (NXGE_OK); 6541 } 6542 6543 static void 6544 nxge_uninit_common_dev(p_nxge_t nxgep) 6545 { 6546 p_nxge_hw_list_t hw_p, h_hw_p; 6547 p_nxge_dma_pt_cfg_t p_dma_cfgp; 6548 p_nxge_hw_pt_cfg_t p_cfgp; 6549 dev_info_t *p_dip; 6550 6551 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 6552 if (nxgep->nxge_hw_p == NULL) { 6553 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6554 "<== nxge_uninit_common_device (no common)")); 6555 return; 6556 } 6557 6558 MUTEX_ENTER(&nxge_common_lock); 6559 h_hw_p = nxge_hw_list; 6560 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6561 p_dip = hw_p->parent_devp; 6562 if (nxgep->nxge_hw_p == hw_p && 6563 p_dip == nxgep->p_dip && 6564 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 6565 hw_p->magic == NXGE_NEPTUNE_MAGIC) { 6566 6567 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6568 "==> nxge_uninit_common_device:func # %d " 6569 "hw_p $%p parent dip $%p " 6570 "ndevs %d (found)", 6571 nxgep->function_num, 6572 hw_p, 6573 p_dip, 6574 hw_p->ndevs)); 6575 6576 /* 6577 * Release the RDC table, a shared resoruce 6578 * of the nxge hardware. The RDC table was 6579 * assigned to this instance of nxge in 6580 * nxge_use_cfg_dma_config(). 6581 */ 6582 if (!isLDOMguest(nxgep)) { 6583 p_dma_cfgp = 6584 (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 6585 p_cfgp = 6586 (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 6587 (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6588 p_cfgp->def_mac_rxdma_grpid); 6589 } 6590 6591 if (hw_p->ndevs) { 6592 hw_p->ndevs--; 6593 } 6594 hw_p->nxge_p[nxgep->function_num] = NULL; 6595 if (!hw_p->ndevs) { 6596 MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 6597 MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 6598 MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 6599 MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 6600 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6601 "==> nxge_uninit_common_device: " 6602 "func # %d " 6603 "hw_p $%p parent dip $%p " 6604 "ndevs %d (last)", 6605 nxgep->function_num, 6606 hw_p, 6607 p_dip, 6608 hw_p->ndevs)); 6609 6610 nxge_hio_uninit(nxgep); 6611 6612 if (hw_p == nxge_hw_list) { 6613 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6614 "==> nxge_uninit_common_device:" 6615 "remove head func # %d " 6616 "hw_p $%p parent dip $%p " 6617 "ndevs %d (head)", 6618 nxgep->function_num, 6619 hw_p, 6620 p_dip, 6621 hw_p->ndevs)); 6622 nxge_hw_list = hw_p->next; 6623 } else { 6624 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6625 "==> nxge_uninit_common_device:" 6626 "remove middle func # %d " 6627 "hw_p $%p parent dip $%p " 6628 "ndevs %d (middle)", 6629 nxgep->function_num, 6630 hw_p, 6631 p_dip, 6632 hw_p->ndevs)); 6633 h_hw_p->next = hw_p->next; 6634 } 6635 6636 nxgep->nxge_hw_p = NULL; 6637 KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 6638 } 6639 break; 6640 } else { 6641 h_hw_p = hw_p; 6642 } 6643 } 6644 6645 MUTEX_EXIT(&nxge_common_lock); 6646 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6647 "==> nxge_uninit_common_device (nxge_hw_list) $%p", 6648 nxge_hw_list)); 6649 6650 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 6651 } 6652 6653 /* 6654 * Determines the number of ports from the niu_type or the platform type. 6655 * Returns the number of ports, or returns zero on failure. 6656 */ 6657 6658 int 6659 nxge_get_nports(p_nxge_t nxgep) 6660 { 6661 int nports = 0; 6662 6663 switch (nxgep->niu_type) { 6664 case N2_NIU: 6665 case NEPTUNE_2_10GF: 6666 nports = 2; 6667 break; 6668 case NEPTUNE_4_1GC: 6669 case NEPTUNE_2_10GF_2_1GC: 6670 case NEPTUNE_1_10GF_3_1GC: 6671 case NEPTUNE_1_1GC_1_10GF_2_1GC: 6672 case NEPTUNE_2_10GF_2_1GRF: 6673 nports = 4; 6674 break; 6675 default: 6676 switch (nxgep->platform_type) { 6677 case P_NEPTUNE_NIU: 6678 case P_NEPTUNE_ATLAS_2PORT: 6679 nports = 2; 6680 break; 6681 case P_NEPTUNE_ATLAS_4PORT: 6682 case P_NEPTUNE_MARAMBA_P0: 6683 case P_NEPTUNE_MARAMBA_P1: 6684 case P_NEPTUNE_ALONSO: 6685 nports = 4; 6686 break; 6687 default: 6688 break; 6689 } 6690 break; 6691 } 6692 6693 return (nports); 6694 } 6695 6696 /* 6697 * The following two functions are to support 6698 * PSARC/2007/453 MSI-X interrupt limit override. 6699 */ 6700 static int 6701 nxge_create_msi_property(p_nxge_t nxgep) 6702 { 6703 int nmsi; 6704 extern int ncpus; 6705 6706 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6707 6708 switch (nxgep->mac.portmode) { 6709 case PORT_10G_COPPER: 6710 case PORT_10G_FIBER: 6711 case PORT_10G_TN1010: 6712 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6713 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6714 /* 6715 * The maximum MSI-X requested will be 8. 6716 * If the # of CPUs is less than 8, we will reqeust 6717 * # MSI-X based on the # of CPUs. 6718 */ 6719 if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6720 nmsi = NXGE_MSIX_REQUEST_10G; 6721 } else { 6722 nmsi = ncpus; 6723 } 6724 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6725 "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6726 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6727 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6728 break; 6729 6730 default: 6731 nmsi = NXGE_MSIX_REQUEST_1G; 6732 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6733 "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6734 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6735 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6736 break; 6737 } 6738 6739 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6740 return (nmsi); 6741 } 6742 6743 /* ARGSUSED */ 6744 static int 6745 nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 6746 void *pr_val) 6747 { 6748 int err = 0; 6749 link_flowctrl_t fl; 6750 6751 switch (pr_num) { 6752 case MAC_PROP_AUTONEG: 6753 *(uint8_t *)pr_val = 1; 6754 break; 6755 case MAC_PROP_FLOWCTRL: 6756 if (pr_valsize < sizeof (link_flowctrl_t)) 6757 return (EINVAL); 6758 fl = LINK_FLOWCTRL_RX; 6759 bcopy(&fl, pr_val, sizeof (fl)); 6760 break; 6761 case MAC_PROP_ADV_1000FDX_CAP: 6762 case MAC_PROP_EN_1000FDX_CAP: 6763 *(uint8_t *)pr_val = 1; 6764 break; 6765 case MAC_PROP_ADV_100FDX_CAP: 6766 case MAC_PROP_EN_100FDX_CAP: 6767 *(uint8_t *)pr_val = 1; 6768 break; 6769 default: 6770 err = ENOTSUP; 6771 break; 6772 } 6773 return (err); 6774 } 6775 6776 6777 /* 6778 * The following is a software around for the Neptune hardware's 6779 * interrupt bugs; The Neptune hardware may generate spurious interrupts when 6780 * an interrupr handler is removed. 6781 */ 6782 #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 6783 #define NXGE_PIM_RESET (1ULL << 29) 6784 #define NXGE_GLU_RESET (1ULL << 30) 6785 #define NXGE_NIU_RESET (1ULL << 31) 6786 #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 6787 NXGE_GLU_RESET | \ 6788 NXGE_NIU_RESET) 6789 6790 #define NXGE_WAIT_QUITE_TIME 200000 6791 #define NXGE_WAIT_QUITE_RETRY 40 6792 #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 6793 6794 static void 6795 nxge_niu_peu_reset(p_nxge_t nxgep) 6796 { 6797 uint32_t rvalue; 6798 p_nxge_hw_list_t hw_p; 6799 p_nxge_t fnxgep; 6800 int i, j; 6801 6802 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 6803 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 6804 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6805 "==> nxge_niu_peu_reset: NULL hardware pointer")); 6806 return; 6807 } 6808 6809 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6810 "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 6811 hw_p->flags, nxgep->nxge_link_poll_timerid, 6812 nxgep->nxge_timerid)); 6813 6814 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 6815 /* 6816 * Make sure other instances from the same hardware 6817 * stop sending PIO and in quiescent state. 6818 */ 6819 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6820 fnxgep = hw_p->nxge_p[i]; 6821 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6822 "==> nxge_niu_peu_reset: checking entry %d " 6823 "nxgep $%p", i, fnxgep)); 6824 #ifdef NXGE_DEBUG 6825 if (fnxgep) { 6826 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6827 "==> nxge_niu_peu_reset: entry %d (function %d) " 6828 "link timer id %d hw timer id %d", 6829 i, fnxgep->function_num, 6830 fnxgep->nxge_link_poll_timerid, 6831 fnxgep->nxge_timerid)); 6832 } 6833 #endif 6834 if (fnxgep && fnxgep != nxgep && 6835 (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 6836 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6837 "==> nxge_niu_peu_reset: checking $%p " 6838 "(function %d) timer ids", 6839 fnxgep, fnxgep->function_num)); 6840 for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 6841 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6842 "==> nxge_niu_peu_reset: waiting")); 6843 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6844 if (!fnxgep->nxge_timerid && 6845 !fnxgep->nxge_link_poll_timerid) { 6846 break; 6847 } 6848 } 6849 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6850 if (fnxgep->nxge_timerid || 6851 fnxgep->nxge_link_poll_timerid) { 6852 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6853 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6854 "<== nxge_niu_peu_reset: cannot reset " 6855 "hardware (devices are still in use)")); 6856 return; 6857 } 6858 } 6859 } 6860 6861 if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 6862 hw_p->flags |= COMMON_RESET_NIU_PCI; 6863 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 6864 NXGE_PCI_PORT_LOGIC_OFFSET); 6865 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6866 "nxge_niu_peu_reset: read offset 0x%x (%d) " 6867 "(data 0x%x)", 6868 NXGE_PCI_PORT_LOGIC_OFFSET, 6869 NXGE_PCI_PORT_LOGIC_OFFSET, 6870 rvalue)); 6871 6872 rvalue |= NXGE_PCI_RESET_ALL; 6873 pci_config_put32(nxgep->dev_regs->nxge_pciregh, 6874 NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 6875 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6876 "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 6877 rvalue)); 6878 6879 NXGE_DELAY(NXGE_PCI_RESET_WAIT); 6880 } 6881 6882 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6883 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 6884 } 6885 6886 static void 6887 nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6888 { 6889 p_dev_regs_t dev_regs; 6890 uint32_t value; 6891 6892 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6893 6894 if (!nxge_set_replay_timer) { 6895 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6896 "==> nxge_set_pci_replay_timeout: will not change " 6897 "the timeout")); 6898 return; 6899 } 6900 6901 dev_regs = nxgep->dev_regs; 6902 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6903 "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6904 dev_regs, dev_regs->nxge_pciregh)); 6905 6906 if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6907 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6908 "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6909 "no PCI handle", 6910 dev_regs)); 6911 return; 6912 } 6913 value = (pci_config_get32(dev_regs->nxge_pciregh, 6914 PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6915 (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6916 6917 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6918 "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6919 "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6920 pci_config_get32(dev_regs->nxge_pciregh, 6921 PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6922 PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6923 6924 pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6925 value); 6926 6927 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6928 "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6929 pci_config_get32(dev_regs->nxge_pciregh, 6930 PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6931 6932 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6933 } 6934 6935 /* 6936 * quiesce(9E) entry point. 6937 * 6938 * This function is called when the system is single-threaded at high 6939 * PIL with preemption disabled. Therefore, this function must not be 6940 * blocked. 6941 * 6942 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6943 * DDI_FAILURE indicates an error condition and should almost never happen. 6944 */ 6945 static int 6946 nxge_quiesce(dev_info_t *dip) 6947 { 6948 int instance = ddi_get_instance(dip); 6949 p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 6950 6951 if (nxgep == NULL) 6952 return (DDI_FAILURE); 6953 6954 /* Turn off debugging */ 6955 nxge_debug_level = NO_DEBUG; 6956 nxgep->nxge_debug_level = NO_DEBUG; 6957 npi_debug_level = NO_DEBUG; 6958 6959 /* 6960 * Stop link monitor only when linkchkmod is interrupt based 6961 */ 6962 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 6963 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 6964 } 6965 6966 (void) nxge_intr_hw_disable(nxgep); 6967 6968 /* 6969 * Reset the receive MAC side. 6970 */ 6971 (void) nxge_rx_mac_disable(nxgep); 6972 6973 /* Disable and soft reset the IPP */ 6974 if (!isLDOMguest(nxgep)) 6975 (void) nxge_ipp_disable(nxgep); 6976 6977 /* 6978 * Reset the transmit/receive DMA side. 6979 */ 6980 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 6981 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 6982 6983 /* 6984 * Reset the transmit MAC side. 6985 */ 6986 (void) nxge_tx_mac_disable(nxgep); 6987 6988 return (DDI_SUCCESS); 6989 } 6990