1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/nxge/nxge_impl.h> 28 29 /* 30 * Tunable Receive Completion Ring Configuration B parameters. 31 */ 32 uint16_t nxge_rx_pkt_thres; /* 16 bits */ 33 uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 34 35 lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 36 lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 37 lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 38 lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 39 lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 40 lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 41 lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 42 lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 43 lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 44 lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 45 lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 46 lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 47 lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 48 49 uint32_t nxge_lb_dbg = 1; 50 void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 51 void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 52 static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 53 54 extern uint32_t nxge_rx_mode; 55 extern uint32_t nxge_jumbo_mtu; 56 57 static void 58 nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 59 60 /* ARGSUSED */ 61 nxge_status_t 62 nxge_global_reset(p_nxge_t nxgep) 63 { 64 nxge_status_t status = NXGE_OK; 65 66 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 67 68 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 69 return (status); 70 (void) nxge_intr_hw_disable(nxgep); 71 72 if ((nxgep->suspended) || 73 ((nxgep->statsp->port_stats.lb_mode == 74 nxge_lb_phy1000) || 75 (nxgep->statsp->port_stats.lb_mode == 76 nxge_lb_phy10g) || 77 (nxgep->statsp->port_stats.lb_mode == 78 nxge_lb_serdes1000) || 79 (nxgep->statsp->port_stats.lb_mode == 80 nxge_lb_serdes10g))) { 81 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 82 return (status); 83 } 84 85 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK) 86 return (status); 87 if ((status = nxge_mac_init(nxgep)) != NXGE_OK) 88 return (status); 89 (void) nxge_intr_hw_enable(nxgep); 90 91 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 92 return (status); 93 } 94 95 /* ARGSUSED */ 96 void 97 nxge_hw_id_init(p_nxge_t nxgep) 98 { 99 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 100 101 /* 102 * Set up initial hardware parameters required such as mac mtu size. 103 */ 104 nxgep->mac.is_jumbo = B_FALSE; 105 106 /* 107 * Set the maxframe size to 1522 (1518 + 4) to account for 108 * VLAN tagged packets. 109 */ 110 nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64 */ 111 nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */ 112 113 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init: maxframesize %d", 114 nxgep->mac.maxframesize)); 115 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 116 } 117 118 /* ARGSUSED */ 119 void 120 nxge_hw_init_niu_common(p_nxge_t nxgep) 121 { 122 p_nxge_hw_list_t hw_p; 123 124 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 125 126 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 127 return; 128 } 129 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 130 if (hw_p->flags & COMMON_INIT_DONE) { 131 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 132 "nxge_hw_init_niu_common" 133 " already done for dip $%p function %d exiting", 134 hw_p->parent_devp, nxgep->function_num)); 135 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 136 return; 137 } 138 139 hw_p->flags = COMMON_INIT_START; 140 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 141 " Started for device id %x with function %d", 142 hw_p->parent_devp, nxgep->function_num)); 143 144 /* per neptune common block init */ 145 (void) nxge_fflp_hw_reset(nxgep); 146 147 hw_p->flags = COMMON_INIT_DONE; 148 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 149 150 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 151 " Done for device id %x with function %d", 152 hw_p->parent_devp, nxgep->function_num)); 153 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 154 } 155 156 /* ARGSUSED */ 157 uint_t 158 nxge_intr(void *arg1, void *arg2) 159 { 160 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 161 p_nxge_t nxgep = (p_nxge_t)arg2; 162 uint_t serviced = DDI_INTR_UNCLAIMED; 163 uint8_t ldv; 164 npi_handle_t handle; 165 p_nxge_ldgv_t ldgvp; 166 p_nxge_ldg_t ldgp, t_ldgp; 167 p_nxge_ldv_t t_ldvp; 168 uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 169 int i, j, nldvs, nintrs = 1; 170 npi_status_t rs = NPI_SUCCESS; 171 172 /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 173 if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 174 nxgep = ldvp->nxgep; 175 } 176 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 177 178 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 179 NXGE_ERROR_MSG((nxgep, INT_CTL, 180 "<== nxge_intr: not initialized 0x%x", serviced)); 181 return (serviced); 182 } 183 184 ldgvp = nxgep->ldgvp; 185 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 186 if (ldvp == NULL && ldgvp) { 187 t_ldvp = ldvp = ldgvp->ldvp; 188 } 189 if (ldvp) { 190 ldgp = t_ldgp = ldvp->ldgp; 191 } 192 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 193 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 194 if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 195 NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 196 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 197 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 198 return (DDI_INTR_UNCLAIMED); 199 } 200 /* 201 * This interrupt handler will have to go through all the logical 202 * devices to find out which logical device interrupts us and then call 203 * its handler to process the events. 204 */ 205 handle = NXGE_DEV_NPI_HANDLE(nxgep); 206 t_ldgp = ldgp; 207 t_ldvp = ldgp->ldvp; 208 209 nldvs = ldgp->nldvs; 210 211 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 212 nldvs, ldgvp->ldg_intrs)); 213 214 serviced = DDI_INTR_CLAIMED; 215 for (i = 0; i < nintrs; i++, t_ldgp++) { 216 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 217 " #intrs %d", i, nldvs, nintrs)); 218 /* Get this group's flag bits. */ 219 rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 220 &vector0, &vector1, &vector2); 221 if (rs) { 222 continue; 223 } 224 if (!vector0 && !vector1 && !vector2) { 225 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 226 "no interrupts on group %d", t_ldgp->ldg)); 227 continue; 228 } 229 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 230 "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 231 vector0, vector1, vector2)); 232 nldvs = t_ldgp->nldvs; 233 for (j = 0; j < nldvs; j++, t_ldvp++) { 234 /* 235 * Call device's handler if flag bits are on. 236 */ 237 ldv = t_ldvp->ldv; 238 if (((ldv < NXGE_MAC_LD_START) && 239 (LDV_ON(ldv, vector0) | 240 (LDV_ON(ldv, vector1)))) || 241 (ldv >= NXGE_MAC_LD_START && 242 ((LDV2_ON_1(ldv, vector2)) || 243 (LDV2_ON_2(ldv, vector2))))) { 244 (void) (t_ldvp->ldv_intr_handler)( 245 (caddr_t)t_ldvp, arg2); 246 NXGE_DEBUG_MSG((nxgep, INT_CTL, 247 "==> nxge_intr: " 248 "calling device %d #ldvs %d #intrs %d", 249 j, nldvs, nintrs)); 250 } 251 } 252 } 253 254 t_ldgp = ldgp; 255 for (i = 0; i < nintrs; i++, t_ldgp++) { 256 /* rearm group interrupts */ 257 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 258 "group %d", t_ldgp->ldg)); 259 (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 260 t_ldgp->arm, t_ldgp->ldg_timer); 261 } 262 263 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 264 serviced)); 265 return (serviced); 266 } 267 268 269 /* 270 * XFP Related Status Register Values Under 3 Different Conditions 271 * 272 * -------------+-------------------------+------------------------- 273 * | Intel XFP and Avago | Picolight XFP 274 * -------------+---------+---------------+---------+--------------- 275 * | STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT 276 * -------------+---------+---------------+---------+--------------- 277 * No XFP | 0x639C | 0x40 | 0x639C | 0x40 278 * -------------+---------+---------------+---------+--------------- 279 * XFP,linkdown | 0x43BC | 0x40 | 0x639C | 0x40 280 * -------------+---------+---------------+---------+--------------- 281 * XFP,linkup | 0x03FC | 0x0 | 0x03FC | 0x0 282 * -------------+---------+---------------+---------+--------------- 283 * Note: 284 * STATUS0 = BCM8704_USER_ANALOG_STATUS0_REG 285 * TX_ALARM_STAT = BCM8704_USER_TX_ALARM_STATUS_REG 286 */ 287 /* ARGSUSED */ 288 static nxge_status_t 289 nxge_check_xaui_xfp(p_nxge_t nxgep) 290 { 291 nxge_status_t status = NXGE_OK; 292 uint8_t phy_port_addr; 293 uint16_t val; 294 uint16_t val1; 295 uint8_t portn; 296 297 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 298 299 portn = nxgep->mac.portnum; 300 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 301 302 /* 303 * Keep the val1 code even though it is not used. Could be 304 * used to differenciate the "No XFP" case and "XFP,linkdown" 305 * case when a Intel XFP is used. 306 */ 307 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 308 BCM8704_USER_DEV3_ADDR, 309 BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 310 status = nxge_mdio_read(nxgep, phy_port_addr, 311 BCM8704_USER_DEV3_ADDR, 312 BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 313 } 314 315 if (status != NXGE_OK) { 316 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 317 NXGE_FM_EREPORT_XAUI_ERR); 318 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 319 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 320 "XAUI is bad or absent on port<%d>\n", portn)); 321 } 322 #ifdef NXGE_DEBUG 323 /* 324 * As a workaround for CR6693529, do not execute this block of 325 * code for non-debug driver. When a Picolight XFP transceiver 326 * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns 327 * the same 0x639C value in normal link down case, which causes 328 * false FMA messages and link reconnection problem. 329 */ 330 } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 331 /* 332 * 0x03FC = 0000 0011 1111 1100 (XFP is normal) 333 * 0x639C = 0110 0011 1001 1100 (XFP has problem) 334 * bit14 = 1: PDM loss-of-light indicator 335 * bit13 = 1: PDM Rx loss-of-signal 336 * bit6 = 0: Light is NOT ok 337 * bit5 = 0: PMD Rx signal is NOT ok 338 */ 339 if (val == 0x639C) { 340 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 341 NXGE_FM_EREPORT_XFP_ERR); 342 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 343 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 344 "XFP is bad or absent on port<%d>\n", 345 portn)); 346 } 347 status = NXGE_ERROR; 348 } 349 #endif 350 } 351 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 352 return (status); 353 } 354 355 356 /* ARGSUSED */ 357 uint_t 358 nxge_syserr_intr(void *arg1, void *arg2) 359 { 360 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 361 p_nxge_t nxgep = (p_nxge_t)arg2; 362 p_nxge_ldg_t ldgp = NULL; 363 npi_handle_t handle; 364 sys_err_stat_t estat; 365 uint_t serviced = DDI_INTR_UNCLAIMED; 366 367 if (arg1 == NULL && arg2 == NULL) { 368 return (serviced); 369 } 370 if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 371 if (ldvp != NULL) { 372 nxgep = ldvp->nxgep; 373 } 374 } 375 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 376 "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 377 if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 378 ldgp = ldvp->ldgp; 379 if (ldgp == NULL) { 380 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 381 "<== nxge_syserrintr(no logical group): " 382 "arg2 $%p arg1 $%p", nxgep, ldvp)); 383 return (DDI_INTR_UNCLAIMED); 384 } 385 /* 386 * Get the logical device state if the function uses interrupt. 387 */ 388 } 389 390 /* This interrupt handler is for system error interrupts. */ 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 estat.value = 0; 393 (void) npi_fzc_sys_err_stat_get(handle, &estat); 394 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 395 "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 396 397 if (estat.bits.ldw.smx) { 398 /* SMX */ 399 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 400 "==> nxge_syserr_intr: device error - SMX")); 401 } else if (estat.bits.ldw.mac) { 402 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 403 "==> nxge_syserr_intr: device error - MAC")); 404 /* 405 * There is nothing to be done here. All MAC errors go to per 406 * MAC port interrupt. MIF interrupt is the only MAC sub-block 407 * that can generate status here. MIF status reported will be 408 * ignored here. It is checked by per port timer instead. 409 */ 410 } else if (estat.bits.ldw.ipp) { 411 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 412 "==> nxge_syserr_intr: device error - IPP")); 413 (void) nxge_ipp_handle_sys_errors(nxgep); 414 } else if (estat.bits.ldw.zcp) { 415 /* ZCP */ 416 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 417 "==> nxge_syserr_intr: device error - ZCP")); 418 (void) nxge_zcp_handle_sys_errors(nxgep); 419 } else if (estat.bits.ldw.tdmc) { 420 /* TDMC */ 421 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 422 "==> nxge_syserr_intr: device error - TDMC")); 423 /* 424 * There is no TDMC system errors defined in the PRM. All TDMC 425 * channel specific errors are reported on a per channel basis. 426 */ 427 } else if (estat.bits.ldw.rdmc) { 428 /* RDMC */ 429 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 430 "==> nxge_syserr_intr: device error - RDMC")); 431 (void) nxge_rxdma_handle_sys_errors(nxgep); 432 } else if (estat.bits.ldw.txc) { 433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 434 "==> nxge_syserr_intr: device error - TXC")); 435 (void) nxge_txc_handle_sys_errors(nxgep); 436 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 437 /* PCI-E */ 438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 439 "==> nxge_syserr_intr: device error - PCI-E")); 440 } else if (estat.bits.ldw.meta1) { 441 /* META1 */ 442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 443 "==> nxge_syserr_intr: device error - META1")); 444 } else if (estat.bits.ldw.meta2) { 445 /* META2 */ 446 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 447 "==> nxge_syserr_intr: device error - META2")); 448 } else if (estat.bits.ldw.fflp) { 449 /* FFLP */ 450 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 451 "==> nxge_syserr_intr: device error - FFLP")); 452 (void) nxge_fflp_handle_sys_errors(nxgep); 453 } 454 455 /* 456 * nxge_check_xaui_xfg checks XAUI for all of the following 457 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER. 458 */ 459 if (nxgep->mac.portmode == PORT_10G_FIBER || 460 nxgep->mac.portmode == PORT_10G_COPPER || 461 nxgep->mac.portmode == PORT_10G_TN1010 || 462 nxgep->mac.portmode == PORT_1G_TN1010) { 463 if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 464 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 465 "==> nxge_syserr_intr: device error - XAUI")); 466 } 467 } 468 469 serviced = DDI_INTR_CLAIMED; 470 471 if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 472 !ldvp->use_timer) { 473 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 474 B_TRUE, ldgp->ldg_timer); 475 } 476 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 477 return (serviced); 478 } 479 480 /* ARGSUSED */ 481 void 482 nxge_intr_hw_enable(p_nxge_t nxgep) 483 { 484 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 485 (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 486 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 487 } 488 489 /* ARGSUSED */ 490 void 491 nxge_intr_hw_disable(p_nxge_t nxgep) 492 { 493 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 494 (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 495 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 496 } 497 498 /* ARGSUSED */ 499 void 500 nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 501 { 502 p_nxge_t nxgep = (p_nxge_t)arg; 503 uint8_t channel; 504 npi_handle_t handle; 505 p_nxge_ldgv_t ldgvp; 506 p_nxge_ldv_t ldvp; 507 int i; 508 509 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 510 handle = NXGE_DEV_NPI_HANDLE(nxgep); 511 512 if ((ldgvp = nxgep->ldgvp) == NULL) { 513 NXGE_ERROR_MSG((nxgep, INT_CTL, 514 "<== nxge_rx_hw_blank (not enabled)")); 515 return; 516 } 517 ldvp = nxgep->ldgvp->ldvp; 518 if (ldvp == NULL) { 519 return; 520 } 521 for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 522 if (ldvp->is_rxdma) { 523 channel = ldvp->channel; 524 (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 525 channel, count); 526 (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 527 channel, ticks); 528 } 529 } 530 531 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 532 } 533 534 /* ARGSUSED */ 535 void 536 nxge_hw_stop(p_nxge_t nxgep) 537 { 538 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 539 540 (void) nxge_tx_mac_disable(nxgep); 541 (void) nxge_rx_mac_disable(nxgep); 542 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 543 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 544 545 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 546 } 547 548 /* ARGSUSED */ 549 void 550 nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 551 { 552 int cmd; 553 554 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 555 556 if (nxgep == NULL) { 557 miocnak(wq, mp, 0, EINVAL); 558 return; 559 } 560 iocp->ioc_error = 0; 561 cmd = iocp->ioc_cmd; 562 563 switch (cmd) { 564 default: 565 miocnak(wq, mp, 0, EINVAL); 566 return; 567 568 case NXGE_GET_MII: 569 nxge_get_mii(nxgep, mp->b_cont); 570 miocack(wq, mp, sizeof (uint16_t), 0); 571 break; 572 573 case NXGE_PUT_MII: 574 nxge_put_mii(nxgep, mp->b_cont); 575 miocack(wq, mp, 0, 0); 576 break; 577 578 case NXGE_GET64: 579 nxge_get64(nxgep, mp->b_cont); 580 miocack(wq, mp, sizeof (uint32_t), 0); 581 break; 582 583 case NXGE_PUT64: 584 nxge_put64(nxgep, mp->b_cont); 585 miocack(wq, mp, 0, 0); 586 break; 587 588 case NXGE_PUT_TCAM: 589 nxge_put_tcam(nxgep, mp->b_cont); 590 miocack(wq, mp, 0, 0); 591 break; 592 593 case NXGE_GET_TCAM: 594 nxge_get_tcam(nxgep, mp->b_cont); 595 miocack(wq, mp, 0, 0); 596 break; 597 598 case NXGE_TX_REGS_DUMP: 599 nxge_txdma_regs_dump_channels(nxgep); 600 miocack(wq, mp, 0, 0); 601 break; 602 case NXGE_RX_REGS_DUMP: 603 nxge_rxdma_regs_dump_channels(nxgep); 604 miocack(wq, mp, 0, 0); 605 break; 606 case NXGE_VIR_INT_REGS_DUMP: 607 case NXGE_INT_REGS_DUMP: 608 nxge_virint_regs_dump(nxgep); 609 miocack(wq, mp, 0, 0); 610 break; 611 case NXGE_RTRACE: 612 nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 613 break; 614 } 615 } 616 617 /* ARGSUSED */ 618 void 619 nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 620 struct iocblk *iocp) 621 { 622 p_lb_property_t lb_props; 623 624 size_t size; 625 int i; 626 627 if (mp->b_cont == NULL) { 628 miocnak(wq, mp, 0, EINVAL); 629 } 630 switch (iocp->ioc_cmd) { 631 case LB_GET_MODE: 632 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 633 if (nxgep != NULL) { 634 *(lb_info_sz_t *)mp->b_cont->b_rptr = 635 nxgep->statsp->port_stats.lb_mode; 636 miocack(wq, mp, sizeof (nxge_lb_t), 0); 637 } else { 638 miocnak(wq, mp, 0, EINVAL); 639 } 640 break; 641 case LB_SET_MODE: 642 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 643 if (iocp->ioc_count != sizeof (uint32_t)) { 644 miocack(wq, mp, 0, 0); 645 break; 646 } 647 if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 648 miocack(wq, mp, 0, 0); 649 } else { 650 miocnak(wq, mp, 0, EPROTO); 651 } 652 break; 653 case LB_GET_INFO_SIZE: 654 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 655 if (nxgep != NULL) { 656 size = sizeof (lb_normal); 657 if (nxgep->statsp->mac_stats.cap_10gfdx) { 658 /* TN1010 does not support external loopback */ 659 if (nxgep->mac.portmode != PORT_1G_TN1010 && 660 nxgep->mac.portmode != PORT_10G_TN1010) { 661 size += sizeof (lb_external10g); 662 } 663 size += sizeof (lb_mac10g); 664 /* Publish PHY loopback if PHY is present */ 665 if (nxgep->mac.portmode == PORT_10G_COPPER || 666 nxgep->mac.portmode == PORT_10G_TN1010 || 667 nxgep->mac.portmode == PORT_10G_FIBER) 668 size += sizeof (lb_phy10g); 669 } 670 671 /* 672 * Even if cap_10gfdx is false, we still do 10G 673 * serdes loopback as a part of SunVTS xnetlbtest 674 * internal loopback test. 675 */ 676 if (nxgep->mac.portmode == PORT_10G_FIBER || 677 nxgep->mac.portmode == PORT_10G_TN1010 || 678 nxgep->mac.portmode == PORT_10G_SERDES) 679 size += sizeof (lb_serdes10g); 680 681 if (nxgep->statsp->mac_stats.cap_1000fdx) { 682 /* TN1010 does not support external loopback */ 683 if (nxgep->mac.portmode != PORT_1G_TN1010 && 684 nxgep->mac.portmode != PORT_10G_TN1010) { 685 size += sizeof (lb_external1000); 686 } 687 size += sizeof (lb_mac1000); 688 if (nxgep->mac.portmode == PORT_1G_COPPER || 689 nxgep->mac.portmode == PORT_1G_TN1010 || 690 nxgep->mac.portmode == 691 PORT_1G_RGMII_FIBER) 692 size += sizeof (lb_phy1000); 693 } 694 if (nxgep->statsp->mac_stats.cap_100fdx) 695 size += sizeof (lb_external100); 696 if (nxgep->statsp->mac_stats.cap_10fdx) 697 size += sizeof (lb_external10); 698 if (nxgep->mac.portmode == PORT_1G_FIBER || 699 nxgep->mac.portmode == PORT_1G_TN1010 || 700 nxgep->mac.portmode == PORT_1G_SERDES) 701 size += sizeof (lb_serdes1000); 702 703 *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 704 705 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 706 "NXGE_GET_LB_INFO command: size %d", size)); 707 miocack(wq, mp, sizeof (lb_info_sz_t), 0); 708 } else 709 miocnak(wq, mp, 0, EINVAL); 710 break; 711 712 case LB_GET_INFO: 713 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 714 if (nxgep != NULL) { 715 size = sizeof (lb_normal); 716 if (nxgep->statsp->mac_stats.cap_10gfdx) { 717 /* TN1010 does not support external loopback */ 718 if (nxgep->mac.portmode != PORT_1G_TN1010 && 719 nxgep->mac.portmode != PORT_10G_TN1010) { 720 size += sizeof (lb_external10g); 721 } 722 size += sizeof (lb_mac10g); 723 /* Publish PHY loopback if PHY is present */ 724 if (nxgep->mac.portmode == PORT_10G_COPPER || 725 nxgep->mac.portmode == PORT_10G_TN1010 || 726 nxgep->mac.portmode == PORT_10G_FIBER) 727 size += sizeof (lb_phy10g); 728 } 729 if (nxgep->mac.portmode == PORT_10G_FIBER || 730 nxgep->mac.portmode == PORT_10G_TN1010 || 731 nxgep->mac.portmode == PORT_10G_SERDES) 732 size += sizeof (lb_serdes10g); 733 734 if (nxgep->statsp->mac_stats.cap_1000fdx) { 735 /* TN1010 does not support external loopback */ 736 if (nxgep->mac.portmode != PORT_1G_TN1010 && 737 nxgep->mac.portmode != PORT_10G_TN1010) { 738 size += sizeof (lb_external1000); 739 } 740 size += sizeof (lb_mac1000); 741 if (nxgep->mac.portmode == PORT_1G_COPPER || 742 nxgep->mac.portmode == PORT_1G_TN1010 || 743 nxgep->mac.portmode == 744 PORT_1G_RGMII_FIBER) 745 size += sizeof (lb_phy1000); 746 } 747 if (nxgep->statsp->mac_stats.cap_100fdx) 748 size += sizeof (lb_external100); 749 750 if (nxgep->statsp->mac_stats.cap_10fdx) 751 size += sizeof (lb_external10); 752 753 if (nxgep->mac.portmode == PORT_1G_FIBER || 754 nxgep->mac.portmode == PORT_1G_TN1010 || 755 nxgep->mac.portmode == PORT_1G_SERDES) 756 size += sizeof (lb_serdes1000); 757 758 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 759 "NXGE_GET_LB_INFO command: size %d", size)); 760 if (size == iocp->ioc_count) { 761 i = 0; 762 lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 763 lb_props[i++] = lb_normal; 764 765 if (nxgep->statsp->mac_stats.cap_10gfdx) { 766 lb_props[i++] = lb_mac10g; 767 if (nxgep->mac.portmode == 768 PORT_10G_COPPER || 769 nxgep->mac.portmode == 770 PORT_10G_TN1010 || 771 nxgep->mac.portmode == 772 PORT_10G_FIBER) { 773 lb_props[i++] = lb_phy10g; 774 } 775 /* TN1010 does not support ext lb */ 776 if (nxgep->mac.portmode != 777 PORT_10G_TN1010 && 778 nxgep->mac.portmode != 779 PORT_1G_TN1010) { 780 lb_props[i++] = lb_external10g; 781 } 782 } 783 784 if (nxgep->mac.portmode == PORT_10G_FIBER || 785 nxgep->mac.portmode == PORT_10G_TN1010 || 786 nxgep->mac.portmode == PORT_10G_SERDES) 787 lb_props[i++] = lb_serdes10g; 788 789 if (nxgep->statsp->mac_stats.cap_1000fdx) { 790 /* TN1010 does not support ext lb */ 791 if (nxgep->mac.portmode != 792 PORT_10G_TN1010 && 793 nxgep->mac.portmode != 794 PORT_1G_TN1010) { 795 lb_props[i++] = lb_external1000; 796 } 797 } 798 799 if (nxgep->statsp->mac_stats.cap_100fdx) 800 lb_props[i++] = lb_external100; 801 802 if (nxgep->statsp->mac_stats.cap_10fdx) 803 lb_props[i++] = lb_external10; 804 805 if (nxgep->statsp->mac_stats.cap_1000fdx) 806 lb_props[i++] = lb_mac1000; 807 808 if (nxgep->mac.portmode == PORT_1G_COPPER || 809 nxgep->mac.portmode == PORT_1G_TN1010 || 810 nxgep->mac.portmode == 811 PORT_1G_RGMII_FIBER) { 812 if (nxgep->statsp->mac_stats. 813 cap_1000fdx) 814 lb_props[i++] = lb_phy1000; 815 } else if (nxgep->mac.portmode == 816 PORT_1G_FIBER || 817 nxgep->mac.portmode == PORT_1G_TN1010 || 818 nxgep->mac.portmode == PORT_1G_SERDES) { 819 lb_props[i++] = lb_serdes1000; 820 } 821 miocack(wq, mp, size, 0); 822 } else 823 miocnak(wq, mp, 0, EINVAL); 824 } else { 825 miocnak(wq, mp, 0, EINVAL); 826 cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 827 iocp->ioc_cmd); 828 } 829 break; 830 } 831 } 832 833 /* 834 * DMA channel interfaces to access various channel specific 835 * hardware functions. 836 */ 837 /* ARGSUSED */ 838 void 839 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 840 uint32_t reg_base, uint16_t channel, uint64_t reg_data) 841 { 842 uint64_t reg_offset; 843 844 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 845 846 /* 847 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 848 * use the virtual DMA CSR address space from the config space (in PCI 849 * case), then the following code need to be use different offset 850 * computation macro. 851 */ 852 reg_offset = reg_base + DMC_OFFSET(channel); 853 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 854 855 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 856 } 857 858 /* ARGSUSED */ 859 uint64_t 860 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 861 uint32_t reg_base, uint16_t channel) 862 { 863 uint64_t reg_offset; 864 865 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 866 867 /* 868 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 869 * use the virtual DMA CSR address space from the config space (in PCI 870 * case), then the following code need to be use different offset 871 * computation macro. 872 */ 873 reg_offset = reg_base + DMC_OFFSET(channel); 874 875 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 876 877 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 878 } 879 880 /* ARGSUSED */ 881 void 882 nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 883 { 884 nxge_os_acc_handle_t nxge_regh; 885 886 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 887 nxge_regh = nxgep->dev_regs->nxge_regh; 888 889 *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 890 nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 891 892 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 893 *(uint32_t *)mp->b_rptr)); 894 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 895 } 896 897 /* ARGSUSED */ 898 void 899 nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 900 { 901 nxge_os_acc_handle_t nxge_regh; 902 uint32_t *buf; 903 uint8_t *reg; 904 905 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 906 nxge_regh = nxgep->dev_regs->nxge_regh; 907 908 buf = (uint32_t *)mp->b_rptr; 909 reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 910 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 911 "reg = 0x%016llX index = 0x%08X value = 0x%08X", 912 reg, buf[0], buf[1])); 913 NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 914 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 915 } 916 917 /*ARGSUSED*/ 918 boolean_t 919 nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 920 { 921 boolean_t status = B_TRUE; 922 uint32_t lb_mode; 923 lb_property_t *lb_info; 924 925 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 926 lb_mode = nxgep->statsp->port_stats.lb_mode; 927 if (lb_mode == *(uint32_t *)mp->b_rptr) { 928 cmn_err(CE_NOTE, 929 "!nxge%d: Loopback mode already set (lb_mode %d).\n", 930 nxgep->instance, lb_mode); 931 status = B_FALSE; 932 goto nxge_set_lb_exit; 933 } 934 lb_mode = *(uint32_t *)mp->b_rptr; 935 lb_info = NULL; 936 if (lb_mode == lb_normal.value) 937 lb_info = &lb_normal; 938 else if ((lb_mode == lb_external10g.value) && 939 (nxgep->statsp->mac_stats.cap_10gfdx)) 940 lb_info = &lb_external10g; 941 else if ((lb_mode == lb_external1000.value) && 942 (nxgep->statsp->mac_stats.cap_1000fdx)) 943 lb_info = &lb_external1000; 944 else if ((lb_mode == lb_external100.value) && 945 (nxgep->statsp->mac_stats.cap_100fdx)) 946 lb_info = &lb_external100; 947 else if ((lb_mode == lb_external10.value) && 948 (nxgep->statsp->mac_stats.cap_10fdx)) 949 lb_info = &lb_external10; 950 else if ((lb_mode == lb_phy10g.value) && 951 (nxgep->mac.portmode == PORT_10G_COPPER || 952 nxgep->mac.portmode == PORT_10G_TN1010 || 953 nxgep->mac.portmode == PORT_10G_FIBER)) 954 lb_info = &lb_phy10g; 955 else if ((lb_mode == lb_phy1000.value) && 956 (nxgep->mac.portmode == PORT_1G_COPPER || 957 nxgep->mac.portmode == PORT_1G_TN1010 || 958 nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) 959 lb_info = &lb_phy1000; 960 else if ((lb_mode == lb_phy.value) && 961 (nxgep->mac.portmode == PORT_1G_COPPER)) 962 lb_info = &lb_phy; 963 else if ((lb_mode == lb_serdes10g.value) && 964 (nxgep->mac.portmode == PORT_10G_FIBER || 965 nxgep->mac.portmode == PORT_10G_COPPER || 966 nxgep->mac.portmode == PORT_10G_TN1010 || 967 nxgep->mac.portmode == PORT_10G_SERDES)) 968 lb_info = &lb_serdes10g; 969 else if ((lb_mode == lb_serdes1000.value) && 970 (nxgep->mac.portmode == PORT_1G_FIBER || 971 nxgep->mac.portmode == PORT_1G_TN1010 || 972 nxgep->mac.portmode == PORT_1G_SERDES)) 973 lb_info = &lb_serdes1000; 974 else if (lb_mode == lb_mac10g.value) 975 lb_info = &lb_mac10g; 976 else if (lb_mode == lb_mac1000.value) 977 lb_info = &lb_mac1000; 978 else if (lb_mode == lb_mac.value) 979 lb_info = &lb_mac; 980 else { 981 cmn_err(CE_NOTE, 982 "!nxge%d: Loopback mode not supported(mode %d).\n", 983 nxgep->instance, lb_mode); 984 status = B_FALSE; 985 goto nxge_set_lb_exit; 986 } 987 988 if (lb_mode == nxge_lb_normal) { 989 if (nxge_lb_dbg) { 990 cmn_err(CE_NOTE, 991 "!nxge%d: Returning to normal operation", 992 nxgep->instance); 993 } 994 if (nxge_set_lb_normal(nxgep) != NXGE_OK) { 995 status = B_FALSE; 996 cmn_err(CE_NOTE, 997 "!nxge%d: Failed to return to normal operation", 998 nxgep->instance); 999 } 1000 goto nxge_set_lb_exit; 1001 } 1002 nxgep->statsp->port_stats.lb_mode = lb_mode; 1003 1004 if (nxge_lb_dbg) 1005 cmn_err(CE_NOTE, 1006 "!nxge%d: Adapter now in %s loopback mode", 1007 nxgep->instance, lb_info->key); 1008 nxgep->param_arr[param_autoneg].value = 0; 1009 nxgep->param_arr[param_anar_10gfdx].value = 1010 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1011 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1012 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1013 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 1014 nxgep->param_arr[param_anar_10ghdx].value = 0; 1015 nxgep->param_arr[param_anar_1000fdx].value = 1016 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1017 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 1018 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1019 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 1020 nxgep->param_arr[param_anar_1000hdx].value = 0; 1021 nxgep->param_arr[param_anar_100fdx].value = 1022 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 1023 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1024 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 1025 nxgep->param_arr[param_anar_100hdx].value = 0; 1026 nxgep->param_arr[param_anar_10fdx].value = 1027 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1028 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 1029 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 1030 nxgep->param_arr[param_master_cfg_enable].value = 1; 1031 nxgep->param_arr[param_master_cfg_value].value = 1; 1032 } 1033 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1034 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1035 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 1036 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 1037 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1038 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1039 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 1040 1041 if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK) 1042 goto nxge_set_lb_err; 1043 if (nxge_xcvr_find(nxgep) != NXGE_OK) 1044 goto nxge_set_lb_err; 1045 if (nxge_link_init(nxgep) != NXGE_OK) 1046 goto nxge_set_lb_err; 1047 if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK) 1048 goto nxge_set_lb_err; 1049 } 1050 if (lb_info->lb_type == internal) { 1051 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1052 (nxgep->statsp->port_stats.lb_mode == 1053 nxge_lb_phy10g) || 1054 (nxgep->statsp->port_stats.lb_mode == 1055 nxge_lb_serdes10g)) { 1056 nxgep->statsp->mac_stats.link_speed = 10000; 1057 } else if ((nxgep->statsp->port_stats.lb_mode 1058 == nxge_lb_mac1000) || 1059 (nxgep->statsp->port_stats.lb_mode == 1060 nxge_lb_phy1000) || 1061 (nxgep->statsp->port_stats.lb_mode == 1062 nxge_lb_serdes1000)) { 1063 nxgep->statsp->mac_stats.link_speed = 1000; 1064 } else { 1065 nxgep->statsp->mac_stats.link_speed = 100; 1066 } 1067 nxgep->statsp->mac_stats.link_duplex = 2; 1068 nxgep->statsp->mac_stats.link_up = 1; 1069 } 1070 if (nxge_global_reset(nxgep) != NXGE_OK) 1071 goto nxge_set_lb_err; 1072 1073 nxge_set_lb_exit: 1074 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1075 "<== nxge_set_lb status = 0x%08x", status)); 1076 return (status); 1077 nxge_set_lb_err: 1078 status = B_FALSE; 1079 cmn_err(CE_NOTE, 1080 "!nxge%d: Failed to put adapter in %s loopback mode", 1081 nxgep->instance, lb_info->key); 1082 return (status); 1083 } 1084 1085 /* Return to normal (no loopback) mode */ 1086 /* ARGSUSED */ 1087 nxge_status_t 1088 nxge_set_lb_normal(p_nxge_t nxgep) 1089 { 1090 nxge_status_t status = NXGE_OK; 1091 1092 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 1093 1094 nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 1095 nxgep->param_arr[param_autoneg].value = 1096 nxgep->param_arr[param_autoneg].old_value; 1097 nxgep->param_arr[param_anar_1000fdx].value = 1098 nxgep->param_arr[param_anar_1000fdx].old_value; 1099 nxgep->param_arr[param_anar_1000hdx].value = 1100 nxgep->param_arr[param_anar_1000hdx].old_value; 1101 nxgep->param_arr[param_anar_100fdx].value = 1102 nxgep->param_arr[param_anar_100fdx].old_value; 1103 nxgep->param_arr[param_anar_100hdx].value = 1104 nxgep->param_arr[param_anar_100hdx].old_value; 1105 nxgep->param_arr[param_anar_10fdx].value = 1106 nxgep->param_arr[param_anar_10fdx].old_value; 1107 nxgep->param_arr[param_master_cfg_enable].value = 1108 nxgep->param_arr[param_master_cfg_enable].old_value; 1109 nxgep->param_arr[param_master_cfg_value].value = 1110 nxgep->param_arr[param_master_cfg_value].old_value; 1111 1112 if ((status = nxge_global_reset(nxgep)) != NXGE_OK) 1113 return (status); 1114 1115 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 1116 return (status); 1117 if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK) 1118 return (status); 1119 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 1120 return (status); 1121 status = nxge_link_monitor(nxgep, LINK_MONITOR_START); 1122 1123 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 1124 1125 return (status); 1126 } 1127 1128 /* ARGSUSED */ 1129 void 1130 nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 1131 { 1132 uint16_t reg; 1133 1134 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 1135 1136 reg = *(uint16_t *)mp->b_rptr; 1137 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 1138 (uint16_t *)mp->b_rptr); 1139 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 1140 reg, *(uint16_t *)mp->b_rptr)); 1141 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 1142 } 1143 1144 /* ARGSUSED */ 1145 void 1146 nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 1147 { 1148 uint16_t *buf; 1149 uint8_t reg; 1150 1151 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 1152 buf = (uint16_t *)mp->b_rptr; 1153 reg = (uint8_t)buf[0]; 1154 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 1155 "reg = 0x%08X index = 0x%08X value = 0x%08X", 1156 reg, buf[0], buf[1])); 1157 (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 1158 reg, buf[1]); 1159 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 1160 } 1161 1162 /* ARGSUSED */ 1163 void 1164 nxge_check_hw_state(p_nxge_t nxgep) 1165 { 1166 p_nxge_ldgv_t ldgvp; 1167 p_nxge_ldv_t t_ldvp; 1168 1169 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 1170 1171 MUTEX_ENTER(nxgep->genlock); 1172 nxgep->nxge_timerid = 0; 1173 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1174 goto nxge_check_hw_state_exit; 1175 } 1176 nxge_check_tx_hang(nxgep); 1177 1178 ldgvp = nxgep->ldgvp; 1179 if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 1180 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1181 "NULL ldgvp (interrupt not ready).")); 1182 goto nxge_check_hw_state_exit; 1183 } 1184 t_ldvp = ldgvp->ldvp_syserr; 1185 if (!t_ldvp->use_timer) { 1186 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1187 "ldgvp $%p t_ldvp $%p use_timer flag %d", 1188 ldgvp, t_ldvp, t_ldvp->use_timer)); 1189 goto nxge_check_hw_state_exit; 1190 } 1191 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 1192 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1193 "port%d Bad register acc handle", nxgep->mac.portnum)); 1194 } 1195 (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 1196 1197 nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 1198 NXGE_CHECK_TIMER); 1199 1200 nxge_check_hw_state_exit: 1201 MUTEX_EXIT(nxgep->genlock); 1202 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 1203 } 1204 1205 /*ARGSUSED*/ 1206 static void 1207 nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1208 struct iocblk *iocp) 1209 { 1210 ssize_t size; 1211 rtrace_t *rtp; 1212 mblk_t *nmp; 1213 uint32_t i, j; 1214 uint32_t start_blk; 1215 uint32_t base_entry; 1216 uint32_t num_entries; 1217 1218 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 1219 1220 size = 1024; 1221 if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 1222 NXGE_DEBUG_MSG((nxgep, STR_CTL, 1223 "malformed M_IOCTL MBLKL = %d size = %d", 1224 MBLKL(mp->b_cont), size)); 1225 miocnak(wq, mp, 0, EINVAL); 1226 return; 1227 } 1228 nmp = mp->b_cont; 1229 rtp = (rtrace_t *)nmp->b_rptr; 1230 start_blk = rtp->next_idx; 1231 num_entries = rtp->last_idx; 1232 base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 1233 1234 NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 1235 NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 1236 NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 1237 1238 rtp->next_idx = npi_rtracebuf.next_idx; 1239 rtp->last_idx = npi_rtracebuf.last_idx; 1240 rtp->wrapped = npi_rtracebuf.wrapped; 1241 for (i = 0, j = base_entry; i < num_entries; i++, j++) { 1242 rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 1243 rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 1244 rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 1245 } 1246 1247 nmp->b_wptr = nmp->b_rptr + size; 1248 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 1249 miocack(wq, mp, (int)size, 0); 1250 } 1251