1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 30 /* 31 * Tunable Receive Completion Ring Configuration B parameters. 32 */ 33 uint16_t nxge_rx_pkt_thres; /* 16 bits */ 34 uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 35 36 lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 37 lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 38 lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 39 lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 40 lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 41 lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 42 lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 43 lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 44 lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 45 lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 46 lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 47 lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 48 lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 49 50 uint32_t nxge_lb_dbg = 1; 51 void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 52 void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 53 static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 54 55 extern uint32_t nxge_rx_mode; 56 extern uint32_t nxge_jumbo_mtu; 57 extern boolean_t nxge_jumbo_enable; 58 59 static void 60 nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 61 62 /* ARGSUSED */ 63 nxge_status_t 64 nxge_global_reset(p_nxge_t nxgep) 65 { 66 nxge_status_t status = NXGE_OK; 67 68 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 69 70 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 71 return (status); 72 (void) nxge_intr_hw_disable(nxgep); 73 74 if ((nxgep->suspended) || 75 ((nxgep->statsp->port_stats.lb_mode == 76 nxge_lb_phy1000) || 77 (nxgep->statsp->port_stats.lb_mode == 78 nxge_lb_phy10g) || 79 (nxgep->statsp->port_stats.lb_mode == 80 nxge_lb_serdes1000) || 81 (nxgep->statsp->port_stats.lb_mode == 82 nxge_lb_serdes10g))) { 83 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 84 return (status); 85 } 86 87 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK) 88 return (status); 89 if ((status = nxge_mac_init(nxgep)) != NXGE_OK) 90 return (status); 91 (void) nxge_intr_hw_enable(nxgep); 92 93 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 94 return (status); 95 } 96 97 /* ARGSUSED */ 98 void 99 nxge_hw_id_init(p_nxge_t nxgep) 100 { 101 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 102 /* 103 * Set up initial hardware parameters required such as mac mtu size. 104 */ 105 nxgep->mac.is_jumbo = B_FALSE; 106 /* 107 * Set the maxframe size to 1522 (1518 + 4) to account for 108 * VLAN tagged packets. 109 */ 110 nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64 */ 111 nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */ 112 if (nxgep->param_arr[param_accept_jumbo].value || nxge_jumbo_enable) { 113 nxgep->mac.maxframesize = (uint16_t)nxge_jumbo_mtu; 114 nxgep->mac.is_jumbo = B_TRUE; 115 } 116 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 117 "==> nxge_hw_id_init: maxframesize %d", 118 nxgep->mac.maxframesize)); 119 120 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 121 } 122 123 /* ARGSUSED */ 124 void 125 nxge_hw_init_niu_common(p_nxge_t nxgep) 126 { 127 p_nxge_hw_list_t hw_p; 128 129 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 130 131 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 132 return; 133 } 134 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 135 if (hw_p->flags & COMMON_INIT_DONE) { 136 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 137 "nxge_hw_init_niu_common" 138 " already done for dip $%p function %d exiting", 139 hw_p->parent_devp, nxgep->function_num)); 140 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 141 return; 142 } 143 144 hw_p->flags = COMMON_INIT_START; 145 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 146 " Started for device id %x with function %d", 147 hw_p->parent_devp, nxgep->function_num)); 148 149 /* per neptune common block init */ 150 (void) nxge_fflp_hw_reset(nxgep); 151 152 hw_p->flags = COMMON_INIT_DONE; 153 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 154 155 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 156 " Done for device id %x with function %d", 157 hw_p->parent_devp, nxgep->function_num)); 158 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 159 } 160 161 /* ARGSUSED */ 162 uint_t 163 nxge_intr(void *arg1, void *arg2) 164 { 165 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 166 p_nxge_t nxgep = (p_nxge_t)arg2; 167 uint_t serviced = DDI_INTR_UNCLAIMED; 168 uint8_t ldv; 169 npi_handle_t handle; 170 p_nxge_ldgv_t ldgvp; 171 p_nxge_ldg_t ldgp, t_ldgp; 172 p_nxge_ldv_t t_ldvp; 173 uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 174 int i, j, nldvs, nintrs = 1; 175 npi_status_t rs = NPI_SUCCESS; 176 177 /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 178 if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 179 nxgep = ldvp->nxgep; 180 } 181 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 182 183 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 184 NXGE_ERROR_MSG((nxgep, INT_CTL, 185 "<== nxge_intr: not initialized 0x%x", serviced)); 186 return (serviced); 187 } 188 189 ldgvp = nxgep->ldgvp; 190 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 191 if (ldvp == NULL && ldgvp) { 192 t_ldvp = ldvp = ldgvp->ldvp; 193 } 194 if (ldvp) { 195 ldgp = t_ldgp = ldvp->ldgp; 196 } 197 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 198 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 199 if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 200 NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 201 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 202 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 203 return (DDI_INTR_UNCLAIMED); 204 } 205 /* 206 * This interrupt handler will have to go through all the logical 207 * devices to find out which logical device interrupts us and then call 208 * its handler to process the events. 209 */ 210 handle = NXGE_DEV_NPI_HANDLE(nxgep); 211 t_ldgp = ldgp; 212 t_ldvp = ldgp->ldvp; 213 214 nldvs = ldgp->nldvs; 215 216 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 217 nldvs, ldgvp->ldg_intrs)); 218 219 serviced = DDI_INTR_CLAIMED; 220 for (i = 0; i < nintrs; i++, t_ldgp++) { 221 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 222 " #intrs %d", i, nldvs, nintrs)); 223 /* Get this group's flag bits. */ 224 t_ldgp->interrupted = B_FALSE; 225 rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 226 &vector0, &vector1, &vector2); 227 if (rs) { 228 continue; 229 } 230 if (!vector0 && !vector1 && !vector2) { 231 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 232 "no interrupts on group %d", t_ldgp->ldg)); 233 continue; 234 } 235 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 236 "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 237 vector0, vector1, vector2)); 238 t_ldgp->interrupted = B_TRUE; 239 nldvs = t_ldgp->nldvs; 240 for (j = 0; j < nldvs; j++, t_ldvp++) { 241 /* 242 * Call device's handler if flag bits are on. 243 */ 244 ldv = t_ldvp->ldv; 245 if (((ldv < NXGE_MAC_LD_START) && 246 (LDV_ON(ldv, vector0) | 247 (LDV_ON(ldv, vector1)))) || 248 (ldv >= NXGE_MAC_LD_START && 249 ((LDV2_ON_1(ldv, vector2)) || 250 (LDV2_ON_2(ldv, vector2))))) { 251 (void) (t_ldvp->ldv_intr_handler)( 252 (caddr_t)t_ldvp, arg2); 253 NXGE_DEBUG_MSG((nxgep, INT_CTL, 254 "==> nxge_intr: " 255 "calling device %d #ldvs %d #intrs %d", 256 j, nldvs, nintrs)); 257 } 258 } 259 } 260 261 t_ldgp = ldgp; 262 for (i = 0; i < nintrs; i++, t_ldgp++) { 263 /* rearm group interrupts */ 264 if (t_ldgp->interrupted) { 265 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 266 "group %d", t_ldgp->ldg)); 267 (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 268 t_ldgp->arm, t_ldgp->ldg_timer); 269 } 270 } 271 272 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 273 serviced)); 274 return (serviced); 275 } 276 277 278 /* 279 * XFP Related Status Register Values Under 3 Different Conditions 280 * 281 * -------------+-------------------------+------------------------- 282 * | Intel XFP and Avago | Picolight XFP 283 * -------------+---------+---------------+---------+--------------- 284 * | STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT 285 * -------------+---------+---------------+---------+--------------- 286 * No XFP | 0x639C | 0x40 | 0x639C | 0x40 287 * -------------+---------+---------------+---------+--------------- 288 * XFP,linkdown | 0x43BC | 0x40 | 0x639C | 0x40 289 * -------------+---------+---------------+---------+--------------- 290 * XFP,linkup | 0x03FC | 0x0 | 0x03FC | 0x0 291 * -------------+---------+---------------+---------+--------------- 292 * Note: 293 * STATUS0 = BCM8704_USER_ANALOG_STATUS0_REG 294 * TX_ALARM_STAT = BCM8704_USER_TX_ALARM_STATUS_REG 295 */ 296 /* ARGSUSED */ 297 static nxge_status_t 298 nxge_check_xaui_xfp(p_nxge_t nxgep) 299 { 300 nxge_status_t status = NXGE_OK; 301 uint8_t phy_port_addr; 302 uint16_t val; 303 uint16_t val1; 304 uint8_t portn; 305 306 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 307 308 portn = nxgep->mac.portnum; 309 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 310 311 /* 312 * Keep the val1 code even though it is not used. Could be 313 * used to differenciate the "No XFP" case and "XFP,linkdown" 314 * case when a Intel XFP is used. 315 */ 316 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 317 BCM8704_USER_DEV3_ADDR, 318 BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 319 status = nxge_mdio_read(nxgep, phy_port_addr, 320 BCM8704_USER_DEV3_ADDR, 321 BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 322 } 323 324 if (status != NXGE_OK) { 325 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 326 NXGE_FM_EREPORT_XAUI_ERR); 327 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 328 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 329 "XAUI is bad or absent on port<%d>\n", portn)); 330 } 331 #ifdef NXGE_DEBUG 332 /* 333 * As a workaround for CR6693529, do not execute this block of 334 * code for non-debug driver. When a Picolight XFP transceiver 335 * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns 336 * the same 0x639C value in normal link down case, which causes 337 * false FMA messages and link reconnection problem. 338 */ 339 } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 340 /* 341 * 0x03FC = 0000 0011 1111 1100 (XFP is normal) 342 * 0x639C = 0110 0011 1001 1100 (XFP has problem) 343 * bit14 = 1: PDM loss-of-light indicator 344 * bit13 = 1: PDM Rx loss-of-signal 345 * bit6 = 0: Light is NOT ok 346 * bit5 = 0: PMD Rx signal is NOT ok 347 */ 348 if (val == 0x639C) { 349 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 350 NXGE_FM_EREPORT_XFP_ERR); 351 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 352 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 353 "XFP is bad or absent on port<%d>\n", 354 portn)); 355 } 356 status = NXGE_ERROR; 357 } 358 #endif 359 } 360 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 361 return (status); 362 } 363 364 365 /* ARGSUSED */ 366 uint_t 367 nxge_syserr_intr(void *arg1, void *arg2) 368 { 369 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 370 p_nxge_t nxgep = (p_nxge_t)arg2; 371 p_nxge_ldg_t ldgp = NULL; 372 npi_handle_t handle; 373 sys_err_stat_t estat; 374 uint_t serviced = DDI_INTR_UNCLAIMED; 375 376 if (arg1 == NULL && arg2 == NULL) { 377 return (serviced); 378 } 379 if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 380 if (ldvp != NULL) { 381 nxgep = ldvp->nxgep; 382 } 383 } 384 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 385 "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 386 if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 387 ldgp = ldvp->ldgp; 388 if (ldgp == NULL) { 389 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 390 "<== nxge_syserrintr(no logical group): " 391 "arg2 $%p arg1 $%p", nxgep, ldvp)); 392 return (DDI_INTR_UNCLAIMED); 393 } 394 /* 395 * Get the logical device state if the function uses interrupt. 396 */ 397 } 398 399 /* This interrupt handler is for system error interrupts. */ 400 handle = NXGE_DEV_NPI_HANDLE(nxgep); 401 estat.value = 0; 402 (void) npi_fzc_sys_err_stat_get(handle, &estat); 403 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 404 "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 405 406 if (estat.bits.ldw.smx) { 407 /* SMX */ 408 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 409 "==> nxge_syserr_intr: device error - SMX")); 410 } else if (estat.bits.ldw.mac) { 411 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 412 "==> nxge_syserr_intr: device error - MAC")); 413 /* 414 * There is nothing to be done here. All MAC errors go to per 415 * MAC port interrupt. MIF interrupt is the only MAC sub-block 416 * that can generate status here. MIF status reported will be 417 * ignored here. It is checked by per port timer instead. 418 */ 419 } else if (estat.bits.ldw.ipp) { 420 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 421 "==> nxge_syserr_intr: device error - IPP")); 422 (void) nxge_ipp_handle_sys_errors(nxgep); 423 } else if (estat.bits.ldw.zcp) { 424 /* ZCP */ 425 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 426 "==> nxge_syserr_intr: device error - ZCP")); 427 (void) nxge_zcp_handle_sys_errors(nxgep); 428 } else if (estat.bits.ldw.tdmc) { 429 /* TDMC */ 430 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 431 "==> nxge_syserr_intr: device error - TDMC")); 432 /* 433 * There is no TDMC system errors defined in the PRM. All TDMC 434 * channel specific errors are reported on a per channel basis. 435 */ 436 } else if (estat.bits.ldw.rdmc) { 437 /* RDMC */ 438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 439 "==> nxge_syserr_intr: device error - RDMC")); 440 (void) nxge_rxdma_handle_sys_errors(nxgep); 441 } else if (estat.bits.ldw.txc) { 442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 443 "==> nxge_syserr_intr: device error - TXC")); 444 (void) nxge_txc_handle_sys_errors(nxgep); 445 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 446 /* PCI-E */ 447 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 448 "==> nxge_syserr_intr: device error - PCI-E")); 449 } else if (estat.bits.ldw.meta1) { 450 /* META1 */ 451 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 452 "==> nxge_syserr_intr: device error - META1")); 453 } else if (estat.bits.ldw.meta2) { 454 /* META2 */ 455 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 456 "==> nxge_syserr_intr: device error - META2")); 457 } else if (estat.bits.ldw.fflp) { 458 /* FFLP */ 459 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 460 "==> nxge_syserr_intr: device error - FFLP")); 461 (void) nxge_fflp_handle_sys_errors(nxgep); 462 } 463 464 /* 465 * nxge_check_xaui_xfg checks XAUI for all of the following 466 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER. 467 */ 468 if (nxgep->mac.portmode == PORT_10G_FIBER || 469 nxgep->mac.portmode == PORT_10G_COPPER || 470 nxgep->mac.portmode == PORT_10G_TN1010 || 471 nxgep->mac.portmode == PORT_1G_TN1010) { 472 if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 473 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 474 "==> nxge_syserr_intr: device error - XAUI")); 475 } 476 } 477 478 serviced = DDI_INTR_CLAIMED; 479 480 if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 481 !ldvp->use_timer) { 482 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 483 B_TRUE, ldgp->ldg_timer); 484 } 485 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 486 return (serviced); 487 } 488 489 /* ARGSUSED */ 490 void 491 nxge_intr_hw_enable(p_nxge_t nxgep) 492 { 493 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 494 (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 495 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 496 } 497 498 /* ARGSUSED */ 499 void 500 nxge_intr_hw_disable(p_nxge_t nxgep) 501 { 502 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 503 (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 504 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 505 } 506 507 /* ARGSUSED */ 508 void 509 nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 510 { 511 p_nxge_t nxgep = (p_nxge_t)arg; 512 uint8_t channel; 513 npi_handle_t handle; 514 p_nxge_ldgv_t ldgvp; 515 p_nxge_ldv_t ldvp; 516 int i; 517 518 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 519 handle = NXGE_DEV_NPI_HANDLE(nxgep); 520 521 if ((ldgvp = nxgep->ldgvp) == NULL) { 522 NXGE_ERROR_MSG((nxgep, INT_CTL, 523 "<== nxge_rx_hw_blank (not enabled)")); 524 return; 525 } 526 ldvp = nxgep->ldgvp->ldvp; 527 if (ldvp == NULL) { 528 return; 529 } 530 for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 531 if (ldvp->is_rxdma) { 532 channel = ldvp->channel; 533 (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 534 channel, count); 535 (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 536 channel, ticks); 537 } 538 } 539 540 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 541 } 542 543 /* ARGSUSED */ 544 void 545 nxge_hw_stop(p_nxge_t nxgep) 546 { 547 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 548 549 (void) nxge_tx_mac_disable(nxgep); 550 (void) nxge_rx_mac_disable(nxgep); 551 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 552 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 553 554 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 555 } 556 557 /* ARGSUSED */ 558 void 559 nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 560 { 561 int cmd; 562 563 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 564 565 if (nxgep == NULL) { 566 miocnak(wq, mp, 0, EINVAL); 567 return; 568 } 569 iocp->ioc_error = 0; 570 cmd = iocp->ioc_cmd; 571 572 switch (cmd) { 573 default: 574 miocnak(wq, mp, 0, EINVAL); 575 return; 576 577 case NXGE_GET_MII: 578 nxge_get_mii(nxgep, mp->b_cont); 579 miocack(wq, mp, sizeof (uint16_t), 0); 580 break; 581 582 case NXGE_PUT_MII: 583 nxge_put_mii(nxgep, mp->b_cont); 584 miocack(wq, mp, 0, 0); 585 break; 586 587 case NXGE_GET64: 588 nxge_get64(nxgep, mp->b_cont); 589 miocack(wq, mp, sizeof (uint32_t), 0); 590 break; 591 592 case NXGE_PUT64: 593 nxge_put64(nxgep, mp->b_cont); 594 miocack(wq, mp, 0, 0); 595 break; 596 597 case NXGE_PUT_TCAM: 598 nxge_put_tcam(nxgep, mp->b_cont); 599 miocack(wq, mp, 0, 0); 600 break; 601 602 case NXGE_GET_TCAM: 603 nxge_get_tcam(nxgep, mp->b_cont); 604 miocack(wq, mp, 0, 0); 605 break; 606 607 case NXGE_TX_REGS_DUMP: 608 nxge_txdma_regs_dump_channels(nxgep); 609 miocack(wq, mp, 0, 0); 610 break; 611 case NXGE_RX_REGS_DUMP: 612 nxge_rxdma_regs_dump_channels(nxgep); 613 miocack(wq, mp, 0, 0); 614 break; 615 case NXGE_VIR_INT_REGS_DUMP: 616 case NXGE_INT_REGS_DUMP: 617 nxge_virint_regs_dump(nxgep); 618 miocack(wq, mp, 0, 0); 619 break; 620 case NXGE_RTRACE: 621 nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 622 break; 623 } 624 } 625 626 /* ARGSUSED */ 627 void 628 nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 629 struct iocblk *iocp) 630 { 631 p_lb_property_t lb_props; 632 633 size_t size; 634 int i; 635 636 if (mp->b_cont == NULL) { 637 miocnak(wq, mp, 0, EINVAL); 638 } 639 switch (iocp->ioc_cmd) { 640 case LB_GET_MODE: 641 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 642 if (nxgep != NULL) { 643 *(lb_info_sz_t *)mp->b_cont->b_rptr = 644 nxgep->statsp->port_stats.lb_mode; 645 miocack(wq, mp, sizeof (nxge_lb_t), 0); 646 } else { 647 miocnak(wq, mp, 0, EINVAL); 648 } 649 break; 650 case LB_SET_MODE: 651 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 652 if (iocp->ioc_count != sizeof (uint32_t)) { 653 miocack(wq, mp, 0, 0); 654 break; 655 } 656 if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 657 miocack(wq, mp, 0, 0); 658 } else { 659 miocnak(wq, mp, 0, EPROTO); 660 } 661 break; 662 case LB_GET_INFO_SIZE: 663 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 664 if (nxgep != NULL) { 665 size = sizeof (lb_normal); 666 if (nxgep->statsp->mac_stats.cap_10gfdx) { 667 /* TN1010 does not support external loopback */ 668 if (nxgep->mac.portmode != PORT_1G_TN1010 && 669 nxgep->mac.portmode != PORT_10G_TN1010) { 670 size += sizeof (lb_external10g); 671 } 672 size += sizeof (lb_mac10g); 673 /* Publish PHY loopback if PHY is present */ 674 if (nxgep->mac.portmode == PORT_10G_COPPER || 675 nxgep->mac.portmode == PORT_10G_TN1010 || 676 nxgep->mac.portmode == PORT_10G_FIBER) 677 size += sizeof (lb_phy10g); 678 } 679 680 /* 681 * Even if cap_10gfdx is false, we still do 10G 682 * serdes loopback as a part of SunVTS xnetlbtest 683 * internal loopback test. 684 */ 685 if (nxgep->mac.portmode == PORT_10G_FIBER || 686 nxgep->mac.portmode == PORT_10G_TN1010 || 687 nxgep->mac.portmode == PORT_10G_SERDES) 688 size += sizeof (lb_serdes10g); 689 690 if (nxgep->statsp->mac_stats.cap_1000fdx) { 691 /* TN1010 does not support external loopback */ 692 if (nxgep->mac.portmode != PORT_1G_TN1010 && 693 nxgep->mac.portmode != PORT_10G_TN1010) { 694 size += sizeof (lb_external1000); 695 } 696 size += sizeof (lb_mac1000); 697 if (nxgep->mac.portmode == PORT_1G_COPPER || 698 nxgep->mac.portmode == PORT_1G_TN1010 || 699 nxgep->mac.portmode == 700 PORT_1G_RGMII_FIBER) 701 size += sizeof (lb_phy1000); 702 } 703 if (nxgep->statsp->mac_stats.cap_100fdx) 704 size += sizeof (lb_external100); 705 if (nxgep->statsp->mac_stats.cap_10fdx) 706 size += sizeof (lb_external10); 707 if (nxgep->mac.portmode == PORT_1G_FIBER || 708 nxgep->mac.portmode == PORT_1G_TN1010 || 709 nxgep->mac.portmode == PORT_1G_SERDES) 710 size += sizeof (lb_serdes1000); 711 712 *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 713 714 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 715 "NXGE_GET_LB_INFO command: size %d", size)); 716 miocack(wq, mp, sizeof (lb_info_sz_t), 0); 717 } else 718 miocnak(wq, mp, 0, EINVAL); 719 break; 720 721 case LB_GET_INFO: 722 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 723 if (nxgep != NULL) { 724 size = sizeof (lb_normal); 725 if (nxgep->statsp->mac_stats.cap_10gfdx) { 726 /* TN1010 does not support external loopback */ 727 if (nxgep->mac.portmode != PORT_1G_TN1010 && 728 nxgep->mac.portmode != PORT_10G_TN1010) { 729 size += sizeof (lb_external10g); 730 } 731 size += sizeof (lb_mac10g); 732 /* Publish PHY loopback if PHY is present */ 733 if (nxgep->mac.portmode == PORT_10G_COPPER || 734 nxgep->mac.portmode == PORT_10G_TN1010 || 735 nxgep->mac.portmode == PORT_10G_FIBER) 736 size += sizeof (lb_phy10g); 737 } 738 if (nxgep->mac.portmode == PORT_10G_FIBER || 739 nxgep->mac.portmode == PORT_10G_TN1010 || 740 nxgep->mac.portmode == PORT_10G_SERDES) 741 size += sizeof (lb_serdes10g); 742 743 if (nxgep->statsp->mac_stats.cap_1000fdx) { 744 /* TN1010 does not support external loopback */ 745 if (nxgep->mac.portmode != PORT_1G_TN1010 && 746 nxgep->mac.portmode != PORT_10G_TN1010) { 747 size += sizeof (lb_external1000); 748 } 749 size += sizeof (lb_mac1000); 750 if (nxgep->mac.portmode == PORT_1G_COPPER || 751 nxgep->mac.portmode == PORT_1G_TN1010 || 752 nxgep->mac.portmode == 753 PORT_1G_RGMII_FIBER) 754 size += sizeof (lb_phy1000); 755 } 756 if (nxgep->statsp->mac_stats.cap_100fdx) 757 size += sizeof (lb_external100); 758 759 if (nxgep->statsp->mac_stats.cap_10fdx) 760 size += sizeof (lb_external10); 761 762 if (nxgep->mac.portmode == PORT_1G_FIBER || 763 nxgep->mac.portmode == PORT_1G_TN1010 || 764 nxgep->mac.portmode == PORT_1G_SERDES) 765 size += sizeof (lb_serdes1000); 766 767 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 768 "NXGE_GET_LB_INFO command: size %d", size)); 769 if (size == iocp->ioc_count) { 770 i = 0; 771 lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 772 lb_props[i++] = lb_normal; 773 774 if (nxgep->statsp->mac_stats.cap_10gfdx) { 775 lb_props[i++] = lb_mac10g; 776 if (nxgep->mac.portmode == 777 PORT_10G_COPPER || 778 nxgep->mac.portmode == 779 PORT_10G_TN1010 || 780 nxgep->mac.portmode == 781 PORT_10G_FIBER) { 782 lb_props[i++] = lb_phy10g; 783 } 784 /* TN1010 does not support ext lb */ 785 if (nxgep->mac.portmode != 786 PORT_10G_TN1010 && 787 nxgep->mac.portmode != 788 PORT_1G_TN1010) { 789 lb_props[i++] = lb_external10g; 790 } 791 } 792 793 if (nxgep->mac.portmode == PORT_10G_FIBER || 794 nxgep->mac.portmode == PORT_10G_TN1010 || 795 nxgep->mac.portmode == PORT_10G_SERDES) 796 lb_props[i++] = lb_serdes10g; 797 798 if (nxgep->statsp->mac_stats.cap_1000fdx) { 799 /* TN1010 does not support ext lb */ 800 if (nxgep->mac.portmode != 801 PORT_10G_TN1010 && 802 nxgep->mac.portmode != 803 PORT_1G_TN1010) { 804 lb_props[i++] = lb_external1000; 805 } 806 } 807 808 if (nxgep->statsp->mac_stats.cap_100fdx) 809 lb_props[i++] = lb_external100; 810 811 if (nxgep->statsp->mac_stats.cap_10fdx) 812 lb_props[i++] = lb_external10; 813 814 if (nxgep->statsp->mac_stats.cap_1000fdx) 815 lb_props[i++] = lb_mac1000; 816 817 if (nxgep->mac.portmode == PORT_1G_COPPER || 818 nxgep->mac.portmode == PORT_1G_TN1010 || 819 nxgep->mac.portmode == 820 PORT_1G_RGMII_FIBER) { 821 if (nxgep->statsp->mac_stats. 822 cap_1000fdx) 823 lb_props[i++] = lb_phy1000; 824 } else if (nxgep->mac.portmode == 825 PORT_1G_FIBER || 826 nxgep->mac.portmode == PORT_1G_TN1010 || 827 nxgep->mac.portmode == PORT_1G_SERDES) { 828 lb_props[i++] = lb_serdes1000; 829 } 830 miocack(wq, mp, size, 0); 831 } else 832 miocnak(wq, mp, 0, EINVAL); 833 } else { 834 miocnak(wq, mp, 0, EINVAL); 835 cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 836 iocp->ioc_cmd); 837 } 838 break; 839 } 840 } 841 842 /* 843 * DMA channel interfaces to access various channel specific 844 * hardware functions. 845 */ 846 /* ARGSUSED */ 847 void 848 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 849 uint32_t reg_base, uint16_t channel, uint64_t reg_data) 850 { 851 uint64_t reg_offset; 852 853 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 854 855 /* 856 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 857 * use the virtual DMA CSR address space from the config space (in PCI 858 * case), then the following code need to be use different offset 859 * computation macro. 860 */ 861 reg_offset = reg_base + DMC_OFFSET(channel); 862 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 863 864 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 865 } 866 867 /* ARGSUSED */ 868 uint64_t 869 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 870 uint32_t reg_base, uint16_t channel) 871 { 872 uint64_t reg_offset; 873 874 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 875 876 /* 877 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 878 * use the virtual DMA CSR address space from the config space (in PCI 879 * case), then the following code need to be use different offset 880 * computation macro. 881 */ 882 reg_offset = reg_base + DMC_OFFSET(channel); 883 884 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 885 886 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 887 } 888 889 /* ARGSUSED */ 890 void 891 nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 892 { 893 nxge_os_acc_handle_t nxge_regh; 894 895 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 896 nxge_regh = nxgep->dev_regs->nxge_regh; 897 898 *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 899 nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 900 901 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 902 *(uint32_t *)mp->b_rptr)); 903 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 904 } 905 906 /* ARGSUSED */ 907 void 908 nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 909 { 910 nxge_os_acc_handle_t nxge_regh; 911 uint32_t *buf; 912 uint8_t *reg; 913 914 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 915 nxge_regh = nxgep->dev_regs->nxge_regh; 916 917 buf = (uint32_t *)mp->b_rptr; 918 reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 919 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 920 "reg = 0x%016llX index = 0x%08X value = 0x%08X", 921 reg, buf[0], buf[1])); 922 NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 923 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 924 } 925 926 /*ARGSUSED*/ 927 boolean_t 928 nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 929 { 930 boolean_t status = B_TRUE; 931 uint32_t lb_mode; 932 lb_property_t *lb_info; 933 934 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 935 lb_mode = nxgep->statsp->port_stats.lb_mode; 936 if (lb_mode == *(uint32_t *)mp->b_rptr) { 937 cmn_err(CE_NOTE, 938 "!nxge%d: Loopback mode already set (lb_mode %d).\n", 939 nxgep->instance, lb_mode); 940 status = B_FALSE; 941 goto nxge_set_lb_exit; 942 } 943 lb_mode = *(uint32_t *)mp->b_rptr; 944 lb_info = NULL; 945 if (lb_mode == lb_normal.value) 946 lb_info = &lb_normal; 947 else if ((lb_mode == lb_external10g.value) && 948 (nxgep->statsp->mac_stats.cap_10gfdx)) 949 lb_info = &lb_external10g; 950 else if ((lb_mode == lb_external1000.value) && 951 (nxgep->statsp->mac_stats.cap_1000fdx)) 952 lb_info = &lb_external1000; 953 else if ((lb_mode == lb_external100.value) && 954 (nxgep->statsp->mac_stats.cap_100fdx)) 955 lb_info = &lb_external100; 956 else if ((lb_mode == lb_external10.value) && 957 (nxgep->statsp->mac_stats.cap_10fdx)) 958 lb_info = &lb_external10; 959 else if ((lb_mode == lb_phy10g.value) && 960 (nxgep->mac.portmode == PORT_10G_COPPER || 961 nxgep->mac.portmode == PORT_10G_TN1010 || 962 nxgep->mac.portmode == PORT_10G_FIBER)) 963 lb_info = &lb_phy10g; 964 else if ((lb_mode == lb_phy1000.value) && 965 (nxgep->mac.portmode == PORT_1G_COPPER || 966 nxgep->mac.portmode == PORT_1G_TN1010 || 967 nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) 968 lb_info = &lb_phy1000; 969 else if ((lb_mode == lb_phy.value) && 970 (nxgep->mac.portmode == PORT_1G_COPPER)) 971 lb_info = &lb_phy; 972 else if ((lb_mode == lb_serdes10g.value) && 973 (nxgep->mac.portmode == PORT_10G_FIBER || 974 nxgep->mac.portmode == PORT_10G_COPPER || 975 nxgep->mac.portmode == PORT_10G_TN1010 || 976 nxgep->mac.portmode == PORT_10G_SERDES)) 977 lb_info = &lb_serdes10g; 978 else if ((lb_mode == lb_serdes1000.value) && 979 (nxgep->mac.portmode == PORT_1G_FIBER || 980 nxgep->mac.portmode == PORT_1G_TN1010 || 981 nxgep->mac.portmode == PORT_1G_SERDES)) 982 lb_info = &lb_serdes1000; 983 else if (lb_mode == lb_mac10g.value) 984 lb_info = &lb_mac10g; 985 else if (lb_mode == lb_mac1000.value) 986 lb_info = &lb_mac1000; 987 else if (lb_mode == lb_mac.value) 988 lb_info = &lb_mac; 989 else { 990 cmn_err(CE_NOTE, 991 "!nxge%d: Loopback mode not supported(mode %d).\n", 992 nxgep->instance, lb_mode); 993 status = B_FALSE; 994 goto nxge_set_lb_exit; 995 } 996 997 if (lb_mode == nxge_lb_normal) { 998 if (nxge_lb_dbg) { 999 cmn_err(CE_NOTE, 1000 "!nxge%d: Returning to normal operation", 1001 nxgep->instance); 1002 } 1003 if (nxge_set_lb_normal(nxgep) != NXGE_OK) { 1004 status = B_FALSE; 1005 cmn_err(CE_NOTE, 1006 "!nxge%d: Failed to return to normal operation", 1007 nxgep->instance); 1008 } 1009 goto nxge_set_lb_exit; 1010 } 1011 nxgep->statsp->port_stats.lb_mode = lb_mode; 1012 1013 if (nxge_lb_dbg) 1014 cmn_err(CE_NOTE, 1015 "!nxge%d: Adapter now in %s loopback mode", 1016 nxgep->instance, lb_info->key); 1017 nxgep->param_arr[param_autoneg].value = 0; 1018 nxgep->param_arr[param_anar_10gfdx].value = 1019 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1020 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1021 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1022 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 1023 nxgep->param_arr[param_anar_10ghdx].value = 0; 1024 nxgep->param_arr[param_anar_1000fdx].value = 1025 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1026 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 1027 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1028 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 1029 nxgep->param_arr[param_anar_1000hdx].value = 0; 1030 nxgep->param_arr[param_anar_100fdx].value = 1031 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 1032 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1033 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 1034 nxgep->param_arr[param_anar_100hdx].value = 0; 1035 nxgep->param_arr[param_anar_10fdx].value = 1036 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1037 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 1038 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 1039 nxgep->param_arr[param_master_cfg_enable].value = 1; 1040 nxgep->param_arr[param_master_cfg_value].value = 1; 1041 } 1042 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1043 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1044 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 1045 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 1046 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1047 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1048 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 1049 1050 if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK) 1051 goto nxge_set_lb_err; 1052 if (nxge_xcvr_find(nxgep) != NXGE_OK) 1053 goto nxge_set_lb_err; 1054 if (nxge_link_init(nxgep) != NXGE_OK) 1055 goto nxge_set_lb_err; 1056 if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK) 1057 goto nxge_set_lb_err; 1058 } 1059 if (lb_info->lb_type == internal) { 1060 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1061 (nxgep->statsp->port_stats.lb_mode == 1062 nxge_lb_phy10g) || 1063 (nxgep->statsp->port_stats.lb_mode == 1064 nxge_lb_serdes10g)) { 1065 nxgep->statsp->mac_stats.link_speed = 10000; 1066 } else if ((nxgep->statsp->port_stats.lb_mode 1067 == nxge_lb_mac1000) || 1068 (nxgep->statsp->port_stats.lb_mode == 1069 nxge_lb_phy1000) || 1070 (nxgep->statsp->port_stats.lb_mode == 1071 nxge_lb_serdes1000)) { 1072 nxgep->statsp->mac_stats.link_speed = 1000; 1073 } else { 1074 nxgep->statsp->mac_stats.link_speed = 100; 1075 } 1076 nxgep->statsp->mac_stats.link_duplex = 2; 1077 nxgep->statsp->mac_stats.link_up = 1; 1078 } 1079 if (nxge_global_reset(nxgep) != NXGE_OK) 1080 goto nxge_set_lb_err; 1081 1082 nxge_set_lb_exit: 1083 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1084 "<== nxge_set_lb status = 0x%08x", status)); 1085 return (status); 1086 nxge_set_lb_err: 1087 status = B_FALSE; 1088 cmn_err(CE_NOTE, 1089 "!nxge%d: Failed to put adapter in %s loopback mode", 1090 nxgep->instance, lb_info->key); 1091 return (status); 1092 } 1093 1094 /* Return to normal (no loopback) mode */ 1095 /* ARGSUSED */ 1096 nxge_status_t 1097 nxge_set_lb_normal(p_nxge_t nxgep) 1098 { 1099 nxge_status_t status = NXGE_OK; 1100 1101 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 1102 1103 nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 1104 nxgep->param_arr[param_autoneg].value = 1105 nxgep->param_arr[param_autoneg].old_value; 1106 nxgep->param_arr[param_anar_1000fdx].value = 1107 nxgep->param_arr[param_anar_1000fdx].old_value; 1108 nxgep->param_arr[param_anar_1000hdx].value = 1109 nxgep->param_arr[param_anar_1000hdx].old_value; 1110 nxgep->param_arr[param_anar_100fdx].value = 1111 nxgep->param_arr[param_anar_100fdx].old_value; 1112 nxgep->param_arr[param_anar_100hdx].value = 1113 nxgep->param_arr[param_anar_100hdx].old_value; 1114 nxgep->param_arr[param_anar_10fdx].value = 1115 nxgep->param_arr[param_anar_10fdx].old_value; 1116 nxgep->param_arr[param_master_cfg_enable].value = 1117 nxgep->param_arr[param_master_cfg_enable].old_value; 1118 nxgep->param_arr[param_master_cfg_value].value = 1119 nxgep->param_arr[param_master_cfg_value].old_value; 1120 1121 if ((status = nxge_global_reset(nxgep)) != NXGE_OK) 1122 return (status); 1123 1124 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 1125 return (status); 1126 if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK) 1127 return (status); 1128 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 1129 return (status); 1130 status = nxge_link_monitor(nxgep, LINK_MONITOR_START); 1131 1132 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 1133 1134 return (status); 1135 } 1136 1137 /* ARGSUSED */ 1138 void 1139 nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 1140 { 1141 uint16_t reg; 1142 1143 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 1144 1145 reg = *(uint16_t *)mp->b_rptr; 1146 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 1147 (uint16_t *)mp->b_rptr); 1148 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 1149 reg, *(uint16_t *)mp->b_rptr)); 1150 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 1151 } 1152 1153 /* ARGSUSED */ 1154 void 1155 nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 1156 { 1157 uint16_t *buf; 1158 uint8_t reg; 1159 1160 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 1161 buf = (uint16_t *)mp->b_rptr; 1162 reg = (uint8_t)buf[0]; 1163 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 1164 "reg = 0x%08X index = 0x%08X value = 0x%08X", 1165 reg, buf[0], buf[1])); 1166 (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 1167 reg, buf[1]); 1168 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 1169 } 1170 1171 /* ARGSUSED */ 1172 void 1173 nxge_check_hw_state(p_nxge_t nxgep) 1174 { 1175 p_nxge_ldgv_t ldgvp; 1176 p_nxge_ldv_t t_ldvp; 1177 1178 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 1179 1180 MUTEX_ENTER(nxgep->genlock); 1181 nxgep->nxge_timerid = 0; 1182 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1183 goto nxge_check_hw_state_exit; 1184 } 1185 nxge_check_tx_hang(nxgep); 1186 1187 ldgvp = nxgep->ldgvp; 1188 if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 1189 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1190 "NULL ldgvp (interrupt not ready).")); 1191 goto nxge_check_hw_state_exit; 1192 } 1193 t_ldvp = ldgvp->ldvp_syserr; 1194 if (!t_ldvp->use_timer) { 1195 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1196 "ldgvp $%p t_ldvp $%p use_timer flag %d", 1197 ldgvp, t_ldvp, t_ldvp->use_timer)); 1198 goto nxge_check_hw_state_exit; 1199 } 1200 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 1201 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1202 "port%d Bad register acc handle", nxgep->mac.portnum)); 1203 } 1204 (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 1205 1206 nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 1207 NXGE_CHECK_TIMER); 1208 1209 nxge_check_hw_state_exit: 1210 MUTEX_EXIT(nxgep->genlock); 1211 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 1212 } 1213 1214 /*ARGSUSED*/ 1215 static void 1216 nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1217 struct iocblk *iocp) 1218 { 1219 ssize_t size; 1220 rtrace_t *rtp; 1221 mblk_t *nmp; 1222 uint32_t i, j; 1223 uint32_t start_blk; 1224 uint32_t base_entry; 1225 uint32_t num_entries; 1226 1227 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 1228 1229 size = 1024; 1230 if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 1231 NXGE_DEBUG_MSG((nxgep, STR_CTL, 1232 "malformed M_IOCTL MBLKL = %d size = %d", 1233 MBLKL(mp->b_cont), size)); 1234 miocnak(wq, mp, 0, EINVAL); 1235 return; 1236 } 1237 nmp = mp->b_cont; 1238 rtp = (rtrace_t *)nmp->b_rptr; 1239 start_blk = rtp->next_idx; 1240 num_entries = rtp->last_idx; 1241 base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 1242 1243 NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 1244 NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 1245 NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 1246 1247 rtp->next_idx = npi_rtracebuf.next_idx; 1248 rtp->last_idx = npi_rtracebuf.last_idx; 1249 rtp->wrapped = npi_rtracebuf.wrapped; 1250 for (i = 0, j = base_entry; i < num_entries; i++, j++) { 1251 rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 1252 rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 1253 rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 1254 } 1255 1256 nmp->b_wptr = nmp->b_rptr + size; 1257 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 1258 miocack(wq, mp, (int)size, 0); 1259 } 1260