1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls called by niu leaf driver. 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/hypervisor_api.h> 35#include <sys/nxge/nxge_impl.h> 36 37/* 38 * NIU HV API v1.0 definitions 39 */ 40#define N2NIU_RX_LP_SET 0x142 41#define N2NIU_RX_LP_GET 0x143 42#define N2NIU_TX_LP_SET 0x144 43#define N2NIU_TX_LP_GET 0x145 44 45/* 46 * NIU HV API v1.1 definitions 47 */ 48#define N2NIU_VR_ASSIGN 0x146 49#define N2NIU_VR_UNASSIGN 0x147 50#define N2NIU_VR_GETINFO 0x148 51 52#define N2NIU_VR_RX_DMA_ASSIGN 0x149 53#define N2NIU_VR_RX_DMA_UNASSIGN 0x14a 54#define N2NIU_VR_TX_DMA_ASSIGN 0x14b 55#define N2NIU_VR_TX_DMA_UNASSIGN 0x14c 56 57#define N2NIU_VR_GET_RX_MAP 0x14d 58#define N2NIU_VR_GET_TX_MAP 0x14e 59 60#define N2NIU_VRRX_SET_INO 0x150 61#define N2NIU_VRTX_SET_INO 0x151 62 63#define N2NIU_VRRX_GET_INFO 0x152 64#define N2NIU_VRTX_GET_INFO 0x153 65 66#define N2NIU_VRRX_LP_SET 0x154 67#define N2NIU_VRRX_LP_GET 0x155 68#define N2NIU_VRTX_LP_SET 0x156 69#define N2NIU_VRTX_LP_GET 0x157 70 71#define N2NIU_VRRX_PARAM_GET 0x158 72#define N2NIU_VRRX_PARAM_SET 0x159 73 74#define N2NIU_VRTX_PARAM_GET 0x15a 75#define N2NIU_VRTX_PARAM_SET 0x15b 76 77#if defined(lint) || defined(__lint) 78 79/*ARGSUSED*/ 80uint64_t 81hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx, 82 uint64_t raddr, uint64_t size) 83{ return (0); } 84 85/*ARGSUSED*/ 86uint64_t 87hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx, 88 uint64_t *raddr, uint64_t *size) 89{ return (0); } 90 91/*ARGSUSED*/ 92uint64_t 93hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx, 94 uint64_t raddr, uint64_t size) 95{ return (0); } 96 97/*ARGSUSED*/ 98uint64_t 99hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx, 100 uint64_t *raddr, uint64_t *size) 101{ return (0); } 102 103/*ARGSUSED*/ 104uint64_t 105hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie) 106{ return (0); } 107 108/*ARGSUSED*/ 109uint64_t 110hv_niu_vr_unassign(uint32_t cookie) 111{ return (0); } 112 113/*ARGSUSED*/ 114uint64_t 115hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size) 116{ return (0); } 117 118/*ARGSUSED*/ 119uint64_t 120hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map) 121{ return (0); } 122 123/*ARGSUSED*/ 124uint64_t 125hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map) 126{ return (0); } 127 128/*ARGSUSED*/ 129uint64_t 130hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx) 131{ return (0); } 132 133/*ARGSUSED*/ 134uint64_t 135hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx) 136{ return (0); } 137 138/*ARGSUSED*/ 139uint64_t 140hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx) 141{ return (0); } 142 143/*ARGSUSED*/ 144uint64_t 145hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx) 146{ return (0); } 147 148/*ARGSUSED*/ 149uint64_t 150hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx, 151 uint64_t raddr, uint64_t size) 152{ return (0); } 153 154/*ARGSUSED*/ 155uint64_t 156hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx, 157 uint64_t *raddr, uint64_t *size) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx, 163 uint64_t raddr, uint64_t size) 164{ return (0); } 165 166/*ARGSUSED*/ 167uint64_t 168hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx, 169 uint64_t *raddr, uint64_t *size) 170{ return (0); } 171 172/*ARGSUSED*/ 173uint64_t 174hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param, 175 uint64_t *value) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param, 181 uint64_t value) 182{ return (0); } 183 184/*ARGSUSED*/ 185uint64_t 186hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param, 187 uint64_t *value) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param, 193 uint64_t value) 194{ return (0); } 195 196/*ARGSUSED*/ 197uint64_t 198hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx, 199 uint64_t *group, uint64_t *logdev) 200{ return (0); } 201 202/*ARGSUSED*/ 203uint64_t 204hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx, 205 uint64_t *group, uint64_t *logdev) 206{ return (0); } 207 208/*ARGSUSED*/ 209uint64_t 210hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino) 216{ return (0); } 217 218#else /* lint || __lint */ 219 220 /* 221 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx, 222 * uint64_t raddr, uint64_t size) 223 */ 224 ENTRY(hv_niu_rx_logical_page_conf) 225 mov N2NIU_RX_LP_CONF, %o5 226 ta FAST_TRAP 227 retl 228 nop 229 SET_SIZE(hv_niu_rx_logical_page_conf) 230 231 /* 232 * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx, 233 * uint64_t *raddr, uint64_t *size) 234 */ 235 ENTRY(hv_niu_rx_logical_page_info) 236 mov %o2, %g1 237 mov %o3, %g2 238 mov N2NIU_RX_LP_INFO, %o5 239 ta FAST_TRAP 240 stx %o1, [%g1] 241 retl 242 stx %o2, [%g2] 243 SET_SIZE(hv_niu_rx_logical_page_info) 244 245 /* 246 * hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx, 247 * uint64_t raddr, uint64_t size) 248 */ 249 ENTRY(hv_niu_tx_logical_page_conf) 250 mov N2NIU_TX_LP_CONF, %o5 251 ta FAST_TRAP 252 retl 253 nop 254 SET_SIZE(hv_niu_tx_logical_page_conf) 255 256 /* 257 * hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx, 258 * uint64_t *raddr, uint64_t *size) 259 */ 260 ENTRY(hv_niu_tx_logical_page_info) 261 mov %o2, %g1 262 mov %o3, %g2 263 mov N2NIU_TX_LP_INFO, %o5 264 ta FAST_TRAP 265 stx %o1, [%g1] 266 retl 267 stx %o2, [%g2] 268 SET_SIZE(hv_niu_tx_logical_page_info) 269 270 /* 271 * hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, 272 * uint32_t *cookie) 273 */ 274 ENTRY(hv_niu_vr_assign) 275 mov %o2, %g1 276 mov N2NIU_VR_ASSIGN, %o5 277 ta FAST_TRAP 278 retl 279 stw %o1, [%g1] 280 SET_SIZE(hv_niu_vr_assign) 281 282 /* 283 * hv_niu_vr_unassign(uint32_t cookie) 284 */ 285 ENTRY(hv_niu_vr_unassign) 286 mov N2NIU_VR_UNASSIGN, %o5 287 ta FAST_TRAP 288 retl 289 nop 290 SET_SIZE(hv_niu_vr_unassign) 291 292 /* 293 * hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start, 294 * uint64_t &size) 295 */ 296 ENTRY(hv_niu_vr_getinfo) 297 mov %o1, %g1 298 mov %o2, %g2 299 mov N2NIU_VR_GETINFO, %o5 300 ta FAST_TRAP 301 stx %o1, [%g1] 302 retl 303 stx %o2, [%g2] 304 SET_SIZE(hv_niu_vr_getinfo) 305 306 /* 307 * hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map) 308 */ 309 ENTRY(hv_niu_vr_get_rxmap) 310 mov %o1, %g1 311 mov N2NIU_VR_GET_RX_MAP, %o5 312 ta FAST_TRAP 313 retl 314 stx %o1, [%g1] 315 SET_SIZE(hv_niu_vr_get_rxmap) 316 317 /* 318 * hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map) 319 */ 320 ENTRY(hv_niu_vr_get_txmap) 321 mov %o1, %g1 322 mov N2NIU_VR_GET_TX_MAP, %o5 323 ta FAST_TRAP 324 retl 325 stx %o1, [%g1] 326 SET_SIZE(hv_niu_vr_get_txmap) 327 328 /* 329 * hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, 330 * uint64_t *vchidx) 331 */ 332 ENTRY(hv_niu_rx_dma_assign) 333 mov %o2, %g1 334 mov N2NIU_VR_RX_DMA_ASSIGN, %o5 335 ta FAST_TRAP 336 retl 337 stx %o1, [%g1] 338 SET_SIZE(hv_niu_rx_dma_assign) 339 340 /* 341 * hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx) 342 */ 343 ENTRY(hv_niu_rx_dma_unassign) 344 mov N2NIU_VR_RX_DMA_UNASSIGN, %o5 345 ta FAST_TRAP 346 retl 347 nop 348 SET_SIZE(hv_niu_rx_dma_unassign) 349 350 /* 351 * hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, 352 * uint64_t *vchidx) 353 */ 354 ENTRY(hv_niu_tx_dma_assign) 355 mov %o2, %g1 356 mov N2NIU_VR_TX_DMA_ASSIGN, %o5 357 ta FAST_TRAP 358 retl 359 stx %o1, [%g1] 360 SET_SIZE(hv_niu_tx_dma_assign) 361 362 /* 363 * hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t vchidx) 364 */ 365 ENTRY(hv_niu_tx_dma_unassign) 366 mov N2NIU_VR_TX_DMA_UNASSIGN, %o5 367 ta FAST_TRAP 368 retl 369 nop 370 SET_SIZE(hv_niu_tx_dma_unassign) 371 372 /* 373 * hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, 374 * uint64_t pgidx, uint64_t raddr, uint64_t size) 375 */ 376 ENTRY(hv_niu_vrrx_logical_page_conf) 377 mov N2NIU_VRRX_LP_SET, %o5 378 ta FAST_TRAP 379 retl 380 nop 381 SET_SIZE(hv_niu_vrrx_logical_page_conf) 382 383 /* 384 * hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, 385 * uint64_t pgidx, uint64_t *raddr, uint64_t *size) 386 */ 387 ENTRY(hv_niu_vrrx_logical_page_info) 388 mov %o3, %g1 389 mov %o4, %g2 390 mov N2NIU_VRRX_LP_GET, %o5 391 ta FAST_TRAP 392 stx %o1, [%g1] 393 retl 394 stx %o2, [%g2] 395 SET_SIZE(hv_niu_vrrx_logical_page_info) 396 397 /* 398 * hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, 399 * uint64_t pgidx, uint64_t raddr, uint64_t size) 400 */ 401 ENTRY(hv_niu_vrtx_logical_page_conf) 402 mov N2NIU_VRTX_LP_SET, %o5 403 ta FAST_TRAP 404 retl 405 nop 406 SET_SIZE(hv_niu_vrtx_logical_page_conf) 407 408 /* 409 * hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, 410 * uint64_t pgidx, uint64_t *raddr, uint64_t *size) 411 */ 412 ENTRY(hv_niu_vrtx_logical_page_info) 413 mov %o3, %g1 414 mov %o4, %g2 415 mov N2NIU_VRTX_LP_GET, %o5 416 ta FAST_TRAP 417 stx %o1, [%g1] 418 retl 419 stx %o2, [%g2] 420 SET_SIZE(hv_niu_vrtx_logical_page_info) 421 422 /* 423 * hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx, 424 * uint64_t *group, uint64_t *logdev) 425 */ 426 ENTRY(hv_niu_vrrx_getinfo) 427 mov %o2, %g1 428 mov %o3, %g2 429 mov N2NIU_VRRX_GET_INFO, %o5 430 ta FAST_TRAP 431 stx %o2, [%g2] 432 retl 433 stx %o1, [%g1] 434 SET_SIZE(hv_niu_vrrx_getinfo) 435 436 /* 437 * hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx, 438 * uint64_t *group, uint64_t *logdev) 439 */ 440 ENTRY(hv_niu_vrtx_getinfo) 441 mov %o2, %g1 442 mov %o3, %g2 443 mov N2NIU_VRTX_GET_INFO, %o5 444 ta FAST_TRAP 445 stx %o2, [%g2] 446 retl 447 stx %o1, [%g1] 448 SET_SIZE(hv_niu_vrtx_getinfo) 449 450 /* 451 * hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino) 452 */ 453 ENTRY(hv_niu_vrrx_set_ino) 454 mov N2NIU_VRRX_SET_INO, %o5 455 ta FAST_TRAP 456 retl 457 nop 458 SET_SIZE(hv_niu_vrrx_set_ino) 459 460 /* 461 * hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino) 462 */ 463 ENTRY(hv_niu_vrtx_set_ino) 464 mov N2NIU_VRTX_SET_INO, %o5 465 ta FAST_TRAP 466 retl 467 nop 468 SET_SIZE(hv_niu_vrtx_set_ino) 469 470 /* 471 * hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, 472 * uint64_t param, uint64_t *value) 473 * 474 */ 475 ENTRY(hv_niu_vrrx_param_get) 476 mov %o3, %g1 477 mov N2NIU_VRRX_PARAM_GET, %o5 478 ta FAST_TRAP 479 retl 480 stx %o1, [%g1] 481 SET_SIZE(hv_niu_vrrx_param_get) 482 483 /* 484 * hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, 485 * uint64_t param, uint64_t value) 486 * 487 */ 488 ENTRY(hv_niu_vrrx_param_set) 489 mov N2NIU_VRRX_PARAM_SET, %o5 490 ta FAST_TRAP 491 retl 492 nop 493 SET_SIZE(hv_niu_vrrx_param_set) 494 495 /* 496 * hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, 497 * uint64_t param, uint64_t *value) 498 * 499 */ 500 ENTRY(hv_niu_vrtx_param_get) 501 mov %o3, %g1 502 mov N2NIU_VRTX_PARAM_GET, %o5 503 ta FAST_TRAP 504 retl 505 stx %o1, [%g1] 506 SET_SIZE(hv_niu_vrtx_param_get) 507 508 /* 509 * hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, 510 * uint64_t param, uint64_t value) 511 * 512 */ 513 ENTRY(hv_niu_vrtx_param_set) 514 mov N2NIU_VRTX_PARAM_SET, %o5 515 ta FAST_TRAP 516 retl 517 nop 518 SET_SIZE(hv_niu_vrtx_param_set) 519 520#endif /* lint || __lint */ 521