1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 27 * Use is subject to license terms. 28 */ 29 #ifndef _UNM_NIC_ 30 #define _UNM_NIC_ 31 32 #include <sys/inttypes.h> 33 #include <sys/rwlock.h> 34 #include <sys/mutex.h> 35 #include <sys/ddi.h> 36 37 #include <sys/sunddi.h> 38 #include <sys/types.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strsubr.h> 42 #include <sys/dlpi.h> 43 #include <sys/devops.h> 44 #include <sys/stat.h> 45 #include <sys/pci.h> 46 #include <sys/note.h> 47 #include <sys/modctl.h> 48 #include <sys/kstat.h> 49 #include <sys/ethernet.h> 50 #include <sys/errno.h> 51 #include <netinet/ip6.h> 52 #include <inet/common.h> 53 #include <sys/pattr.h> 54 #include <inet/mi.h> 55 #include <inet/nd.h> 56 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/miiregs.h> /* by fjlite out of intel */ 60 61 #include "unm_nic_hw.h" 62 #include "nic_cmn.h" 63 #include "unm_inc.h" /* For MAX_RCV_CTX */ 64 #include "unm_brdcfg.h" 65 #include "unm_version.h" 66 #include "nic_phan_reg.h" 67 #include "unm_nic_ioctl.h" 68 69 #define MAX_ADDR_LEN 6 70 71 #define ADDR_IN_WINDOW1(off) \ 72 ((off > UNM_CRB_PCIX_HOST2) && (off < UNM_CRB_MAX)) ? 1 : 0 73 74 typedef unsigned long uptr_t; 75 76 #define FIRST_PAGE_GROUP_START 0 77 #define FIRST_PAGE_GROUP_END 0x100000 78 79 #define SECOND_PAGE_GROUP_START 0x6000000 80 #define SECOND_PAGE_GROUP_END 0x68BC000 81 82 #define THIRD_PAGE_GROUP_START 0x70E4000 83 #define THIRD_PAGE_GROUP_END 0x8000000 84 85 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START 86 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START 87 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START 88 89 /* 90 * normalize a 64MB crb address to 32MB PCI window 91 * To use CRB_NORMALIZE, window _must_ be set to 1 92 */ 93 #define CRB_NORMAL(reg) \ 94 (reg) - UNM_CRB_PCIX_HOST2 + UNM_CRB_PCIX_HOST 95 #define CRB_NORMALIZE(adapter, reg) \ 96 (void *)(unsigned long)(pci_base_offset(adapter, CRB_NORMAL(reg))) 97 98 #define DB_NORMALIZE(adapter, off) \ 99 (void *)((unsigned long)adapter->ahw.db_base + (off)) 100 101 #define find_diff_among(a, b, range) \ 102 ((a) < (b)?((b)-(a)):((b)+(range)-(a))) 103 104 #define __FUNCTION__ __func__ 105 #define nx_msleep(_msecs_) delay(drv_usectohz(_msecs_ * 1000)) 106 107 #define HOST_TO_LE_64 LE_64 108 #define HOST_TO_LE_32 LE_32 109 #define LE_TO_HOST_32 LE_32 110 #define HOST_TO_LE_16 LE_16 111 #define LE_TO_HOST_16 LE_16 112 113 #define dbwritel(DATA, ADDRESS) \ 114 ddi_put32(adapter->db_handle, (uint32_t *)(ADDRESS), (DATA)) 115 116 /* 117 * Following macros require the mapped addresses to access 118 * the Phantom memory. 119 */ 120 #define UNM_NIC_PCI_READ_8(ADDRESS) \ 121 ddi_get8(adapter->regs_handle, (uint8_t *)(ADDRESS)) 122 #define UNM_NIC_PCI_READ_16(ADDRESS) \ 123 ddi_get16(adapter->regs_handle, (uint16_t *)(ADDRESS)) 124 #define UNM_NIC_PCI_READ_32(ADDRESS) \ 125 ddi_get32(adapter->regs_handle, (uint32_t *)(ADDRESS)) 126 #define UNM_NIC_PCI_READ_64(ADDRESS) \ 127 ddi_get64(adapter->regs_handle, (uint64_t *)(ADDRESS)) 128 129 #define UNM_NIC_PCI_WRITE_8(DATA, ADDRESS) \ 130 ddi_put8(adapter->regs_handle, (uint8_t *)(ADDRESS), (DATA)) 131 #define UNM_NIC_PCI_WRITE_16(DATA, ADDRESS) \ 132 ddi_put16(adapter->regs_handle, (uint16_t *)(ADDRESS), (DATA)) 133 #define UNM_NIC_PCI_WRITE_32(DATA, ADDRESS) \ 134 ddi_put32(adapter->regs_handle, (uint32_t *)(ADDRESS), (DATA)) 135 #define UNM_NIC_PCI_WRITE_64(DATA, ADDRESS) \ 136 ddi_put64(adapter->regs_handle, (uint64_t *)(ADDRESS), (DATA)) 137 138 #ifdef DEBUG_LEVEL 139 #define DPRINTF(n, args) if (DEBUG_LEVEL > (n)) cmn_err args; 140 #else 141 #define DPRINTF(n, args) 142 #endif 143 144 #define UNM_SPIN_LOCK(_lp_) mutex_enter((_lp_)) 145 #define UNM_SPIN_UNLOCK(_lp_) mutex_exit((_lp_)) 146 #define UNM_SPIN_LOCK_ISR(_lp_) mutex_enter((_lp_)) 147 #define UNM_SPIN_UNLOCK_ISR(_lp_) mutex_exit((_lp_)) 148 149 #define UNM_WRITE_LOCK(_lp_) rw_enter((_lp_), RW_WRITER) 150 #define UNM_WRITE_UNLOCK(_lp_) rw_exit((_lp_)) 151 #define UNM_READ_LOCK(_lp_) rw_enter((_lp_), RW_READER) 152 #define UNM_READ_UNLOCK(_lp_) rw_exit((_lp_)) 153 #define UNM_WRITE_LOCK_IRQS(_lp_, _fl_) rw_enter((_lp_), RW_WRITER) 154 #define UNM_WRITE_UNLOCK_IRQR(_lp_, _fl_) rw_exit((_lp_)) 155 156 extern char unm_nic_driver_name[]; 157 extern int verbmsg; 158 159 typedef struct unm_dmah_node { 160 struct unm_dmah_node *next; 161 ddi_dma_handle_t dmahdl; 162 }unm_dmah_node_t; 163 164 typedef struct dma_area { 165 ddi_acc_handle_t acc_hdl; /* handle for memory */ 166 ddi_dma_handle_t dma_hdl; /* DMA handle */ 167 uint32_t ncookies; 168 u64 dma_addr; 169 void *vaddr; 170 } dma_area_t; 171 172 struct unm_cmd_buffer { 173 dma_area_t dma_area; 174 mblk_t *msg; 175 unm_dmah_node_t *head, *tail; 176 }; 177 178 typedef struct pkt_info { 179 uint32_t total_len; 180 uint16_t mblk_no; 181 uint16_t etype; 182 uint16_t mac_hlen; 183 uint16_t ip_hlen; 184 uint16_t l4_proto; 185 } pktinfo_t; 186 187 typedef struct unm_rcv_desc_context_s unm_rcv_desc_ctx_t; 188 typedef struct unm_adapter_s unm_adapter; 189 190 typedef struct unm_rx_buffer { 191 struct unm_rx_buffer *next; 192 dma_area_t dma_info; 193 frtn_t rx_recycle; /* recycle function */ 194 mblk_t *mp; 195 unm_rcv_desc_ctx_t *rcv_desc; 196 unm_adapter *adapter; 197 }unm_rx_buffer_t; 198 199 /* Board types */ 200 #define UNM_NIC_GBE 0x01 201 #define UNM_NIC_XGBE 0x02 202 203 /* 204 * One hardware_context{} per adapter 205 * contains interrupt info as well shared hardware info. 206 */ 207 typedef struct _hardware_context { 208 unsigned long pci_base0; 209 unsigned long pci_len0; 210 unsigned long pci_base1; 211 unsigned long pci_len1; 212 unsigned long pci_base2; 213 unsigned long pci_len2; 214 unsigned long first_page_group_end; 215 unsigned long first_page_group_start; 216 uint8_t revision_id; 217 uint8_t cut_through; 218 uint16_t board_type; 219 int pci_func; 220 uint16_t max_ports; 221 unm_board_info_t boardcfg; 222 uint32_t linkup; 223 224 struct unm_adapter_s *adapter; 225 cmdDescType0_t *cmdDescHead; 226 227 uint32_t cmdProducer; 228 uint32_t cmdConsumer; 229 uint32_t rcvFlag; 230 uint32_t crb_base; 231 unsigned long db_base; /* base of mapped db memory */ 232 unsigned long db_len; /* length of mapped db memory */ 233 234 235 uint64_t cmdDesc_physAddr; 236 int qdr_sn_window, ddr_mn_window; 237 unsigned long mn_win_crb, ms_win_crb; 238 ddi_dma_handle_t cmd_desc_dma_handle; 239 ddi_acc_handle_t cmd_desc_acc_handle; 240 ddi_dma_cookie_t cmd_desc_dma_cookie; 241 } hardware_context, *phardware_context; 242 243 #define NX_CT_DEFAULT_RX_BUF_LEN 2048 244 #define MTU_SIZE 1500 245 #define MAX_COOKIES_PER_CMD 16 246 #define UNM_DB_MAPSIZE_BYTES 0x1000 247 #define EXTRA_HANDLES 512 248 #define UNM_TX_BCOPY_THRESHOLD 128 249 #define UNM_RX_BCOPY_THRESHOLD 128 250 #define NX_MIN_DRIVER_RDS_SIZE 64 251 252 typedef struct unm_pauseparam { 253 uint16_t rx_pause; 254 uint16_t tx_pause; 255 } unm_pauseparam_t; 256 257 /* 258 * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback 259 * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE 260 * 261 * These are the values to use with LD_SET_MODE. 262 */ 263 #define UNM_LOOP_NONE 0 264 #define UNM_LOOP_INTERNAL_PHY 1 265 #define UNM_LOOP_INTERNAL_MAC 2 266 267 /* 268 * Named Data (ND) Parameter Management Structure 269 */ 270 typedef struct { 271 int ndp_info; 272 int ndp_min; 273 int ndp_max; 274 int ndp_val; 275 char *ndp_name; 276 } nd_param_t; /* 0x18 (24) bytes */ 277 278 /* 279 * NDD parameter indexes, divided into: 280 * 281 * read-only parameters describing the hardware's capabilities 282 * read-write parameters controlling the advertised capabilities 283 * read-only parameters describing the partner's capabilities 284 * read-only parameters describing the link state 285 */ 286 enum { 287 PARAM_AUTONEG_CAP = 0, 288 PARAM_PAUSE_CAP, 289 PARAM_ASYM_PAUSE_CAP, 290 PARAM_10000FDX_CAP, 291 PARAM_1000FDX_CAP, 292 PARAM_1000HDX_CAP, 293 PARAM_100T4_CAP, 294 PARAM_100FDX_CAP, 295 PARAM_100HDX_CAP, 296 PARAM_10FDX_CAP, 297 PARAM_10HDX_CAP, 298 299 PARAM_ADV_AUTONEG_CAP, 300 PARAM_ADV_PAUSE_CAP, 301 PARAM_ADV_ASYM_PAUSE_CAP, 302 PARAM_ADV_10000FDX_CAP, 303 PARAM_ADV_1000FDX_CAP, 304 PARAM_ADV_1000HDX_CAP, 305 PARAM_ADV_100T4_CAP, 306 PARAM_ADV_100FDX_CAP, 307 PARAM_ADV_100HDX_CAP, 308 PARAM_ADV_10FDX_CAP, 309 PARAM_ADV_10HDX_CAP, 310 311 PARAM_LINK_STATUS, 312 PARAM_LINK_SPEED, 313 PARAM_LINK_DUPLEX, 314 315 PARAM_LOOP_MODE, 316 317 PARAM_COUNT 318 }; 319 320 struct unm_adapter_stats { 321 uint64_t rcvdbadmsg; 322 uint64_t xmitcalled; 323 uint64_t xmitedframes; 324 uint64_t xmitfinished; 325 uint64_t badmsglen; 326 uint64_t nocmddescriptor; 327 uint64_t polled; 328 uint64_t uphappy; 329 uint64_t updropped; 330 uint64_t uplcong; 331 uint64_t uphcong; 332 uint64_t upmcong; 333 uint64_t updunno; 334 uint64_t msgfreed; 335 uint64_t txdropped; 336 uint64_t txnullmsg; 337 uint64_t csummed; 338 uint64_t no_rcv; 339 uint64_t rxbytes; 340 uint64_t txbytes; 341 uint64_t ints; 342 uint64_t desballocfailed; 343 uint64_t txcopyed; 344 uint64_t txmapped; 345 uint64_t outoftxdmahdl; 346 uint64_t outofcmddesc; 347 uint64_t rxcopyed; 348 uint64_t rxmapped; 349 uint64_t outofrxbuf; 350 uint64_t promiscmode; 351 uint64_t rxbufshort; 352 uint64_t allocbfailed; 353 }; 354 355 /* descriptor types */ 356 #define RCV_RING_STD RCV_DESC_NORMAL 357 #define RCV_RING_JUMBO RCV_DESC_JUMBO 358 #define RCV_RING_LRO RCV_DESC_LRO 359 360 /* 361 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 362 * be one Rcv Descriptor for normal packets, one for jumbo, 363 * one for LRO and may be expanded. 364 */ 365 struct unm_rcv_desc_context_s { 366 uint32_t producer; 367 368 uint64_t phys_addr; 369 dev_info_t *phys_pdev; 370 /* address of rx ring in Phantom */ 371 rcvDesc_t *desc_head; 372 373 uint32_t MaxRxDescCount; 374 uint32_t rx_desc_handled; 375 uint32_t rx_buf_card; 376 uint32_t rx_buf_total; 377 uint32_t rx_buf_free; 378 uint32_t rx_buf_recycle; 379 unm_rx_buffer_t *rx_buf_pool; 380 unm_rx_buffer_t *pool_list; 381 unm_rx_buffer_t *recycle_list; 382 kmutex_t pool_lock[1]; /* buffer pool lock */ 383 kmutex_t recycle_lock[1]; /* buffer recycle lock */ 384 /* size of the receive buf */ 385 uint32_t buf_size; 386 /* rx buffers for receive */ 387 388 ddi_dma_handle_t rx_desc_dma_handle; 389 ddi_acc_handle_t rx_desc_acc_handle; 390 ddi_dma_cookie_t rx_desc_dma_cookie; 391 uint32_t host_rx_producer; 392 uint32_t dma_size; 393 }; 394 395 /* 396 * Receive context. There is one such structure per instance of the 397 * receive processing. Any state information that is relevant to 398 * the receive, and is must be in this structure. The global data may be 399 * present elsewhere. 400 */ 401 typedef struct unm_recv_context_s { 402 unm_rcv_desc_ctx_t rcv_desc[NUM_RCV_DESC_RINGS]; 403 404 uint32_t statusRxConsumer; 405 406 uint64_t rcvStatusDesc_physAddr; 407 statusDesc_t *rcvStatusDescHead; 408 409 ddi_dma_handle_t status_desc_dma_handle; 410 ddi_acc_handle_t status_desc_acc_handle; 411 ddi_dma_cookie_t status_desc_dma_cookie; 412 413 uint32_t state, host_sds_consumer; 414 uint16_t context_id, virt_port; 415 } unm_recv_context_t; 416 417 #define UNM_NIC_MSI_ENABLED 0x02 418 #define UNM_NIC_MSIX_ENABLED 0x04 419 #define UNM_IS_MSI_FAMILY(ADAPTER) \ 420 ((ADAPTER)->flags & (UNM_NIC_MSI_ENABLED | UNM_NIC_MSIX_ENABLED)) 421 422 #define NX_USE_MSIX 423 424 /* msix defines */ 425 #define MSIX_ENTRIES_PER_ADAPTER 8 426 #define UNM_MSIX_TBL_SPACE 8192 427 #define UNM_PCI_REG_MSIX_TBL 0x44 428 429 /* 430 * Bug: word or char write on MSI-X capcabilities register (0x40) in PCI config 431 * space has no effect on register values. Need to write dword. 432 */ 433 #define UNM_HWBUG_8_WORKAROUND 434 435 /* 436 * Bug: Can not reset bit 32 (msix enable bit) on MSI-X capcabilities 437 * register (0x40) independently. 438 * Need to write 0x0 (zero) to MSI-X capcabilities register in order to reset 439 * msix enable bit. On writing zero rest of the bits are not touched. 440 */ 441 #define UNM_HWBUG_9_WORKAROUND 442 443 #define UNM_MC_COUNT 38 /* == ((UNM_ADDR_L2LU_COUNT-1)/4) -2 */ 444 445 /* Following structure is for specific port information */ 446 struct unm_adapter_s { 447 hardware_context ahw; 448 uint8_t id[32]; 449 uint16_t portnum; 450 uint16_t physical_port; 451 uint16_t link_speed; 452 uint16_t link_duplex; 453 454 struct unm_adapter_stats stats; 455 int rx_csum; 456 int status; 457 kmutex_t stats_lock; 458 unsigned char mac_addr[MAX_ADDR_LEN]; 459 int mtu; /* active mtu */ 460 int maxmtu; /* max possible mtu value */ 461 uint32_t promisc; 462 463 mac_resource_handle_t mac_rx_ring_ha; 464 mac_handle_t mach; 465 int flags; 466 467 int instance; 468 dev_info_t *dip; 469 ddi_acc_handle_t pci_cfg_handle; 470 ddi_acc_handle_t regs_handle; 471 ddi_dma_attr_t gc_dma_attr_desc; 472 473 struct ddi_device_acc_attr gc_attr_desc; 474 ddi_iblock_cookie_t iblock_cookie; 475 const char *name; 476 ddi_acc_handle_t db_handle; 477 478 ddi_intr_handle_t intr_handle; 479 int intr_type; 480 uint_t intr_pri; 481 unm_dmah_node_t *dmahdl_pool; 482 unm_dmah_node_t tx_dma_hdls[MAX_CMD_DESCRIPTORS+EXTRA_HANDLES]; 483 uint64_t freehdls; 484 uint64_t freecmds; 485 int tx_bcopy_threshold; 486 kmutex_t tx_lock; 487 krwlock_t adapter_lock; 488 kmutex_t lock; 489 struct nx_legacy_intr_set legacy_intr; 490 timeout_id_t watchdog_timer; 491 kstat_t *kstats[1]; 492 493 uint32_t curr_window; 494 uint32_t crb_win; 495 uint32_t cmdProducer; 496 uint32_t *cmdConsumer; 497 498 uint32_t interrupt_crb; 499 uint32_t fw_major; 500 uint32_t crb_addr_cmd_producer; 501 uint32_t crb_addr_cmd_consumer; 502 uint16_t tx_context_id; 503 short context_alloced; 504 int max_rds_rings; 505 506 uint32_t lastCmdConsumer; 507 /* Num of bufs posted in phantom */ 508 uint32_t pendingCmdCount; 509 uint32_t MaxTxDescCount; 510 uint32_t MaxRxDescCount; 511 uint32_t MaxJumboRxDescCount; 512 uint32_t MaxLroRxDescCount; 513 /* Num of instances active on cmd buffer ring */ 514 int resched_needed; 515 516 int driver_mismatch; 517 uint32_t temp; 518 519 struct unm_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ 520 int rx_bcopy_threshold; 521 522 /* 523 * Receive instances. These can be either one per port, 524 * or one per peg, etc. 525 */ 526 unm_recv_context_t recv_ctx[MAX_RCV_CTX]; 527 int is_up; 528 529 /* context interface shared between card and host */ 530 RingContext *ctxDesc; 531 uint64_t ctxDesc_physAddr; 532 ddi_dma_handle_t ctxDesc_dma_handle; 533 ddi_acc_handle_t ctxDesc_acc_handle; 534 535 struct { 536 void *addr; 537 uint64_t phys_addr; 538 ddi_dma_handle_t dma_handle; 539 ddi_acc_handle_t acc_handle; 540 } dummy_dma; 541 542 void (*unm_nic_pci_change_crbwindow)(struct unm_adapter_s *, 543 uint32_t); 544 int (*unm_crb_writelit_adapter)(struct unm_adapter_s *, 545 unsigned long, int); 546 unsigned long long 547 (*unm_nic_pci_set_window)(struct unm_adapter_s *, 548 unsigned long long); 549 int (*unm_nic_fill_statistics)(struct unm_adapter_s *, 550 struct unm_statistics *); 551 int (*unm_nic_clear_statistics)(struct unm_adapter_s *); 552 int (*unm_nic_hw_write_wx)(struct unm_adapter_s *, u64, 553 void *, int); 554 int (*unm_nic_hw_read_wx)(struct unm_adapter_s *, u64, void *, int); 555 int (*unm_nic_hw_write_ioctl)(struct unm_adapter_s *, u64, void *, 556 int); 557 int (*unm_nic_hw_read_ioctl)(struct unm_adapter_s *, u64, void *, 558 int); 559 int (*unm_nic_pci_mem_write)(struct unm_adapter_s *, u64, void *, 560 int); 561 int (*unm_nic_pci_mem_read)(struct unm_adapter_s *, u64, void *, 562 int); 563 int (*unm_nic_pci_write_immediate)(struct unm_adapter_s *, u64, 564 u32 *); 565 int (*unm_nic_pci_read_immediate)(struct unm_adapter_s *, u64, 566 u32 *); 567 void (*unm_nic_pci_write_normalize)(struct unm_adapter_s *, u64, 568 u32); 569 u32 (*unm_nic_pci_read_normalize)(struct unm_adapter_s *, u64); 570 571 caddr_t nd_data_p; 572 nd_param_t nd_params[PARAM_COUNT]; 573 }; /* unm_adapter structure */ 574 575 #define UNM_HOST_DUMMY_DMA_SIZE 1024 576 577 /* Following structure is for specific port information */ 578 579 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ 580 ((adapter)->ahw.pci_base0 + off) 581 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ 582 ((adapter)->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START) 583 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ 584 ((adapter)->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START) 585 586 #define pci_base_offset(adapter, off) \ 587 ((((off) < ((adapter)->ahw.first_page_group_end)) && \ 588 ((off) >= ((adapter)->ahw.first_page_group_start))) ? \ 589 ((adapter)->ahw.pci_base0 + (off)) : \ 590 ((((off) < SECOND_PAGE_GROUP_END) && \ 591 ((off) >= SECOND_PAGE_GROUP_START)) ? \ 592 ((adapter)->ahw.pci_base1 + \ 593 (off) - SECOND_PAGE_GROUP_START) : \ 594 ((((off) < THIRD_PAGE_GROUP_END) && \ 595 ((off) >= THIRD_PAGE_GROUP_START)) ? \ 596 ((adapter)->ahw.pci_base2 + (off) - \ 597 THIRD_PAGE_GROUP_START) : \ 598 0))) 599 #define unm_nic_reg_write(_adp_, _off_, _val_) \ 600 { \ 601 __uint32_t _v1_ = (_val_); \ 602 ((_adp_)->unm_nic_hw_write_wx((_adp_), (_off_), \ 603 &_v1_, 4)); \ 604 } 605 606 #define unm_nic_reg_read(_adp_, _off_, _ptr_) \ 607 ((_adp_)->unm_nic_hw_read_wx((_adp_), (_off_), (_ptr_), 4)) 608 609 610 #define unm_nic_write_w0(_adp_, _idx_, _val_) \ 611 ((_adp_)->unm_nic_hw_write_wx((_adp_), (_idx_), &(_val_), 4)) 612 613 #define unm_nic_read_w0(_adp_, _idx_, _val_) \ 614 ((_adp_)->unm_nic_hw_read_wx((_adp_), (_idx_), (_val_), 4)) 615 616 /* Functions available from unm_nic_hw.c */ 617 int unm_nic_get_board_info(struct unm_adapter_s *adapter); 618 void _unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index, 619 uint32_t value); 620 void unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index, 621 uint32_t value); 622 void _unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index, 623 uint32_t *value); 624 void unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index, 625 uint32_t *value); 626 // int unm_nic_reg_read (unm_adapter *adapter, u64 off); 627 int _unm_nic_hw_write(struct unm_adapter_s *adapter, 628 u64 off, void *data, int len); 629 int unm_nic_hw_write(struct unm_adapter_s *adapter, 630 u64 off, void *data, int len); 631 int _unm_nic_hw_read(struct unm_adapter_s *adapter, 632 u64 off, void *data, int len); 633 int unm_nic_hw_read(struct unm_adapter_s *adapter, 634 u64 off, void *data, int len); 635 void _unm_nic_hw_block_read(struct unm_adapter_s *adapter, 636 u64 off, void *data, int num_words); 637 void unm_nic_hw_block_read(struct unm_adapter_s *adapter, 638 u64 off, void *data, int num_words); 639 void _unm_nic_hw_block_write(struct unm_adapter_s *adapter, 640 u64 off, void *data, int num_words); 641 void unm_nic_hw_block_write(struct unm_adapter_s *adapter, 642 u64 off, void *data, int num_words); 643 int unm_nic_pci_mem_write(struct unm_adapter_s *adapter, 644 u64 off, void *data, int size); 645 void unm_nic_mem_block_read(struct unm_adapter_s *adapter, u64 off, 646 void *data, int num_words); 647 void unm_nic_mem_block_write(struct unm_adapter_s *adapter, u64 off, 648 void *data, int num_words); 649 int unm_nic_hw_read_ioctl(unm_adapter *adapter, u64 off, void *data, int len); 650 int unm_nic_hw_write_ioctl(unm_adapter *adapter, u64 off, void *data, int len); 651 int unm_nic_macaddr_set(struct unm_adapter_s *, __uint8_t *addr); 652 void unm_tcl_resetall(struct unm_adapter_s *adapter); 653 void unm_tcl_phaninit(struct unm_adapter_s *adapter); 654 void unm_tcl_postimage(struct unm_adapter_s *adapter); 655 int unm_nic_set_mtu(struct unm_adapter_s *adapter, int new_mtu); 656 long unm_nic_phy_read(unm_adapter *adapter, long reg, __uint32_t *); 657 long unm_nic_init_port(struct unm_adapter_s *adapter); 658 void unm_crb_write_adapter(unsigned long off, void *data, 659 struct unm_adapter_s *adapter); 660 int unm_crb_read_adapter(unsigned long off, void *data, 661 struct unm_adapter_s *adapter); 662 int unm_crb_read_val_adapter(unsigned long off, 663 struct unm_adapter_s *adapter); 664 void unm_nic_stop_port(struct unm_adapter_s *adapter); 665 int unm_nic_set_promisc_mode(struct unm_adapter_s *adapter); 666 int unm_nic_unset_promisc_mode(struct unm_adapter_s *adapter); 667 668 /* unm_nic_hw.c */ 669 void unm_nic_pci_change_crbwindow_128M(unm_adapter *adapter, uint32_t wndw); 670 int unm_crb_writelit_adapter_128M(struct unm_adapter_s *, unsigned long, int); 671 int unm_nic_hw_write_wx_128M(unm_adapter *adapter, u64 off, void *data, 672 int len); 673 int unm_nic_hw_read_wx_128M(unm_adapter *adapter, u64 off, void *data, int len); 674 int unm_nic_hw_write_ioctl_128M(unm_adapter *adapter, u64 off, void *data, 675 int len); 676 int unm_nic_hw_read_ioctl_128M(unm_adapter *adapter, u64 off, void *data, 677 int len); 678 int unm_nic_pci_mem_write_128M(struct unm_adapter_s *adapter, u64 off, 679 void *data, int size); 680 int unm_nic_pci_mem_read_128M(struct unm_adapter_s *adapter, u64 off, 681 void *data, int size); 682 void unm_nic_pci_write_normalize_128M(unm_adapter *adapter, u64 off, u32 data); 683 u32 unm_nic_pci_read_normalize_128M(unm_adapter *adapter, u64 off); 684 int unm_nic_pci_write_immediate_128M(unm_adapter *adapter, u64 off, u32 *data); 685 int unm_nic_pci_read_immediate_128M(unm_adapter *adapter, u64 off, u32 *data); 686 unsigned long long unm_nic_pci_set_window_128M(unm_adapter *adapter, 687 unsigned long long addr); 688 int unm_nic_clear_statistics_128M(struct unm_adapter_s *adapter); 689 int unm_nic_fill_statistics_128M(struct unm_adapter_s *adapter, 690 struct unm_statistics *unm_stats); 691 692 void unm_nic_pci_change_crbwindow_2M(unm_adapter *adapter, uint32_t wndw); 693 int unm_crb_writelit_adapter_2M(struct unm_adapter_s *, unsigned long, int); 694 int unm_nic_hw_write_wx_2M(unm_adapter *adapter, u64 off, void *data, int len); 695 int unm_nic_pci_mem_write_2M(struct unm_adapter_s *adapter, u64 off, 696 void *data, int size); 697 int unm_nic_pci_mem_read_2M(struct unm_adapter_s *adapter, u64 off, 698 void *data, int size); 699 int unm_nic_hw_read_wx_2M(unm_adapter *adapter, u64 off, void *data, int len); 700 void unm_nic_pci_write_normalize_2M(unm_adapter *adapter, u64 off, u32 data); 701 u32 unm_nic_pci_read_normalize_2M(unm_adapter *adapter, u64 off); 702 int unm_nic_pci_write_immediate_2M(unm_adapter *adapter, u64 off, u32 *data); 703 int unm_nic_pci_read_immediate_2M(unm_adapter *adapter, u64 off, u32 *data); 704 unsigned long long unm_nic_pci_set_window_2M(unm_adapter *adapter, 705 unsigned long long addr); 706 int unm_nic_clear_statistics_2M(struct unm_adapter_s *adapter); 707 int unm_nic_fill_statistics_2M(struct unm_adapter_s *adapter, 708 struct unm_statistics *unm_stats); 709 void nx_p3_nic_set_multi(unm_adapter *adapter); 710 711 /* unm_nic_init.c */ 712 int phantom_init(struct unm_adapter_s *adapter, int first_time); 713 int load_from_flash(struct unm_adapter_s *adapter); 714 int pinit_from_rom(unm_adapter *adapter, int verbose); 715 int rom_fast_read(struct unm_adapter_s *adapter, int addr, int *valp); 716 717 /* unm_nic_isr.c */ 718 void unm_nic_handle_phy_intr(unm_adapter *adapter); 719 720 /* niu.c */ 721 native_t unm_niu_set_promiscuous_mode(struct unm_adapter_s *adapter, 722 unm_niu_prom_mode_t mode); 723 native_t unm_niu_xg_set_promiscuous_mode(struct unm_adapter_s *adapter, 724 unm_niu_prom_mode_t mode); 725 726 int unm_niu_xg_macaddr_set(struct unm_adapter_s *adapter, 727 unm_ethernet_macaddr_t addr); 728 native_t unm_niu_disable_xg_port(struct unm_adapter_s *adapter); 729 730 long unm_niu_gbe_init_port(long port); 731 native_t unm_niu_enable_gbe_port(struct unm_adapter_s *adapter, 732 unm_niu_gbe_ifmode_t mode); 733 native_t unm_niu_disable_gbe_port(struct unm_adapter_s *adapter); 734 735 int unm_niu_macaddr_get(struct unm_adapter_s *adapter, unsigned char *addr); 736 int unm_niu_macaddr_set(struct unm_adapter_s *adapter, 737 unm_ethernet_macaddr_t addr); 738 739 int unm_niu_xg_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable); 740 int unm_niu_gbe_set_rx_flow_ctl(struct unm_adapter_s *adapter, int enable); 741 int unm_niu_gbe_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable); 742 long unm_niu_gbe_disable_phy_interrupts(struct unm_adapter_s *); 743 long unm_niu_gbe_phy_read(struct unm_adapter_s *, 744 long reg, unm_crbword_t *readval); 745 746 /* unm_nic_ctx.c */ 747 int netxen_create_rxtx(struct unm_adapter_s *adapter); 748 void netxen_destroy_rxtx(struct unm_adapter_s *adapter); 749 int nx_fw_cmd_set_mtu(struct unm_adapter_s *adapter, int mtu); 750 751 /* unm_nic_main.c */ 752 int receive_peg_ready(struct unm_adapter_s *adapter); 753 void unm_nic_update_cmd_producer(struct unm_adapter_s *adapter, 754 uint32_t crb_producer); 755 void unm_desc_dma_sync(ddi_dma_handle_t handle, uint_t start, uint_t count, 756 uint_t range, uint_t unit_size, uint_t direction); 757 int unm_pci_alloc_consistent(unm_adapter *, int, caddr_t *, 758 ddi_dma_cookie_t *, ddi_dma_handle_t *, ddi_acc_handle_t *); 759 void unm_pci_free_consistent(ddi_dma_handle_t *, ddi_acc_handle_t *); 760 761 /* unm_ndd.c */ 762 int unm_nd_init(unm_adapter *adapter); 763 enum ioc_reply unm_nd_ioctl(unm_adapter *adapter, queue_t *wq, 764 mblk_t *mp, struct iocblk *iocp); 765 void unm_nd_cleanup(unm_adapter *adapter); 766 767 /* unm_gem.c */ 768 void unm_destroy_intr(unm_adapter *adapter); 769 void unm_free_dummy_dma(unm_adapter *adapter); 770 771 /* 772 * (Internal) return values from ioctl subroutines 773 */ 774 enum ioc_reply { 775 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 776 IOC_DONE, /* OK, reply sent */ 777 IOC_ACK, /* OK, just send ACK */ 778 IOC_REPLY, /* OK, just send reply */ 779 IOC_RESTART_ACK, /* OK, restart & ACK */ 780 IOC_RESTART_REPLY /* OK, restart & reply */ 781 }; 782 783 /* 784 * Shorthand for the NDD parameters 785 */ 786 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 787 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 788 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 789 #define param_adv_10000fdx nd_params[PARAM_ADV_10000FDX_CAP].ndp_val 790 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 791 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 792 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 793 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 794 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 795 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 796 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 797 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 798 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 799 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 800 801 /* 802 * Property lookups 803 */ 804 #define UNM_PROP_EXISTS(d, n) \ 805 ddi_prop_exists(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n)) 806 #define UNM_PROP_GET_INT(d, n) \ 807 ddi_prop_get_int(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n), -1) 808 809 /* 810 * Bit flags in the 'debug' word ... 811 */ 812 #define UNM_DBG_TRACE 0x00000002 /* general flow tracing */ 813 #define UNM_DBG_NDD 0x20000000 /* NDD operations */ 814 815 #define MBPS_10 10 816 #define MBPS_100 100 817 #define MBPS_1000 1000 818 819 #endif /* !_UNM_NIC_ */ 820