1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 NetXen, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _UNM_INC_H_ 28 #define _UNM_INC_H_ 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "nx_errorcode.h" 35 36 #define PREALIGN(x) 37 #define POSTALIGN(x) 38 39 typedef char __int8_t; 40 typedef short __int16_t; 41 typedef int __int32_t; 42 typedef long long __int64_t; 43 typedef unsigned char __uint8_t; 44 typedef unsigned short __uint16_t; 45 typedef unsigned int __uint32_t; 46 typedef unsigned long long __uint64_t; 47 typedef __uint64_t jiffies_t; 48 49 typedef uint8_t u8; 50 typedef uint8_t U8; 51 typedef uint16_t U16; 52 typedef uint32_t u32; 53 typedef uint32_t U32; 54 typedef unsigned long long u64; 55 typedef unsigned long long U64; 56 57 #define UNUSED __attribute__((unused)) 58 #define NOINLINE __attribute__((noinline)) 59 60 #include "nx_hw_pci_regs.h" 61 62 #define UNM_CONF_X86 3 63 64 #define bzero(A, B) memset((A), 0, (B)) 65 66 /* 67 * MAX_RCV_CTX : The number of receive contexts that are available on 68 * the phantom. 69 */ 70 #define MAX_RCV_CTX 1 71 72 /* ------------------------------------------------------------------------ */ 73 /* CRB Hub and Agent addressing */ 74 /* ------------------------------------------------------------------------ */ 75 /* 76 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an 77 * ILLEGAL hub!!!!! 78 */ 79 #define UNM_HW_H0_CH_HUB_ADR 0x05 80 #define UNM_HW_H1_CH_HUB_ADR 0x0E 81 #define UNM_HW_H2_CH_HUB_ADR 0x03 82 #define UNM_HW_H3_CH_HUB_ADR 0x01 83 #define UNM_HW_H4_CH_HUB_ADR 0x06 84 #define UNM_HW_H5_CH_HUB_ADR 0x07 85 #define UNM_HW_H6_CH_HUB_ADR 0x08 86 /* 87 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an 88 * ILLEGAL hub!!!!! 89 */ 90 91 /* Hub 0 */ 92 #define UNM_HW_MN_CRB_AGT_ADR 0x15 93 #define UNM_HW_MS_CRB_AGT_ADR 0x25 94 95 /* Hub 1 */ 96 #define UNM_HW_PS_CRB_AGT_ADR 0x73 97 #define UNM_HW_SS_CRB_AGT_ADR 0x20 98 #define UNM_HW_RPMX3_CRB_AGT_ADR 0x0b 99 #define UNM_HW_QMS_CRB_AGT_ADR 0x00 100 #define UNM_HW_SQGS0_CRB_AGT_ADR 0x01 101 #define UNM_HW_SQGS1_CRB_AGT_ADR 0x02 102 #define UNM_HW_SQGS2_CRB_AGT_ADR 0x03 103 #define UNM_HW_SQGS3_CRB_AGT_ADR 0x04 104 #define UNM_HW_C2C0_CRB_AGT_ADR 0x58 105 #define UNM_HW_C2C1_CRB_AGT_ADR 0x59 106 #define UNM_HW_C2C2_CRB_AGT_ADR 0x5a 107 #define UNM_HW_RPMX2_CRB_AGT_ADR 0x0a 108 #define UNM_HW_RPMX4_CRB_AGT_ADR 0x0c 109 #define UNM_HW_RPMX7_CRB_AGT_ADR 0x0f 110 #define UNM_HW_RPMX9_CRB_AGT_ADR 0x12 111 #define UNM_HW_SMB_CRB_AGT_ADR 0x18 112 113 /* Hub 2 */ 114 #define UNM_HW_NIU_CRB_AGT_ADR 0x31 115 #define UNM_HW_I2C0_CRB_AGT_ADR 0x19 116 #define UNM_HW_I2C1_CRB_AGT_ADR 0x29 117 118 #define UNM_HW_SN_CRB_AGT_ADR 0x10 119 #define UNM_HW_I2Q_CRB_AGT_ADR 0x20 120 #define UNM_HW_LPC_CRB_AGT_ADR 0x22 121 #define UNM_HW_ROMUSB_CRB_AGT_ADR 0x21 122 #define UNM_HW_QM_CRB_AGT_ADR 0x66 123 #define UNM_HW_SQG0_CRB_AGT_ADR 0x60 124 #define UNM_HW_SQG1_CRB_AGT_ADR 0x61 125 #define UNM_HW_SQG2_CRB_AGT_ADR 0x62 126 #define UNM_HW_SQG3_CRB_AGT_ADR 0x63 127 #define UNM_HW_RPMX1_CRB_AGT_ADR 0x09 128 #define UNM_HW_RPMX5_CRB_AGT_ADR 0x0d 129 #define UNM_HW_RPMX6_CRB_AGT_ADR 0x0e 130 #define UNM_HW_RPMX8_CRB_AGT_ADR 0x11 131 132 /* Hub 3 */ 133 #define UNM_HW_PH_CRB_AGT_ADR 0x1A 134 #define UNM_HW_SRE_CRB_AGT_ADR 0x50 135 #define UNM_HW_EG_CRB_AGT_ADR 0x51 136 #define UNM_HW_RPMX0_CRB_AGT_ADR 0x08 137 138 /* Hub 4 */ 139 #define UNM_HW_PEGN0_CRB_AGT_ADR 0x40 140 #define UNM_HW_PEGN1_CRB_AGT_ADR 0x41 141 #define UNM_HW_PEGN2_CRB_AGT_ADR 0x42 142 #define UNM_HW_PEGN3_CRB_AGT_ADR 0x43 143 #define UNM_HW_PEGNI_CRB_AGT_ADR 0x44 144 #define UNM_HW_PEGND_CRB_AGT_ADR 0x45 145 #define UNM_HW_PEGNC_CRB_AGT_ADR 0x46 146 #define UNM_HW_PEGR0_CRB_AGT_ADR 0x47 147 #define UNM_HW_PEGR1_CRB_AGT_ADR 0x48 148 #define UNM_HW_PEGR2_CRB_AGT_ADR 0x49 149 #define UNM_HW_PEGR3_CRB_AGT_ADR 0x4a 150 #define UNM_HW_PEGN4_CRB_AGT_ADR 0x4b 151 152 /* Hub 5 */ 153 #define UNM_HW_PEGS0_CRB_AGT_ADR 0x40 154 #define UNM_HW_PEGS1_CRB_AGT_ADR 0x41 155 #define UNM_HW_PEGS2_CRB_AGT_ADR 0x42 156 #define UNM_HW_PEGS3_CRB_AGT_ADR 0x43 157 #define UNM_HW_PEGSI_CRB_AGT_ADR 0x44 158 #define UNM_HW_PEGSD_CRB_AGT_ADR 0x45 159 #define UNM_HW_PEGSC_CRB_AGT_ADR 0x46 160 161 /* Hub 6 */ 162 #define UNM_HW_CAS0_CRB_AGT_ADR 0x46 163 #define UNM_HW_CAS1_CRB_AGT_ADR 0x47 164 #define UNM_HW_CAS2_CRB_AGT_ADR 0x48 165 #define UNM_HW_CAS3_CRB_AGT_ADR 0x49 166 #define UNM_HW_NCM_CRB_AGT_ADR 0x16 167 #define UNM_HW_TMR_CRB_AGT_ADR 0x17 168 #define UNM_HW_XDMA_CRB_AGT_ADR 0x05 169 #define UNM_HW_OCM0_CRB_AGT_ADR 0x06 170 #define UNM_HW_OCM1_CRB_AGT_ADR 0x07 171 172 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 173 /* */ 174 #define UNM_HW_PX_MAP_CRB_PH 0 175 #define UNM_HW_PX_MAP_CRB_PS 1 176 #define UNM_HW_PX_MAP_CRB_MN 2 177 #define UNM_HW_PX_MAP_CRB_MS 3 178 #define UNM_HW_PX_MAP_CRB_SRE 5 179 #define UNM_HW_PX_MAP_CRB_NIU 6 180 #define UNM_HW_PX_MAP_CRB_QMN 7 181 #define UNM_HW_PX_MAP_CRB_SQN0 8 182 #define UNM_HW_PX_MAP_CRB_SQN1 9 183 #define UNM_HW_PX_MAP_CRB_SQN2 10 184 #define UNM_HW_PX_MAP_CRB_SQN3 11 185 #define UNM_HW_PX_MAP_CRB_QMS 12 186 #define UNM_HW_PX_MAP_CRB_SQS0 13 187 #define UNM_HW_PX_MAP_CRB_SQS1 14 188 #define UNM_HW_PX_MAP_CRB_SQS2 15 189 #define UNM_HW_PX_MAP_CRB_SQS3 16 190 #define UNM_HW_PX_MAP_CRB_PGN0 17 191 #define UNM_HW_PX_MAP_CRB_PGN1 18 192 #define UNM_HW_PX_MAP_CRB_PGN2 19 193 #define UNM_HW_PX_MAP_CRB_PGN3 20 194 #define UNM_HW_PX_MAP_CRB_PGND 21 195 #define UNM_HW_PX_MAP_CRB_PGNI 22 196 #define UNM_HW_PX_MAP_CRB_PGS0 23 197 #define UNM_HW_PX_MAP_CRB_PGS1 24 198 #define UNM_HW_PX_MAP_CRB_PGS2 25 199 #define UNM_HW_PX_MAP_CRB_PGS3 26 200 #define UNM_HW_PX_MAP_CRB_PGSD 27 201 #define UNM_HW_PX_MAP_CRB_PGSI 28 202 #define UNM_HW_PX_MAP_CRB_SN 29 203 #define UNM_HW_PX_MAP_CRB_EG 31 204 #define UNM_HW_PX_MAP_CRB_PH2 32 205 #define UNM_HW_PX_MAP_CRB_PS2 33 206 #define UNM_HW_PX_MAP_CRB_CAM 34 207 #define UNM_HW_PX_MAP_CRB_CAS0 35 208 #define UNM_HW_PX_MAP_CRB_CAS1 36 209 #define UNM_HW_PX_MAP_CRB_CAS2 37 210 #define UNM_HW_PX_MAP_CRB_C2C0 38 211 #define UNM_HW_PX_MAP_CRB_C2C1 39 212 #define UNM_HW_PX_MAP_CRB_TIMR 40 213 /* N/A: Not use in either Phantom1 or Phantom2 => use for TIMR */ 214 /* #define PX_MAP_CRB_C2C2 40 */ 215 /* #define PX_MAP_CRB_SS 41 */ 216 #define UNM_HW_PX_MAP_CRB_RPMX1 42 217 #define UNM_HW_PX_MAP_CRB_RPMX2 43 218 #define UNM_HW_PX_MAP_CRB_RPMX3 44 219 #define UNM_HW_PX_MAP_CRB_RPMX4 45 220 #define UNM_HW_PX_MAP_CRB_RPMX5 46 221 #define UNM_HW_PX_MAP_CRB_RPMX6 47 222 #define UNM_HW_PX_MAP_CRB_RPMX7 48 223 #define UNM_HW_PX_MAP_CRB_XDMA 49 224 #define UNM_HW_PX_MAP_CRB_I2Q 50 225 #define UNM_HW_PX_MAP_CRB_ROMUSB 51 226 #define UNM_HW_PX_MAP_CRB_CAS3 52 227 #define UNM_HW_PX_MAP_CRB_RPMX0 53 228 #define UNM_HW_PX_MAP_CRB_RPMX8 54 229 #define UNM_HW_PX_MAP_CRB_RPMX9 55 230 #define UNM_HW_PX_MAP_CRB_OCM0 56 231 #define UNM_HW_PX_MAP_CRB_OCM1 57 232 #define UNM_HW_PX_MAP_CRB_SMB 58 233 #define UNM_HW_PX_MAP_CRB_I2C0 59 234 #define UNM_HW_PX_MAP_CRB_I2C1 60 235 #define UNM_HW_PX_MAP_CRB_LPC 61 236 #define UNM_HW_PX_MAP_CRB_PGNC 62 237 #define UNM_HW_PX_MAP_CRB_PGR0 63 238 #define UNM_HW_PX_MAP_CRB_PGR1 4 239 #define UNM_HW_PX_MAP_CRB_PGR2 30 240 #define UNM_HW_PX_MAP_CRB_PGR3 41 241 242 /* This field defines CRB adr [31:20] of the agents */ 243 /* */ 244 245 #define UNM_HW_CRB_HUB_AGT_ADR_MN ((UNM_HW_H0_CH_HUB_ADR << 7) \ 246 | UNM_HW_MN_CRB_AGT_ADR) 247 #define UNM_HW_CRB_HUB_AGT_ADR_PH ((UNM_HW_H0_CH_HUB_ADR << 7) \ 248 | UNM_HW_PH_CRB_AGT_ADR) 249 #define UNM_HW_CRB_HUB_AGT_ADR_MS ((UNM_HW_H0_CH_HUB_ADR << 7) \ 250 | UNM_HW_MS_CRB_AGT_ADR) 251 252 #define UNM_HW_CRB_HUB_AGT_ADR_PS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 253 | UNM_HW_PS_CRB_AGT_ADR) 254 #define UNM_HW_CRB_HUB_AGT_ADR_SS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 255 | UNM_HW_SS_CRB_AGT_ADR) 256 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX3 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 257 | UNM_HW_RPMX3_CRB_AGT_ADR) 258 #define UNM_HW_CRB_HUB_AGT_ADR_QMS ((UNM_HW_H1_CH_HUB_ADR << 7) \ 259 | UNM_HW_QMS_CRB_AGT_ADR) 260 #define UNM_HW_CRB_HUB_AGT_ADR_SQS0 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 261 | UNM_HW_SQGS0_CRB_AGT_ADR) 262 #define UNM_HW_CRB_HUB_AGT_ADR_SQS1 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 263 | UNM_HW_SQGS1_CRB_AGT_ADR) 264 #define UNM_HW_CRB_HUB_AGT_ADR_SQS2 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 265 | UNM_HW_SQGS2_CRB_AGT_ADR) 266 #define UNM_HW_CRB_HUB_AGT_ADR_SQS3 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 267 | UNM_HW_SQGS3_CRB_AGT_ADR) 268 #define UNM_HW_CRB_HUB_AGT_ADR_C2C0 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 269 | UNM_HW_C2C0_CRB_AGT_ADR) 270 #define UNM_HW_CRB_HUB_AGT_ADR_C2C1 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 271 | UNM_HW_C2C1_CRB_AGT_ADR) 272 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX2 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 273 | UNM_HW_RPMX2_CRB_AGT_ADR) 274 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX4 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 275 | UNM_HW_RPMX4_CRB_AGT_ADR) 276 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX7 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 277 | UNM_HW_RPMX7_CRB_AGT_ADR) 278 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX9 ((UNM_HW_H1_CH_HUB_ADR << 7) \ 279 | UNM_HW_RPMX9_CRB_AGT_ADR) 280 #define UNM_HW_CRB_HUB_AGT_ADR_SMB ((UNM_HW_H1_CH_HUB_ADR << 7) \ 281 | UNM_HW_SMB_CRB_AGT_ADR) 282 283 #define UNM_HW_CRB_HUB_AGT_ADR_NIU ((UNM_HW_H2_CH_HUB_ADR << 7) \ 284 | UNM_HW_NIU_CRB_AGT_ADR) 285 #define UNM_HW_CRB_HUB_AGT_ADR_I2C0 ((UNM_HW_H2_CH_HUB_ADR << 7) \ 286 | UNM_HW_I2C0_CRB_AGT_ADR) 287 #define UNM_HW_CRB_HUB_AGT_ADR_I2C1 ((UNM_HW_H2_CH_HUB_ADR << 7) \ 288 | UNM_HW_I2C1_CRB_AGT_ADR) 289 290 #define UNM_HW_CRB_HUB_AGT_ADR_SRE ((UNM_HW_H3_CH_HUB_ADR << 7) \ 291 | UNM_HW_SRE_CRB_AGT_ADR) 292 #define UNM_HW_CRB_HUB_AGT_ADR_EG ((UNM_HW_H3_CH_HUB_ADR << 7) \ 293 | UNM_HW_EG_CRB_AGT_ADR) 294 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 295 | UNM_HW_RPMX0_CRB_AGT_ADR) 296 #define UNM_HW_CRB_HUB_AGT_ADR_QMN ((UNM_HW_H3_CH_HUB_ADR << 7) \ 297 | UNM_HW_QM_CRB_AGT_ADR) 298 #define UNM_HW_CRB_HUB_AGT_ADR_SQN0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 299 | UNM_HW_SQG0_CRB_AGT_ADR) 300 #define UNM_HW_CRB_HUB_AGT_ADR_SQN1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 301 | UNM_HW_SQG1_CRB_AGT_ADR) 302 #define UNM_HW_CRB_HUB_AGT_ADR_SQN2 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 303 | UNM_HW_SQG2_CRB_AGT_ADR) 304 #define UNM_HW_CRB_HUB_AGT_ADR_SQN3 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 305 | UNM_HW_SQG3_CRB_AGT_ADR) 306 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 307 | UNM_HW_RPMX1_CRB_AGT_ADR) 308 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX5 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 309 | UNM_HW_RPMX5_CRB_AGT_ADR) 310 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX6 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 311 | UNM_HW_RPMX6_CRB_AGT_ADR) 312 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX8 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 313 | UNM_HW_RPMX8_CRB_AGT_ADR) 314 #define UNM_HW_CRB_HUB_AGT_ADR_CAS0 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 315 | UNM_HW_CAS0_CRB_AGT_ADR) 316 #define UNM_HW_CRB_HUB_AGT_ADR_CAS1 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 317 | UNM_HW_CAS1_CRB_AGT_ADR) 318 #define UNM_HW_CRB_HUB_AGT_ADR_CAS2 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 319 | UNM_HW_CAS2_CRB_AGT_ADR) 320 #define UNM_HW_CRB_HUB_AGT_ADR_CAS3 ((UNM_HW_H3_CH_HUB_ADR << 7) \ 321 | UNM_HW_CAS3_CRB_AGT_ADR) 322 323 #define UNM_HW_CRB_HUB_AGT_ADR_PGNI ((UNM_HW_H4_CH_HUB_ADR << 7) \ 324 | UNM_HW_PEGNI_CRB_AGT_ADR) 325 #define UNM_HW_CRB_HUB_AGT_ADR_PGND ((UNM_HW_H4_CH_HUB_ADR << 7) \ 326 | UNM_HW_PEGND_CRB_AGT_ADR) 327 #define UNM_HW_CRB_HUB_AGT_ADR_PGN0 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 328 | UNM_HW_PEGN0_CRB_AGT_ADR) 329 #define UNM_HW_CRB_HUB_AGT_ADR_PGN1 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 330 | UNM_HW_PEGN1_CRB_AGT_ADR) 331 #define UNM_HW_CRB_HUB_AGT_ADR_PGN2 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 332 | UNM_HW_PEGN2_CRB_AGT_ADR) 333 #define UNM_HW_CRB_HUB_AGT_ADR_PGN3 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 334 | UNM_HW_PEGN3_CRB_AGT_ADR) 335 #define UNM_HW_CRB_HUB_AGT_ADR_PGN4 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 336 | UNM_HW_PEGN4_CRB_AGT_ADR) 337 338 #define UNM_HW_CRB_HUB_AGT_ADR_PGNC ((UNM_HW_H4_CH_HUB_ADR << 7) \ 339 | UNM_HW_PEGNC_CRB_AGT_ADR) 340 #define UNM_HW_CRB_HUB_AGT_ADR_PGR0 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 341 | UNM_HW_PEGR0_CRB_AGT_ADR) 342 #define UNM_HW_CRB_HUB_AGT_ADR_PGR1 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 343 | UNM_HW_PEGR1_CRB_AGT_ADR) 344 #define UNM_HW_CRB_HUB_AGT_ADR_PGR2 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 345 | UNM_HW_PEGR2_CRB_AGT_ADR) 346 #define UNM_HW_CRB_HUB_AGT_ADR_PGR3 ((UNM_HW_H4_CH_HUB_ADR << 7) \ 347 | UNM_HW_PEGR3_CRB_AGT_ADR) 348 349 #define UNM_HW_CRB_HUB_AGT_ADR_PGSI ((UNM_HW_H5_CH_HUB_ADR << 7) \ 350 | UNM_HW_PEGSI_CRB_AGT_ADR) 351 #define UNM_HW_CRB_HUB_AGT_ADR_PGSD ((UNM_HW_H5_CH_HUB_ADR << 7) \ 352 | UNM_HW_PEGSD_CRB_AGT_ADR) 353 #define UNM_HW_CRB_HUB_AGT_ADR_PGS0 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 354 | UNM_HW_PEGS0_CRB_AGT_ADR) 355 #define UNM_HW_CRB_HUB_AGT_ADR_PGS1 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 356 | UNM_HW_PEGS1_CRB_AGT_ADR) 357 #define UNM_HW_CRB_HUB_AGT_ADR_PGS2 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 358 | UNM_HW_PEGS2_CRB_AGT_ADR) 359 #define UNM_HW_CRB_HUB_AGT_ADR_PGS3 ((UNM_HW_H5_CH_HUB_ADR << 7) \ 360 | UNM_HW_PEGS3_CRB_AGT_ADR) 361 #define UNM_HW_CRB_HUB_AGT_ADR_PGSC ((UNM_HW_H5_CH_HUB_ADR << 7) \ 362 | UNM_HW_PEGSC_CRB_AGT_ADR) 363 364 #define UNM_HW_CRB_HUB_AGT_ADR_CAM ((UNM_HW_H6_CH_HUB_ADR << 7) \ 365 | UNM_HW_NCM_CRB_AGT_ADR) 366 #define UNM_HW_CRB_HUB_AGT_ADR_TIMR ((UNM_HW_H6_CH_HUB_ADR << 7) \ 367 | UNM_HW_TMR_CRB_AGT_ADR) 368 #define UNM_HW_CRB_HUB_AGT_ADR_XDMA ((UNM_HW_H6_CH_HUB_ADR << 7) \ 369 | UNM_HW_XDMA_CRB_AGT_ADR) 370 #define UNM_HW_CRB_HUB_AGT_ADR_SN ((UNM_HW_H6_CH_HUB_ADR << 7) \ 371 | UNM_HW_SN_CRB_AGT_ADR) 372 #define UNM_HW_CRB_HUB_AGT_ADR_I2Q ((UNM_HW_H6_CH_HUB_ADR << 7) \ 373 | UNM_HW_I2Q_CRB_AGT_ADR) 374 #define UNM_HW_CRB_HUB_AGT_ADR_ROMUSB ((UNM_HW_H6_CH_HUB_ADR << 7) \ 375 | UNM_HW_ROMUSB_CRB_AGT_ADR) 376 #define UNM_HW_CRB_HUB_AGT_ADR_OCM0 ((UNM_HW_H6_CH_HUB_ADR << 7) \ 377 | UNM_HW_OCM0_CRB_AGT_ADR) 378 #define UNM_HW_CRB_HUB_AGT_ADR_OCM1 ((UNM_HW_H6_CH_HUB_ADR << 7) \ 379 | UNM_HW_OCM1_CRB_AGT_ADR) 380 #define UNM_HW_CRB_HUB_AGT_ADR_LPC ((UNM_HW_H6_CH_HUB_ADR << 7) \ 381 | UNM_HW_LPC_CRB_AGT_ADR) 382 383 /* 384 * ROM USB CRB space is divided into 4 regions depending on decode of 385 * address bits [19:16] 386 */ 387 #define ROMUSB_GLB (UNM_CRB_ROMUSB + 0x00000) 388 #define ROMUSB_ROM (UNM_CRB_ROMUSB + 0x10000) 389 #define ROMUSB_USB (UNM_CRB_ROMUSB + 0x20000) 390 #define ROMUSB_DIRECT_ROM (UNM_CRB_ROMUSB + 0x30000) 391 #define ROMUSB_TAP (UNM_CRB_ROMUSB + 0x40000) 392 393 /* ROMUSB GLB register definitions */ 394 #define UNM_ROMUSB_GLB_CONTROL (ROMUSB_GLB + 0x0000) 395 #define UNM_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 396 #define UNM_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 397 #define UNM_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) 398 #define UNM_ROMUSB_GLB_RNG_PLL_CTL (ROMUSB_GLB + 0x0010) 399 #define UNM_ROMUSB_GLB_TEST_MUX_O (ROMUSB_GLB + 0x0014) 400 #define UNM_ROMUSB_GLB_PLL0_CTRL (ROMUSB_GLB + 0x0018) 401 #define UNM_ROMUSB_GLB_PLL1_CTRL (ROMUSB_GLB + 0x001c) 402 #define UNM_ROMUSB_GLB_PLL2_CTRL (ROMUSB_GLB + 0x0020) 403 #define UNM_ROMUSB_GLB_PLL3_CTRL (ROMUSB_GLB + 0x0024) 404 #define UNM_ROMUSB_GLB_PLL_LOCK (ROMUSB_GLB + 0x0028) 405 #define UNM_ROMUSB_GLB_EXTERN_INT (ROMUSB_GLB + 0x002c) 406 #define UNM_ROMUSB_GLB_PH_RST (ROMUSB_GLB + 0x0030) 407 #define UNM_ROMUSB_GLB_PS_RST (ROMUSB_GLB + 0x0034) 408 #define UNM_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 409 #define UNM_ROMUSB_GLB_MIU_RST (ROMUSB_GLB + 0x003c) 410 #define UNM_ROMUSB_GLB_CRB_RST (ROMUSB_GLB + 0x0040) 411 #define UNM_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) 412 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050) 413 #define UNM_ROMUSB_GLB_REV_ID (ROMUSB_GLB + 0x0054) 414 #define UNM_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 415 #define UNM_ROMUSB_GLB_VENDOR_DEV_ID (ROMUSB_GLB + 0x0058) 416 #define UNM_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00a8) 417 418 #define UNM_ROMUSB_GPIO(n) ((n) <= 15 ? (ROMUSB_GLB + 0x60 + (4 * (n))): \ 419 ((n) <= 18)?(ROMUSB_GLB + 0x70 + (4 * (n))): \ 420 (ROMUSB_GLB + 0x70 + (4 * (19)))) 421 422 #define UNM_ROMUSB_ROM_CONTROL (ROMUSB_ROM + 0x0000) 423 #define UNM_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 424 #define UNM_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 425 #define UNM_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 426 #define UNM_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 427 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 428 #define UNM_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 429 #define UNM_ROMUSB_ROM_AGT_TAG (ROMUSB_ROM + 0x001c) 430 #define UNM_ROMUSB_ROM_TIME_PARM (ROMUSB_ROM + 0x0020) 431 #define UNM_ROMUSB_ROM_CLK_DIV (ROMUSB_ROM + 0x0024) 432 #define UNM_ROMUSB_ROM_MISS_INSTR (ROMUSB_ROM + 0x0028) 433 434 /* Lock IDs for ROM lock */ 435 #define ROM_LOCK_DRIVER 0x0d417340 436 437 /* Lock IDs for PHY lock */ 438 #define PHY_LOCK_DRIVER 0x44524956 439 440 #define UNM_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 441 #define UNM_PCI_CRB_WINDOW(A) (UNM_PCI_CRBSPACE + (A)*UNM_PCI_CRB_WINDOWSIZE) 442 #define UNM_CRB_C2C_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C0) 443 #define UNM_CRB_C2C_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C1) 444 #define UNM_CRB_C2C_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C2) 445 #define UNM_CRB_CAM UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAM) 446 #define UNM_CRB_CASPER UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS) 447 #define UNM_CRB_CASPER_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS0) 448 #define UNM_CRB_CASPER_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS1) 449 #define UNM_CRB_CASPER_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS2) 450 #define UNM_CRB_DDR_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MS) 451 #define UNM_CRB_DDR_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN) 452 #define UNM_CRB_EPG UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_EG) 453 #define UNM_CRB_I2Q UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2Q) 454 #define UNM_CRB_NIU UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_NIU) 455 /* HACK upon HACK upon HACK (for PCIE builds) */ 456 #define UNM_CRB_PCIX_HOST UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH) 457 #define UNM_CRB_PCIX_HOST2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH2) 458 #define UNM_CRB_PCIX_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS) 459 #define UNM_CRB_PCIE UNM_CRB_PCIX_MD 460 // window 1 pcie slot 461 #define UNM_CRB_PCIE2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS2) 462 463 #define UNM_CRB_PEG_MD_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS0) 464 #define UNM_CRB_PEG_MD_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS1) 465 #define UNM_CRB_PEG_MD_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS2) 466 #define UNM_CRB_PEG_MD_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3) 467 #define UNM_CRB_PEG_MD_D UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSD) 468 #define UNM_CRB_PEG_MD_I UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSI) 469 #define UNM_CRB_PEG_NET_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN0) 470 #define UNM_CRB_PEG_NET_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN1) 471 #define UNM_CRB_PEG_NET_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN2) 472 #define UNM_CRB_PEG_NET_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN3) 473 #define UNM_CRB_PEG_NET_D UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGND) 474 #define UNM_CRB_PEG_NET_I UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGNI) 475 #define UNM_CRB_PQM_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMS) 476 #define UNM_CRB_PQM_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMN) 477 #define UNM_CRB_QDR_MD UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SS) 478 #define UNM_CRB_QDR_NET UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SN) 479 #define UNM_CRB_ROMUSB UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_ROMUSB) 480 #define UNM_CRB_RPMX_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX0) 481 #define UNM_CRB_RPMX_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX1) 482 #define UNM_CRB_RPMX_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX2) 483 #define UNM_CRB_RPMX_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX3) 484 #define UNM_CRB_RPMX_4 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX4) 485 #define UNM_CRB_RPMX_5 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX5) 486 #define UNM_CRB_RPMX_6 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX6) 487 #define UNM_CRB_RPMX_7 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX7) 488 #define UNM_CRB_SQM_MD_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS0) 489 #define UNM_CRB_SQM_MD_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS1) 490 #define UNM_CRB_SQM_MD_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS2) 491 #define UNM_CRB_SQM_MD_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS3) 492 #define UNM_CRB_SQM_NET_0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN0) 493 #define UNM_CRB_SQM_NET_1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN1) 494 #define UNM_CRB_SQM_NET_2 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN2) 495 #define UNM_CRB_SQM_NET_3 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN3) 496 #define UNM_CRB_SRE UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SRE) 497 #define UNM_CRB_TIMER UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_TIMR) 498 #define UNM_CRB_XDMA UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_XDMA) 499 #define UNM_CRB_I2C0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C0) 500 #define UNM_CRB_I2C1 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C1) 501 #define UNM_CRB_OCM0 UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_OCM0) 502 #define UNM_CRB_SMB UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SMB) 503 504 #define UNM_CRB_MAX UNM_PCI_CRB_WINDOW(64) 505 506 /* 507 * ====================== BASE ADDRESSES ON-CHIP ====================== 508 * Base addresses of major components on-chip. 509 * ====================== BASE ADDRESSES ON-CHIP ====================== 510 */ 511 #define UNM_ADDR_DDR_NET (0x0000000000000000ULL) 512 #define UNM_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 513 514 /* 515 * Imbus address bit used to indicate a host address. This bit is 516 * eliminated by the pcie bar and bar select before presentation 517 * over pcie. 518 */ 519 /* host memory via IMBUS */ 520 #define NX_P2_ADDR_PCIE (0x0000000800000000ULL) 521 #define NX_P3_ADDR_PCIE (0x0000008000000000ULL) 522 523 #define UNM_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 524 #define UNM_ADDR_OCM0 (0x0000000200000000ULL) 525 #define UNM_ADDR_OCM0_MAX (0x00000002000fffffULL) 526 #define UNM_ADDR_OCM1 (0x0000000200400000ULL) 527 #define UNM_ADDR_OCM1_MAX (0x00000002004fffffULL) 528 #define UNM_ADDR_QDR_NET (0x0000000300000000ULL) 529 530 #define NX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 531 #define NX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 532 /* 533 * The ifdef at the bottom should go. All drivers should start using the 534 * above 2 defines. 535 */ 536 #ifdef P3 537 #define UNM_ADDR_QDR_NET_MAX NX_P3_ADDR_QDR_NET_MAX 538 #else 539 #define UNM_ADDR_QDR_NET_MAX NX_P2_ADDR_QDR_NET_MAX 540 #endif 541 542 #define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084)) 543 #define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084)) 544 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084)) 545 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084)) 546 547 548 #define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO)) 549 #define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI)) 550 #define UNM_PCI_ARCH_CRB_BASE (UNM_PCI_DIRECT_CRB) 551 552 /* we're mapping 128MB of mem on the PCI bus */ 553 #define UNM_PCI_MAPSIZE 128 554 #define UNM_PCI_DDR_NET (unsigned long)0x00000000 555 #define UNM_PCI_DDR_NET_MAX (unsigned long)0x01ffffff 556 #define UNM_PCI_DDR_MD (unsigned long)0x02000000 557 #define UNM_PCI_DDR_MD_MAX (unsigned long)0x03ffffff 558 #define UNM_PCI_QDR_NET (unsigned long)0x04000000 559 #define UNM_PCI_QDR_NET_MAX (unsigned long)0x043fffff 560 #define UNM_PCI_DIRECT_CRB (unsigned long)0x04400000 561 #define UNM_PCI_DIRECT_CRB_MAX (unsigned long)0x047fffff 562 #define UNM_PCI_CAMQM (unsigned long)0x04800000 563 #define UNM_PCI_CAMQM_MAX (unsigned long)0x04ffffff 564 #define UNM_PCI_OCM0 (unsigned long)0x05000000 565 #define UNM_PCI_OCM0_MAX (unsigned long)0x050fffff 566 #define UNM_PCI_OCM1 (unsigned long)0x05100000 567 #define UNM_PCI_OCM1_MAX (unsigned long)0x051fffff 568 #define UNM_PCI_CRBSPACE (unsigned long)0x06000000 569 #define UNM_PCI_CRBSPACE_MAX (unsigned long)0x07ffffff 570 #define UNM_PCI_128MB_SIZE (unsigned long)0x08000000 571 #define UNM_PCI_32MB_SIZE (unsigned long)0x02000000 572 #define UNM_PCI_2MB_SIZE (unsigned long)0x00200000 573 574 /* 575 * The basic unit of access when reading/writing control registers. 576 */ 577 typedef long native_t; /* most efficient integer on h/w */ 578 typedef __uint64_t unm_dataword_t; /* single word in data space */ 579 typedef __uint64_t unm64ptr_t; /* a pointer that occupies 64 bits */ 580 #define UNM64PTR(P) ((unm64ptr_t)((native_t)(P))) /* convert for us */ 581 582 typedef __uint32_t unm_crbword_t; /* single word in CRB space */ 583 584 /* 585 * Definitions relating to access/control of the Network Interface Unit 586 * h/w block. 587 */ 588 /* 589 * Configuration registers. 590 */ 591 #define UNM_NIU_MODE (UNM_CRB_NIU + 0x00000) 592 593 #define UNM_NIU_XG_SINGLE_TERM (UNM_CRB_NIU + 0x00004) 594 #define UNM_NIU_XG_DRIVE_HI (UNM_CRB_NIU + 0x00008) 595 #define UNM_NIU_XG_DRIVE_LO (UNM_CRB_NIU + 0x0000c) 596 #define UNM_NIU_XG_DTX (UNM_CRB_NIU + 0x00010) 597 #define UNM_NIU_XG_DEQ (UNM_CRB_NIU + 0x00014) 598 #define UNM_NIU_XG_WORD_ALIGN (UNM_CRB_NIU + 0x00018) 599 #define UNM_NIU_XG_RESET (UNM_CRB_NIU + 0x0001c) 600 #define UNM_NIU_XG_POWER_DOWN (UNM_CRB_NIU + 0x00020) 601 #define UNM_NIU_XG_RESET_PLL (UNM_CRB_NIU + 0x00024) 602 #define UNM_NIU_XG_SERDES_LOOPBACK (UNM_CRB_NIU + 0x00028) 603 #define UNM_NIU_XG_DO_BYTE_ALIGN (UNM_CRB_NIU + 0x0002c) 604 #define UNM_NIU_XG_TX_ENABLE (UNM_CRB_NIU + 0x00030) 605 #define UNM_NIU_XG_RX_ENABLE (UNM_CRB_NIU + 0x00034) 606 #define UNM_NIU_XG_STATUS (UNM_CRB_NIU + 0x00038) 607 #define UNM_NIU_XG_PAUSE_THRESHOLD (UNM_CRB_NIU + 0x0003c) 608 #define UNM_NIU_INT_MASK (UNM_CRB_NIU + 0x00040) 609 #define UNM_NIU_ACTIVE_INT (UNM_CRB_NIU + 0x00044) 610 #define UNM_NIU_MASKABLE_INT (UNM_CRB_NIU + 0x00048) 611 #define UNM_NIU_TEST_MUX_CTL (UNM_CRB_NIU + 0x00094) 612 #define UNM_NIU_XG_PAUSE_CTL (UNM_CRB_NIU + 0x00098) 613 #define UNM_NIU_XG_PAUSE_LEVEL (UNM_CRB_NIU + 0x000dc) 614 #define UNM_NIU_XG_SEL (UNM_CRB_NIU + 0x00128) 615 #define UNM_NIU_GB_PAUSE_CTL (UNM_CRB_NIU + 0x0030c) 616 #define UNM_NIU_FULL_LEVEL_XG (UNM_CRB_NIU + 0x00450) 617 618 619 #define UNM_NIU_XG1_RESET (UNM_CRB_NIU + 0x0011c) 620 #define UNM_NIU_XG1_POWER_DOWN (UNM_CRB_NIU + 0x00120) 621 #define UNM_NIU_XG1_RESET_PLL (UNM_CRB_NIU + 0x00124) 622 623 #define UNM_NIU_STRAP_VALUE_SAVE_HIGHER (UNM_CRB_NIU + 0x0004c) 624 625 #define UNM_NIU_GB_SERDES_RESET (UNM_CRB_NIU + 0x00050) 626 #define UNM_NIU_GB0_GMII_MODE (UNM_CRB_NIU + 0x00054) 627 #define UNM_NIU_GB0_MII_MODE (UNM_CRB_NIU + 0x00058) 628 #define UNM_NIU_GB1_GMII_MODE (UNM_CRB_NIU + 0x0005c) 629 #define UNM_NIU_GB1_MII_MODE (UNM_CRB_NIU + 0x00060) 630 #define UNM_NIU_GB2_GMII_MODE (UNM_CRB_NIU + 0x00064) 631 #define UNM_NIU_GB2_MII_MODE (UNM_CRB_NIU + 0x00068) 632 #define UNM_NIU_GB3_GMII_MODE (UNM_CRB_NIU + 0x0006c) 633 #define UNM_NIU_GB3_MII_MODE (UNM_CRB_NIU + 0x00070) 634 #define UNM_NIU_REMOTE_LOOPBACK (UNM_CRB_NIU + 0x00074) 635 #define UNM_NIU_GB0_HALF_DUPLEX (UNM_CRB_NIU + 0x00078) 636 #define UNM_NIU_GB1_HALF_DUPLEX (UNM_CRB_NIU + 0x0007c) 637 #define UNM_NIU_GB2_HALF_DUPLEX (UNM_CRB_NIU + 0x00080) 638 #define UNM_NIU_GB3_HALF_DUPLEX (UNM_CRB_NIU + 0x00084) 639 #define UNM_NIU_RESET_SYS_FIFOS (UNM_CRB_NIU + 0x00088) 640 #define UNM_NIU_GB_CRC_DROP (UNM_CRB_NIU + 0x0008c) 641 #define UNM_NIU_GB_DROP_WRONGADDR (UNM_CRB_NIU + 0x00090) 642 #define UNM_NIU_TEST_MUX_CTL (UNM_CRB_NIU + 0x00094) 643 #define UNM_NIU_XG_PAUSE_CTL (UNM_CRB_NIU + 0x00098) 644 #define UNM_NIU_GB0_PAUSE_LEVEL (UNM_CRB_NIU + 0x000cc) 645 #define UNM_NIU_GB1_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d0) 646 #define UNM_NIU_GB2_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d4) 647 #define UNM_NIU_GB3_PAUSE_LEVEL (UNM_CRB_NIU + 0x000d8) 648 #define UNM_NIU_XG_PAUSE_LEVEL (UNM_CRB_NIU + 0x000dc) 649 #define UNM_NIU_FRAME_COUNT_SELECT (UNM_CRB_NIU + 0x000ac) 650 #define UNM_NIU_FRAME_COUNT (UNM_CRB_NIU + 0x000b0) 651 #define UNM_NIU_XG_SE (UNM_CRB_NIU + 0x00128) 652 #define UNM_NIU_FULL_LEVEL_XG (UNM_CRB_NIU + 0x00450) 653 654 #define UNM_NIU_FC_RX_STATUS(I) (UNM_CRB_NIU + 0x10000 + (I)*0x10000) 655 #define UNM_NIU_FC_RX_COMMA_DETECT(I) (UNM_CRB_NIU + 0x10004 + (I)*0x10000) 656 #define UNM_NIU_FC_LASER_UNSAFE(I) (UNM_CRB_NIU + 0x10008 + (I)*0x10000) 657 #define UNM_NIU_FC_TX_CONTROL(I) (UNM_CRB_NIU + 0x1000c + (I)*0x10000) 658 #define UNM_NIU_FC_ON_OFFLINE_CTL(I) (UNM_CRB_NIU + 0x10010 + (I)*0x10000) 659 #define UNM_NIU_FC_PORT_ACTIVE_STAT(I) (UNM_CRB_NIU + 0x10014 + (I)*0x10000) 660 #define UNM_NIU_FC_PORT_INACTIVE_STAT(I)(UNM_CRB_NIU + 0x10018 + (I)*0x10000) 661 #define UNM_NIU_FC_LINK_FAILURE_CNT(I) (UNM_CRB_NIU + 0x1001c + (I)*0x10000) 662 #define UNM_NIU_FC_LOSS_SYNC_CNT(I) (UNM_CRB_NIU + 0x10020 + (I)*0x10000) 663 #define UNM_NIU_FC_LOSS_SIGNAL_CNT(I) (UNM_CRB_NIU + 0x10024 + (I)*0x10000) 664 #define UNM_NIU_FC_PRIM_SEQ_ERR_CNT(I) (UNM_CRB_NIU + 0x10028 + (I)*0x10000) 665 #define UNM_NIU_FC_INVLD_TX_WORD_CNT(I) (UNM_CRB_NIU + 0x1002c + (I)*0x10000) 666 #define UNM_NIU_FC_INVLD_CRC_CNT(I) (UNM_CRB_NIU + 0x10030 + (I)*0x10000) 667 #define UNM_NIU_FC_RX_CELL_CNT(I) (UNM_CRB_NIU + 0x10034 + (I)*0x10000) 668 #define UNM_NIU_FC_TX_CELL_CNT(I) (UNM_CRB_NIU + 0x10038 + (I)*0x10000) 669 #define UNM_NIU_FC_B2B_CREDIT(I) (UNM_CRB_NIU + 0x1003c + (I)*0x10000) 670 #define UNM_NIU_FC_LOGIN_DONE(I) (UNM_CRB_NIU + 0x10040 + (I)*0x10000) 671 #define UNM_NIU_FC_OPERATING_SPEED(I) (UNM_CRB_NIU + 0x10044 + (I)*0x10000) 672 673 #define UNM_NIU_GB_MAC_CONFIG_0(I) (UNM_CRB_NIU + 0x30000 + (I)*0x10000) 674 #define UNM_NIU_GB_MAC_CONFIG_1(I) (UNM_CRB_NIU + 0x30004 + (I)*0x10000) 675 #define UNM_NIU_GB_MAC_IPG_IFG(I) (UNM_CRB_NIU + 0x30008 + (I)*0x10000) 676 #define UNM_NIU_GB_HALF_DUPLEX_CTRL(I) (UNM_CRB_NIU + 0x3000c + (I)*0x10000) 677 #define UNM_NIU_GB_MAX_FRAME_SIZE(I) (UNM_CRB_NIU + 0x30010 + (I)*0x10000) 678 #define UNM_NIU_GB_TEST_REG(I) (UNM_CRB_NIU + 0x3001c + (I)*0x10000) 679 #define UNM_NIU_GB_MII_MGMT_CONFIG(I) (UNM_CRB_NIU + 0x30020 + (I)*0x10000) 680 #define UNM_NIU_GB_MII_MGMT_COMMAND(I) (UNM_CRB_NIU + 0x30024 + (I)*0x10000) 681 #define UNM_NIU_GB_MII_MGMT_ADDR(I) (UNM_CRB_NIU + 0x30028 + (I)*0x10000) 682 #define UNM_NIU_GB_MII_MGMT_CTRL(I) (UNM_CRB_NIU + 0x3002c + (I)*0x10000) 683 #define UNM_NIU_GB_MII_MGMT_STATUS(I) (UNM_CRB_NIU + 0x30030 + (I)*0x10000) 684 #define UNM_NIU_GB_MII_MGMT_INDICATE(I) (UNM_CRB_NIU + 0x30034 + (I)*0x10000) 685 #define UNM_NIU_GB_INTERFACE_CTRL(I) (UNM_CRB_NIU + 0x30038 + (I)*0x10000) 686 #define UNM_NIU_GB_INTERFACE_STATUS(I) (UNM_CRB_NIU + 0x3003c + (I)*0x10000) 687 #define UNM_NIU_GB_STATION_ADDR_0(I) (UNM_CRB_NIU + 0x30040 + (I)*0x10000) 688 #define UNM_NIU_GB_STATION_ADDR_1(I) (UNM_CRB_NIU + 0x30044 + (I)*0x10000) 689 690 #define UNM_NIU_XGE_CONFIG_0 (UNM_CRB_NIU + 0x70000) 691 #define UNM_NIU_XGE_CONFIG_1 (UNM_CRB_NIU + 0x70004) 692 #define UNM_NIU_XGE_IPG (UNM_CRB_NIU + 0x70008) 693 #define UNM_NIU_XGE_STATION_ADDR_0_HI (UNM_CRB_NIU + 0x7000c) 694 #define UNM_NIU_XGE_STATION_ADDR_0_1 (UNM_CRB_NIU + 0x70010) 695 #define UNM_NIU_XGE_STATION_ADDR_1_LO (UNM_CRB_NIU + 0x70014) 696 #define UNM_NIU_XGE_STATUS (UNM_CRB_NIU + 0x70018) 697 #define UNM_NIU_XGE_MAX_FRAME_SIZE (UNM_CRB_NIU + 0x7001c) 698 #define UNM_NIU_XGE_PAUSE_FRAME_VALUE (UNM_CRB_NIU + 0x70020) 699 #define UNM_NIU_XGE_TX_BYTE_CNT (UNM_CRB_NIU + 0x70024) 700 #define UNM_NIU_XGE_TX_FRAME_CNT (UNM_CRB_NIU + 0x70028) 701 #define UNM_NIU_XGE_RX_BYTE_CNT (UNM_CRB_NIU + 0x7002c) 702 #define UNM_NIU_XGE_RX_FRAME_CNT (UNM_CRB_NIU + 0x70030) 703 #define UNM_NIU_XGE_AGGR_ERROR_CNT (UNM_CRB_NIU + 0x70034) 704 #define UNM_NIU_XGE_MULTICAST_FRAME_CNT (UNM_CRB_NIU + 0x70038) 705 #define UNM_NIU_XGE_UNICAST_FRAME_CNT (UNM_CRB_NIU + 0x7003c) 706 #define UNM_NIU_XGE_CRC_ERROR_CNT (UNM_CRB_NIU + 0x70040) 707 #define UNM_NIU_XGE_OVERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x70044) 708 #define UNM_NIU_XGE_UNDERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x70048) 709 #define UNM_NIU_XGE_LOCAL_ERROR_CNT (UNM_CRB_NIU + 0x7004c) 710 #define UNM_NIU_XGE_REMOTE_ERROR_CNT (UNM_CRB_NIU + 0x70050) 711 #define UNM_NIU_XGE_CONTROL_CHAR_CNT (UNM_CRB_NIU + 0x70054) 712 #define UNM_NIU_XGE_PAUSE_FRAME_CNT (UNM_CRB_NIU + 0x70058) 713 #define UNM_NIU_XG1_CONFIG_0 (UNM_CRB_NIU + 0x80000) 714 #define UNM_NIU_XG1_CONFIG_1 (UNM_CRB_NIU + 0x80004) 715 #define UNM_NIU_XG1_IPG (UNM_CRB_NIU + 0x80008) 716 #define UNM_NIU_XG1_STATION_ADDR_0_HI (UNM_CRB_NIU + 0x8000c) 717 #define UNM_NIU_XG1_STATION_ADDR_0_1 (UNM_CRB_NIU + 0x80010) 718 #define UNM_NIU_XG1_STATION_ADDR_1_LO (UNM_CRB_NIU + 0x80014) 719 #define UNM_NIU_XG1_STATUS (UNM_CRB_NIU + 0x80018) 720 #define UNM_NIU_XG1_MAX_FRAME_SIZE (UNM_CRB_NIU + 0x8001c) 721 #define UNM_NIU_XG1_PAUSE_FRAME_VALUE (UNM_CRB_NIU + 0x80020) 722 #define UNM_NIU_XG1_TX_BYTE_CNT (UNM_CRB_NIU + 0x80024) 723 #define UNM_NIU_XG1_TX_FRAME_CNT (UNM_CRB_NIU + 0x80028) 724 #define UNM_NIU_XG1_RX_BYTE_CNT (UNM_CRB_NIU + 0x8002c) 725 #define UNM_NIU_XG1_RX_FRAME_CNT (UNM_CRB_NIU + 0x80030) 726 #define UNM_NIU_XG1_AGGR_ERROR_CNT (UNM_CRB_NIU + 0x80034) 727 #define UNM_NIU_XG1_MULTICAST_FRAME_CNT (UNM_CRB_NIU + 0x80038) 728 #define UNM_NIU_XG1_UNICAST_FRAME_CNT (UNM_CRB_NIU + 0x8003c) 729 #define UNM_NIU_XG1_CRC_ERROR_CNT (UNM_CRB_NIU + 0x80040) 730 #define UNM_NIU_XG1_OVERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x80044) 731 #define UNM_NIU_XG1_UNDERSIZE_FRAME_ERR (UNM_CRB_NIU + 0x80048) 732 #define UNM_NIU_XG1_LOCAL_ERROR_CNT (UNM_CRB_NIU + 0x8004c) 733 #define UNM_NIU_XG1_REMOTE_ERROR_CNT (UNM_CRB_NIU + 0x80050) 734 #define UNM_NIU_XG1_CONTROL_CHAR_CNT (UNM_CRB_NIU + 0x80054) 735 #define UNM_NIU_XG1_PAUSE_FRAME_CNT (UNM_CRB_NIU + 0x80058) 736 737 #define UNM_TIMER_GT_TICKCTL (UNM_CRB_TIMER + 0x00200) 738 #define UNM_TIMER_GLOBAL_TIMESTAMP_LO (UNM_CRB_TIMER + 0x00220) 739 #define UNM_TIMER_TIMESTAMP (UNM_CRB_TIMER + 0x00208) 740 741 #define UNM_PEXQ_REQ_HDR_LO (UNM_CRB_XDMA + 0x00110) 742 #define UNM_PEXQ_REQ_HDR_HI (UNM_CRB_XDMA + 0x00114) 743 744 /* P3 802.3ap */ 745 #define UNM_NIU_AP_MAC_CONFIG_0(I) (UNM_CRB_NIU + 0xa0000 + (I)*0x10000) 746 #define UNM_NIU_AP_MAC_CONFIG_1(I) (UNM_CRB_NIU + 0xa0004 + (I)*0x10000) 747 #define UNM_NIU_AP_MAC_IPG_IFG(I) (UNM_CRB_NIU + 0xa0008 + (I)*0x10000) 748 #define UNM_NIU_AP_HALF_DUPLEX_CTRL(I) (UNM_CRB_NIU + 0xa000c + (I)*0x10000) 749 #define UNM_NIU_AP_MAX_FRAME_SIZE(I) (UNM_CRB_NIU + 0xa0010 + (I)*0x10000) 750 #define UNM_NIU_AP_TEST_REG(I) (UNM_CRB_NIU + 0xa001c + (I)*0x10000) 751 #define UNM_NIU_AP_MII_MGMT_CONFIG(I) (UNM_CRB_NIU + 0xa0020 + (I)*0x10000) 752 #define UNM_NIU_AP_MII_MGMT_COMMAND(I) (UNM_CRB_NIU + 0xa0024 + (I)*0x10000) 753 #define UNM_NIU_AP_MII_MGMT_ADDR(I) (UNM_CRB_NIU + 0xa0028 + (I)*0x10000) 754 #define UNM_NIU_AP_MII_MGMT_CTRL(I) (UNM_CRB_NIU + 0xa002c + (I)*0x10000) 755 #define UNM_NIU_AP_MII_MGMT_STATUS(I) (UNM_CRB_NIU + 0xa0030 + (I)*0x10000) 756 #define UNM_NIU_AP_MII_MGMT_INDICATE(I) (UNM_CRB_NIU + 0xa0034 + (I)*0x10000) 757 #define UNM_NIU_AP_INTERFACE_CTRL(I) (UNM_CRB_NIU + 0xa0038 + (I)*0x10000) 758 #define UNM_NIU_AP_INTERFACE_STATUS(I) (UNM_CRB_NIU + 0xa003c + (I)*0x10000) 759 #define UNM_NIU_AP_STATION_ADDR_0(I) (UNM_CRB_NIU + 0xa0040 + (I)*0x10000) 760 #define UNM_NIU_AP_STATION_ADDR_1(I) (UNM_CRB_NIU + 0xa0044 + (I)*0x10000) 761 762 /* 763 * Register offsets for MN 764 */ 765 #define MIU_CONTROL (0x000) 766 #define MIU_TAG (0x004) 767 #define MIU_TEST_AGT_CTRL (0x090) 768 #define MIU_TEST_AGT_ADDR_LO (0x094) 769 #define MIU_TEST_AGT_ADDR_HI (0x098) 770 #define MIU_TEST_AGT_WRDATA_LO (0x0a0) 771 #define MIU_TEST_AGT_WRDATA_HI (0x0a4) 772 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 773 #define MIU_TEST_AGT_RDDATA_LO (0x0a8) 774 #define MIU_TEST_AGT_RDDATA_HI (0x0ac) 775 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 776 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 777 #define MIU_TEST_AGT_UPPER_ADDR(off) (0) 778 779 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 780 #define MIU_TA_CTL_START 1 781 #define MIU_TA_CTL_ENABLE 2 782 #define MIU_TA_CTL_WRITE 4 783 #define MIU_TA_CTL_BUSY 8 784 785 #define SIU_TEST_AGT_CTRL (0x060) 786 #define SIU_TEST_AGT_ADDR_LO (0x064) 787 #define SIU_TEST_AGT_ADDR_HI (0x078) 788 #define SIU_TEST_AGT_WRDATA_LO (0x068) 789 #define SIU_TEST_AGT_WRDATA_HI (0x06c) 790 #define SIU_TEST_AGT_WRDATA(i) (0x068+(4*(i))) 791 #define SIU_TEST_AGT_RDDATA_LO (0x070) 792 #define SIU_TEST_AGT_RDDATA_HI (0x074) 793 #define SIU_TEST_AGT_RDDATA(i) (0x070+(4*(i))) 794 795 #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 796 #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22) 797 798 /* XG Link status */ 799 #define XG_LINK_UP 0x10 800 801 802 /* ====================== Configuration Constants ======================== */ 803 #define UNM_NIU_PHY_WAITLEN 200000 /* 200ms delay in each loop */ 804 #define UNM_NIU_PHY_WAITMAX 50 /* 10 seconds before we give up */ 805 #define UNM_NIU_MAX_GBE_PORTS 4 806 #define UNM_NIU_MAX_XG_PORTS 2 807 808 typedef __uint8_t unm_ethernet_macaddr_t[6]; 809 810 #define MIN_CORE_CLK_SPEED 200 811 #define MAX_CORE_CLK_SPEED 400 812 #define ACCEPTABLE_CORE_CLK_RANGE(speed) \ 813 ((speed >= MIN_CORE_CLK_SPEED) && (speed <= MAX_CORE_CLK_SPEED)) 814 815 #define P2_TICKS_PER_SEC 2048 816 #define P2_MIN_TICKS_PER_SEC (P2_TICKS_PER_SEC-10) 817 #define P2_MAX_TICKS_PER_SEC (P2_TICKS_PER_SEC+10) 818 #define CHECK_TICKS_PER_SEC(ticks) \ 819 ((ticks >= P2_MIN_TICKS_PER_SEC) && (ticks <= P2_MAX_TICKS_PER_SEC)) 820 821 /* ============================= 1GbE =============================== */ 822 /* Nibble or Byte mode for phy interface (GbE mode only) */ 823 typedef enum { 824 UNM_NIU_10_100_MB = 0, 825 UNM_NIU_1000_MB 826 } unm_niu_gbe_ifmode_t; 827 828 /* Promiscous mode options (GbE mode only) */ 829 typedef enum { 830 UNM_NIU_PROMISCOUS_MODE = 0, 831 UNM_NIU_NON_PROMISCOUS_MODE 832 } unm_niu_prom_mode_t; 833 834 /* 835 * NIU GB Drop CRC Register 836 */ 837 typedef struct { 838 unm_crbword_t 839 drop_gb0:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 840 drop_gb1:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 841 drop_gb2:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 842 drop_gb3:1, /* 1:drop pkts with bad CRCs, 0:pass them on */ 843 rsvd:28; 844 } unm_niu_gb_drop_crc_t; 845 846 /* 847 * NIU GB GMII Mode Register (applies to GB0, GB1, GB2, GB3) 848 * To change the mode, turn off the existing mode, then turn on the new mode. 849 */ 850 typedef struct { 851 unm_crbword_t 852 gmiimode:1, /* 1:GMII mode, 0:xmit clk taken from SERDES */ 853 rsvd:29; 854 } unm_niu_gb_gmii_mode_t; 855 856 /* 857 * NIU GB MII Mode Register (applies to GB0, GB1, GB2, GB3) 858 * To change the mode, turn off the existing mode, then turn on the new mode. 859 */ 860 typedef struct { 861 unm_crbword_t 862 miimode:1, /* 1:MII mode, 0:xmit clk provided to SERDES */ 863 rsvd:29; 864 } unm_niu_gb_mii_mode_t; 865 866 /* 867 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) 868 */ 869 typedef struct { 870 unm_crbword_t 871 tx_enable:1, /* 1:enable frame xmit, 0:disable */ 872 tx_synched:1, /* R/O: xmit enable synched to xmit stream */ 873 rx_enable:1, /* 1:enable frame recv, 0:disable */ 874 rx_synched:1, /* R/O: recv enable synched to recv stream */ 875 tx_flowctl:1, /* 1:enable pause frame generation, 0:disable */ 876 rx_flowctl:1, /* 1:act on recv'd pause frames, 0:ignore */ 877 rsvd1:2, 878 loopback:1, /* 1:loop MAC xmits to MAC recvs, 0:normal */ 879 rsvd2:7, 880 tx_reset_pb:1, /* 1:reset frame xmit protocol blk, 0:no-op */ 881 rx_reset_pb:1, /* 1:reset frame recv protocol blk, 0:no-op */ 882 tx_reset_mac:1, /* 1:reset data/ctl multiplexer blk, 0:no-op */ 883 rx_reset_mac:1, /* 1:reset ctl frames & timers blk, 0:no-op */ 884 rsvd3:11, 885 soft_reset:1; /* 1:reset the MAC and the SERDES, 0:no-op */ 886 } unm_niu_gb_mac_config_0_t; 887 888 /* 889 * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3) 890 */ 891 typedef struct { 892 unm_crbword_t 893 duplex:1, /* 1:full duplex mode, 0:half duplex */ 894 crc_enable:1, /* 1:append CRC to xmit frames, 0:dont append */ 895 padshort:1, /* 1:pad short frames and add CRC, 0:dont pad */ 896 rsvd1:1, 897 checklength:1, /* 1:check framelen with actual, 0:dont check */ 898 hugeframes:1, /* 1:allow oversize xmit frames, 0:dont allow */ 899 rsvd2:2, 900 intfmode:2, /* 01:nibble (10/100), 10:byte (1000) */ 901 rsvd3:2, 902 preamblelen:4, /* preamble field length in bytes, default 7 */ 903 rsvd4:16; 904 } unm_niu_gb_mac_config_1_t; 905 906 /* 907 * NIU XG Pause Ctl Register 908 */ 909 typedef struct { 910 unm_crbword_t 911 xg0_mask:1, /* 1:disable tx pause frames */ 912 xg0_request:1, /* request single pause frame */ 913 xg0_on_off:1, /* 1:req is pause on, 0:off */ 914 xg1_mask:1, /* 1:disable tx pause frames */ 915 xg1_request:1, /* request single pause frame */ 916 xg1_on_off:1, /* 1:req is pause on, 0:off */ 917 rsvd:26; 918 } unm_niu_xg_pause_ctl_t; 919 920 /* 921 * NIU GBe Pause Ctl Register 922 */ 923 typedef struct { 924 unm_crbword_t 925 gb0_mask:1, /* 1:disable tx pause frames */ 926 gb0_pause_req:1, /* 1: send pause on, 0: send pause off */ 927 gb1_mask:1, /* 1:disable tx pause frames */ 928 gb1_pause_req:1, /* 1: send pause on, 0: send pause off */ 929 gb2_mask:1, /* 1:disable tx pause frames */ 930 gb2_pause_req:1, /* 1: send pause on, 0: send pause off */ 931 gb3_mask:1, /* 1:disable tx pause frames */ 932 gb3_pause_req:1, /* 1: send pause on, 0: send pause off */ 933 rsvd:24; 934 } unm_niu_gb_pause_ctl_t; 935 936 937 /* 938 * NIU XG MAC Config Register 939 */ 940 typedef struct { 941 unm_crbword_t 942 tx_enable:1, /* 1:enable frame xmit, 0:disable */ 943 rsvd1:1, 944 rx_enable:1, /* 1:enable frame recv, 0:disable */ 945 rsvd2:1, 946 soft_reset:1, /* 1:reset the MAC , 0:no-op */ 947 rsvd3:22, 948 xaui_framer_reset:1, 949 xaui_rx_reset:1, 950 xaui_tx_reset:1, 951 xg_ingress_afifo_reset:1, 952 xg_egress_afifo_reset:1; 953 } unm_niu_xg_mac_config_0_t; 954 955 /* 956 * NIU GB MII Mgmt Config Register (applies to GB0, GB1, GB2, GB3) 957 */ 958 typedef struct { 959 unm_crbword_t 960 clockselect:3, /* 0:clk/4, 1:clk/4, 2:clk/6, 3:clk/8 */ 961 /* 4:clk/10, 5:clk/14, 6:clk/20, 7:clk/28 */ 962 rsvd1:1, 963 nopreamble:1, /* 1:suppress preamble generation, 0:normal */ 964 scanauto:1, /* ???? */ 965 rsvd2:25, 966 reset:1; /* 1:reset MII mgmt, 0:no-op */ 967 } unm_niu_gb_mii_mgmt_config_t; 968 969 /* 970 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3) 971 */ 972 typedef struct { 973 unm_crbword_t 974 read_cycle:1, /* 1:perform single read cycle, 0:no-op */ 975 scan_cycle:1, /* 1:perform continuous read cycles, 0:no-op */ 976 rsvd:30; 977 } unm_niu_gb_mii_mgmt_command_t; 978 979 /* 980 * NIU GB MII Mgmt Address Register (applies to GB0, GB1, GB2, GB3) 981 */ 982 typedef struct { 983 unm_crbword_t 984 reg_addr:5, /* which mgmt register we want to talk to */ 985 rsvd1:3, 986 phy_addr:5, /* which PHY to talk to (0 is reserved) */ 987 rsvd:19; 988 } unm_niu_gb_mii_mgmt_address_t; 989 990 /* 991 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3) 992 * Read-only register. 993 */ 994 typedef struct { 995 unm_crbword_t 996 busy:1, /* 1:performing an MII mgmt cycle, 0:idle */ 997 scanning:1, /* 1:scan operation in progress, 0:idle */ 998 notvalid:1, /* 1:mgmt result data not yet valid, 0:idle */ 999 rsvd:29; 1000 } unm_niu_gb_mii_mgmt_indicators_t; 1001 1002 /* 1003 * NIU GB Station Address High Register 1004 * NOTE: this value is in network byte order. 1005 */ 1006 typedef struct { 1007 unm_crbword_t 1008 address:32; /* station address [47:16] */ 1009 } unm_niu_gb_station_address_high_t; 1010 1011 /* 1012 * NIU GB Station Address Low Register 1013 * NOTE: this value is in network byte order. 1014 */ 1015 typedef struct { 1016 unm_crbword_t 1017 rsvd:16, 1018 address:16; /* station address [15:0] */ 1019 } unm_niu_gb_station_address_low_t; 1020 1021 /* ============================ PHY Definitions ========================== */ 1022 /* 1023 * PHY-Specific MII control/status registers. 1024 */ 1025 typedef enum { 1026 UNM_NIU_GB_MII_MGMT_ADDR_CONTROL = 0, 1027 UNM_NIU_GB_MII_MGMT_ADDR_STATUS = 1, 1028 UNM_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2, 1029 UNM_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3, 1030 UNM_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4, 1031 UNM_NIU_GB_MII_MGMT_ADDR_LNKPART = 5, 1032 UNM_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6, 1033 UNM_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7, 1034 UNM_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8, 1035 UNM_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9, 1036 UNM_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10, 1037 UNM_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15, 1038 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16, 1039 UNM_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17, 1040 UNM_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18, 1041 UNM_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19, 1042 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20, 1043 UNM_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21, 1044 UNM_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24, 1045 UNM_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25, 1046 UNM_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26, 1047 UNM_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27 1048 } unm_niu_phy_register_t; 1049 1050 /* 1051 * PHY-Specific Status Register (reg 17). 1052 */ 1053 typedef struct { 1054 unm_crbword_t 1055 jabber:1, /* 1:jabber detected, 0:not */ 1056 polarity:1, /* 1:polarity reversed, 0:normal */ 1057 recvpause:1, /* 1:receive pause enabled, 0:disabled */ 1058 xmitpause:1, /* 1:transmit pause enabled, 0:disabled */ 1059 energydetect:1, /* 1:sleep, 0:active */ 1060 downshift:1, /* 1:downshift, 0:no downshift */ 1061 crossover:1, /* 1:MDIX (crossover), 0:MDI (no crossover) */ 1062 cablelen:3, /* not valid in 10Mb/s mode */ 1063 /* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m */ 1064 link:1, /* 1:link up, 0:link down */ 1065 resolved:1, /* 1:speed and duplex resolved, 0:not yet */ 1066 pagercvd:1, /* 1:page received, 0:page not received */ 1067 duplex:1, /* 1:full duplex, 0:half duplex */ 1068 speed:2, /* 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd */ 1069 rsvd:16; 1070 } unm_niu_phy_status_t; 1071 1072 /* 1073 * Interrupt Register definition 1074 * This definition applies to registers 18 and 19 (int enable and int status). 1075 */ 1076 typedef struct { 1077 unm_crbword_t 1078 jabber:1, 1079 polarity_changed:1, 1080 reserved:2, 1081 energy_detect:1, 1082 downshift:1, 1083 mdi_xover_changed:1, 1084 fifo_over_underflow:1, 1085 false_carrier:1, 1086 symbol_error:1, 1087 link_status_changed:1, 1088 autoneg_completed:1, 1089 page_received:1, 1090 duplex_changed:1, 1091 speed_changed:1, 1092 autoneg_error:1, 1093 rsvd:16; 1094 } unm_niu_phy_interrupt_t; 1095 1096 /* ============================= 10GbE =============================== */ 1097 /* 1098 * NIU Mode Register. 1099 */ 1100 typedef struct { 1101 unm_crbword_t 1102 enable_fc:1, /* enable FibreChannel */ 1103 enable_ge:1, /* enable 10/100/1000 Ethernet */ 1104 enable_xgb:1, /* enable 10Gb Ethernet */ 1105 rsvd:29; 1106 } unm_niu_control_t; 1107 1108 /* ========================== Interface Functions ======================= */ 1109 1110 /* Generic enable for GbE ports. Will detect the speed of the link. */ 1111 long unm_niu_gbe_init_port(long port); 1112 1113 /* XG Link status */ 1114 #define XG_LINK_UP 0x10 1115 #define XG_LINK_DOWN 0x20 1116 1117 #define XG_LINK_UP_P3 0x1 1118 #define XG_LINK_DOWN_P3 0x2 1119 #define XG_LINK_UNKNOWN_P3 0 1120 1121 #define XG_LINK_STATE_P3_MASK 0xf 1122 #define XG_LINK_STATE_P3(pcifn, val) \ 1123 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) 1124 1125 #define MTU_MARGIN 100 1126 1127 #define PF_LINK_SPEED_MHZ 100 1128 #define PF_LINK_SPEED_REG(pcifn) (CRB_PF_LINK_SPEED_1 + (((pcifn)/4)* 4)) 1129 #define PF_LINK_SPEED_MASK 0xff 1130 #define PF_LINK_SPEED_VAL(pcifn, reg) \ 1131 (((reg) >> (8 * ((pcifn) & 0x3))) & PF_LINK_SPEED_MASK) 1132 1133 1134 1135 /* 1136 * Definitions relating to access/control of the CAM RAM 1137 */ 1138 1139 typedef union { 1140 struct { 1141 /* 1142 * =1 if watchdog is active. 1143 * =0 if watchdog is inactive 1144 * This is read-only for anyone 1145 * but the watchdog itself. 1146 */ 1147 unsigned int enabled: 1, 1148 /* 1149 * Set this to 1 to send disable 1150 * request to watchdog . Watchdog 1151 * will complete the shutdown 1152 * process and acknowledge it 1153 * by clearing this bit and the 1154 * "enable" bit. 1155 */ 1156 disable_request: 1, 1157 /* 1158 * Set this to 1 to send enable 1159 * request to watchdog . Watchdog 1160 * will complete the enable 1161 * process and acknowledge it 1162 * by clearing this bit and 1163 * setting the "enable" bit. 1164 */ 1165 enable_request: 1, 1166 unused: 29; 1167 } s1; 1168 unm_crbword_t word; 1169 } dma_watchdog_ctrl_t; 1170 1171 #define UNM_CAM_RAM_BASE (UNM_CRB_CAM + 0x02000) 1172 #define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg)) 1173 1174 #define UNM_PORT_MODE_NONE 0 1175 #define UNM_PORT_MODE_XG 1 1176 #define UNM_PORT_MODE_GB 2 1177 #define UNM_PORT_MODE_802_3_AP 3 1178 #define UNM_PORT_MODE_AUTO_NEG 4 1179 #define UNM_PORT_MODE_AUTO_NEG_1G 5 1180 #define UNM_PORT_MODE_AUTO_NEG_XG 6 1181 #define UNM_PORT_MODE_ADDR (UNM_CAM_RAM(0x24)) 1182 #define UNM_WOL_PORT_MODE (UNM_CAM_RAM(0x198)) 1183 1184 #define UNM_ROM_LOCK_ID (UNM_CAM_RAM(0x100)) 1185 #define UNM_I2C_ROM_LOCK_ID (UNM_CAM_RAM(0x104)) 1186 #define UNM_PHY_LOCK_ID (UNM_CAM_RAM(0x120)) 1187 #define UNM_CRB_WIN_LOCK_ID (UNM_CAM_RAM(0x124)) 1188 #define CAM_RAM_DMA_WATCHDOG_CTRL 0x14 /* See dma_watchdog_ctrl_t */ 1189 #define UNM_EFUSE_CHIP_ID (UNM_CAM_RAM(0x18)) 1190 1191 #define UNM_FW_VERSION_MAJOR (UNM_CAM_RAM(0x150)) 1192 #define UNM_FW_VERSION_MINOR (UNM_CAM_RAM(0x154)) 1193 #define UNM_FW_VERSION_BUILD (UNM_CAM_RAM(0x168)) 1194 #define UNM_FW_VERSION_SUB (UNM_CAM_RAM(0x158)) 1195 #define UNM_TCP_FW_VERSION_MAJOR_ADDR (UNM_CAM_RAM(0x15c)) 1196 #define UNM_TCP_FW_VERSION_MINOR_ADDR (UNM_CAM_RAM(0x160)) 1197 #define UNM_TCP_FW_VERSION_SUB_ADDR (UNM_CAM_RAM(0x164)) 1198 #define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg)) 1199 1200 #define PCIE_DCR (0x00d8) 1201 #define PCIE_DB_DATA2 (0x10070) 1202 #define PCIE_DB_CTRL (0x100a0) 1203 #define PCIE_DB_ADDR (0x100a4) 1204 #define PCIE_DB_DATA (0x100a8) 1205 #define PCIE_IMBUS_CONTROL (0x101b8) 1206 #define PCIE_SETUP_FUNCTION (0x12040) 1207 #define PCIE_SETUP_FUNCTION2 (0x12048) 1208 #define PCIE_TGT_SPLIT_CHICKEN (0x12080) 1209 #define PCIE_CHICKEN3 (0x120c8) 1210 #define PCIE_MAX_MASTER_SPLIT (0x14048) 1211 #define PCIE_MAX_DMA_XFER_SIZE (0x1404c) 1212 1213 #define UNM_WOL_WAKE (UNM_CAM_RAM(0x180)) 1214 #define UNM_WOL_CONFIG_NV (UNM_CAM_RAM(0x184)) 1215 #define UNM_WOL_CONFIG (UNM_CAM_RAM(0x188)) 1216 #define UNM_PRE_WOL_RX_ENABLE (UNM_CAM_RAM(0x18c)) 1217 1218 /* 1219 * Following define address space withing PCIX CRB space to talk with 1220 * devices on the storage side PCI bus. 1221 */ 1222 #define PCIX_PS_MEM_SPACE (0x90000) 1223 1224 #define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg)) 1225 1226 /* 1227 * Configuration registers. These are the same offsets on both host and 1228 * storage side PCI blocks. 1229 */ 1230 /* Used for PS PCI Memory access */ 1231 #define PCIX_PS_OP_ADDR_LO (0x10000) 1232 #define PCIX_PS_OP_ADDR_HI (0x10004) /* via CRB (PS side only) */ 1233 1234 #define PCIX_MS_WINDOW (0x10204) /* UNUSED */ 1235 1236 #define PCIX_CRB_WINDOW (0x10210) 1237 #define PCIX_CRB_WINDOW_F0 (0x10210) 1238 #define PCIX_CRB_WINDOW_F1 (0x10230) 1239 #define PCIX_CRB_WINDOW_F2 (0x10250) 1240 #define PCIX_CRB_WINDOW_F3 (0x10270) 1241 #define PCIX_CRB_WINDOW_F4 (0x102ac) 1242 #define PCIX_CRB_WINDOW_F5 (0x102bc) 1243 #define PCIX_CRB_WINDOW_F6 (0x102cc) 1244 #define PCIX_CRB_WINDOW_F7 (0x102dc) 1245 #define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \ 1246 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) :\ 1247 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func)-4)))) 1248 1249 #define PCIX_MN_WINDOW (0x10200) 1250 #define PCIX_MN_WINDOW_F0 (0x10200) 1251 #define PCIX_MN_WINDOW_F1 (0x10220) 1252 #define PCIX_MN_WINDOW_F2 (0x10240) 1253 #define PCIX_MN_WINDOW_F3 (0x10260) 1254 #define PCIX_MN_WINDOW_F4 (0x102a0) 1255 #define PCIX_MN_WINDOW_F5 (0x102b0) 1256 #define PCIX_MN_WINDOW_F6 (0x102c0) 1257 #define PCIX_MN_WINDOW_F7 (0x102d0) 1258 #define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \ 1259 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) :\ 1260 (PCIX_MN_WINDOW_F4 + (0x10 * ((func)-4)))) 1261 1262 #define PCIX_SN_WINDOW (0x10208) 1263 #define PCIX_SN_WINDOW_F0 (0x10208) 1264 #define PCIX_SN_WINDOW_F1 (0x10228) 1265 #define PCIX_SN_WINDOW_F2 (0x10248) 1266 #define PCIX_SN_WINDOW_F3 (0x10268) 1267 #define PCIX_SN_WINDOW_F4 (0x102a8) 1268 #define PCIX_SN_WINDOW_F5 (0x102b8) 1269 #define PCIX_SN_WINDOW_F6 (0x102c8) 1270 #define PCIX_SN_WINDOW_F7 (0x102d8) 1271 #define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \ 1272 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) :\ 1273 (PCIX_SN_WINDOW_F4 + (0x10 * ((func)-4)))) 1274 1275 #define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg)) 1276 #define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg)) 1277 #define MANAGEMENT_COMMAND_REG (UNM_CRB_PCIE + (4)) 1278 1279 #define UNM_PH_INT_MASK (UNM_CRB_PCIE + PCIX_INT_MASK) 1280 1281 /* 1282 * CRB window register. 1283 */ 1284 typedef struct { 1285 unm_crbword_t rsvd1:25, 1286 addrbit:1, /* bit 25 of CRB address */ 1287 rsvd2:6; 1288 } unm_pcix_crb_window_t; 1289 1290 /* 1291 * Tell which interrupt source we want to operate on. 1292 */ 1293 typedef enum { 1294 UNM_PCIX_INT_SRC_UNDEFINED = 0, 1295 UNM_PCIX_INT_SRC_DMA0, /* DMA engine 0 */ 1296 UNM_PCIX_INT_SRC_DMA1, /* DMA engine 1 */ 1297 UNM_PCIX_INT_SRC_I2Q /* I2Q block */ 1298 } unm_pcix_int_source_t; 1299 1300 typedef enum { 1301 UNM_PCIX_INT_SRC_UNDEFINEDSTATE = 0, 1302 UNM_PCIX_INT_SRC_ALLOW, /* Allow this src to int. the host */ 1303 UNM_PCIX_INT_SRC_MASK /* Mask this src */ 1304 } unm_pcix_int_state_t; 1305 1306 /* 1307 * PCIX Interrupt Mask Register. 1308 */ 1309 typedef struct { 1310 /* 0=DMA0 not masked, 1=masked */ 1311 unm_crbword_t dma0:1, 1312 /* 0=DMA1 not masked, 1=masked */ 1313 dma1:1, 1314 /* 0=I2Q not masked, 1=masked */ 1315 i2q:1, 1316 dma0_err:1, 1317 dma1_err:1, 1318 target_status:1, 1319 mega_err:1, 1320 ps_serr_int:1, 1321 split_discard:1, 1322 io_write_func0:1, 1323 io_write_func1:1, 1324 io_write_func2:1, 1325 io_write_func3:1, 1326 msi_write_func0:1, 1327 msi_write_func1:1, 1328 msi_write_func2:1, 1329 msi_write_func3:1, 1330 rsvd:15; 1331 } unm_pcix_int_mask_t; 1332 1333 int unm_pcix_int_control(unm_pcix_int_source_t src, 1334 unm_pcix_int_state_t state); 1335 1336 #define UNM_SRE_INT_STATUS (UNM_CRB_SRE + 0x00034) 1337 #define UNM_SRE_BUF_CTL (UNM_CRB_SRE + 0x01000) 1338 #define UNM_SRE_PBI_ACTIVE_STATUS (UNM_CRB_SRE + 0x01014) 1339 #define UNM_SRE_SCRATCHPAD (UNM_CRB_SRE + 0x01018) 1340 #define UNM_SRE_L1RE_CTL (UNM_CRB_SRE + 0x03000) 1341 #define UNM_SRE_L2RE_CTL (UNM_CRB_SRE + 0x05000) 1342 1343 // These are offset to a particular Peg's CRB base address 1344 #define CRB_REG_EX_PC 0x3c 1345 1346 #define PEG_NETWORK_BASE(N) (UNM_CRB_PEG_NET_0 + (((N)&3) << 20)) 1347 1348 /* 1349 * Definitions relating to enqueue/dequeue/control of the Queue Operations 1350 * to either the Primary Queue Manager or the Secondary Queue Manager. 1351 */ 1352 1353 /* 1354 * General configuration constants. 1355 */ 1356 #define UNM_QM_MAX_SIDE 1 1357 1358 /* 1359 * Data movement registers (differs based on processor). 1360 */ 1361 #define UNM_QM_COMMAND (UNM_PCI_CAMQM + 0x00000) 1362 #define UNM_QM_STATUS (UNM_PCI_CAMQM + 0x00008) 1363 #define UNM_QM_DATA(W, P) (UNM_PCI_CAMQM + 0x00010 + \ 1364 (W)*sizeof (unm_dataword_t)) 1365 #define UNM_QM_REPLY(W, P)(UNM_PCI_CAMQM + 0x00050 + \ 1366 (W)*sizeof (unm_dataword_t)) 1367 1368 /* 1369 * Control commands to the QM block. 1370 */ 1371 #define UNM_QM_CMD_READ 0x0 /* interpret "readop" field */ 1372 1373 /* 1374 * Platform-specific fields in the queue command word 1375 */ 1376 #define UNM_QM_CMD_SIDE 0 1377 /* Casper and Peg need this bit. PCI interface does not */ 1378 #define UNM_QM_CMD_START 1 1379 1380 1381 /* 1382 * Pegasus has two QM ports. This is the default one to use (unless 1383 * QM async interface is called explicitly with other port). 1384 */ 1385 #define UNM_QM_DEFAULT_PORT 0 1386 1387 /* 1388 * Status result returned to caller of unm_qm_request_status() 1389 */ 1390 typedef enum { 1391 /* error in HW - most likely PCI bug. retry */ 1392 unm_qm_status_unknown = 0, 1393 unm_qm_status_done, /* done with last command */ 1394 unm_qm_status_busy, /* busy */ 1395 unm_qm_status_notfound, /* queue is empty to read or full to write */ 1396 unm_qm_status_error /* error (e.g. timeout) encountered */ 1397 } unm_qm_result_t; 1398 1399 /* 1400 * Definitions relating to access/control of the I2Q h/w block. 1401 */ 1402 /* 1403 * Configuration registers. 1404 */ 1405 #define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000) 1406 #define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010) 1407 #define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014) 1408 #define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018) 1409 #define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c) 1410 #define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020) 1411 #define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024) 1412 #define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030) 1413 #define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034) 1414 #define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038) 1415 #define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c) 1416 #define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I)*0x8) 1417 #define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I)*0x8) 1418 1419 /* 1420 * List the bit positions in the registers of the interrupt sources. 1421 */ 1422 typedef enum { 1423 UNM_I2Q_SRC_PCI32 = 0, /* PCI32 block */ 1424 UNM_I2Q_SRC_PCIE = 1, /* PCI-Express block */ 1425 UNM_I2Q_SRC_CASPER = 2, /* Casper */ 1426 UNM_I2Q_SRC_CASPER_ERR = 3, /* Casper error */ 1427 UNM_I2Q_SRC_PEG_0 = 4, /* Peg 0 */ 1428 UNM_I2Q_SRC_PEG_1 = 5, /* Peg 1 */ 1429 UNM_I2Q_SRC_PEG_2 = 6, /* Peg 2 */ 1430 UNM_I2Q_SRC_PEG_3 = 7, /* Peg 3 */ 1431 UNM_I2Q_SRC_PEG_DCACHE = 8, /* Peg Data cache */ 1432 UNM_I2Q_SRC_PEG_ICACHE = 9, /* Peg Instruction cache */ 1433 UNM_I2Q_SRC_DMA0 = 10, /* DMA engine 0 */ 1434 UNM_I2Q_SRC_DMA1 = 11, /* DMA engine 1 */ 1435 UNM_I2Q_SRC_DMA2 = 12, /* DMA engine 2 */ 1436 NM_I2Q_SRC_DMA3 = 13, /* DMA engine 3 */ 1437 UNM_I2Q_SRC_LPC = 14, /* */ 1438 UNM_I2Q_SRC_SMB = 15, /* */ 1439 UNM_I2Q_SRC_TIMER = 16, /* One of the global timers */ 1440 UNM_I2Q_SRC_SQG0 = 17, /* SQM SQG0 empty->non-empty */ 1441 UNM_I2Q_SRC_SQG1 = 18, /* SQM SQG1 empty->non-empty */ 1442 UNM_I2Q_SRC_SQG2 = 19, /* SQM SQG2 empty->non-empty */ 1443 UNM_I2Q_SRC_SQG3 = 20, /* SQM SQG3 empty->non-empty */ 1444 UNM_I2Q_SRC_SQG0_LW = 21, /* SQM SQG0 low on free buffers */ 1445 UNM_I2Q_SRC_SQG1_LW = 22, /* SQM SQG1 low on free buffers */ 1446 UNM_I2Q_SRC_SQG2_LW = 23, /* SQM SQG2 low on free buffers */ 1447 UNM_I2Q_SRC_SQG3_LW = 24, /* SQM SQG3 low on free buffers */ 1448 UNM_I2Q_SRC_PQM_0 = 25, /* PQM group 0 */ 1449 UNM_I2Q_SRC_PQM_1 = 26, /* PQM group 1 */ 1450 UNM_I2Q_SRC_PQM_2 = 27, /* PQM group 2 */ 1451 UNM_I2Q_SRC_PQM_3 = 28, /* PQM group 3 */ 1452 /* [29:31] reserved */ 1453 UNM_I2Q_SRC_SW_0 = 32, /* SW INT 0 */ 1454 UNM_I2Q_SRC_SW_1 = 33, /* SW INT 1 */ 1455 UNM_I2Q_SRC_SW_2 = 34, /* SW INT 2 */ 1456 UNM_I2Q_SRC_SW_3 = 35, /* SW INT 3 */ 1457 UNM_I2Q_SRC_SW_4 = 36, /* SW INT 4 */ 1458 UNM_I2Q_SRC_SW_5 = 37, /* SW INT 5 */ 1459 UNM_I2Q_SRC_SW_6 = 38, /* SW INT 6 */ 1460 UNM_I2Q_SRC_SW_7 = 39, /* SW INT 7 */ 1461 UNM_I2Q_SRC_SRE_EPG = 40, /* SRE/EPG aggregate interrupt */ 1462 UNM_I2Q_SRC_XDMA = 41, /* XDMA engine */ 1463 UNM_I2Q_SRC_MN = 42, /* DDR interface unit */ 1464 UNM_I2Q_SRC_NIU = 43, /* Network interface unit */ 1465 UNM_I2Q_SRC_SN = 44, /* QDR interface unit */ 1466 UNM_I2Q_SRC_CAM = 45, /* CAM */ 1467 UNM_I2Q_SRC_EXT1 = 46, /* External 1 */ 1468 UNM_I2Q_SRC_EXT2 = 47, /* External 2 */ 1469 /* [48:63] reserved */ 1470 UNM_I2Q_SRC_MAX = 47, /* max used interrupt line */ 1471 UNM_I2Q_SRC_MAX_LO = 32 /* max bits in "lo" register */ 1472 } unm_i2q_source_t; 1473 1474 /* 1475 * Interrupt Source Enable/Clear registers for the I2Q. 1476 */ 1477 typedef struct { 1478 unm_crbword_t source:32; /* int enable/status bits */ 1479 } unm_i2q_source_lo_t; 1480 1481 typedef struct { 1482 unm_crbword_t source:16, /* int enable/status bits */ 1483 rsvd:16; 1484 } unm_i2q_source_hi_t; 1485 1486 /* 1487 * List the possible interrupt sources and the 1488 * control operations to be performed for each. 1489 */ 1490 typedef enum { 1491 UNM_I2Q_CTL_SRCUNKNOWN = 0, /* undefined */ 1492 UNM_I2Q_CTL_PCI, /* PCI block */ 1493 UNM_I2Q_CTL_CASPER, /* Casper */ 1494 UNM_I2Q_CTL_QM /* Queue Manager */ 1495 } unm_i2q_ctl_src_t; 1496 1497 typedef enum { 1498 UNM_I2Q_CTL_OPUNKNOWN = 0, /* undefined */ 1499 UNM_I2Q_CTL_ADD, /* add int'ing for that source */ 1500 UNM_I2Q_CTL_DEL /* stop int'ing for that source */ 1501 } unm_i2q_ctl_op_t; 1502 1503 /* 1504 * Definitions relating to access/control of the Secondary Queue Manager 1505 * h/w block. 1506 */ 1507 /* 1508 * Configuration registers. 1509 */ 1510 #define UNM_SQM_BASE(G) \ 1511 ((G) == 0 ? UNM_CRB_SQM_NET_0 : \ 1512 ((G) == 1 ? UNM_CRB_SQM_NET_1 : \ 1513 ((G) == 2 ? UNM_CRB_SQM_NET_2 : UNM_CRB_SQM_NET_3))) 1514 1515 #define UNM_SQM_INT_ENABLE(G) (UNM_SQM_BASE(G) + 0x00018) 1516 #define UNM_SQM_INT_STATUS(G) (UNM_SQM_BASE(G) + 0x0001c) 1517 #define UNN_SQM_SCRATCHPAD(G) (UNM_SQM_BASE(G) + 0x01000) 1518 1519 #define UNM_SQM_MAX_GRP 4 /* num groups per side */ 1520 #define UNM_SQM_MAX_SUBQ 16 /* num Q's per type-0 group */ 1521 #define UNM_SQM_MAX_SUBGRP 4 /* subgrps per type-1 group */ 1522 1523 #define UNM_SQM_MAX_TYPE_1_NUM (256*1024) 1524 1525 /* 1526 * Interrupt enables and interrupt status for all 16 queues in a group. 1527 */ 1528 typedef struct { 1529 unm_crbword_t queues:16, /* enable/status: 0x1=Q0, 0x8000=Q15 */ 1530 rsvd:16; 1531 } unm_sqm_int_enstat_t; 1532 1533 /* 1534 * Control operation for an SQM Group interrupt. 1535 */ 1536 typedef enum { 1537 UNM_SQM_INTOP_OPUNKNOWN = 0, /* undefined */ 1538 UNM_SQM_INTOP_GET, /* return all bits for that group */ 1539 UNM_SQM_INTOP_SET, /* assign all bits for that group */ 1540 UNM_SQM_INTOP_ADD, /* set one bit for that group */ 1541 UNM_SQM_INTOP_DEL /* clear one bit for that group */ 1542 } unm_sqm_int_op_t; 1543 typedef enum { 1544 UNM_SQM_INTARG_ARGUNKNOWN = 0, /* undefined */ 1545 UNM_SQM_INTARG_ENABLE, /* affect the 'enable' register */ 1546 UNM_SQM_INTARG_STATUS /* affect the 'status' register */ 1547 } unm_sqm_int_arg_t; 1548 1549 int unm_sqm_int_control(unm_sqm_int_op_t op, unm_sqm_int_arg_t arg, 1550 int side, int group, int queue, int *image); 1551 1552 1553 int unm_crb_read(unsigned long off, void *data); 1554 native_t unm_crb_read_val(unsigned long off); 1555 int unm_crb_write(unsigned long off, void *data); 1556 int unm_crb_writelit(unsigned long off, int data); 1557 int unm_imb_read(unsigned long off, void *data); 1558 int unm_imb_write(unsigned long off, void *data); 1559 int unm_imb_writelit64(unsigned long off, __uint64_t data); 1560 1561 unsigned long unm_xport_lock(void); 1562 void unm_xport_unlock(unsigned long); 1563 1564 #define UNM_CRB_READ_VAL(ADDR) unm_crb_read_val((ADDR)) 1565 #define UNM_CRB_READ(ADDR, VALUE) unm_crb_read((ADDR), (unm_crbword_t *)(VALUE)) 1566 #define UNM_CRB_READ_CHECK(ADDR, VALUE) \ 1567 do { \ 1568 if (unm_crb_read(ADDR, VALUE)) \ 1569 return (-1); \ 1570 } while (0) 1571 #define UNM_CRB_WRITE_CHECK(ADDR, VALUE) \ 1572 do { \ 1573 if (unm_crb_write(ADDR, VALUE)) \ 1574 return (-1); \ 1575 } while (0) 1576 #define UNM_CRB_WRITELIT(ADDR, VALUE) \ 1577 do { \ 1578 unm_crb_writelit(ADDR, VALUE); \ 1579 } while (0) 1580 #define UNM_CRB_WRITE(ADDR, VALUE) \ 1581 do { \ 1582 unm_crb_write(ADDR, VALUE); \ 1583 } while (0) 1584 #define UNM_CRB_WRITELIT_CHECK(ADDR, VALUE) \ 1585 do { \ 1586 if (unm_crb_writelit(ADDR, VALUE)) \ 1587 return (-1); \ 1588 } while (0) 1589 1590 #define UNM_IMB_READ_CHECK(ADDR, VALUE) \ 1591 do { \ 1592 if (unm_imb_read(ADDR, VALUE)) \ 1593 return (-1); \ 1594 } while (0) 1595 #define UNM_IMB_WRITE_CHECK(ADDR, VALUE) \ 1596 do { \ 1597 if (unm_imb_write(ADDR, VALUE)) \ 1598 return (-1); \ 1599 } while (0) 1600 #define UNM_IMB_WRITELIT_CHECK(ADDR, VALUE) \ 1601 do { \ 1602 if (unm_imb_writelit64(ADDR, VALUE)) \ 1603 return (-1); \ 1604 } while (0) 1605 1606 /* 1607 * Configuration registers. 1608 */ 1609 #ifdef PCIX 1610 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_HOST + 0x20000 + ((U)<<16)) 1611 #else 1612 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_MD + 0x20000 + ((U)<<16)) 1613 #endif 1614 #define UNM_DMA_COMMAND(U) (UNM_DMA_BASE(U) + 0x00008) 1615 1616 1617 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 1618 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 1619 #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ 1620 #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ 1621 #define PCIE_SEM4_LOCK (0x1c020) /* I2C lock */ 1622 #define PCIE_SEM4_UNLOCK (0x1c024) /* I2C unlock */ 1623 #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ 1624 #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ 1625 #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ 1626 #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ 1627 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 1628 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock */ 1629 1630 1631 #define PCIE_PS_STRAP_RESET (0x18000) 1632 1633 #define M25P_INSTR_WREN 0x06 1634 #define M25P_INSTR_RDSR 0x05 1635 #define M25P_INSTR_PP 0x02 1636 #define M25P_INSTR_SE 0xd8 1637 #define CAM_RAM_P2I_ENABLE 0xc 1638 #define CAM_RAM_P2D_ENABLE 0x8 1639 #define PCIX_IMBTAG (0x18004) 1640 #define UNM_MAC_ADDR_CNTL_REG (UNM_CRB_NIU + 0x1000) 1641 1642 #define UNM_MULTICAST_ADDR_HI_0 (UNM_CRB_NIU + 0x1010) 1643 #define UNM_MULTICAST_ADDR_HI_1 (UNM_CRB_NIU + 0x1014) 1644 #define UNM_MULTICAST_ADDR_HI_2 (UNM_CRB_NIU + 0x1018) 1645 #define UNM_MULTICAST_ADDR_HI_3 (UNM_CRB_NIU + 0x101c) 1646 1647 #define M_UNICAST_ADDR_BASE (UNM_CRB_NIU + 0x1080) 1648 1649 #define UNM_UNICAST_ADDR_LO_0_0 (UNM_CRB_NIU + 0x1080) // port 0 1650 #define UNM_UNICAST_ADDR_HI_0_0 (UNM_CRB_NIU + 0x1084) 1651 #define UNM_UNICAST_ADDR_LO_0_1 (UNM_CRB_NIU + 0x1088) 1652 #define UNM_UNICAST_ADDR_HI_0_1 (UNM_CRB_NIU + 0x108c) 1653 #define UNM_UNICAST_ADDR_LO_0_2 (UNM_CRB_NIU + 0x1090) 1654 #define UNM_UNICAST_ADDR_HI_0_2 (UNM_CRB_NIU + 0x1084) 1655 #define UNM_UNICAST_ADDR_LO_0_3 (UNM_CRB_NIU + 0x1098) 1656 #define UNM_UNICAST_ADDR_HI_0_3 (UNM_CRB_NIU + 0x109c) 1657 1658 #define UNM_UNICAST_ADDR_LO_1_0 (UNM_CRB_NIU + 0x10a0) 1659 #define UNM_UNICAST_ADDR_HI_1_0 (UNM_CRB_NIU + 0x10a4) 1660 #define UNM_UNICAST_ADDR_LO_1_1 (UNM_CRB_NIU + 0x10a8) 1661 #define UNM_UNICAST_ADDR_HI_1_1 (UNM_CRB_NIU + 0x10ac) 1662 #define UNM_UNICAST_ADDR_LO_1_2 (UNM_CRB_NIU + 0x10b0) 1663 #define UNM_UNICAST_ADDR_HI_1_2 (UNM_CRB_NIU + 0x10b4) 1664 #define UNM_UNICAST_ADDR_LO_1_3 (UNM_CRB_NIU + 0x10b8) 1665 #define UNM_UNICAST_ADDR_HI_1_3 (UNM_CRB_NIU + 0x10bc) 1666 1667 #define UNM_UNICAST_ADDR_LO_2_0 (UNM_CRB_NIU + 0x10c0) 1668 #define UNM_UNICAST_ADDR_HI_2_0 (UNM_CRB_NIU + 0x10c4) 1669 #define UNM_UNICAST_ADDR_LO_2_1 (UNM_CRB_NIU + 0x10c8) 1670 #define UNM_UNICAST_ADDR_HI_2_1 (UNM_CRB_NIU + 0x10cc) 1671 #define UNM_UNICAST_ADDR_LO_2_2 (UNM_CRB_NIU + 0x10d0) 1672 #define UNM_UNICAST_ADDR_HI_2_2 (UNM_CRB_NIU + 0x10d4) 1673 #define UNM_UNICAST_ADDR_LO_2_3 (UNM_CRB_NIU + 0x10d8) 1674 #define UNM_UNICAST_ADDR_HI_2_3 (UNM_CRB_NIU + 0x10dc) 1675 1676 #define UNM_UNICAST_ADDR_LO_3_0 (UNM_CRB_NIU + 0x10e0) 1677 #define UNM_UNICAST_ADDR_HI_3_0 (UNM_CRB_NIU + 0x10e4) 1678 #define UNM_UNICAST_ADDR_LO_3_1 (UNM_CRB_NIU + 0x10e8) 1679 #define UNM_UNICAST_ADDR_HI_3_1 (UNM_CRB_NIU + 0x10ec) 1680 #define UNM_UNICAST_ADDR_LO_3_2 (UNM_CRB_NIU + 0x10f0) 1681 #define UNM_UNICAST_ADDR_HI_3_2 (UNM_CRB_NIU + 0x10f4) 1682 #define UNM_UNICAST_ADDR_LO_3_3 (UNM_CRB_NIU + 0x10f8) 1683 #define UNM_UNICAST_ADDR_HI_3_3 (UNM_CRB_NIU + 0x10fc) 1684 1685 #define UNM_MULTICAST_ADDR_BASE (UNM_CRB_NIU + 0x1100) 1686 1687 // BASE ADDRESS FOR POOL/PORT 0 1688 #define UNM_MULTICAST_ADDR_LO_0 (UNM_CRB_NIU + 0x1100) 1689 // FOR PORT 1 1690 #define UNM_MULTICAST_ADDR_LO_1 (UNM_CRB_NIU + 0x1180) 1691 // FOR PORT 2 1692 #define UNM_MULTICAST_ADDR_LO_2 (UNM_CRB_NIU + 0x1200) 1693 // PORT 3 1694 #define UNM_MULTICAST_ADDR_LO_3 (UNM_CRB_NIU + 0x1280) 1695 1696 #define PHAN_VENDOR_ID 0x4040 1697 1698 #define CAM_RAM_PEG_ENABLES 0x4 1699 1700 /* 1701 * The PCI VendorID and DeviceID for our board. 1702 */ 1703 #define PCI_VENDOR_ID_NX 0x4040 1704 #define PCI_DEVICE_ID_NX_XG 0x0001 1705 #define PCI_DEVICE_ID_NX_CX4 0x0002 1706 #define PCI_DEVICE_ID_NX_QG 0x0003 1707 #define PCI_DEVICE_ID_NX_IMEZ 0x0004 1708 #define PCI_DEVICE_ID_NX_HMEZ 0x0005 1709 #define PCI_DEVICE_ID_NX_IMEZ_DUP 0x0024 1710 #define PCI_DEVICE_ID_NX_HMEZ_DUP 0x0025 1711 #define PCI_DEVICE_ID_NX_P3_XG 0x0100 1712 1713 /* 1714 * Time base tick control registers (global and per-flow). 1715 */ 1716 1717 typedef struct { 1718 /* half period of time cycle */ 1719 /* global: in units of core clock */ 1720 /* per-flow: in units of global ticks */ 1721 unm_crbword_t count:16, 1722 rsvd:15, 1723 enable:1; /* 0=disable, 1=enable */ 1724 } unm_timer_tickctl_t; 1725 1726 1727 typedef struct 1728 { 1729 unm_crbword_t 1730 id_pool_0:2, 1731 enable_xtnd_0:1, 1732 rsvd1:1, 1733 id_pool_1:2, 1734 enable_xtnd_1:1, 1735 rsvd2:1, 1736 id_pool_2:2, 1737 enable_xtnd_2:1, 1738 rsvd3:1, 1739 id_pool_3:2, 1740 enable_xtnd_3:1, 1741 rsvd4:9, 1742 mode_select:2, 1743 rsvd5:2, 1744 enable_pool:4; 1745 } unm_mac_addr_cntl_t; 1746 1747 typedef struct { 1748 unm_crbword_t start:1, 1749 enable:1, 1750 command:1, 1751 busy:1, 1752 rsvd:28; 1753 } unm_miu_test_agt_ctrl_t; 1754 1755 #define UNM_MIU_TEST_AGENT_CMD_READ 0 1756 #define UNM_MIU_TEST_AGENT_CMD_WRITE 1 1757 #define UNM_MIU_TEST_AGENT_BUSY 1 1758 #define UNM_MIU_TEST_AGENT_ENABLE 1 1759 #define UNM_MIU_TEST_AGENT_START 1 1760 1761 #define UNM_MIU_MN_CONTROL (UNM_CRB_DDR_NET + MIU_CONTROL) 1762 #define UNM_MIU_MN_TAG (UNM_CRB_DDR_NET + MIU_TAG) 1763 #define UNM_MIU_MN_TEST_AGT_ADDR_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_LO) 1764 #define UNM_MIU_MN_TEST_AGT_ADDR_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_ADDR_HI) 1765 #define UNM_MIU_MN_TEST_AGT_WRDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_LO) 1766 #define UNM_MIU_MN_TEST_AGT_WRDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_WRDATA_HI) 1767 #define UNM_MIU_MN_TEST_AGT_CTRL (UNM_CRB_DDR_NET + MIU_TEST_AGT_CTRL) 1768 #define UNM_MIU_MN_TEST_AGT_RDDATA_LO (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_LO) 1769 #define UNM_MIU_MN_TEST_AGT_RDDATA_HI (UNM_CRB_DDR_NET + MIU_TEST_AGT_RDDATA_HI) 1770 1771 #define UNM_SIU_SN_TEST_AGT_ADDR_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_ADDR_LO) 1772 #define UNM_SIU_SN_TEST_AGT_ADDR_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_ADDR_HI) 1773 #define UNM_SIU_SN_TEST_AGT_WRDATA_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_WRDATA_LO) 1774 #define UNM_SIU_SN_TEST_AGT_WRDATA_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_WRDATA_HI) 1775 #define UNM_SIU_SN_TEST_AGT_CTRL (UNM_CRB_QDR_NET + SIU_TEST_AGT_CTRL) 1776 #define UNM_SIU_SN_TEST_AGT_RDDATA_LO (UNM_CRB_QDR_NET + SIU_TEST_AGT_RDDATA_LO) 1777 #define UNM_SIU_SN_TEST_AGT_RDDATA_HI (UNM_CRB_QDR_NET + SIU_TEST_AGT_RDDATA_HI) 1778 1779 #define NX_IS_SYSTEM_CUT_THROUGH(MIU_CTRL) (((MIU_CTRL) & 0x4) ? 1 : 0) 1780 #define NX_SET_SYSTEM_LEGACY(MIU_CTRL) {(MIU_CTRL) &= ~0x4; } 1781 #define NX_SET_SYSTEM_CUT_THROUGH(MIU_CTRL) {(MIU_CTRL) |= 0x4; } 1782 1783 #ifdef __cplusplus 1784 } 1785 #endif 1786 1787 #endif /* _UNM_INC_H_ */ 1788