1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "nge.h" 30 31 /* 32 * Describes the chip's DMA engine 33 */ 34 35 static ddi_dma_attr_t hot_dma_attr = { 36 DMA_ATTR_V0, /* dma_attr version */ 37 0x0000000000000000ull, /* dma_attr_addr_lo */ 38 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 39 0x000000007FFFFFFFull, /* dma_attr_count_max */ 40 0x0000000000000010ull, /* dma_attr_align */ 41 0x00000FFF, /* dma_attr_burstsizes */ 42 0x00000001, /* dma_attr_minxfer */ 43 0x000000000000FFFFull, /* dma_attr_maxxfer */ 44 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 45 1, /* dma_attr_sgllen */ 46 0x00000001, /* dma_attr_granular */ 47 0 48 }; 49 50 static ddi_dma_attr_t hot_tx_dma_attr = { 51 DMA_ATTR_V0, /* dma_attr version */ 52 0x0000000000000000ull, /* dma_attr_addr_lo */ 53 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 54 0x0000000000003FFFull, /* dma_attr_count_max */ 55 0x0000000000000010ull, /* dma_attr_align */ 56 0x00000FFF, /* dma_attr_burstsizes */ 57 0x00000001, /* dma_attr_minxfer */ 58 0x0000000000003FFFull, /* dma_attr_maxxfer */ 59 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 60 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 61 1, /* dma_attr_granular */ 62 0 63 }; 64 65 static ddi_dma_attr_t sum_dma_attr = { 66 DMA_ATTR_V0, /* dma_attr version */ 67 0x0000000000000000ull, /* dma_attr_addr_lo */ 68 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 69 0x000000007FFFFFFFull, /* dma_attr_count_max */ 70 0x0000000000000010ull, /* dma_attr_align */ 71 0x00000FFF, /* dma_attr_burstsizes */ 72 0x00000001, /* dma_attr_minxfer */ 73 0x000000000000FFFFull, /* dma_attr_maxxfer */ 74 0x00000000FFFFFFFFull, /* dma_attr_seg */ 75 1, /* dma_attr_sgllen */ 76 0x00000001, /* dma_attr_granular */ 77 0 78 }; 79 80 static ddi_dma_attr_t sum_tx_dma_attr = { 81 DMA_ATTR_V0, /* dma_attr version */ 82 0x0000000000000000ull, /* dma_attr_addr_lo */ 83 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 84 0x0000000000003FFFull, /* dma_attr_count_max */ 85 0x0000000000000010ull, /* dma_attr_align */ 86 0x00000FFF, /* dma_attr_burstsizes */ 87 0x00000001, /* dma_attr_minxfer */ 88 0x0000000000003FFFull, /* dma_attr_maxxfer */ 89 0x00000000FFFFFFFFull, /* dma_attr_seg */ 90 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 91 1, /* dma_attr_granular */ 92 0 93 }; 94 95 /* 96 * DMA access attributes for data. 97 */ 98 ddi_device_acc_attr_t nge_data_accattr = { 99 DDI_DEVICE_ATTR_V0, 100 DDI_STRUCTURE_LE_ACC, 101 DDI_STRICTORDER_ACC, 102 DDI_DEFAULT_ACC 103 }; 104 105 /* 106 * DMA access attributes for descriptors. 107 */ 108 static ddi_device_acc_attr_t nge_desc_accattr = { 109 DDI_DEVICE_ATTR_V0, 110 DDI_STRUCTURE_LE_ACC, 111 DDI_STRICTORDER_ACC, 112 DDI_DEFAULT_ACC 113 }; 114 115 /* 116 * PIO access attributes for registers 117 */ 118 static ddi_device_acc_attr_t nge_reg_accattr = { 119 DDI_DEVICE_ATTR_V0, 120 DDI_STRUCTURE_LE_ACC, 121 DDI_STRICTORDER_ACC, 122 DDI_DEFAULT_ACC 123 }; 124 125 /* 126 * NIC DESC MODE 2 127 */ 128 129 static const nge_desc_attr_t nge_sum_desc = { 130 131 sizeof (sum_rx_bd), 132 sizeof (sum_tx_bd), 133 &sum_dma_attr, 134 &sum_tx_dma_attr, 135 nge_sum_rxd_fill, 136 nge_sum_rxd_check, 137 nge_sum_txd_fill, 138 nge_sum_txd_check, 139 }; 140 141 /* 142 * NIC DESC MODE 3 143 */ 144 145 static const nge_desc_attr_t nge_hot_desc = { 146 147 sizeof (hot_rx_bd), 148 sizeof (hot_tx_bd), 149 &hot_dma_attr, 150 &hot_tx_dma_attr, 151 nge_hot_rxd_fill, 152 nge_hot_rxd_check, 153 nge_hot_txd_fill, 154 nge_hot_txd_check, 155 }; 156 157 static char nge_ident[] = "nVidia 1Gb Ethernet"; 158 static char clsize_propname[] = "cache-line-size"; 159 static char latency_propname[] = "latency-timer"; 160 static char debug_propname[] = "nge-debug-flags"; 161 static char intr_moderation[] = "intr-moderation"; 162 static char rx_data_hw[] = "rx-data-hw"; 163 static char rx_prd_lw[] = "rx-prd-lw"; 164 static char rx_prd_hw[] = "rx-prd-hw"; 165 static char sw_intr_intv[] = "sw-intr-intvl"; 166 static char nge_desc_mode[] = "desc-mode"; 167 static char default_mtu[] = "default_mtu"; 168 static char low_memory_mode[] = "minimal-memory-usage"; 169 extern kmutex_t nge_log_mutex[1]; 170 171 static int nge_m_start(void *); 172 static void nge_m_stop(void *); 173 static int nge_m_promisc(void *, boolean_t); 174 static int nge_m_multicst(void *, boolean_t, const uint8_t *); 175 static int nge_m_unicst(void *, const uint8_t *); 176 static void nge_m_ioctl(void *, queue_t *, mblk_t *); 177 static boolean_t nge_m_getcapab(void *, mac_capab_t, void *); 178 static int nge_m_setprop(void *, const char *, mac_prop_id_t, 179 uint_t, const void *); 180 static int nge_m_getprop(void *, const char *, mac_prop_id_t, 181 uint_t, uint_t, void *); 182 static int nge_set_priv_prop(nge_t *, const char *, uint_t, 183 const void *); 184 static int nge_get_priv_prop(nge_t *, const char *, uint_t, 185 uint_t, void *); 186 187 #define NGE_M_CALLBACK_FLAGS\ 188 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 189 190 static mac_callbacks_t nge_m_callbacks = { 191 NGE_M_CALLBACK_FLAGS, 192 nge_m_stat, 193 nge_m_start, 194 nge_m_stop, 195 nge_m_promisc, 196 nge_m_multicst, 197 nge_m_unicst, 198 nge_m_tx, 199 NULL, 200 nge_m_ioctl, 201 nge_m_getcapab, 202 NULL, 203 NULL, 204 nge_m_setprop, 205 nge_m_getprop 206 }; 207 208 mac_priv_prop_t nge_priv_props[] = { 209 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 210 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 211 {"_recv_max_packet", MAC_PROP_PERM_RW}, 212 {"_poll_quiet_time", MAC_PROP_PERM_RW}, 213 {"_poll_busy_time", MAC_PROP_PERM_RW}, 214 {"_rx_intr_hwater", MAC_PROP_PERM_RW}, 215 {"_rx_intr_lwater", MAC_PROP_PERM_RW}, 216 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 217 {"_adv_asym_pause_cap", MAC_PROP_PERM_RW}, 218 {"_tx_n_intr", MAC_PROP_PERM_RW} 219 }; 220 221 #define NGE_MAX_PRIV_PROPS \ 222 (sizeof (nge_priv_props)/sizeof (mac_priv_prop_t)) 223 224 static int nge_add_intrs(nge_t *, int); 225 static void nge_rem_intrs(nge_t *); 226 static int nge_register_intrs_and_init_locks(nge_t *); 227 228 /* 229 * NGE MSI tunable: 230 */ 231 boolean_t nge_enable_msi = B_FALSE; 232 233 static enum ioc_reply 234 nge_set_loop_mode(nge_t *ngep, uint32_t mode) 235 { 236 /* 237 * If the mode isn't being changed, there's nothing to do ... 238 */ 239 if (mode == ngep->param_loop_mode) 240 return (IOC_ACK); 241 242 /* 243 * Validate the requested mode and prepare a suitable message 244 * to explain the link down/up cycle that the change will 245 * probably induce ... 246 */ 247 switch (mode) { 248 default: 249 return (IOC_INVAL); 250 251 case NGE_LOOP_NONE: 252 case NGE_LOOP_EXTERNAL_100: 253 case NGE_LOOP_EXTERNAL_10: 254 case NGE_LOOP_INTERNAL_PHY: 255 break; 256 } 257 258 /* 259 * All OK; tell the caller to reprogram 260 * the PHY and/or MAC for the new mode ... 261 */ 262 ngep->param_loop_mode = mode; 263 return (IOC_RESTART_ACK); 264 } 265 266 #undef NGE_DBG 267 #define NGE_DBG NGE_DBG_INIT 268 269 /* 270 * Utility routine to carve a slice off a chunk of allocated memory, 271 * updating the chunk descriptor accordingly. The size of the slice 272 * is given by the product of the <qty> and <size> parameters. 273 */ 274 void 275 nge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 276 uint32_t qty, uint32_t size) 277 { 278 size_t totsize; 279 280 totsize = qty*size; 281 ASSERT(size > 0); 282 ASSERT(totsize <= chunk->alength); 283 284 *slice = *chunk; 285 slice->nslots = qty; 286 slice->size = size; 287 slice->alength = totsize; 288 289 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 290 chunk->alength -= totsize; 291 chunk->offset += totsize; 292 chunk->cookie.dmac_laddress += totsize; 293 chunk->cookie.dmac_size -= totsize; 294 } 295 296 /* 297 * Allocate an area of memory and a DMA handle for accessing it 298 */ 299 int 300 nge_alloc_dma_mem(nge_t *ngep, size_t memsize, ddi_device_acc_attr_t *attr_p, 301 uint_t dma_flags, dma_area_t *dma_p) 302 { 303 int err; 304 caddr_t va; 305 306 NGE_TRACE(("nge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 307 (void *)ngep, memsize, attr_p, dma_flags, dma_p)); 308 /* 309 * Allocate handle 310 */ 311 err = ddi_dma_alloc_handle(ngep->devinfo, ngep->desc_attr.dma_attr, 312 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 313 if (err != DDI_SUCCESS) 314 goto fail; 315 316 /* 317 * Allocate memory 318 */ 319 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 320 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 321 DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, &dma_p->acc_hdl); 322 if (err != DDI_SUCCESS) 323 goto fail; 324 325 /* 326 * Bind the two together 327 */ 328 dma_p->mem_va = va; 329 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 330 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 331 &dma_p->cookie, &dma_p->ncookies); 332 333 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 334 goto fail; 335 336 dma_p->nslots = ~0U; 337 dma_p->size = ~0U; 338 dma_p->offset = 0; 339 340 return (DDI_SUCCESS); 341 342 fail: 343 nge_free_dma_mem(dma_p); 344 NGE_DEBUG(("nge_alloc_dma_mem: fail to alloc dma memory!")); 345 346 return (DDI_FAILURE); 347 } 348 349 /* 350 * Free one allocated area of DMAable memory 351 */ 352 void 353 nge_free_dma_mem(dma_area_t *dma_p) 354 { 355 if (dma_p->dma_hdl != NULL) { 356 if (dma_p->ncookies) { 357 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 358 dma_p->ncookies = 0; 359 } 360 } 361 if (dma_p->acc_hdl != NULL) { 362 ddi_dma_mem_free(&dma_p->acc_hdl); 363 dma_p->acc_hdl = NULL; 364 } 365 if (dma_p->dma_hdl != NULL) { 366 ddi_dma_free_handle(&dma_p->dma_hdl); 367 dma_p->dma_hdl = NULL; 368 } 369 } 370 371 #define ALLOC_TX_BUF 0x1 372 #define ALLOC_TX_DESC 0x2 373 #define ALLOC_RX_DESC 0x4 374 375 int 376 nge_alloc_bufs(nge_t *ngep) 377 { 378 int err; 379 int split; 380 int progress; 381 size_t txbuffsize; 382 size_t rxdescsize; 383 size_t txdescsize; 384 385 txbuffsize = ngep->tx_desc * ngep->buf_size; 386 rxdescsize = ngep->rx_desc; 387 txdescsize = ngep->tx_desc; 388 rxdescsize *= ngep->desc_attr.rxd_size; 389 txdescsize *= ngep->desc_attr.txd_size; 390 progress = 0; 391 392 NGE_TRACE(("nge_alloc_bufs($%p)", (void *)ngep)); 393 /* 394 * Allocate memory & handles for TX buffers 395 */ 396 ASSERT((txbuffsize % ngep->nge_split) == 0); 397 for (split = 0; split < ngep->nge_split; ++split) { 398 err = nge_alloc_dma_mem(ngep, txbuffsize/ngep->nge_split, 399 &nge_data_accattr, DDI_DMA_WRITE | NGE_DMA_MODE, 400 &ngep->send->buf[split]); 401 if (err != DDI_SUCCESS) 402 goto fail; 403 } 404 405 progress |= ALLOC_TX_BUF; 406 407 /* 408 * Allocate memory & handles for receive return rings and 409 * buffer (producer) descriptor rings 410 */ 411 err = nge_alloc_dma_mem(ngep, rxdescsize, &nge_desc_accattr, 412 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->recv->desc); 413 if (err != DDI_SUCCESS) 414 goto fail; 415 progress |= ALLOC_RX_DESC; 416 417 /* 418 * Allocate memory & handles for TX descriptor rings, 419 */ 420 err = nge_alloc_dma_mem(ngep, txdescsize, &nge_desc_accattr, 421 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->send->desc); 422 if (err != DDI_SUCCESS) 423 goto fail; 424 return (DDI_SUCCESS); 425 426 fail: 427 if (progress & ALLOC_RX_DESC) 428 nge_free_dma_mem(&ngep->recv->desc); 429 if (progress & ALLOC_TX_BUF) { 430 for (split = 0; split < ngep->nge_split; ++split) 431 nge_free_dma_mem(&ngep->send->buf[split]); 432 } 433 434 return (DDI_FAILURE); 435 } 436 437 /* 438 * This routine frees the transmit and receive buffers and descriptors. 439 * Make sure the chip is stopped before calling it! 440 */ 441 void 442 nge_free_bufs(nge_t *ngep) 443 { 444 int split; 445 446 NGE_TRACE(("nge_free_bufs($%p)", (void *)ngep)); 447 448 nge_free_dma_mem(&ngep->recv->desc); 449 nge_free_dma_mem(&ngep->send->desc); 450 451 for (split = 0; split < ngep->nge_split; ++split) 452 nge_free_dma_mem(&ngep->send->buf[split]); 453 } 454 455 /* 456 * Clean up initialisation done above before the memory is freed 457 */ 458 static void 459 nge_fini_send_ring(nge_t *ngep) 460 { 461 uint32_t slot; 462 size_t dmah_num; 463 send_ring_t *srp; 464 sw_tx_sbd_t *ssbdp; 465 466 srp = ngep->send; 467 ssbdp = srp->sw_sbds; 468 469 NGE_TRACE(("nge_fini_send_ring($%p)", (void *)ngep)); 470 471 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 472 473 for (slot = 0; slot < dmah_num; ++slot) { 474 if (srp->dmahndl[slot].hndl) { 475 (void) ddi_dma_unbind_handle(srp->dmahndl[slot].hndl); 476 ddi_dma_free_handle(&srp->dmahndl[slot].hndl); 477 srp->dmahndl[slot].hndl = NULL; 478 srp->dmahndl[slot].next = NULL; 479 } 480 } 481 482 srp->dmah_free.head = NULL; 483 srp->dmah_free.tail = NULL; 484 485 kmem_free(ssbdp, srp->desc.nslots*sizeof (*ssbdp)); 486 487 } 488 489 /* 490 * Initialise the specified Send Ring, using the information in the 491 * <dma_area> descriptors that it contains to set up all the other 492 * fields. This routine should be called only once for each ring. 493 */ 494 static int 495 nge_init_send_ring(nge_t *ngep) 496 { 497 size_t dmah_num; 498 uint32_t nslots; 499 uint32_t err; 500 uint32_t slot; 501 uint32_t split; 502 send_ring_t *srp; 503 sw_tx_sbd_t *ssbdp; 504 dma_area_t desc; 505 dma_area_t pbuf; 506 507 srp = ngep->send; 508 srp->desc.nslots = ngep->tx_desc; 509 nslots = srp->desc.nslots; 510 511 NGE_TRACE(("nge_init_send_ring($%p)", (void *)ngep)); 512 /* 513 * Other one-off initialisation of per-ring data 514 */ 515 srp->ngep = ngep; 516 517 /* 518 * Allocate the array of s/w Send Buffer Descriptors 519 */ 520 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 521 srp->sw_sbds = ssbdp; 522 523 /* 524 * Now initialise each array element once and for all 525 */ 526 desc = srp->desc; 527 for (split = 0; split < ngep->nge_split; ++split) { 528 pbuf = srp->buf[split]; 529 for (slot = 0; slot < nslots/ngep->nge_split; ++ssbdp, ++slot) { 530 nge_slice_chunk(&ssbdp->desc, &desc, 1, 531 ngep->desc_attr.txd_size); 532 nge_slice_chunk(&ssbdp->pbuf, &pbuf, 1, 533 ngep->buf_size); 534 } 535 ASSERT(pbuf.alength == 0); 536 } 537 ASSERT(desc.alength == 0); 538 539 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 540 541 /* preallocate dma handles for tx buffer */ 542 for (slot = 0; slot < dmah_num; ++slot) { 543 544 err = ddi_dma_alloc_handle(ngep->devinfo, 545 ngep->desc_attr.tx_dma_attr, DDI_DMA_DONTWAIT, 546 NULL, &srp->dmahndl[slot].hndl); 547 548 if (err != DDI_SUCCESS) { 549 nge_fini_send_ring(ngep); 550 nge_error(ngep, 551 "nge_init_send_ring: alloc dma handle fails"); 552 return (DDI_FAILURE); 553 } 554 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 555 } 556 557 srp->dmah_free.head = srp->dmahndl; 558 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 559 srp->dmah_free.tail->next = NULL; 560 561 return (DDI_SUCCESS); 562 } 563 564 /* 565 * Intialize the tx recycle pointer and tx sending pointer of tx ring 566 * and set the type of tx's data descriptor by default. 567 */ 568 static void 569 nge_reinit_send_ring(nge_t *ngep) 570 { 571 size_t dmah_num; 572 uint32_t slot; 573 send_ring_t *srp; 574 sw_tx_sbd_t *ssbdp; 575 576 srp = ngep->send; 577 578 /* 579 * Reinitialise control variables ... 580 */ 581 582 srp->tx_hwmark = NGE_DESC_MIN; 583 srp->tx_lwmark = NGE_DESC_MIN; 584 585 srp->tx_next = 0; 586 srp->tx_free = srp->desc.nslots; 587 srp->tc_next = 0; 588 589 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 590 591 for (slot = 0; slot - dmah_num != 0; ++slot) 592 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 593 594 srp->dmah_free.head = srp->dmahndl; 595 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 596 srp->dmah_free.tail->next = NULL; 597 598 /* 599 * Zero and sync all the h/w Send Buffer Descriptors 600 */ 601 for (slot = 0; slot < srp->desc.nslots; ++slot) { 602 ssbdp = &srp->sw_sbds[slot]; 603 ssbdp->flags = HOST_OWN; 604 } 605 606 DMA_ZERO(srp->desc); 607 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 608 } 609 610 /* 611 * Initialize the slot number of rx's ring 612 */ 613 static void 614 nge_init_recv_ring(nge_t *ngep) 615 { 616 recv_ring_t *rrp; 617 618 rrp = ngep->recv; 619 rrp->desc.nslots = ngep->rx_desc; 620 rrp->ngep = ngep; 621 } 622 623 /* 624 * Intialize the rx recycle pointer and rx sending pointer of rx ring 625 */ 626 static void 627 nge_reinit_recv_ring(nge_t *ngep) 628 { 629 recv_ring_t *rrp; 630 631 rrp = ngep->recv; 632 633 /* 634 * Reinitialise control variables ... 635 */ 636 rrp->prod_index = 0; 637 /* 638 * Zero and sync all the h/w Send Buffer Descriptors 639 */ 640 DMA_ZERO(rrp->desc); 641 DMA_SYNC(rrp->desc, DDI_DMA_SYNC_FORDEV); 642 } 643 644 /* 645 * Clean up initialisation done above before the memory is freed 646 */ 647 static void 648 nge_fini_buff_ring(nge_t *ngep) 649 { 650 uint32_t i; 651 buff_ring_t *brp; 652 dma_area_t *bufp; 653 sw_rx_sbd_t *bsbdp; 654 655 brp = ngep->buff; 656 bsbdp = brp->sw_rbds; 657 658 NGE_DEBUG(("nge_fini_buff_ring($%p)", (void *)ngep)); 659 660 mutex_enter(brp->recycle_lock); 661 brp->buf_sign++; 662 mutex_exit(brp->recycle_lock); 663 for (i = 0; i < ngep->rx_desc; i++, ++bsbdp) { 664 if (bsbdp->bufp) { 665 if (bsbdp->bufp->mp) 666 freemsg(bsbdp->bufp->mp); 667 nge_free_dma_mem(bsbdp->bufp); 668 kmem_free(bsbdp->bufp, sizeof (dma_area_t)); 669 bsbdp->bufp = NULL; 670 } 671 } 672 while (brp->free_list != NULL) { 673 bufp = brp->free_list; 674 brp->free_list = bufp->next; 675 bufp->next = NULL; 676 if (bufp->mp) 677 freemsg(bufp->mp); 678 nge_free_dma_mem(bufp); 679 kmem_free(bufp, sizeof (dma_area_t)); 680 } 681 while (brp->recycle_list != NULL) { 682 bufp = brp->recycle_list; 683 brp->recycle_list = bufp->next; 684 bufp->next = NULL; 685 if (bufp->mp) 686 freemsg(bufp->mp); 687 nge_free_dma_mem(bufp); 688 kmem_free(bufp, sizeof (dma_area_t)); 689 } 690 691 692 kmem_free(brp->sw_rbds, (ngep->rx_desc * sizeof (*bsbdp))); 693 brp->sw_rbds = NULL; 694 } 695 696 /* 697 * Intialize the Rx's data ring and free ring 698 */ 699 static int 700 nge_init_buff_ring(nge_t *ngep) 701 { 702 uint32_t err; 703 uint32_t slot; 704 uint32_t nslots_buff; 705 uint32_t nslots_recv; 706 buff_ring_t *brp; 707 recv_ring_t *rrp; 708 dma_area_t desc; 709 dma_area_t *bufp; 710 sw_rx_sbd_t *bsbdp; 711 712 rrp = ngep->recv; 713 brp = ngep->buff; 714 brp->nslots = ngep->rx_buf; 715 brp->rx_bcopy = B_FALSE; 716 nslots_recv = rrp->desc.nslots; 717 nslots_buff = brp->nslots; 718 brp->ngep = ngep; 719 720 NGE_TRACE(("nge_init_buff_ring($%p)", (void *)ngep)); 721 722 /* 723 * Allocate the array of s/w Recv Buffer Descriptors 724 */ 725 bsbdp = kmem_zalloc(nslots_recv *sizeof (*bsbdp), KM_SLEEP); 726 brp->sw_rbds = bsbdp; 727 brp->free_list = NULL; 728 brp->recycle_list = NULL; 729 for (slot = 0; slot < nslots_buff; ++slot) { 730 bufp = kmem_zalloc(sizeof (dma_area_t), KM_SLEEP); 731 err = nge_alloc_dma_mem(ngep, (ngep->buf_size 732 + NGE_HEADROOM), 733 &nge_data_accattr, DDI_DMA_READ | NGE_DMA_MODE, bufp); 734 if (err != DDI_SUCCESS) { 735 kmem_free(bufp, sizeof (dma_area_t)); 736 return (DDI_FAILURE); 737 } 738 739 bufp->alength -= NGE_HEADROOM; 740 bufp->offset += NGE_HEADROOM; 741 bufp->private = (caddr_t)ngep; 742 bufp->rx_recycle.free_func = nge_recv_recycle; 743 bufp->rx_recycle.free_arg = (caddr_t)bufp; 744 bufp->signature = brp->buf_sign; 745 bufp->rx_delivered = B_FALSE; 746 bufp->mp = desballoc(DMA_VPTR(*bufp), 747 ngep->buf_size + NGE_HEADROOM, 748 0, &bufp->rx_recycle); 749 750 if (bufp->mp == NULL) { 751 return (DDI_FAILURE); 752 } 753 bufp->next = brp->free_list; 754 brp->free_list = bufp; 755 } 756 757 /* 758 * Now initialise each array element once and for all 759 */ 760 desc = rrp->desc; 761 for (slot = 0; slot < nslots_recv; ++slot, ++bsbdp) { 762 nge_slice_chunk(&bsbdp->desc, &desc, 1, 763 ngep->desc_attr.rxd_size); 764 bufp = brp->free_list; 765 brp->free_list = bufp->next; 766 bsbdp->bufp = bufp; 767 bsbdp->flags = CONTROLER_OWN; 768 bufp->next = NULL; 769 } 770 771 ASSERT(desc.alength == 0); 772 return (DDI_SUCCESS); 773 } 774 775 /* 776 * Fill the host address of data in rx' descriptor 777 * and initialize free pointers of rx free ring 778 */ 779 static int 780 nge_reinit_buff_ring(nge_t *ngep) 781 { 782 uint32_t slot; 783 uint32_t nslots_recv; 784 buff_ring_t *brp; 785 recv_ring_t *rrp; 786 sw_rx_sbd_t *bsbdp; 787 void *hw_bd_p; 788 789 brp = ngep->buff; 790 rrp = ngep->recv; 791 bsbdp = brp->sw_rbds; 792 nslots_recv = rrp->desc.nslots; 793 for (slot = 0; slot < nslots_recv; ++bsbdp, ++slot) { 794 hw_bd_p = DMA_VPTR(bsbdp->desc); 795 /* 796 * There is a scenario: When the traffic of small tcp 797 * packet is heavy, suspending the tcp traffic will 798 * cause the preallocated buffers for rx not to be 799 * released in time by tcp taffic and cause rx's buffer 800 * pointers not to be refilled in time. 801 * 802 * At this point, if we reinitialize the driver, the bufp 803 * pointer for rx's traffic will be NULL. 804 * So the result of the reinitializion fails. 805 */ 806 if (bsbdp->bufp == NULL) 807 return (DDI_FAILURE); 808 809 ngep->desc_attr.rxd_fill(hw_bd_p, &bsbdp->bufp->cookie, 810 bsbdp->bufp->alength); 811 } 812 return (DDI_SUCCESS); 813 } 814 815 static void 816 nge_init_ring_param_lock(nge_t *ngep) 817 { 818 buff_ring_t *brp; 819 send_ring_t *srp; 820 821 srp = ngep->send; 822 brp = ngep->buff; 823 824 /* Init the locks for send ring */ 825 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 826 DDI_INTR_PRI(ngep->intr_pri)); 827 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 828 DDI_INTR_PRI(ngep->intr_pri)); 829 mutex_init(&srp->dmah_lock, NULL, MUTEX_DRIVER, 830 DDI_INTR_PRI(ngep->intr_pri)); 831 832 /* Init parameters of buffer ring */ 833 brp->free_list = NULL; 834 brp->recycle_list = NULL; 835 brp->rx_hold = 0; 836 brp->buf_sign = 0; 837 838 /* Init recycle list lock */ 839 mutex_init(brp->recycle_lock, NULL, MUTEX_DRIVER, 840 DDI_INTR_PRI(ngep->intr_pri)); 841 } 842 843 int 844 nge_init_rings(nge_t *ngep) 845 { 846 uint32_t err; 847 848 err = nge_init_send_ring(ngep); 849 if (err != DDI_SUCCESS) { 850 return (err); 851 } 852 nge_init_recv_ring(ngep); 853 854 err = nge_init_buff_ring(ngep); 855 if (err != DDI_SUCCESS) { 856 nge_fini_send_ring(ngep); 857 return (DDI_FAILURE); 858 } 859 860 return (err); 861 } 862 863 static int 864 nge_reinit_ring(nge_t *ngep) 865 { 866 int err; 867 868 nge_reinit_recv_ring(ngep); 869 nge_reinit_send_ring(ngep); 870 err = nge_reinit_buff_ring(ngep); 871 return (err); 872 } 873 874 875 void 876 nge_fini_rings(nge_t *ngep) 877 { 878 /* 879 * For receive ring, nothing need to be finished. 880 * So only finish buffer ring and send ring here. 881 */ 882 nge_fini_buff_ring(ngep); 883 nge_fini_send_ring(ngep); 884 } 885 886 /* 887 * Loopback ioctl code 888 */ 889 890 static lb_property_t loopmodes[] = { 891 { normal, "normal", NGE_LOOP_NONE }, 892 { external, "100Mbps", NGE_LOOP_EXTERNAL_100 }, 893 { external, "10Mbps", NGE_LOOP_EXTERNAL_10 }, 894 { internal, "PHY", NGE_LOOP_INTERNAL_PHY }, 895 }; 896 897 enum ioc_reply 898 nge_loop_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 899 { 900 int cmd; 901 uint32_t *lbmp; 902 lb_info_sz_t *lbsp; 903 lb_property_t *lbpp; 904 905 /* 906 * Validate format of ioctl 907 */ 908 if (mp->b_cont == NULL) 909 return (IOC_INVAL); 910 911 cmd = iocp->ioc_cmd; 912 913 switch (cmd) { 914 default: 915 return (IOC_INVAL); 916 917 case LB_GET_INFO_SIZE: 918 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 919 return (IOC_INVAL); 920 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 921 *lbsp = sizeof (loopmodes); 922 return (IOC_REPLY); 923 924 case LB_GET_INFO: 925 if (iocp->ioc_count != sizeof (loopmodes)) 926 return (IOC_INVAL); 927 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 928 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 929 return (IOC_REPLY); 930 931 case LB_GET_MODE: 932 if (iocp->ioc_count != sizeof (uint32_t)) 933 return (IOC_INVAL); 934 lbmp = (uint32_t *)mp->b_cont->b_rptr; 935 *lbmp = ngep->param_loop_mode; 936 return (IOC_REPLY); 937 938 case LB_SET_MODE: 939 if (iocp->ioc_count != sizeof (uint32_t)) 940 return (IOC_INVAL); 941 lbmp = (uint32_t *)mp->b_cont->b_rptr; 942 return (nge_set_loop_mode(ngep, *lbmp)); 943 } 944 } 945 946 #undef NGE_DBG 947 #define NGE_DBG NGE_DBG_NEMO 948 949 950 static void 951 nge_check_desc_prop(nge_t *ngep) 952 { 953 if (ngep->desc_mode != DESC_HOT && ngep->desc_mode != DESC_OFFLOAD) 954 ngep->desc_mode = DESC_HOT; 955 956 if (ngep->desc_mode == DESC_OFFLOAD) { 957 958 ngep->desc_attr = nge_sum_desc; 959 960 } else if (ngep->desc_mode == DESC_HOT) { 961 962 ngep->desc_attr = nge_hot_desc; 963 } 964 } 965 966 /* 967 * nge_get_props -- get the parameters to tune the driver 968 */ 969 static void 970 nge_get_props(nge_t *ngep) 971 { 972 chip_info_t *infop; 973 dev_info_t *devinfo; 974 nge_dev_spec_param_t *dev_param_p; 975 976 devinfo = ngep->devinfo; 977 infop = (chip_info_t *)&ngep->chipinfo; 978 dev_param_p = &ngep->dev_spec_param; 979 980 infop->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 981 DDI_PROP_DONTPASS, clsize_propname, 32); 982 983 infop->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 984 DDI_PROP_DONTPASS, latency_propname, 64); 985 ngep->intr_moderation = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 986 DDI_PROP_DONTPASS, intr_moderation, NGE_SET); 987 ngep->rx_datahwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 988 DDI_PROP_DONTPASS, rx_data_hw, 0x20); 989 ngep->rx_prdlwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 990 DDI_PROP_DONTPASS, rx_prd_lw, 0x4); 991 ngep->rx_prdhwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 992 DDI_PROP_DONTPASS, rx_prd_hw, 0xc); 993 994 ngep->sw_intr_intv = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 995 DDI_PROP_DONTPASS, sw_intr_intv, SWTR_ITC); 996 ngep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 997 DDI_PROP_DONTPASS, debug_propname, NGE_DBG_CHIP); 998 ngep->desc_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 999 DDI_PROP_DONTPASS, nge_desc_mode, dev_param_p->desc_type); 1000 ngep->lowmem_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1001 DDI_PROP_DONTPASS, low_memory_mode, 0); 1002 1003 if (dev_param_p->jumbo) { 1004 ngep->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1005 DDI_PROP_DONTPASS, default_mtu, ETHERMTU); 1006 } else 1007 ngep->default_mtu = ETHERMTU; 1008 1009 if (ngep->default_mtu > ETHERMTU && 1010 ngep->default_mtu <= NGE_MTU_2500) { 1011 ngep->buf_size = NGE_JB2500_BUFSZ; 1012 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1013 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1014 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1015 ngep->nge_split = NGE_SPLIT_256; 1016 } else if (ngep->default_mtu > NGE_MTU_2500 && 1017 ngep->default_mtu <= NGE_MTU_4500) { 1018 ngep->buf_size = NGE_JB4500_BUFSZ; 1019 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1020 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1021 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1022 ngep->nge_split = NGE_SPLIT_256; 1023 } else if (ngep->default_mtu > NGE_MTU_4500 && 1024 ngep->default_mtu <= NGE_MAX_MTU) { 1025 ngep->buf_size = NGE_JB9000_BUFSZ; 1026 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1027 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1028 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1029 ngep->nge_split = NGE_SPLIT_256; 1030 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1031 ngep->default_mtu = NGE_MAX_MTU; 1032 ngep->buf_size = NGE_JB9000_BUFSZ; 1033 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1034 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1035 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1036 ngep->nge_split = NGE_SPLIT_256; 1037 } else if (ngep->lowmem_mode != 0) { 1038 ngep->default_mtu = ETHERMTU; 1039 ngep->buf_size = NGE_STD_BUFSZ; 1040 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1041 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1042 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1043 ngep->nge_split = NGE_SPLIT_32; 1044 } else { 1045 ngep->default_mtu = ETHERMTU; 1046 ngep->buf_size = NGE_STD_BUFSZ; 1047 ngep->tx_desc = dev_param_p->tx_desc_num; 1048 ngep->rx_desc = dev_param_p->rx_desc_num; 1049 ngep->rx_buf = dev_param_p->rx_desc_num * 2; 1050 ngep->nge_split = dev_param_p->nge_split; 1051 } 1052 1053 nge_check_desc_prop(ngep); 1054 } 1055 1056 1057 static int 1058 nge_reset(nge_t *ngep) 1059 { 1060 int err; 1061 nge_mul_addr1 maddr1; 1062 nge_sw_statistics_t *sw_stp; 1063 sw_stp = &ngep->statistics.sw_statistics; 1064 send_ring_t *srp = ngep->send; 1065 1066 ASSERT(mutex_owned(ngep->genlock)); 1067 mutex_enter(srp->tc_lock); 1068 mutex_enter(srp->tx_lock); 1069 1070 nge_tx_recycle_all(ngep); 1071 err = nge_reinit_ring(ngep); 1072 if (err == DDI_FAILURE) { 1073 mutex_exit(srp->tx_lock); 1074 mutex_exit(srp->tc_lock); 1075 return (err); 1076 } 1077 err = nge_chip_reset(ngep); 1078 /* 1079 * Clear the Multicast mac address table 1080 */ 1081 nge_reg_put32(ngep, NGE_MUL_ADDR0, 0); 1082 maddr1.addr_val = nge_reg_get32(ngep, NGE_MUL_ADDR1); 1083 maddr1.addr_bits.addr = 0; 1084 nge_reg_put32(ngep, NGE_MUL_ADDR1, maddr1.addr_val); 1085 1086 mutex_exit(srp->tx_lock); 1087 mutex_exit(srp->tc_lock); 1088 if (err == DDI_FAILURE) 1089 return (err); 1090 ngep->watchdog = 0; 1091 ngep->resched_needed = B_FALSE; 1092 ngep->promisc = B_FALSE; 1093 ngep->param_loop_mode = NGE_LOOP_NONE; 1094 ngep->factotum_flag = 0; 1095 ngep->resched_needed = 0; 1096 ngep->nge_mac_state = NGE_MAC_RESET; 1097 ngep->max_sdu = ngep->default_mtu + ETHER_HEAD_LEN + ETHERFCSL; 1098 ngep->max_sdu += VTAG_SIZE; 1099 ngep->rx_def = 0x16; 1100 1101 /* Clear the software statistics */ 1102 sw_stp->recv_count = 0; 1103 sw_stp->xmit_count = 0; 1104 sw_stp->rbytes = 0; 1105 sw_stp->obytes = 0; 1106 1107 return (DDI_SUCCESS); 1108 } 1109 1110 static void 1111 nge_m_stop(void *arg) 1112 { 1113 nge_t *ngep = arg; /* private device info */ 1114 1115 NGE_TRACE(("nge_m_stop($%p)", arg)); 1116 1117 /* 1118 * Just stop processing, then record new MAC state 1119 */ 1120 mutex_enter(ngep->genlock); 1121 /* If suspended, the adapter is already stopped, just return. */ 1122 if (ngep->suspended) { 1123 ASSERT(ngep->nge_mac_state == NGE_MAC_STOPPED); 1124 mutex_exit(ngep->genlock); 1125 return; 1126 } 1127 rw_enter(ngep->rwlock, RW_WRITER); 1128 1129 (void) nge_chip_stop(ngep, B_FALSE); 1130 ngep->nge_mac_state = NGE_MAC_STOPPED; 1131 1132 /* Recycle all the TX BD */ 1133 nge_tx_recycle_all(ngep); 1134 nge_fini_rings(ngep); 1135 nge_free_bufs(ngep); 1136 1137 NGE_DEBUG(("nge_m_stop($%p) done", arg)); 1138 1139 rw_exit(ngep->rwlock); 1140 mutex_exit(ngep->genlock); 1141 } 1142 1143 static int 1144 nge_m_start(void *arg) 1145 { 1146 int err; 1147 nge_t *ngep = arg; 1148 1149 NGE_TRACE(("nge_m_start($%p)", arg)); 1150 1151 /* 1152 * Start processing and record new MAC state 1153 */ 1154 mutex_enter(ngep->genlock); 1155 /* 1156 * If suspended, don't start, as the resume processing 1157 * will recall this function with the suspended flag off. 1158 */ 1159 if (ngep->suspended) { 1160 mutex_exit(ngep->genlock); 1161 return (EIO); 1162 } 1163 rw_enter(ngep->rwlock, RW_WRITER); 1164 err = nge_alloc_bufs(ngep); 1165 if (err != DDI_SUCCESS) { 1166 nge_problem(ngep, "nge_m_start: DMA buffer allocation failed"); 1167 goto finish; 1168 } 1169 err = nge_init_rings(ngep); 1170 if (err != DDI_SUCCESS) { 1171 nge_free_bufs(ngep); 1172 nge_problem(ngep, "nge_init_rings() failed,err=%x", err); 1173 goto finish; 1174 } 1175 err = nge_restart(ngep); 1176 1177 NGE_DEBUG(("nge_m_start($%p) done", arg)); 1178 finish: 1179 rw_exit(ngep->rwlock); 1180 mutex_exit(ngep->genlock); 1181 1182 return (err == DDI_SUCCESS ? 0 : EIO); 1183 } 1184 1185 static int 1186 nge_m_unicst(void *arg, const uint8_t *macaddr) 1187 { 1188 nge_t *ngep = arg; 1189 1190 NGE_TRACE(("nge_m_unicst($%p)", arg)); 1191 /* 1192 * Remember the new current address in the driver state 1193 * Sync the chip's idea of the address too ... 1194 */ 1195 mutex_enter(ngep->genlock); 1196 1197 ethaddr_copy(macaddr, ngep->cur_uni_addr.addr); 1198 ngep->cur_uni_addr.set = 1; 1199 1200 /* 1201 * If we are suspended, we want to quit now, and not update 1202 * the chip. Doing so might put it in a bad state, but the 1203 * resume will get the unicast address installed. 1204 */ 1205 if (ngep->suspended) { 1206 mutex_exit(ngep->genlock); 1207 return (DDI_SUCCESS); 1208 } 1209 nge_chip_sync(ngep); 1210 1211 NGE_DEBUG(("nge_m_unicst($%p) done", arg)); 1212 mutex_exit(ngep->genlock); 1213 1214 return (0); 1215 } 1216 1217 static int 1218 nge_m_promisc(void *arg, boolean_t on) 1219 { 1220 nge_t *ngep = arg; 1221 1222 NGE_TRACE(("nge_m_promisc($%p)", arg)); 1223 1224 /* 1225 * Store specified mode and pass to chip layer to update h/w 1226 */ 1227 mutex_enter(ngep->genlock); 1228 /* 1229 * If suspended, there is no need to do anything, even 1230 * recording the promiscuious mode is not neccessary, as 1231 * it won't be properly set on resume. Just return failing. 1232 */ 1233 if (ngep->suspended) { 1234 mutex_exit(ngep->genlock); 1235 return (DDI_FAILURE); 1236 } 1237 if (ngep->promisc == on) { 1238 mutex_exit(ngep->genlock); 1239 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1240 return (0); 1241 } 1242 ngep->promisc = on; 1243 ngep->record_promisc = ngep->promisc; 1244 nge_chip_sync(ngep); 1245 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1246 mutex_exit(ngep->genlock); 1247 1248 return (0); 1249 } 1250 1251 static void nge_mulparam(nge_t *ngep) 1252 { 1253 uint8_t number; 1254 ether_addr_t pand; 1255 ether_addr_t por; 1256 mul_item *plist; 1257 1258 for (number = 0; number < ETHERADDRL; number++) { 1259 pand[number] = 0x00; 1260 por[number] = 0x00; 1261 } 1262 for (plist = ngep->pcur_mulist; plist != NULL; plist = plist->next) { 1263 for (number = 0; number < ETHERADDRL; number++) { 1264 pand[number] &= plist->mul_addr[number]; 1265 por[number] |= plist->mul_addr[number]; 1266 } 1267 } 1268 for (number = 0; number < ETHERADDRL; number++) { 1269 ngep->cur_mul_addr.addr[number] 1270 = pand[number] & por[number]; 1271 ngep->cur_mul_mask.addr[number] 1272 = pand [number] | (~por[number]); 1273 } 1274 } 1275 static int 1276 nge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1277 { 1278 boolean_t update; 1279 boolean_t b_eq; 1280 nge_t *ngep = arg; 1281 mul_item *plist; 1282 mul_item *plist_prev; 1283 mul_item *pitem; 1284 1285 NGE_TRACE(("nge_m_multicst($%p, %s, %s)", arg, 1286 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 1287 1288 update = B_FALSE; 1289 plist = plist_prev = NULL; 1290 mutex_enter(ngep->genlock); 1291 if (add) { 1292 if (ngep->pcur_mulist != NULL) { 1293 for (plist = ngep->pcur_mulist; plist != NULL; 1294 plist = plist->next) { 1295 b_eq = ether_eq(plist->mul_addr, mca); 1296 if (b_eq) { 1297 plist->ref_cnt++; 1298 break; 1299 } 1300 plist_prev = plist; 1301 } 1302 } 1303 1304 if (plist == NULL) { 1305 pitem = kmem_zalloc(sizeof (mul_item), KM_SLEEP); 1306 ether_copy(mca, pitem->mul_addr); 1307 pitem ->ref_cnt++; 1308 pitem ->next = NULL; 1309 if (plist_prev == NULL) 1310 ngep->pcur_mulist = pitem; 1311 else 1312 plist_prev->next = pitem; 1313 update = B_TRUE; 1314 } 1315 } else { 1316 if (ngep->pcur_mulist != NULL) { 1317 for (plist = ngep->pcur_mulist; plist != NULL; 1318 plist = plist->next) { 1319 b_eq = ether_eq(plist->mul_addr, mca); 1320 if (b_eq) { 1321 update = B_TRUE; 1322 break; 1323 } 1324 plist_prev = plist; 1325 } 1326 1327 if (update) { 1328 if ((plist_prev == NULL) && 1329 (plist->next == NULL)) 1330 ngep->pcur_mulist = NULL; 1331 else if ((plist_prev == NULL) && 1332 (plist->next != NULL)) 1333 ngep->pcur_mulist = plist->next; 1334 else 1335 plist_prev->next = plist->next; 1336 kmem_free(plist, sizeof (mul_item)); 1337 } 1338 } 1339 } 1340 1341 if (update && !ngep->suspended) { 1342 nge_mulparam(ngep); 1343 nge_chip_sync(ngep); 1344 } 1345 NGE_DEBUG(("nge_m_multicst($%p) done", arg)); 1346 mutex_exit(ngep->genlock); 1347 1348 return (0); 1349 } 1350 1351 static void 1352 nge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1353 { 1354 int err; 1355 int cmd; 1356 nge_t *ngep = arg; 1357 struct iocblk *iocp; 1358 enum ioc_reply status; 1359 boolean_t need_privilege; 1360 1361 /* 1362 * If suspended, we might actually be able to do some of 1363 * these ioctls, but it is harder to make sure they occur 1364 * without actually putting the hardware in an undesireable 1365 * state. So just NAK it. 1366 */ 1367 mutex_enter(ngep->genlock); 1368 if (ngep->suspended) { 1369 miocnak(wq, mp, 0, EINVAL); 1370 mutex_exit(ngep->genlock); 1371 return; 1372 } 1373 mutex_exit(ngep->genlock); 1374 1375 /* 1376 * Validate the command before bothering with the mutex ... 1377 */ 1378 iocp = (struct iocblk *)mp->b_rptr; 1379 iocp->ioc_error = 0; 1380 need_privilege = B_TRUE; 1381 cmd = iocp->ioc_cmd; 1382 1383 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x", cmd)); 1384 switch (cmd) { 1385 default: 1386 NGE_LDB(NGE_DBG_BADIOC, 1387 ("nge_m_ioctl: unknown cmd 0x%x", cmd)); 1388 1389 miocnak(wq, mp, 0, EINVAL); 1390 return; 1391 1392 case NGE_MII_READ: 1393 case NGE_MII_WRITE: 1394 case NGE_SEE_READ: 1395 case NGE_SEE_WRITE: 1396 case NGE_DIAG: 1397 case NGE_PEEK: 1398 case NGE_POKE: 1399 case NGE_PHY_RESET: 1400 case NGE_SOFT_RESET: 1401 case NGE_HARD_RESET: 1402 break; 1403 1404 case LB_GET_INFO_SIZE: 1405 case LB_GET_INFO: 1406 case LB_GET_MODE: 1407 need_privilege = B_FALSE; 1408 break; 1409 case LB_SET_MODE: 1410 break; 1411 } 1412 1413 if (need_privilege) { 1414 /* 1415 * Check for specific net_config privilege. 1416 */ 1417 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1418 if (err != 0) { 1419 NGE_DEBUG(("nge_m_ioctl: rejected cmd 0x%x, err %d", 1420 cmd, err)); 1421 miocnak(wq, mp, 0, err); 1422 return; 1423 } 1424 } 1425 1426 mutex_enter(ngep->genlock); 1427 1428 switch (cmd) { 1429 default: 1430 _NOTE(NOTREACHED) 1431 status = IOC_INVAL; 1432 break; 1433 1434 case NGE_MII_READ: 1435 case NGE_MII_WRITE: 1436 case NGE_SEE_READ: 1437 case NGE_SEE_WRITE: 1438 case NGE_DIAG: 1439 case NGE_PEEK: 1440 case NGE_POKE: 1441 case NGE_PHY_RESET: 1442 case NGE_SOFT_RESET: 1443 case NGE_HARD_RESET: 1444 status = nge_chip_ioctl(ngep, mp, iocp); 1445 break; 1446 1447 case LB_GET_INFO_SIZE: 1448 case LB_GET_INFO: 1449 case LB_GET_MODE: 1450 case LB_SET_MODE: 1451 status = nge_loop_ioctl(ngep, mp, iocp); 1452 break; 1453 1454 } 1455 1456 /* 1457 * Do we need to reprogram the PHY and/or the MAC? 1458 * Do it now, while we still have the mutex. 1459 * 1460 * Note: update the PHY first, 'cos it controls the 1461 * speed/duplex parameters that the MAC code uses. 1462 */ 1463 1464 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x status %d", cmd, status)); 1465 1466 switch (status) { 1467 case IOC_RESTART_REPLY: 1468 case IOC_RESTART_ACK: 1469 (*ngep->physops->phys_update)(ngep); 1470 nge_chip_sync(ngep); 1471 break; 1472 1473 default: 1474 break; 1475 } 1476 1477 mutex_exit(ngep->genlock); 1478 1479 /* 1480 * Finally, decide how to reply 1481 */ 1482 switch (status) { 1483 1484 default: 1485 case IOC_INVAL: 1486 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1487 EINVAL : iocp->ioc_error); 1488 break; 1489 1490 case IOC_DONE: 1491 break; 1492 1493 case IOC_RESTART_ACK: 1494 case IOC_ACK: 1495 miocack(wq, mp, 0, 0); 1496 break; 1497 1498 case IOC_RESTART_REPLY: 1499 case IOC_REPLY: 1500 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1501 M_IOCACK : M_IOCNAK; 1502 qreply(wq, mp); 1503 break; 1504 } 1505 } 1506 1507 static boolean_t 1508 nge_param_locked(mac_prop_id_t pr_num) 1509 { 1510 /* 1511 * All adv_* parameters are locked (read-only) while 1512 * the device is in any sort of loopback mode ... 1513 */ 1514 switch (pr_num) { 1515 case MAC_PROP_ADV_1000FDX_CAP: 1516 case MAC_PROP_EN_1000FDX_CAP: 1517 case MAC_PROP_ADV_1000HDX_CAP: 1518 case MAC_PROP_EN_1000HDX_CAP: 1519 case MAC_PROP_ADV_100FDX_CAP: 1520 case MAC_PROP_EN_100FDX_CAP: 1521 case MAC_PROP_ADV_100HDX_CAP: 1522 case MAC_PROP_EN_100HDX_CAP: 1523 case MAC_PROP_ADV_10FDX_CAP: 1524 case MAC_PROP_EN_10FDX_CAP: 1525 case MAC_PROP_ADV_10HDX_CAP: 1526 case MAC_PROP_EN_10HDX_CAP: 1527 case MAC_PROP_AUTONEG: 1528 case MAC_PROP_FLOWCTRL: 1529 return (B_TRUE); 1530 } 1531 return (B_FALSE); 1532 } 1533 1534 /* 1535 * callback functions for set/get of properties 1536 */ 1537 static int 1538 nge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1539 uint_t pr_valsize, const void *pr_val) 1540 { 1541 nge_t *ngep = barg; 1542 int err = 0; 1543 uint32_t cur_mtu, new_mtu; 1544 link_flowctrl_t fl; 1545 1546 mutex_enter(ngep->genlock); 1547 if (ngep->param_loop_mode != NGE_LOOP_NONE && 1548 nge_param_locked(pr_num)) { 1549 /* 1550 * All adv_* parameters are locked (read-only) 1551 * while the device is in any sort of loopback mode. 1552 */ 1553 mutex_exit(ngep->genlock); 1554 return (EBUSY); 1555 } 1556 switch (pr_num) { 1557 case MAC_PROP_EN_1000FDX_CAP: 1558 ngep->param_en_1000fdx = *(uint8_t *)pr_val; 1559 ngep->param_adv_1000fdx = *(uint8_t *)pr_val; 1560 goto reprogram; 1561 case MAC_PROP_EN_100FDX_CAP: 1562 ngep->param_en_100fdx = *(uint8_t *)pr_val; 1563 ngep->param_adv_100fdx = *(uint8_t *)pr_val; 1564 goto reprogram; 1565 case MAC_PROP_EN_100HDX_CAP: 1566 ngep->param_en_100hdx = *(uint8_t *)pr_val; 1567 ngep->param_adv_100hdx = *(uint8_t *)pr_val; 1568 goto reprogram; 1569 case MAC_PROP_EN_10FDX_CAP: 1570 ngep->param_en_10fdx = *(uint8_t *)pr_val; 1571 ngep->param_adv_10fdx = *(uint8_t *)pr_val; 1572 goto reprogram; 1573 case MAC_PROP_EN_10HDX_CAP: 1574 ngep->param_en_10hdx = *(uint8_t *)pr_val; 1575 ngep->param_adv_10hdx = *(uint8_t *)pr_val; 1576 reprogram: 1577 (*ngep->physops->phys_update)(ngep); 1578 nge_chip_sync(ngep); 1579 break; 1580 1581 case MAC_PROP_ADV_1000FDX_CAP: 1582 case MAC_PROP_ADV_1000HDX_CAP: 1583 case MAC_PROP_ADV_100FDX_CAP: 1584 case MAC_PROP_ADV_100HDX_CAP: 1585 case MAC_PROP_ADV_10FDX_CAP: 1586 case MAC_PROP_ADV_10HDX_CAP: 1587 case MAC_PROP_STATUS: 1588 case MAC_PROP_SPEED: 1589 case MAC_PROP_DUPLEX: 1590 case MAC_PROP_EN_1000HDX_CAP: 1591 err = ENOTSUP; /* read-only prop. Can't set this */ 1592 break; 1593 case MAC_PROP_AUTONEG: 1594 ngep->param_adv_autoneg = *(uint8_t *)pr_val; 1595 (*ngep->physops->phys_update)(ngep); 1596 nge_chip_sync(ngep); 1597 break; 1598 case MAC_PROP_MTU: 1599 cur_mtu = ngep->default_mtu; 1600 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 1601 if (new_mtu == cur_mtu) { 1602 err = 0; 1603 break; 1604 } 1605 if (new_mtu < ETHERMTU || 1606 new_mtu > NGE_MAX_MTU) { 1607 err = EINVAL; 1608 break; 1609 } 1610 if ((new_mtu > ETHERMTU) && 1611 (!ngep->dev_spec_param.jumbo)) { 1612 err = EINVAL; 1613 break; 1614 } 1615 if (ngep->nge_mac_state == NGE_MAC_STARTED) { 1616 err = EBUSY; 1617 break; 1618 } 1619 1620 ngep->default_mtu = new_mtu; 1621 if (ngep->default_mtu > ETHERMTU && 1622 ngep->default_mtu <= NGE_MTU_2500) { 1623 ngep->buf_size = NGE_JB2500_BUFSZ; 1624 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1625 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1626 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1627 ngep->nge_split = NGE_SPLIT_256; 1628 } else if (ngep->default_mtu > NGE_MTU_2500 && 1629 ngep->default_mtu <= NGE_MTU_4500) { 1630 ngep->buf_size = NGE_JB4500_BUFSZ; 1631 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1632 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1633 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1634 ngep->nge_split = NGE_SPLIT_256; 1635 } else if (ngep->default_mtu > NGE_MTU_4500 && 1636 ngep->default_mtu <= NGE_MAX_MTU) { 1637 ngep->buf_size = NGE_JB9000_BUFSZ; 1638 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1639 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1640 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1641 ngep->nge_split = NGE_SPLIT_256; 1642 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1643 ngep->default_mtu = NGE_MAX_MTU; 1644 ngep->buf_size = NGE_JB9000_BUFSZ; 1645 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1646 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1647 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1648 ngep->nge_split = NGE_SPLIT_256; 1649 } else if (ngep->lowmem_mode != 0) { 1650 ngep->default_mtu = ETHERMTU; 1651 ngep->buf_size = NGE_STD_BUFSZ; 1652 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1653 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1654 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1655 ngep->nge_split = NGE_SPLIT_32; 1656 } else { 1657 ngep->default_mtu = ETHERMTU; 1658 ngep->buf_size = NGE_STD_BUFSZ; 1659 ngep->tx_desc = 1660 ngep->dev_spec_param.tx_desc_num; 1661 ngep->rx_desc = 1662 ngep->dev_spec_param.rx_desc_num; 1663 ngep->rx_buf = 1664 ngep->dev_spec_param.rx_desc_num * 2; 1665 ngep->nge_split = 1666 ngep->dev_spec_param.nge_split; 1667 } 1668 1669 err = mac_maxsdu_update(ngep->mh, ngep->default_mtu); 1670 1671 break; 1672 case MAC_PROP_FLOWCTRL: 1673 bcopy(pr_val, &fl, sizeof (fl)); 1674 switch (fl) { 1675 default: 1676 err = ENOTSUP; 1677 break; 1678 case LINK_FLOWCTRL_NONE: 1679 ngep->param_adv_pause = 0; 1680 ngep->param_adv_asym_pause = 0; 1681 1682 ngep->param_link_rx_pause = B_FALSE; 1683 ngep->param_link_tx_pause = B_FALSE; 1684 break; 1685 case LINK_FLOWCTRL_RX: 1686 if (!((ngep->param_lp_pause == 0) && 1687 (ngep->param_lp_asym_pause == 1))) { 1688 err = EINVAL; 1689 break; 1690 } 1691 ngep->param_adv_pause = 1; 1692 ngep->param_adv_asym_pause = 1; 1693 1694 ngep->param_link_rx_pause = B_TRUE; 1695 ngep->param_link_tx_pause = B_FALSE; 1696 break; 1697 case LINK_FLOWCTRL_TX: 1698 if (!((ngep->param_lp_pause == 1) && 1699 (ngep->param_lp_asym_pause == 1))) { 1700 err = EINVAL; 1701 break; 1702 } 1703 ngep->param_adv_pause = 0; 1704 ngep->param_adv_asym_pause = 1; 1705 1706 ngep->param_link_rx_pause = B_FALSE; 1707 ngep->param_link_tx_pause = B_TRUE; 1708 break; 1709 case LINK_FLOWCTRL_BI: 1710 if (ngep->param_lp_pause != 1) { 1711 err = EINVAL; 1712 break; 1713 } 1714 ngep->param_adv_pause = 1; 1715 1716 ngep->param_link_rx_pause = B_TRUE; 1717 ngep->param_link_tx_pause = B_TRUE; 1718 break; 1719 } 1720 1721 if (err == 0) { 1722 (*ngep->physops->phys_update)(ngep); 1723 nge_chip_sync(ngep); 1724 } 1725 1726 break; 1727 case MAC_PROP_PRIVATE: 1728 err = nge_set_priv_prop(ngep, pr_name, pr_valsize, 1729 pr_val); 1730 if (err == 0) { 1731 (*ngep->physops->phys_update)(ngep); 1732 nge_chip_sync(ngep); 1733 } 1734 break; 1735 default: 1736 err = ENOTSUP; 1737 } 1738 mutex_exit(ngep->genlock); 1739 return (err); 1740 } 1741 1742 static int 1743 nge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1744 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 1745 { 1746 nge_t *ngep = barg; 1747 int err = 0; 1748 link_flowctrl_t fl; 1749 uint64_t speed; 1750 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 1751 1752 if (pr_valsize == 0) 1753 return (EINVAL); 1754 1755 bzero(pr_val, pr_valsize); 1756 switch (pr_num) { 1757 case MAC_PROP_DUPLEX: 1758 if (pr_valsize >= sizeof (link_duplex_t)) { 1759 bcopy(&ngep->param_link_duplex, pr_val, 1760 sizeof (link_duplex_t)); 1761 } else 1762 err = EINVAL; 1763 break; 1764 case MAC_PROP_SPEED: 1765 if (pr_valsize >= sizeof (uint64_t)) { 1766 speed = ngep->param_link_speed * 1000000ull; 1767 bcopy(&speed, pr_val, sizeof (speed)); 1768 } else 1769 err = EINVAL; 1770 break; 1771 case MAC_PROP_AUTONEG: 1772 if (is_default) { 1773 *(uint8_t *)pr_val = 1; 1774 } else { 1775 *(uint8_t *)pr_val = ngep->param_adv_autoneg; 1776 } 1777 break; 1778 case MAC_PROP_FLOWCTRL: 1779 if (pr_valsize >= sizeof (link_flowctrl_t)) { 1780 if (pr_flags & MAC_PROP_DEFAULT) { 1781 fl = LINK_FLOWCTRL_BI; 1782 bcopy(&fl, pr_val, sizeof (fl)); 1783 break; 1784 } 1785 if (ngep->param_link_rx_pause && 1786 !ngep->param_link_tx_pause) 1787 fl = LINK_FLOWCTRL_RX; 1788 1789 if (!ngep->param_link_rx_pause && 1790 !ngep->param_link_tx_pause) 1791 fl = LINK_FLOWCTRL_NONE; 1792 1793 if (!ngep->param_link_rx_pause && 1794 ngep->param_link_tx_pause) 1795 fl = LINK_FLOWCTRL_TX; 1796 1797 if (ngep->param_link_rx_pause && 1798 ngep->param_link_tx_pause) 1799 fl = LINK_FLOWCTRL_BI; 1800 bcopy(&fl, pr_val, sizeof (fl)); 1801 } else 1802 err = EINVAL; 1803 break; 1804 case MAC_PROP_ADV_1000FDX_CAP: 1805 if (is_default) { 1806 *(uint8_t *)pr_val = 1; 1807 } else { 1808 *(uint8_t *)pr_val = ngep->param_adv_1000fdx; 1809 } 1810 break; 1811 case MAC_PROP_EN_1000FDX_CAP: 1812 if (is_default) { 1813 *(uint8_t *)pr_val = 1; 1814 } else { 1815 *(uint8_t *)pr_val = ngep->param_en_1000fdx; 1816 } 1817 break; 1818 case MAC_PROP_ADV_1000HDX_CAP: 1819 if (is_default) { 1820 *(uint8_t *)pr_val = 0; 1821 } else { 1822 *(uint8_t *)pr_val = ngep->param_adv_1000hdx; 1823 } 1824 break; 1825 case MAC_PROP_EN_1000HDX_CAP: 1826 if (is_default) { 1827 *(uint8_t *)pr_val = 0; 1828 } else { 1829 *(uint8_t *)pr_val = ngep->param_en_1000hdx; 1830 } 1831 break; 1832 case MAC_PROP_ADV_100FDX_CAP: 1833 if (is_default) { 1834 *(uint8_t *)pr_val = 1; 1835 } else { 1836 *(uint8_t *)pr_val = ngep->param_adv_100fdx; 1837 } 1838 break; 1839 case MAC_PROP_EN_100FDX_CAP: 1840 if (is_default) { 1841 *(uint8_t *)pr_val = 1; 1842 } else { 1843 *(uint8_t *)pr_val = ngep->param_en_100fdx; 1844 } 1845 break; 1846 case MAC_PROP_ADV_100HDX_CAP: 1847 if (is_default) { 1848 *(uint8_t *)pr_val = 1; 1849 } else { 1850 *(uint8_t *)pr_val = ngep->param_adv_100hdx; 1851 } 1852 break; 1853 case MAC_PROP_EN_100HDX_CAP: 1854 if (is_default) { 1855 *(uint8_t *)pr_val = 1; 1856 } else { 1857 *(uint8_t *)pr_val = ngep->param_en_100hdx; 1858 } 1859 break; 1860 case MAC_PROP_ADV_10FDX_CAP: 1861 if (is_default) { 1862 *(uint8_t *)pr_val = 1; 1863 } else { 1864 *(uint8_t *)pr_val = ngep->param_adv_10fdx; 1865 } 1866 break; 1867 case MAC_PROP_EN_10FDX_CAP: 1868 if (is_default) { 1869 *(uint8_t *)pr_val = 1; 1870 } else { 1871 *(uint8_t *)pr_val = ngep->param_en_10fdx; 1872 } 1873 break; 1874 case MAC_PROP_ADV_10HDX_CAP: 1875 if (is_default) { 1876 *(uint8_t *)pr_val = 1; 1877 } else { 1878 *(uint8_t *)pr_val = ngep->param_adv_10hdx; 1879 } 1880 break; 1881 case MAC_PROP_EN_10HDX_CAP: 1882 if (is_default) { 1883 *(uint8_t *)pr_val = 1; 1884 } else { 1885 *(uint8_t *)pr_val = ngep->param_en_10hdx; 1886 } 1887 break; 1888 case MAC_PROP_ADV_100T4_CAP: 1889 case MAC_PROP_EN_100T4_CAP: 1890 *(uint8_t *)pr_val = 0; 1891 break; 1892 case MAC_PROP_PRIVATE: 1893 err = nge_get_priv_prop(ngep, pr_name, pr_flags, 1894 pr_valsize, pr_val); 1895 break; 1896 default: 1897 err = ENOTSUP; 1898 } 1899 return (err); 1900 } 1901 1902 /* ARGSUSED */ 1903 static int 1904 nge_set_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_valsize, 1905 const void *pr_val) 1906 { 1907 int err = 0; 1908 long result; 1909 1910 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 1911 if (pr_val == NULL) { 1912 err = EINVAL; 1913 return (err); 1914 } 1915 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1916 if (result < 0 || result > NGE_MAX_SDU) { 1917 err = EINVAL; 1918 } else { 1919 ngep->param_txbcopy_threshold = (uint32_t)result; 1920 goto reprogram; 1921 } 1922 return (err); 1923 } 1924 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 1925 if (pr_val == NULL) { 1926 err = EINVAL; 1927 return (err); 1928 } 1929 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1930 if (result < 0 || result > NGE_MAX_SDU) { 1931 err = EINVAL; 1932 } else { 1933 ngep->param_rxbcopy_threshold = (uint32_t)result; 1934 goto reprogram; 1935 } 1936 return (err); 1937 } 1938 if (strcmp(pr_name, "_recv_max_packet") == 0) { 1939 if (pr_val == NULL) { 1940 err = EINVAL; 1941 return (err); 1942 } 1943 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1944 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1945 err = EINVAL; 1946 } else { 1947 ngep->param_recv_max_packet = (uint32_t)result; 1948 goto reprogram; 1949 } 1950 return (err); 1951 } 1952 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 1953 if (pr_val == NULL) { 1954 err = EINVAL; 1955 return (err); 1956 } 1957 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1958 if (result < 0 || result > 10000) { 1959 err = EINVAL; 1960 } else { 1961 ngep->param_poll_quiet_time = (uint32_t)result; 1962 goto reprogram; 1963 } 1964 return (err); 1965 } 1966 if (strcmp(pr_name, "_poll_busy_time") == 0) { 1967 if (pr_val == NULL) { 1968 err = EINVAL; 1969 return (err); 1970 } 1971 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1972 if (result < 0 || result > 10000) { 1973 err = EINVAL; 1974 } else { 1975 ngep->param_poll_busy_time = (uint32_t)result; 1976 goto reprogram; 1977 } 1978 return (err); 1979 } 1980 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 1981 if (pr_val == NULL) { 1982 err = EINVAL; 1983 return (err); 1984 } 1985 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1986 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1987 err = EINVAL; 1988 } else { 1989 ngep->param_rx_intr_hwater = (uint32_t)result; 1990 goto reprogram; 1991 } 1992 return (err); 1993 } 1994 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 1995 if (pr_val == NULL) { 1996 err = EINVAL; 1997 return (err); 1998 } 1999 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2000 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 2001 err = EINVAL; 2002 } else { 2003 ngep->param_rx_intr_lwater = (uint32_t)result; 2004 goto reprogram; 2005 } 2006 return (err); 2007 } 2008 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2009 if (pr_val == NULL) { 2010 err = EINVAL; 2011 return (err); 2012 } 2013 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2014 if (result < 1 || result > 10000) { 2015 err = EINVAL; 2016 } else { 2017 ngep->param_tx_n_intr = (uint32_t)result; 2018 goto reprogram; 2019 } 2020 return (err); 2021 } 2022 2023 err = ENOTSUP; 2024 return (err); 2025 2026 reprogram: 2027 if (err == 0) { 2028 (*ngep->physops->phys_update)(ngep); 2029 nge_chip_sync(ngep); 2030 } 2031 2032 return (err); 2033 } 2034 2035 static int 2036 nge_get_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_flags, 2037 uint_t pr_valsize, void *pr_val) 2038 { 2039 int err = ENOTSUP; 2040 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 2041 int value; 2042 2043 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 2044 value = (is_default ? 1 : ngep->param_adv_pause); 2045 err = 0; 2046 goto done; 2047 } 2048 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 2049 value = (is_default ? 1 : ngep->param_adv_asym_pause); 2050 err = 0; 2051 goto done; 2052 } 2053 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2054 value = (is_default ? NGE_TX_COPY_SIZE : 2055 ngep->param_txbcopy_threshold); 2056 err = 0; 2057 goto done; 2058 } 2059 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2060 value = (is_default ? NGE_RX_COPY_SIZE : 2061 ngep->param_rxbcopy_threshold); 2062 err = 0; 2063 goto done; 2064 } 2065 if (strcmp(pr_name, "_recv_max_packet") == 0) { 2066 value = (is_default ? 128 : ngep->param_recv_max_packet); 2067 err = 0; 2068 goto done; 2069 } 2070 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 2071 value = (is_default ? NGE_POLL_QUIET_TIME : 2072 ngep->param_poll_quiet_time); 2073 err = 0; 2074 goto done; 2075 } 2076 if (strcmp(pr_name, "_poll_busy_time") == 0) { 2077 value = (is_default ? NGE_POLL_BUSY_TIME : 2078 ngep->param_poll_busy_time); 2079 err = 0; 2080 goto done; 2081 } 2082 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 2083 value = (is_default ? 1 : ngep->param_rx_intr_hwater); 2084 err = 0; 2085 goto done; 2086 } 2087 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 2088 value = (is_default ? 8 : ngep->param_rx_intr_lwater); 2089 err = 0; 2090 goto done; 2091 } 2092 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2093 value = (is_default ? NGE_TX_N_INTR : 2094 ngep->param_tx_n_intr); 2095 err = 0; 2096 goto done; 2097 } 2098 2099 done: 2100 if (err == 0) { 2101 (void) snprintf(pr_val, pr_valsize, "%d", value); 2102 } 2103 return (err); 2104 } 2105 2106 /* ARGSUSED */ 2107 static boolean_t 2108 nge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2109 { 2110 nge_t *ngep = arg; 2111 nge_dev_spec_param_t *dev_param_p; 2112 2113 dev_param_p = &ngep->dev_spec_param; 2114 2115 switch (cap) { 2116 case MAC_CAPAB_HCKSUM: { 2117 uint32_t *hcksum_txflags = cap_data; 2118 2119 if (dev_param_p->tx_hw_checksum) { 2120 *hcksum_txflags = dev_param_p->tx_hw_checksum; 2121 } else 2122 return (B_FALSE); 2123 break; 2124 } 2125 case MAC_CAPAB_POLL: 2126 /* 2127 * There's nothing for us to fill in, simply returning 2128 * B_TRUE, stating that we support polling is sufficient. 2129 */ 2130 break; 2131 default: 2132 return (B_FALSE); 2133 } 2134 return (B_TRUE); 2135 } 2136 2137 #undef NGE_DBG 2138 #define NGE_DBG NGE_DBG_INIT /* debug flag for this code */ 2139 int 2140 nge_restart(nge_t *ngep) 2141 { 2142 int err = 0; 2143 err = nge_reset(ngep); 2144 /* write back the promisc setting */ 2145 ngep->promisc = ngep->record_promisc; 2146 nge_chip_sync(ngep); 2147 if (!err) 2148 err = nge_chip_start(ngep); 2149 2150 if (err) { 2151 ngep->nge_mac_state = NGE_MAC_STOPPED; 2152 return (DDI_FAILURE); 2153 } else { 2154 ngep->nge_mac_state = NGE_MAC_STARTED; 2155 return (DDI_SUCCESS); 2156 } 2157 } 2158 2159 void 2160 nge_wake_factotum(nge_t *ngep) 2161 { 2162 mutex_enter(ngep->softlock); 2163 if (ngep->factotum_flag == 0) { 2164 ngep->factotum_flag = 1; 2165 (void) ddi_intr_trigger_softint(ngep->factotum_hdl, NULL); 2166 } 2167 mutex_exit(ngep->softlock); 2168 } 2169 2170 /* 2171 * High-level cyclic handler 2172 * 2173 * This routine schedules a (low-level) softint callback to the 2174 * factotum. 2175 */ 2176 2177 static void 2178 nge_chip_cyclic(void *arg) 2179 { 2180 nge_t *ngep; 2181 2182 ngep = (nge_t *)arg; 2183 2184 switch (ngep->nge_chip_state) { 2185 default: 2186 return; 2187 2188 case NGE_CHIP_RUNNING: 2189 break; 2190 2191 case NGE_CHIP_FAULT: 2192 case NGE_CHIP_ERROR: 2193 break; 2194 } 2195 2196 nge_wake_factotum(ngep); 2197 } 2198 2199 static void 2200 nge_unattach(nge_t *ngep) 2201 { 2202 send_ring_t *srp; 2203 buff_ring_t *brp; 2204 2205 srp = ngep->send; 2206 brp = ngep->buff; 2207 NGE_TRACE(("nge_unattach($%p)", (void *)ngep)); 2208 2209 /* 2210 * Flag that no more activity may be initiated 2211 */ 2212 ngep->progress &= ~PROGRESS_READY; 2213 ngep->nge_mac_state = NGE_MAC_UNATTACH; 2214 2215 /* 2216 * Quiesce the PHY and MAC (leave it reset but still powered). 2217 * Clean up and free all NGE data structures 2218 */ 2219 if (ngep->periodic_id != NULL) { 2220 ddi_periodic_delete(ngep->periodic_id); 2221 ngep->periodic_id = NULL; 2222 } 2223 2224 if (ngep->progress & PROGRESS_KSTATS) 2225 nge_fini_kstats(ngep); 2226 2227 if (ngep->progress & PROGRESS_HWINT) { 2228 mutex_enter(ngep->genlock); 2229 nge_restore_mac_addr(ngep); 2230 (void) nge_chip_stop(ngep, B_FALSE); 2231 mutex_exit(ngep->genlock); 2232 } 2233 2234 if (ngep->progress & PROGRESS_SWINT) 2235 nge_rem_intrs(ngep); 2236 2237 if (ngep->progress & PROGRESS_FACTOTUM) 2238 (void) ddi_intr_remove_softint(ngep->factotum_hdl); 2239 2240 if (ngep->progress & PROGRESS_RESCHED) 2241 (void) ddi_intr_remove_softint(ngep->resched_hdl); 2242 2243 if (ngep->progress & PROGRESS_INTR) { 2244 mutex_destroy(srp->tx_lock); 2245 mutex_destroy(srp->tc_lock); 2246 mutex_destroy(&srp->dmah_lock); 2247 mutex_destroy(brp->recycle_lock); 2248 2249 mutex_destroy(ngep->genlock); 2250 mutex_destroy(ngep->softlock); 2251 rw_destroy(ngep->rwlock); 2252 } 2253 2254 if (ngep->progress & PROGRESS_REGS) 2255 ddi_regs_map_free(&ngep->io_handle); 2256 2257 if (ngep->progress & PROGRESS_CFG) 2258 pci_config_teardown(&ngep->cfg_handle); 2259 2260 ddi_remove_minor_node(ngep->devinfo, NULL); 2261 2262 kmem_free(ngep, sizeof (*ngep)); 2263 } 2264 2265 static int 2266 nge_resume(dev_info_t *devinfo) 2267 { 2268 nge_t *ngep; 2269 chip_info_t *infop; 2270 int err; 2271 2272 ASSERT(devinfo != NULL); 2273 2274 ngep = ddi_get_driver_private(devinfo); 2275 err = 0; 2276 2277 /* 2278 * If there are state inconsistancies, this is bad. Returning 2279 * DDI_FAILURE here will eventually cause the machine to panic, 2280 * so it is best done here so that there is a possibility of 2281 * debugging the problem. 2282 */ 2283 if (ngep == NULL) 2284 cmn_err(CE_PANIC, 2285 "nge: ngep returned from ddi_get_driver_private was NULL"); 2286 infop = (chip_info_t *)&ngep->chipinfo; 2287 2288 if (ngep->devinfo != devinfo) 2289 cmn_err(CE_PANIC, 2290 "nge: passed devinfo not the same as saved devinfo"); 2291 2292 mutex_enter(ngep->genlock); 2293 rw_enter(ngep->rwlock, RW_WRITER); 2294 2295 /* 2296 * Fetch the config space. Even though we have most of it cached, 2297 * some values *might* change across a suspend/resume. 2298 */ 2299 nge_chip_cfg_init(ngep, infop, B_FALSE); 2300 2301 /* 2302 * Only in one case, this conditional branch can be executed: the port 2303 * hasn't been plumbed. 2304 */ 2305 if (ngep->suspended == B_FALSE) { 2306 rw_exit(ngep->rwlock); 2307 mutex_exit(ngep->genlock); 2308 return (DDI_SUCCESS); 2309 } 2310 2311 nge_tx_recycle_all(ngep); 2312 err = nge_reinit_ring(ngep); 2313 if (!err) { 2314 err = nge_chip_reset(ngep); 2315 if (!err) 2316 err = nge_chip_start(ngep); 2317 } 2318 2319 if (err) { 2320 /* 2321 * We note the failure, but return success, as the 2322 * system is still usable without this controller. 2323 */ 2324 cmn_err(CE_WARN, "nge: resume: failed to restart controller"); 2325 } else { 2326 ngep->nge_mac_state = NGE_MAC_STARTED; 2327 } 2328 ngep->suspended = B_FALSE; 2329 2330 rw_exit(ngep->rwlock); 2331 mutex_exit(ngep->genlock); 2332 2333 return (DDI_SUCCESS); 2334 } 2335 2336 /* 2337 * attach(9E) -- Attach a device to the system 2338 * 2339 * Called once for each board successfully probed. 2340 */ 2341 static int 2342 nge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2343 { 2344 int err; 2345 int i; 2346 int instance; 2347 caddr_t regs; 2348 nge_t *ngep; 2349 chip_info_t *infop; 2350 mac_register_t *macp; 2351 2352 switch (cmd) { 2353 default: 2354 return (DDI_FAILURE); 2355 2356 case DDI_RESUME: 2357 return (nge_resume(devinfo)); 2358 2359 case DDI_ATTACH: 2360 break; 2361 } 2362 2363 ngep = kmem_zalloc(sizeof (*ngep), KM_SLEEP); 2364 instance = ddi_get_instance(devinfo); 2365 ddi_set_driver_private(devinfo, ngep); 2366 ngep->devinfo = devinfo; 2367 2368 (void) snprintf(ngep->ifname, sizeof (ngep->ifname), "%s%d", 2369 NGE_DRIVER_NAME, instance); 2370 err = pci_config_setup(devinfo, &ngep->cfg_handle); 2371 if (err != DDI_SUCCESS) { 2372 nge_problem(ngep, "nge_attach: pci_config_setup() failed"); 2373 goto attach_fail; 2374 } 2375 /* 2376 * param_txbcopy_threshold and param_rxbcopy_threshold are tx/rx bcopy 2377 * thresholds. Bounds: min 0, max NGE_MAX_SDU 2378 */ 2379 ngep->param_txbcopy_threshold = NGE_TX_COPY_SIZE; 2380 ngep->param_rxbcopy_threshold = NGE_RX_COPY_SIZE; 2381 2382 /* 2383 * param_recv_max_packet is max packet received per interupt. 2384 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024 2385 */ 2386 ngep->param_recv_max_packet = 128; 2387 2388 /* 2389 * param_poll_quiet_time and param_poll_busy_time are quiet/busy time 2390 * switch from per packet interrupt to polling interrupt. 2391 * Bounds: min 0, max 10000 2392 */ 2393 ngep->param_poll_quiet_time = NGE_POLL_QUIET_TIME; 2394 ngep->param_poll_busy_time = NGE_POLL_BUSY_TIME; 2395 2396 /* 2397 * param_rx_intr_hwater/param_rx_intr_lwater: ackets received 2398 * to trigger the poll_quiet_time/poll_busy_time counter. 2399 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024. 2400 */ 2401 ngep->param_rx_intr_hwater = 1; 2402 ngep->param_rx_intr_lwater = 8; 2403 2404 /* 2405 * param_tx_n_intr: Per N tx packets to do tx recycle in poll mode. 2406 * Bounds: min 1, max 10000. 2407 */ 2408 ngep->param_tx_n_intr = NGE_TX_N_INTR; 2409 2410 infop = (chip_info_t *)&ngep->chipinfo; 2411 nge_chip_cfg_init(ngep, infop, B_FALSE); 2412 nge_init_dev_spec_param(ngep); 2413 nge_get_props(ngep); 2414 ngep->progress |= PROGRESS_CFG; 2415 2416 err = ddi_regs_map_setup(devinfo, NGE_PCI_OPREGS_RNUMBER, 2417 ®s, 0, 0, &nge_reg_accattr, &ngep->io_handle); 2418 if (err != DDI_SUCCESS) { 2419 nge_problem(ngep, "nge_attach: ddi_regs_map_setup() failed"); 2420 goto attach_fail; 2421 } 2422 ngep->io_regs = regs; 2423 ngep->progress |= PROGRESS_REGS; 2424 2425 err = nge_register_intrs_and_init_locks(ngep); 2426 if (err != DDI_SUCCESS) { 2427 nge_problem(ngep, "nge_attach:" 2428 " register intrs and init locks failed"); 2429 goto attach_fail; 2430 } 2431 nge_init_ring_param_lock(ngep); 2432 ngep->progress |= PROGRESS_INTR; 2433 2434 mutex_enter(ngep->genlock); 2435 2436 /* 2437 * Initialise link state variables 2438 * Stop, reset & reinitialise the chip. 2439 * Initialise the (internal) PHY. 2440 */ 2441 nge_phys_init(ngep); 2442 err = nge_chip_reset(ngep); 2443 if (err != DDI_SUCCESS) { 2444 nge_problem(ngep, "nge_attach: nge_chip_reset() failed"); 2445 mutex_exit(ngep->genlock); 2446 goto attach_fail; 2447 } 2448 nge_chip_sync(ngep); 2449 2450 /* 2451 * Now that mutex locks are initialized, enable interrupts. 2452 */ 2453 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 2454 /* Call ddi_intr_block_enable() for MSI interrupts */ 2455 (void) ddi_intr_block_enable(ngep->htable, 2456 ngep->intr_actual_cnt); 2457 } else { 2458 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 2459 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2460 (void) ddi_intr_enable(ngep->htable[i]); 2461 } 2462 } 2463 2464 ngep->link_state = LINK_STATE_UNKNOWN; 2465 ngep->progress |= PROGRESS_HWINT; 2466 2467 /* 2468 * Register NDD-tweakable parameters 2469 */ 2470 if (nge_nd_init(ngep)) { 2471 nge_problem(ngep, "nge_attach: nge_nd_init() failed"); 2472 mutex_exit(ngep->genlock); 2473 goto attach_fail; 2474 } 2475 ngep->progress |= PROGRESS_NDD; 2476 2477 /* 2478 * Create & initialise named kstats 2479 */ 2480 nge_init_kstats(ngep, instance); 2481 ngep->progress |= PROGRESS_KSTATS; 2482 2483 mutex_exit(ngep->genlock); 2484 2485 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2486 goto attach_fail; 2487 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2488 macp->m_driver = ngep; 2489 macp->m_dip = devinfo; 2490 macp->m_src_addr = infop->vendor_addr.addr; 2491 macp->m_callbacks = &nge_m_callbacks; 2492 macp->m_min_sdu = 0; 2493 macp->m_max_sdu = ngep->default_mtu; 2494 macp->m_margin = VTAG_SIZE; 2495 macp->m_priv_props = nge_priv_props; 2496 macp->m_priv_prop_count = NGE_MAX_PRIV_PROPS; 2497 /* 2498 * Finally, we're ready to register ourselves with the mac 2499 * interface; if this succeeds, we're all ready to start() 2500 */ 2501 err = mac_register(macp, &ngep->mh); 2502 mac_free(macp); 2503 if (err != 0) 2504 goto attach_fail; 2505 2506 /* 2507 * Register a periodical handler. 2508 * nge_chip_cyclic() is invoked in kernel context. 2509 */ 2510 ngep->periodic_id = ddi_periodic_add(nge_chip_cyclic, ngep, 2511 NGE_CYCLIC_PERIOD, DDI_IPL_0); 2512 2513 ngep->progress |= PROGRESS_READY; 2514 return (DDI_SUCCESS); 2515 2516 attach_fail: 2517 nge_unattach(ngep); 2518 return (DDI_FAILURE); 2519 } 2520 2521 static int 2522 nge_suspend(nge_t *ngep) 2523 { 2524 mutex_enter(ngep->genlock); 2525 rw_enter(ngep->rwlock, RW_WRITER); 2526 2527 /* if the port hasn't been plumbed, just return */ 2528 if (ngep->nge_mac_state != NGE_MAC_STARTED) { 2529 rw_exit(ngep->rwlock); 2530 mutex_exit(ngep->genlock); 2531 return (DDI_SUCCESS); 2532 } 2533 ngep->suspended = B_TRUE; 2534 (void) nge_chip_stop(ngep, B_FALSE); 2535 ngep->nge_mac_state = NGE_MAC_STOPPED; 2536 2537 rw_exit(ngep->rwlock); 2538 mutex_exit(ngep->genlock); 2539 return (DDI_SUCCESS); 2540 } 2541 2542 /* 2543 * detach(9E) -- Detach a device from the system 2544 */ 2545 static int 2546 nge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2547 { 2548 int i; 2549 nge_t *ngep; 2550 mul_item *p, *nextp; 2551 buff_ring_t *brp; 2552 2553 NGE_GTRACE(("nge_detach($%p, %d)", (void *)devinfo, cmd)); 2554 2555 ngep = ddi_get_driver_private(devinfo); 2556 brp = ngep->buff; 2557 2558 switch (cmd) { 2559 default: 2560 return (DDI_FAILURE); 2561 2562 case DDI_SUSPEND: 2563 /* 2564 * Stop the NIC 2565 * Note: This driver doesn't currently support WOL, but 2566 * should it in the future, it is important to 2567 * make sure the PHY remains powered so that the 2568 * wakeup packet can actually be recieved. 2569 */ 2570 return (nge_suspend(ngep)); 2571 2572 case DDI_DETACH: 2573 break; 2574 } 2575 2576 /* Try to wait all the buffer post to upper layer be released */ 2577 for (i = 0; i < 1000; i++) { 2578 if (brp->rx_hold == 0) 2579 break; 2580 drv_usecwait(1000); 2581 } 2582 2583 /* If there is any posted buffer, reject to detach */ 2584 if (brp->rx_hold != 0) 2585 return (DDI_FAILURE); 2586 2587 /* 2588 * Unregister from the GLD subsystem. This can fail, in 2589 * particular if there are DLPI style-2 streams still open - 2590 * in which case we just return failure without shutting 2591 * down chip operations. 2592 */ 2593 if (mac_unregister(ngep->mh) != DDI_SUCCESS) 2594 return (DDI_FAILURE); 2595 2596 /* 2597 * Recycle the multicast table. mac_unregister() should be called 2598 * before it to ensure the multicast table can be used even if 2599 * mac_unregister() fails. 2600 */ 2601 for (p = ngep->pcur_mulist; p != NULL; p = nextp) { 2602 nextp = p->next; 2603 kmem_free(p, sizeof (mul_item)); 2604 } 2605 ngep->pcur_mulist = NULL; 2606 2607 /* 2608 * All activity stopped, so we can clean up & exit 2609 */ 2610 nge_unattach(ngep); 2611 return (DDI_SUCCESS); 2612 } 2613 2614 2615 /* 2616 * ========== Module Loading Data & Entry Points ========== 2617 */ 2618 2619 DDI_DEFINE_STREAM_OPS(nge_dev_ops, nulldev, nulldev, nge_attach, nge_detach, 2620 nodev, NULL, D_MP, NULL); 2621 2622 2623 static struct modldrv nge_modldrv = { 2624 &mod_driverops, /* Type of module. This one is a driver */ 2625 nge_ident, /* short description */ 2626 &nge_dev_ops /* driver specific ops */ 2627 }; 2628 2629 static struct modlinkage modlinkage = { 2630 MODREV_1, (void *)&nge_modldrv, NULL 2631 }; 2632 2633 2634 int 2635 _info(struct modinfo *modinfop) 2636 { 2637 return (mod_info(&modlinkage, modinfop)); 2638 } 2639 2640 int 2641 _init(void) 2642 { 2643 int status; 2644 2645 mac_init_ops(&nge_dev_ops, "nge"); 2646 status = mod_install(&modlinkage); 2647 if (status != DDI_SUCCESS) 2648 mac_fini_ops(&nge_dev_ops); 2649 else 2650 mutex_init(nge_log_mutex, NULL, MUTEX_DRIVER, NULL); 2651 2652 return (status); 2653 } 2654 2655 int 2656 _fini(void) 2657 { 2658 int status; 2659 2660 status = mod_remove(&modlinkage); 2661 if (status == DDI_SUCCESS) { 2662 mac_fini_ops(&nge_dev_ops); 2663 mutex_destroy(nge_log_mutex); 2664 } 2665 2666 return (status); 2667 } 2668 2669 /* 2670 * ============ Init MSI/Fixed/SoftInterrupt routines ============== 2671 */ 2672 2673 /* 2674 * Register interrupts and initialize each mutex and condition variables 2675 */ 2676 2677 static int 2678 nge_register_intrs_and_init_locks(nge_t *ngep) 2679 { 2680 int err; 2681 int intr_types; 2682 uint_t soft_prip; 2683 nge_msi_mask msi_mask; 2684 nge_msi_map0_vec map0_vec; 2685 nge_msi_map1_vec map1_vec; 2686 2687 /* 2688 * Add the softint handlers: 2689 * 2690 * Both of these handlers are used to avoid restrictions on the 2691 * context and/or mutexes required for some operations. In 2692 * particular, the hardware interrupt handler and its subfunctions 2693 * can detect a number of conditions that we don't want to handle 2694 * in that context or with that set of mutexes held. So, these 2695 * softints are triggered instead: 2696 * 2697 * the <resched> softint is triggered if if we have previously 2698 * had to refuse to send a packet because of resource shortage 2699 * (we've run out of transmit buffers), but the send completion 2700 * interrupt handler has now detected that more buffers have 2701 * become available. Its only purpose is to call gld_sched() 2702 * to retry the pending transmits (we're not allowed to hold 2703 * driver-defined mutexes across gld_sched()). 2704 * 2705 * the <factotum> is triggered if the h/w interrupt handler 2706 * sees the <link state changed> or <error> bits in the status 2707 * block. It's also triggered periodically to poll the link 2708 * state, just in case we aren't getting link status change 2709 * interrupts ... 2710 */ 2711 err = ddi_intr_add_softint(ngep->devinfo, &ngep->resched_hdl, 2712 DDI_INTR_SOFTPRI_MIN, nge_reschedule, (caddr_t)ngep); 2713 if (err != DDI_SUCCESS) { 2714 nge_problem(ngep, 2715 "nge_attach: add nge_reschedule softintr failed"); 2716 2717 return (DDI_FAILURE); 2718 } 2719 ngep->progress |= PROGRESS_RESCHED; 2720 err = ddi_intr_add_softint(ngep->devinfo, &ngep->factotum_hdl, 2721 DDI_INTR_SOFTPRI_MIN, nge_chip_factotum, (caddr_t)ngep); 2722 if (err != DDI_SUCCESS) { 2723 nge_problem(ngep, 2724 "nge_attach: add nge_chip_factotum softintr failed!"); 2725 2726 return (DDI_FAILURE); 2727 } 2728 if (ddi_intr_get_softint_pri(ngep->factotum_hdl, &soft_prip) 2729 != DDI_SUCCESS) { 2730 nge_problem(ngep, "nge_attach: get softintr priority failed\n"); 2731 2732 return (DDI_FAILURE); 2733 } 2734 ngep->soft_pri = soft_prip; 2735 2736 ngep->progress |= PROGRESS_FACTOTUM; 2737 /* Get supported interrupt types */ 2738 if (ddi_intr_get_supported_types(ngep->devinfo, &intr_types) 2739 != DDI_SUCCESS) { 2740 nge_error(ngep, "ddi_intr_get_supported_types failed\n"); 2741 2742 return (DDI_FAILURE); 2743 } 2744 2745 NGE_DEBUG(("ddi_intr_get_supported_types() returned: %x", 2746 intr_types)); 2747 2748 if ((intr_types & DDI_INTR_TYPE_MSI) && nge_enable_msi) { 2749 2750 /* MSI Configurations for mcp55 chipset */ 2751 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 2752 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 2753 2754 2755 /* Enable the 8 vectors */ 2756 msi_mask.msi_mask_val = 2757 nge_reg_get32(ngep, NGE_MSI_MASK); 2758 msi_mask.msi_msk_bits.vec0 = NGE_SET; 2759 msi_mask.msi_msk_bits.vec1 = NGE_SET; 2760 msi_mask.msi_msk_bits.vec2 = NGE_SET; 2761 msi_mask.msi_msk_bits.vec3 = NGE_SET; 2762 msi_mask.msi_msk_bits.vec4 = NGE_SET; 2763 msi_mask.msi_msk_bits.vec5 = NGE_SET; 2764 msi_mask.msi_msk_bits.vec6 = NGE_SET; 2765 msi_mask.msi_msk_bits.vec7 = NGE_SET; 2766 nge_reg_put32(ngep, NGE_MSI_MASK, 2767 msi_mask.msi_mask_val); 2768 2769 /* 2770 * Remapping the MSI MAP0 and MAP1. MCP55 2771 * is default mapping all the interrupt to 0 vector. 2772 * Software needs to remapping this. 2773 * This mapping is same as CK804. 2774 */ 2775 map0_vec.msi_map0_val = 2776 nge_reg_get32(ngep, NGE_MSI_MAP0); 2777 map1_vec.msi_map1_val = 2778 nge_reg_get32(ngep, NGE_MSI_MAP1); 2779 map0_vec.vecs_bits.reint_vec = 0; 2780 map0_vec.vecs_bits.rcint_vec = 0; 2781 map0_vec.vecs_bits.miss_vec = 3; 2782 map0_vec.vecs_bits.teint_vec = 5; 2783 map0_vec.vecs_bits.tcint_vec = 5; 2784 map0_vec.vecs_bits.stint_vec = 2; 2785 map0_vec.vecs_bits.mint_vec = 6; 2786 map0_vec.vecs_bits.rfint_vec = 0; 2787 map1_vec.vecs_bits.tfint_vec = 5; 2788 map1_vec.vecs_bits.feint_vec = 6; 2789 map1_vec.vecs_bits.resv8_11 = 3; 2790 map1_vec.vecs_bits.resv12_15 = 1; 2791 map1_vec.vecs_bits.resv16_19 = 0; 2792 map1_vec.vecs_bits.resv20_23 = 7; 2793 map1_vec.vecs_bits.resv24_31 = 0xff; 2794 nge_reg_put32(ngep, NGE_MSI_MAP0, 2795 map0_vec.msi_map0_val); 2796 nge_reg_put32(ngep, NGE_MSI_MAP1, 2797 map1_vec.msi_map1_val); 2798 } 2799 if (nge_add_intrs(ngep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2800 NGE_DEBUG(("MSI registration failed, " 2801 "trying FIXED interrupt type\n")); 2802 } else { 2803 nge_log(ngep, "Using MSI interrupt type\n"); 2804 2805 ngep->intr_type = DDI_INTR_TYPE_MSI; 2806 ngep->progress |= PROGRESS_SWINT; 2807 } 2808 } 2809 2810 if (!(ngep->progress & PROGRESS_SWINT) && 2811 (intr_types & DDI_INTR_TYPE_FIXED)) { 2812 if (nge_add_intrs(ngep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2813 nge_error(ngep, "FIXED interrupt " 2814 "registration failed\n"); 2815 2816 return (DDI_FAILURE); 2817 } 2818 2819 nge_log(ngep, "Using FIXED interrupt type\n"); 2820 2821 ngep->intr_type = DDI_INTR_TYPE_FIXED; 2822 ngep->progress |= PROGRESS_SWINT; 2823 } 2824 2825 2826 if (!(ngep->progress & PROGRESS_SWINT)) { 2827 nge_error(ngep, "No interrupts registered\n"); 2828 2829 return (DDI_FAILURE); 2830 } 2831 mutex_init(ngep->genlock, NULL, MUTEX_DRIVER, 2832 DDI_INTR_PRI(ngep->intr_pri)); 2833 mutex_init(ngep->softlock, NULL, MUTEX_DRIVER, 2834 DDI_INTR_PRI(ngep->soft_pri)); 2835 rw_init(ngep->rwlock, NULL, RW_DRIVER, 2836 DDI_INTR_PRI(ngep->intr_pri)); 2837 2838 return (DDI_SUCCESS); 2839 } 2840 2841 /* 2842 * nge_add_intrs: 2843 * 2844 * Register FIXED or MSI interrupts. 2845 */ 2846 static int 2847 nge_add_intrs(nge_t *ngep, int intr_type) 2848 { 2849 dev_info_t *dip = ngep->devinfo; 2850 int avail, actual, intr_size, count = 0; 2851 int i, flag, ret; 2852 2853 NGE_DEBUG(("nge_add_intrs: interrupt type 0x%x\n", intr_type)); 2854 2855 /* Get number of interrupts */ 2856 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 2857 if ((ret != DDI_SUCCESS) || (count == 0)) { 2858 nge_error(ngep, "ddi_intr_get_nintrs() failure, ret: %d, " 2859 "count: %d", ret, count); 2860 2861 return (DDI_FAILURE); 2862 } 2863 2864 /* Get number of available interrupts */ 2865 ret = ddi_intr_get_navail(dip, intr_type, &avail); 2866 if ((ret != DDI_SUCCESS) || (avail == 0)) { 2867 nge_error(ngep, "ddi_intr_get_navail() failure, " 2868 "ret: %d, avail: %d\n", ret, avail); 2869 2870 return (DDI_FAILURE); 2871 } 2872 2873 if (avail < count) { 2874 NGE_DEBUG(("nitrs() returned %d, navail returned %d\n", 2875 count, avail)); 2876 } 2877 flag = DDI_INTR_ALLOC_NORMAL; 2878 2879 /* Allocate an array of interrupt handles */ 2880 intr_size = count * sizeof (ddi_intr_handle_t); 2881 ngep->htable = kmem_alloc(intr_size, KM_SLEEP); 2882 2883 /* Call ddi_intr_alloc() */ 2884 ret = ddi_intr_alloc(dip, ngep->htable, intr_type, 0, 2885 count, &actual, flag); 2886 2887 if ((ret != DDI_SUCCESS) || (actual == 0)) { 2888 nge_error(ngep, "ddi_intr_alloc() failed %d\n", ret); 2889 2890 kmem_free(ngep->htable, intr_size); 2891 return (DDI_FAILURE); 2892 } 2893 2894 if (actual < count) { 2895 NGE_DEBUG(("Requested: %d, Received: %d\n", 2896 count, actual)); 2897 } 2898 2899 ngep->intr_actual_cnt = actual; 2900 ngep->intr_req_cnt = count; 2901 2902 /* 2903 * Get priority for first msi, assume remaining are all the same 2904 */ 2905 if ((ret = ddi_intr_get_pri(ngep->htable[0], &ngep->intr_pri)) != 2906 DDI_SUCCESS) { 2907 nge_error(ngep, "ddi_intr_get_pri() failed %d\n", ret); 2908 2909 /* Free already allocated intr */ 2910 for (i = 0; i < actual; i++) { 2911 (void) ddi_intr_free(ngep->htable[i]); 2912 } 2913 2914 kmem_free(ngep->htable, intr_size); 2915 2916 return (DDI_FAILURE); 2917 } 2918 /* Test for high level mutex */ 2919 if (ngep->intr_pri >= ddi_intr_get_hilevel_pri()) { 2920 nge_error(ngep, "nge_add_intrs:" 2921 "Hi level interrupt not supported"); 2922 2923 for (i = 0; i < actual; i++) 2924 (void) ddi_intr_free(ngep->htable[i]); 2925 2926 kmem_free(ngep->htable, intr_size); 2927 2928 return (DDI_FAILURE); 2929 } 2930 2931 2932 /* Call ddi_intr_add_handler() */ 2933 for (i = 0; i < actual; i++) { 2934 if ((ret = ddi_intr_add_handler(ngep->htable[i], nge_chip_intr, 2935 (caddr_t)ngep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 2936 nge_error(ngep, "ddi_intr_add_handler() " 2937 "failed %d\n", ret); 2938 2939 /* Free already allocated intr */ 2940 for (i = 0; i < actual; i++) { 2941 (void) ddi_intr_free(ngep->htable[i]); 2942 } 2943 2944 kmem_free(ngep->htable, intr_size); 2945 2946 return (DDI_FAILURE); 2947 } 2948 } 2949 2950 if ((ret = ddi_intr_get_cap(ngep->htable[0], &ngep->intr_cap)) 2951 != DDI_SUCCESS) { 2952 nge_error(ngep, "ddi_intr_get_cap() failed %d\n", ret); 2953 2954 for (i = 0; i < actual; i++) { 2955 (void) ddi_intr_remove_handler(ngep->htable[i]); 2956 (void) ddi_intr_free(ngep->htable[i]); 2957 } 2958 2959 kmem_free(ngep->htable, intr_size); 2960 2961 return (DDI_FAILURE); 2962 } 2963 2964 return (DDI_SUCCESS); 2965 } 2966 2967 /* 2968 * nge_rem_intrs: 2969 * 2970 * Unregister FIXED or MSI interrupts 2971 */ 2972 static void 2973 nge_rem_intrs(nge_t *ngep) 2974 { 2975 int i; 2976 2977 NGE_DEBUG(("nge_rem_intrs\n")); 2978 2979 /* Disable all interrupts */ 2980 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 2981 /* Call ddi_intr_block_disable() */ 2982 (void) ddi_intr_block_disable(ngep->htable, 2983 ngep->intr_actual_cnt); 2984 } else { 2985 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2986 (void) ddi_intr_disable(ngep->htable[i]); 2987 } 2988 } 2989 2990 /* Call ddi_intr_remove_handler() */ 2991 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2992 (void) ddi_intr_remove_handler(ngep->htable[i]); 2993 (void) ddi_intr_free(ngep->htable[i]); 2994 } 2995 2996 kmem_free(ngep->htable, 2997 ngep->intr_req_cnt * sizeof (ddi_intr_handle_t)); 2998 } 2999