xref: /titanic_41/usr/src/uts/common/io/nge/nge_main.c (revision 2e02daeede04af58a9d4f18f8dfed1fda3ececa1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 
28 #include "nge.h"
29 
30 /*
31  * Describes the chip's DMA engine
32  */
33 
34 static ddi_dma_attr_t hot_dma_attr = {
35 	DMA_ATTR_V0,			/* dma_attr version	*/
36 	0x0000000000000000ull,		/* dma_attr_addr_lo	*/
37 	0x000000FFFFFFFFFFull,		/* dma_attr_addr_hi	*/
38 	0x000000007FFFFFFFull,		/* dma_attr_count_max	*/
39 	0x0000000000000010ull,		/* dma_attr_align	*/
40 	0x00000FFF,			/* dma_attr_burstsizes	*/
41 	0x00000001,			/* dma_attr_minxfer	*/
42 	0x000000000000FFFFull,		/* dma_attr_maxxfer	*/
43 	0x000000FFFFFFFFFFull,		/* dma_attr_seg		*/
44 	1,				/* dma_attr_sgllen 	*/
45 	0x00000001,			/* dma_attr_granular 	*/
46 	0
47 };
48 
49 static ddi_dma_attr_t hot_tx_dma_attr = {
50 	DMA_ATTR_V0,			/* dma_attr version	*/
51 	0x0000000000000000ull,		/* dma_attr_addr_lo	*/
52 	0x000000FFFFFFFFFFull,		/* dma_attr_addr_hi	*/
53 	0x0000000000003FFFull,		/* dma_attr_count_max	*/
54 	0x0000000000000010ull,		/* dma_attr_align	*/
55 	0x00000FFF,			/* dma_attr_burstsizes	*/
56 	0x00000001,			/* dma_attr_minxfer	*/
57 	0x0000000000003FFFull,		/* dma_attr_maxxfer	*/
58 	0x000000FFFFFFFFFFull,		/* dma_attr_seg		*/
59 	NGE_MAX_COOKIES,		/* dma_attr_sgllen 	*/
60 	1,				/* dma_attr_granular 	*/
61 	0
62 };
63 
64 static ddi_dma_attr_t sum_dma_attr = {
65 	DMA_ATTR_V0,			/* dma_attr version	*/
66 	0x0000000000000000ull,		/* dma_attr_addr_lo	*/
67 	0x00000000FFFFFFFFull,		/* dma_attr_addr_hi	*/
68 	0x000000007FFFFFFFull,		/* dma_attr_count_max	*/
69 	0x0000000000000010ull,		/* dma_attr_align	*/
70 	0x00000FFF,			/* dma_attr_burstsizes	*/
71 	0x00000001,			/* dma_attr_minxfer	*/
72 	0x000000000000FFFFull,		/* dma_attr_maxxfer	*/
73 	0x00000000FFFFFFFFull,		/* dma_attr_seg		*/
74 	1,				/* dma_attr_sgllen 	*/
75 	0x00000001,			/* dma_attr_granular 	*/
76 	0
77 };
78 
79 static ddi_dma_attr_t sum_tx_dma_attr = {
80 	DMA_ATTR_V0,			/* dma_attr version	*/
81 	0x0000000000000000ull,		/* dma_attr_addr_lo	*/
82 	0x00000000FFFFFFFFull,		/* dma_attr_addr_hi	*/
83 	0x0000000000003FFFull,		/* dma_attr_count_max	*/
84 	0x0000000000000010ull,		/* dma_attr_align	*/
85 	0x00000FFF,			/* dma_attr_burstsizes	*/
86 	0x00000001,			/* dma_attr_minxfer	*/
87 	0x0000000000003FFFull,		/* dma_attr_maxxfer	*/
88 	0x00000000FFFFFFFFull,		/* dma_attr_seg		*/
89 	NGE_MAX_COOKIES,		/* dma_attr_sgllen 	*/
90 	1,				/* dma_attr_granular 	*/
91 	0
92 };
93 
94 /*
95  * DMA access attributes for data.
96  */
97 ddi_device_acc_attr_t nge_data_accattr = {
98 	DDI_DEVICE_ATTR_V0,
99 	DDI_STRUCTURE_LE_ACC,
100 	DDI_STRICTORDER_ACC,
101 	DDI_DEFAULT_ACC
102 };
103 
104 /*
105  * DMA access attributes for descriptors.
106  */
107 static ddi_device_acc_attr_t nge_desc_accattr = {
108 	DDI_DEVICE_ATTR_V0,
109 	DDI_STRUCTURE_LE_ACC,
110 	DDI_STRICTORDER_ACC,
111 	DDI_DEFAULT_ACC
112 };
113 
114 /*
115  * PIO access attributes for registers
116  */
117 static ddi_device_acc_attr_t nge_reg_accattr = {
118 	DDI_DEVICE_ATTR_V0,
119 	DDI_STRUCTURE_LE_ACC,
120 	DDI_STRICTORDER_ACC,
121 	DDI_DEFAULT_ACC
122 };
123 
124 /*
125  * NIC DESC MODE 2
126  */
127 
128 static const nge_desc_attr_t nge_sum_desc = {
129 
130 	sizeof (sum_rx_bd),
131 	sizeof (sum_tx_bd),
132 	&sum_dma_attr,
133 	&sum_tx_dma_attr,
134 	nge_sum_rxd_fill,
135 	nge_sum_rxd_check,
136 	nge_sum_txd_fill,
137 	nge_sum_txd_check,
138 };
139 
140 /*
141  * NIC DESC MODE 3
142  */
143 
144 static const nge_desc_attr_t nge_hot_desc = {
145 
146 	sizeof (hot_rx_bd),
147 	sizeof (hot_tx_bd),
148 	&hot_dma_attr,
149 	&hot_tx_dma_attr,
150 	nge_hot_rxd_fill,
151 	nge_hot_rxd_check,
152 	nge_hot_txd_fill,
153 	nge_hot_txd_check,
154 };
155 
156 static char nge_ident[] = "nVidia 1Gb Ethernet";
157 static char clsize_propname[] = "cache-line-size";
158 static char latency_propname[] = "latency-timer";
159 static char debug_propname[]	= "nge-debug-flags";
160 static char intr_moderation[] = "intr-moderation";
161 static char rx_data_hw[] = "rx-data-hw";
162 static char rx_prd_lw[] = "rx-prd-lw";
163 static char rx_prd_hw[] = "rx-prd-hw";
164 static char sw_intr_intv[] = "sw-intr-intvl";
165 static char nge_desc_mode[] = "desc-mode";
166 static char default_mtu[] = "default_mtu";
167 static char low_memory_mode[] = "minimal-memory-usage";
168 static char mac_addr_reversion[] = "mac-addr-reversion";
169 extern kmutex_t nge_log_mutex[1];
170 
171 static int		nge_m_start(void *);
172 static void		nge_m_stop(void *);
173 static int		nge_m_promisc(void *, boolean_t);
174 static int		nge_m_multicst(void *, boolean_t, const uint8_t *);
175 static int		nge_m_unicst(void *, const uint8_t *);
176 static void		nge_m_ioctl(void *, queue_t *, mblk_t *);
177 static boolean_t	nge_m_getcapab(void *, mac_capab_t, void *);
178 static int		nge_m_setprop(void *, const char *, mac_prop_id_t,
179 	uint_t, const void *);
180 static int		nge_m_getprop(void *, const char *, mac_prop_id_t,
181 	uint_t, uint_t, void *, uint_t *);
182 static int		nge_set_priv_prop(nge_t *, const char *, uint_t,
183 	const void *);
184 static int		nge_get_priv_prop(nge_t *, const char *, uint_t,
185 	uint_t, void *);
186 
187 #define		NGE_M_CALLBACK_FLAGS\
188 		(MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP)
189 
190 static mac_callbacks_t nge_m_callbacks = {
191 	NGE_M_CALLBACK_FLAGS,
192 	nge_m_stat,
193 	nge_m_start,
194 	nge_m_stop,
195 	nge_m_promisc,
196 	nge_m_multicst,
197 	nge_m_unicst,
198 	nge_m_tx,
199 	nge_m_ioctl,
200 	nge_m_getcapab,
201 	NULL,
202 	NULL,
203 	nge_m_setprop,
204 	nge_m_getprop
205 };
206 
207 mac_priv_prop_t nge_priv_props[] = {
208 	{"_tx_bcopy_threshold", MAC_PROP_PERM_RW},
209 	{"_rx_bcopy_threshold", MAC_PROP_PERM_RW},
210 	{"_recv_max_packet", MAC_PROP_PERM_RW},
211 	{"_poll_quiet_time", MAC_PROP_PERM_RW},
212 	{"_poll_busy_time", MAC_PROP_PERM_RW},
213 	{"_rx_intr_hwater", MAC_PROP_PERM_RW},
214 	{"_rx_intr_lwater", MAC_PROP_PERM_RW},
215 	{"_adv_pause_cap", MAC_PROP_PERM_RW},
216 	{"_adv_asym_pause_cap", MAC_PROP_PERM_RW},
217 	{"_tx_n_intr", MAC_PROP_PERM_RW}
218 };
219 
220 #define	NGE_MAX_PRIV_PROPS \
221 	(sizeof (nge_priv_props)/sizeof (mac_priv_prop_t))
222 
223 static int nge_add_intrs(nge_t *, int);
224 static void nge_rem_intrs(nge_t *);
225 static int nge_register_intrs_and_init_locks(nge_t *);
226 
227 /*
228  * NGE MSI tunable:
229  */
230 boolean_t nge_enable_msi = B_FALSE;
231 
232 static enum ioc_reply
233 nge_set_loop_mode(nge_t *ngep, uint32_t mode)
234 {
235 	/*
236 	 * If the mode isn't being changed, there's nothing to do ...
237 	 */
238 	if (mode == ngep->param_loop_mode)
239 		return (IOC_ACK);
240 
241 	/*
242 	 * Validate the requested mode and prepare a suitable message
243 	 * to explain the link down/up cycle that the change will
244 	 * probably induce ...
245 	 */
246 	switch (mode) {
247 	default:
248 		return (IOC_INVAL);
249 
250 	case NGE_LOOP_NONE:
251 	case NGE_LOOP_EXTERNAL_100:
252 	case NGE_LOOP_EXTERNAL_10:
253 	case NGE_LOOP_INTERNAL_PHY:
254 		break;
255 	}
256 
257 	/*
258 	 * All OK; tell the caller to reprogram
259 	 * the PHY and/or MAC for the new mode ...
260 	 */
261 	ngep->param_loop_mode = mode;
262 	return (IOC_RESTART_ACK);
263 }
264 
265 #undef	NGE_DBG
266 #define	NGE_DBG		NGE_DBG_INIT
267 
268 /*
269  * Utility routine to carve a slice off a chunk of allocated memory,
270  * updating the chunk descriptor accordingly.  The size of the slice
271  * is given by the product of the <qty> and <size> parameters.
272  */
273 void
274 nge_slice_chunk(dma_area_t *slice, dma_area_t *chunk,
275     uint32_t qty, uint32_t size)
276 {
277 	size_t totsize;
278 
279 	totsize = qty*size;
280 	ASSERT(size > 0);
281 	ASSERT(totsize <= chunk->alength);
282 
283 	*slice = *chunk;
284 	slice->nslots = qty;
285 	slice->size = size;
286 	slice->alength = totsize;
287 
288 	chunk->mem_va = (caddr_t)chunk->mem_va + totsize;
289 	chunk->alength -= totsize;
290 	chunk->offset += totsize;
291 	chunk->cookie.dmac_laddress += totsize;
292 	chunk->cookie.dmac_size -= totsize;
293 }
294 
295 /*
296  * Allocate an area of memory and a DMA handle for accessing it
297  */
298 int
299 nge_alloc_dma_mem(nge_t *ngep, size_t memsize, ddi_device_acc_attr_t *attr_p,
300     uint_t dma_flags, dma_area_t *dma_p)
301 {
302 	int err;
303 	caddr_t va;
304 
305 	NGE_TRACE(("nge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)",
306 	    (void *)ngep, memsize, attr_p, dma_flags, dma_p));
307 	/*
308 	 * Allocate handle
309 	 */
310 	err = ddi_dma_alloc_handle(ngep->devinfo, ngep->desc_attr.dma_attr,
311 	    DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl);
312 	if (err != DDI_SUCCESS)
313 		goto fail;
314 
315 	/*
316 	 * Allocate memory
317 	 */
318 	err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
319 	    dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
320 	    DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, &dma_p->acc_hdl);
321 	if (err != DDI_SUCCESS)
322 		goto fail;
323 
324 	/*
325 	 * Bind the two together
326 	 */
327 	dma_p->mem_va = va;
328 	err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
329 	    va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL,
330 	    &dma_p->cookie, &dma_p->ncookies);
331 
332 	if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1)
333 		goto fail;
334 
335 	dma_p->nslots = ~0U;
336 	dma_p->size = ~0U;
337 	dma_p->offset = 0;
338 
339 	return (DDI_SUCCESS);
340 
341 fail:
342 	nge_free_dma_mem(dma_p);
343 	NGE_DEBUG(("nge_alloc_dma_mem: fail to alloc dma memory!"));
344 
345 	return (DDI_FAILURE);
346 }
347 
348 /*
349  * Free one allocated area of DMAable memory
350  */
351 void
352 nge_free_dma_mem(dma_area_t *dma_p)
353 {
354 	if (dma_p->dma_hdl != NULL) {
355 		if (dma_p->ncookies) {
356 			(void) ddi_dma_unbind_handle(dma_p->dma_hdl);
357 			dma_p->ncookies = 0;
358 		}
359 	}
360 	if (dma_p->acc_hdl != NULL) {
361 		ddi_dma_mem_free(&dma_p->acc_hdl);
362 		dma_p->acc_hdl = NULL;
363 	}
364 	if (dma_p->dma_hdl != NULL) {
365 		ddi_dma_free_handle(&dma_p->dma_hdl);
366 		dma_p->dma_hdl = NULL;
367 	}
368 }
369 
370 #define	ALLOC_TX_BUF	0x1
371 #define	ALLOC_TX_DESC	0x2
372 #define	ALLOC_RX_DESC	0x4
373 
374 int
375 nge_alloc_bufs(nge_t *ngep)
376 {
377 	int err;
378 	int split;
379 	int progress;
380 	size_t txbuffsize;
381 	size_t rxdescsize;
382 	size_t txdescsize;
383 
384 	txbuffsize = ngep->tx_desc * ngep->buf_size;
385 	rxdescsize = ngep->rx_desc;
386 	txdescsize = ngep->tx_desc;
387 	rxdescsize *= ngep->desc_attr.rxd_size;
388 	txdescsize *= ngep->desc_attr.txd_size;
389 	progress = 0;
390 
391 	NGE_TRACE(("nge_alloc_bufs($%p)", (void *)ngep));
392 	/*
393 	 * Allocate memory & handles for TX buffers
394 	 */
395 	ASSERT((txbuffsize % ngep->nge_split) == 0);
396 	for (split = 0; split < ngep->nge_split; ++split) {
397 		err = nge_alloc_dma_mem(ngep, txbuffsize/ngep->nge_split,
398 		    &nge_data_accattr, DDI_DMA_WRITE | NGE_DMA_MODE,
399 		    &ngep->send->buf[split]);
400 		if (err != DDI_SUCCESS)
401 			goto fail;
402 	}
403 
404 	progress |= ALLOC_TX_BUF;
405 
406 	/*
407 	 * Allocate memory & handles for receive return rings and
408 	 * buffer (producer) descriptor rings
409 	 */
410 	err = nge_alloc_dma_mem(ngep, rxdescsize, &nge_desc_accattr,
411 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->recv->desc);
412 	if (err != DDI_SUCCESS)
413 		goto fail;
414 	progress |= ALLOC_RX_DESC;
415 
416 	/*
417 	 * Allocate memory & handles for TX descriptor rings,
418 	 */
419 	err = nge_alloc_dma_mem(ngep, txdescsize, &nge_desc_accattr,
420 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->send->desc);
421 	if (err != DDI_SUCCESS)
422 		goto fail;
423 	return (DDI_SUCCESS);
424 
425 fail:
426 	if (progress & ALLOC_RX_DESC)
427 		nge_free_dma_mem(&ngep->recv->desc);
428 	if (progress & ALLOC_TX_BUF) {
429 		for (split = 0; split < ngep->nge_split; ++split)
430 			nge_free_dma_mem(&ngep->send->buf[split]);
431 	}
432 
433 	return (DDI_FAILURE);
434 }
435 
436 /*
437  * This routine frees the transmit and receive buffers and descriptors.
438  * Make sure the chip is stopped before calling it!
439  */
440 void
441 nge_free_bufs(nge_t *ngep)
442 {
443 	int split;
444 
445 	NGE_TRACE(("nge_free_bufs($%p)", (void *)ngep));
446 
447 	nge_free_dma_mem(&ngep->recv->desc);
448 	nge_free_dma_mem(&ngep->send->desc);
449 
450 	for (split = 0; split < ngep->nge_split; ++split)
451 		nge_free_dma_mem(&ngep->send->buf[split]);
452 }
453 
454 /*
455  * Clean up initialisation done above before the memory is freed
456  */
457 static void
458 nge_fini_send_ring(nge_t *ngep)
459 {
460 	uint32_t slot;
461 	size_t dmah_num;
462 	send_ring_t *srp;
463 	sw_tx_sbd_t *ssbdp;
464 
465 	srp = ngep->send;
466 	ssbdp = srp->sw_sbds;
467 
468 	NGE_TRACE(("nge_fini_send_ring($%p)", (void *)ngep));
469 
470 	dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]);
471 
472 	for (slot = 0; slot < dmah_num; ++slot) {
473 		if (srp->dmahndl[slot].hndl) {
474 			(void) ddi_dma_unbind_handle(srp->dmahndl[slot].hndl);
475 			ddi_dma_free_handle(&srp->dmahndl[slot].hndl);
476 			srp->dmahndl[slot].hndl = NULL;
477 			srp->dmahndl[slot].next = NULL;
478 		}
479 	}
480 
481 	srp->dmah_free.head = NULL;
482 	srp->dmah_free.tail = NULL;
483 
484 	kmem_free(ssbdp, srp->desc.nslots*sizeof (*ssbdp));
485 
486 }
487 
488 /*
489  * Initialise the specified Send Ring, using the information in the
490  * <dma_area> descriptors that it contains to set up all the other
491  * fields. This routine should be called only once for each ring.
492  */
493 static int
494 nge_init_send_ring(nge_t *ngep)
495 {
496 	size_t dmah_num;
497 	uint32_t nslots;
498 	uint32_t err;
499 	uint32_t slot;
500 	uint32_t split;
501 	send_ring_t *srp;
502 	sw_tx_sbd_t *ssbdp;
503 	dma_area_t desc;
504 	dma_area_t pbuf;
505 
506 	srp = ngep->send;
507 	srp->desc.nslots = ngep->tx_desc;
508 	nslots = srp->desc.nslots;
509 
510 	NGE_TRACE(("nge_init_send_ring($%p)", (void *)ngep));
511 	/*
512 	 * Other one-off initialisation of per-ring data
513 	 */
514 	srp->ngep = ngep;
515 
516 	/*
517 	 * Allocate the array of s/w Send Buffer Descriptors
518 	 */
519 	ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP);
520 	srp->sw_sbds = ssbdp;
521 
522 	/*
523 	 * Now initialise each array element once and for all
524 	 */
525 	desc = srp->desc;
526 	for (split = 0; split < ngep->nge_split; ++split) {
527 		pbuf = srp->buf[split];
528 		for (slot = 0; slot < nslots/ngep->nge_split; ++ssbdp, ++slot) {
529 			nge_slice_chunk(&ssbdp->desc, &desc, 1,
530 			    ngep->desc_attr.txd_size);
531 			nge_slice_chunk(&ssbdp->pbuf, &pbuf, 1,
532 			    ngep->buf_size);
533 		}
534 		ASSERT(pbuf.alength == 0);
535 	}
536 	ASSERT(desc.alength == 0);
537 
538 	dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]);
539 
540 	/* preallocate dma handles for tx buffer */
541 	for (slot = 0; slot < dmah_num; ++slot) {
542 
543 		err = ddi_dma_alloc_handle(ngep->devinfo,
544 		    ngep->desc_attr.tx_dma_attr, DDI_DMA_DONTWAIT,
545 		    NULL, &srp->dmahndl[slot].hndl);
546 
547 		if (err != DDI_SUCCESS) {
548 			nge_fini_send_ring(ngep);
549 			nge_error(ngep,
550 			    "nge_init_send_ring: alloc dma handle fails");
551 			return (DDI_FAILURE);
552 		}
553 		srp->dmahndl[slot].next = srp->dmahndl + slot + 1;
554 	}
555 
556 	srp->dmah_free.head = srp->dmahndl;
557 	srp->dmah_free.tail = srp->dmahndl + dmah_num - 1;
558 	srp->dmah_free.tail->next = NULL;
559 
560 	return (DDI_SUCCESS);
561 }
562 
563 /*
564  * Intialize the tx recycle pointer and tx sending pointer of tx ring
565  * and set the type of tx's data descriptor by default.
566  */
567 static void
568 nge_reinit_send_ring(nge_t *ngep)
569 {
570 	size_t dmah_num;
571 	uint32_t slot;
572 	send_ring_t *srp;
573 	sw_tx_sbd_t *ssbdp;
574 
575 	srp = ngep->send;
576 
577 	/*
578 	 * Reinitialise control variables ...
579 	 */
580 
581 	srp->tx_hwmark = NGE_DESC_MIN;
582 	srp->tx_lwmark = NGE_DESC_MIN;
583 
584 	srp->tx_next = 0;
585 	srp->tx_free = srp->desc.nslots;
586 	srp->tc_next = 0;
587 
588 	dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]);
589 
590 	for (slot = 0; slot - dmah_num != 0; ++slot)
591 		srp->dmahndl[slot].next = srp->dmahndl + slot + 1;
592 
593 	srp->dmah_free.head = srp->dmahndl;
594 	srp->dmah_free.tail = srp->dmahndl + dmah_num - 1;
595 	srp->dmah_free.tail->next = NULL;
596 
597 	/*
598 	 * Zero and sync all the h/w Send Buffer Descriptors
599 	 */
600 	for (slot = 0; slot < srp->desc.nslots; ++slot) {
601 		ssbdp = &srp->sw_sbds[slot];
602 		ssbdp->flags = HOST_OWN;
603 	}
604 
605 	DMA_ZERO(srp->desc);
606 	DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV);
607 }
608 
609 /*
610  * Initialize the slot number of rx's ring
611  */
612 static void
613 nge_init_recv_ring(nge_t *ngep)
614 {
615 	recv_ring_t *rrp;
616 
617 	rrp = ngep->recv;
618 	rrp->desc.nslots = ngep->rx_desc;
619 	rrp->ngep = ngep;
620 }
621 
622 /*
623  * Intialize the rx recycle pointer and rx sending pointer of rx ring
624  */
625 static void
626 nge_reinit_recv_ring(nge_t *ngep)
627 {
628 	recv_ring_t *rrp;
629 
630 	rrp = ngep->recv;
631 
632 	/*
633 	 * Reinitialise control variables ...
634 	 */
635 	rrp->prod_index = 0;
636 	/*
637 	 * Zero and sync all the h/w Send Buffer Descriptors
638 	 */
639 	DMA_ZERO(rrp->desc);
640 	DMA_SYNC(rrp->desc, DDI_DMA_SYNC_FORDEV);
641 }
642 
643 /*
644  * Clean up initialisation done above before the memory is freed
645  */
646 static void
647 nge_fini_buff_ring(nge_t *ngep)
648 {
649 	uint32_t i;
650 	buff_ring_t *brp;
651 	dma_area_t *bufp;
652 	sw_rx_sbd_t *bsbdp;
653 
654 	brp = ngep->buff;
655 	bsbdp = brp->sw_rbds;
656 
657 	NGE_DEBUG(("nge_fini_buff_ring($%p)", (void *)ngep));
658 
659 	mutex_enter(brp->recycle_lock);
660 	brp->buf_sign++;
661 	mutex_exit(brp->recycle_lock);
662 	for (i = 0; i < ngep->rx_desc; i++, ++bsbdp) {
663 		if (bsbdp->bufp) {
664 			if (bsbdp->bufp->mp)
665 				freemsg(bsbdp->bufp->mp);
666 			nge_free_dma_mem(bsbdp->bufp);
667 			kmem_free(bsbdp->bufp, sizeof (dma_area_t));
668 			bsbdp->bufp = NULL;
669 		}
670 	}
671 	while (brp->free_list != NULL) {
672 		bufp = brp->free_list;
673 		brp->free_list = bufp->next;
674 		bufp->next = NULL;
675 		if (bufp->mp)
676 			freemsg(bufp->mp);
677 		nge_free_dma_mem(bufp);
678 		kmem_free(bufp, sizeof (dma_area_t));
679 	}
680 	while (brp->recycle_list != NULL) {
681 		bufp = brp->recycle_list;
682 		brp->recycle_list = bufp->next;
683 		bufp->next = NULL;
684 		if (bufp->mp)
685 			freemsg(bufp->mp);
686 		nge_free_dma_mem(bufp);
687 		kmem_free(bufp, sizeof (dma_area_t));
688 	}
689 
690 
691 	kmem_free(brp->sw_rbds, (ngep->rx_desc * sizeof (*bsbdp)));
692 	brp->sw_rbds = NULL;
693 }
694 
695 /*
696  * Intialize the Rx's data ring and free ring
697  */
698 static int
699 nge_init_buff_ring(nge_t *ngep)
700 {
701 	uint32_t err;
702 	uint32_t slot;
703 	uint32_t nslots_buff;
704 	uint32_t nslots_recv;
705 	buff_ring_t *brp;
706 	recv_ring_t *rrp;
707 	dma_area_t desc;
708 	dma_area_t *bufp;
709 	sw_rx_sbd_t *bsbdp;
710 
711 	rrp = ngep->recv;
712 	brp = ngep->buff;
713 	brp->nslots = ngep->rx_buf;
714 	brp->rx_bcopy = B_FALSE;
715 	nslots_recv = rrp->desc.nslots;
716 	nslots_buff = brp->nslots;
717 	brp->ngep = ngep;
718 
719 	NGE_TRACE(("nge_init_buff_ring($%p)", (void *)ngep));
720 
721 	/*
722 	 * Allocate the array of s/w Recv Buffer Descriptors
723 	 */
724 	bsbdp = kmem_zalloc(nslots_recv *sizeof (*bsbdp), KM_SLEEP);
725 	brp->sw_rbds = bsbdp;
726 	brp->free_list = NULL;
727 	brp->recycle_list = NULL;
728 	for (slot = 0; slot < nslots_buff; ++slot) {
729 		bufp = kmem_zalloc(sizeof (dma_area_t), KM_SLEEP);
730 		err = nge_alloc_dma_mem(ngep, (ngep->buf_size
731 		    + NGE_HEADROOM),
732 		    &nge_data_accattr, DDI_DMA_READ | NGE_DMA_MODE, bufp);
733 		if (err != DDI_SUCCESS) {
734 			kmem_free(bufp, sizeof (dma_area_t));
735 			return (DDI_FAILURE);
736 		}
737 
738 		bufp->alength -= NGE_HEADROOM;
739 		bufp->offset += NGE_HEADROOM;
740 		bufp->private = (caddr_t)ngep;
741 		bufp->rx_recycle.free_func = nge_recv_recycle;
742 		bufp->rx_recycle.free_arg = (caddr_t)bufp;
743 		bufp->signature = brp->buf_sign;
744 		bufp->rx_delivered = B_FALSE;
745 		bufp->mp = desballoc(DMA_VPTR(*bufp),
746 		    ngep->buf_size + NGE_HEADROOM,
747 		    0, &bufp->rx_recycle);
748 
749 		if (bufp->mp == NULL) {
750 			return (DDI_FAILURE);
751 		}
752 		bufp->next = brp->free_list;
753 		brp->free_list = bufp;
754 	}
755 
756 	/*
757 	 * Now initialise each array element once and for all
758 	 */
759 	desc = rrp->desc;
760 	for (slot = 0; slot < nslots_recv; ++slot, ++bsbdp) {
761 		nge_slice_chunk(&bsbdp->desc, &desc, 1,
762 		    ngep->desc_attr.rxd_size);
763 		bufp = brp->free_list;
764 		brp->free_list = bufp->next;
765 		bsbdp->bufp = bufp;
766 		bsbdp->flags = CONTROLER_OWN;
767 		bufp->next = NULL;
768 	}
769 
770 	ASSERT(desc.alength == 0);
771 	return (DDI_SUCCESS);
772 }
773 
774 /*
775  * Fill the host address of data in rx' descriptor
776  * and initialize free pointers of rx free ring
777  */
778 static int
779 nge_reinit_buff_ring(nge_t *ngep)
780 {
781 	uint32_t slot;
782 	uint32_t nslots_recv;
783 	buff_ring_t *brp;
784 	recv_ring_t *rrp;
785 	sw_rx_sbd_t *bsbdp;
786 	void *hw_bd_p;
787 
788 	brp = ngep->buff;
789 	rrp = ngep->recv;
790 	bsbdp = brp->sw_rbds;
791 	nslots_recv = rrp->desc.nslots;
792 	for (slot = 0; slot < nslots_recv; ++bsbdp, ++slot) {
793 		hw_bd_p = DMA_VPTR(bsbdp->desc);
794 	/*
795 	 * There is a scenario: When the traffic of small tcp
796 	 * packet is heavy, suspending the tcp traffic will
797 	 * cause the preallocated buffers for rx not to be
798 	 * released in time by tcp taffic and cause rx's buffer
799 	 * pointers not to be refilled in time.
800 	 *
801 	 * At this point, if we reinitialize the driver, the bufp
802 	 * pointer for rx's traffic will be NULL.
803 	 * So the result of the reinitializion fails.
804 	 */
805 		if (bsbdp->bufp == NULL)
806 			return (DDI_FAILURE);
807 
808 		ngep->desc_attr.rxd_fill(hw_bd_p, &bsbdp->bufp->cookie,
809 		    bsbdp->bufp->alength);
810 	}
811 	return (DDI_SUCCESS);
812 }
813 
814 static void
815 nge_init_ring_param_lock(nge_t *ngep)
816 {
817 	buff_ring_t *brp;
818 	send_ring_t *srp;
819 
820 	srp = ngep->send;
821 	brp = ngep->buff;
822 
823 	/* Init the locks for send ring */
824 	mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER,
825 	    DDI_INTR_PRI(ngep->intr_pri));
826 	mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER,
827 	    DDI_INTR_PRI(ngep->intr_pri));
828 	mutex_init(&srp->dmah_lock, NULL, MUTEX_DRIVER,
829 	    DDI_INTR_PRI(ngep->intr_pri));
830 
831 	/* Init parameters of buffer ring */
832 	brp->free_list = NULL;
833 	brp->recycle_list = NULL;
834 	brp->rx_hold = 0;
835 	brp->buf_sign = 0;
836 
837 	/* Init recycle list lock */
838 	mutex_init(brp->recycle_lock, NULL, MUTEX_DRIVER,
839 	    DDI_INTR_PRI(ngep->intr_pri));
840 }
841 
842 int
843 nge_init_rings(nge_t *ngep)
844 {
845 	uint32_t err;
846 
847 	err = nge_init_send_ring(ngep);
848 	if (err != DDI_SUCCESS) {
849 		return (err);
850 	}
851 	nge_init_recv_ring(ngep);
852 
853 	err = nge_init_buff_ring(ngep);
854 	if (err != DDI_SUCCESS) {
855 		nge_fini_send_ring(ngep);
856 		return (DDI_FAILURE);
857 	}
858 
859 	return (err);
860 }
861 
862 static int
863 nge_reinit_ring(nge_t *ngep)
864 {
865 	int err;
866 
867 	nge_reinit_recv_ring(ngep);
868 	nge_reinit_send_ring(ngep);
869 	err = nge_reinit_buff_ring(ngep);
870 	return (err);
871 }
872 
873 
874 void
875 nge_fini_rings(nge_t *ngep)
876 {
877 	/*
878 	 * For receive ring, nothing need to be finished.
879 	 * So only finish buffer ring and send ring here.
880 	 */
881 	nge_fini_buff_ring(ngep);
882 	nge_fini_send_ring(ngep);
883 }
884 
885 /*
886  * Loopback ioctl code
887  */
888 
889 static lb_property_t loopmodes[] = {
890 	{ normal,	"normal",	NGE_LOOP_NONE		},
891 	{ external,	"100Mbps",	NGE_LOOP_EXTERNAL_100	},
892 	{ external,	"10Mbps",	NGE_LOOP_EXTERNAL_10	},
893 	{ internal,	"PHY",		NGE_LOOP_INTERNAL_PHY	},
894 };
895 
896 enum ioc_reply
897 nge_loop_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp)
898 {
899 	int cmd;
900 	uint32_t *lbmp;
901 	lb_info_sz_t *lbsp;
902 	lb_property_t *lbpp;
903 
904 	/*
905 	 * Validate format of ioctl
906 	 */
907 	if (mp->b_cont == NULL)
908 		return (IOC_INVAL);
909 
910 	cmd = iocp->ioc_cmd;
911 
912 	switch (cmd) {
913 	default:
914 		return (IOC_INVAL);
915 
916 	case LB_GET_INFO_SIZE:
917 		if (iocp->ioc_count != sizeof (lb_info_sz_t))
918 			return (IOC_INVAL);
919 		lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr;
920 		*lbsp = sizeof (loopmodes);
921 		return (IOC_REPLY);
922 
923 	case LB_GET_INFO:
924 		if (iocp->ioc_count != sizeof (loopmodes))
925 			return (IOC_INVAL);
926 		lbpp = (lb_property_t *)mp->b_cont->b_rptr;
927 		bcopy(loopmodes, lbpp, sizeof (loopmodes));
928 		return (IOC_REPLY);
929 
930 	case LB_GET_MODE:
931 		if (iocp->ioc_count != sizeof (uint32_t))
932 			return (IOC_INVAL);
933 		lbmp = (uint32_t *)mp->b_cont->b_rptr;
934 		*lbmp = ngep->param_loop_mode;
935 		return (IOC_REPLY);
936 
937 	case LB_SET_MODE:
938 		if (iocp->ioc_count != sizeof (uint32_t))
939 			return (IOC_INVAL);
940 		lbmp = (uint32_t *)mp->b_cont->b_rptr;
941 		return (nge_set_loop_mode(ngep, *lbmp));
942 	}
943 }
944 
945 #undef	NGE_DBG
946 #define	NGE_DBG	NGE_DBG_NEMO
947 
948 
949 static void
950 nge_check_desc_prop(nge_t *ngep)
951 {
952 	if (ngep->desc_mode != DESC_HOT && ngep->desc_mode != DESC_OFFLOAD)
953 		ngep->desc_mode = DESC_HOT;
954 
955 	if (ngep->desc_mode == DESC_OFFLOAD)	{
956 
957 		ngep->desc_attr = nge_sum_desc;
958 
959 	}	else if (ngep->desc_mode == DESC_HOT)	{
960 
961 		ngep->desc_attr = nge_hot_desc;
962 	}
963 }
964 
965 /*
966  * nge_get_props -- get the parameters to tune the driver
967  */
968 static void
969 nge_get_props(nge_t *ngep)
970 {
971 	chip_info_t *infop;
972 	dev_info_t *devinfo;
973 	nge_dev_spec_param_t *dev_param_p;
974 
975 	devinfo = ngep->devinfo;
976 	infop = (chip_info_t *)&ngep->chipinfo;
977 	dev_param_p = &ngep->dev_spec_param;
978 
979 	infop->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
980 	    DDI_PROP_DONTPASS, clsize_propname, 32);
981 
982 	infop->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
983 	    DDI_PROP_DONTPASS, latency_propname, 64);
984 	ngep->intr_moderation = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
985 	    DDI_PROP_DONTPASS, intr_moderation, NGE_SET);
986 	ngep->rx_datahwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
987 	    DDI_PROP_DONTPASS, rx_data_hw, 0x20);
988 	ngep->rx_prdlwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
989 	    DDI_PROP_DONTPASS, rx_prd_lw, 0x4);
990 	ngep->rx_prdhwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
991 	    DDI_PROP_DONTPASS, rx_prd_hw, 0xc);
992 
993 	ngep->sw_intr_intv = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
994 	    DDI_PROP_DONTPASS, sw_intr_intv, SWTR_ITC);
995 	ngep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
996 	    DDI_PROP_DONTPASS, debug_propname, NGE_DBG_CHIP);
997 	ngep->desc_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
998 	    DDI_PROP_DONTPASS, nge_desc_mode, dev_param_p->desc_type);
999 	ngep->lowmem_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
1000 	    DDI_PROP_DONTPASS, low_memory_mode, 0);
1001 	ngep->mac_addr_reversion = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
1002 	    DDI_PROP_DONTPASS, mac_addr_reversion, 0);
1003 
1004 	if (dev_param_p->jumbo) {
1005 		ngep->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
1006 		    DDI_PROP_DONTPASS, default_mtu, ETHERMTU);
1007 	} else
1008 		ngep->default_mtu = ETHERMTU;
1009 
1010 	if (ngep->default_mtu > ETHERMTU &&
1011 	    ngep->default_mtu <= NGE_MTU_2500) {
1012 		ngep->buf_size = NGE_JB2500_BUFSZ;
1013 		ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC;
1014 		ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC;
1015 		ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2;
1016 		ngep->nge_split = NGE_SPLIT_256;
1017 	} else if (ngep->default_mtu > NGE_MTU_2500 &&
1018 	    ngep->default_mtu <= NGE_MTU_4500) {
1019 		ngep->buf_size = NGE_JB4500_BUFSZ;
1020 		ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC;
1021 		ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC;
1022 		ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2;
1023 		ngep->nge_split = NGE_SPLIT_256;
1024 	} else if (ngep->default_mtu > NGE_MTU_4500 &&
1025 	    ngep->default_mtu <= NGE_MAX_MTU) {
1026 		ngep->buf_size = NGE_JB9000_BUFSZ;
1027 		ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC;
1028 		ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC;
1029 		ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2;
1030 		ngep->nge_split = NGE_SPLIT_256;
1031 	} else if (ngep->default_mtu > NGE_MAX_MTU) {
1032 		ngep->default_mtu = NGE_MAX_MTU;
1033 		ngep->buf_size = NGE_JB9000_BUFSZ;
1034 		ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC;
1035 		ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC;
1036 		ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2;
1037 		ngep->nge_split = NGE_SPLIT_256;
1038 	} else if (ngep->lowmem_mode != 0) {
1039 		ngep->default_mtu = ETHERMTU;
1040 		ngep->buf_size = NGE_STD_BUFSZ;
1041 		ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC;
1042 		ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC;
1043 		ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2;
1044 		ngep->nge_split = NGE_SPLIT_32;
1045 	} else {
1046 		ngep->default_mtu = ETHERMTU;
1047 		ngep->buf_size = NGE_STD_BUFSZ;
1048 		ngep->tx_desc = dev_param_p->tx_desc_num;
1049 		ngep->rx_desc = dev_param_p->rx_desc_num;
1050 		ngep->rx_buf = dev_param_p->rx_desc_num * 2;
1051 		ngep->nge_split = dev_param_p->nge_split;
1052 	}
1053 
1054 	nge_check_desc_prop(ngep);
1055 }
1056 
1057 
1058 static int
1059 nge_reset_dev(nge_t *ngep)
1060 {
1061 	int err;
1062 	nge_mul_addr1 maddr1;
1063 	nge_sw_statistics_t *sw_stp;
1064 	sw_stp = &ngep->statistics.sw_statistics;
1065 	send_ring_t *srp = ngep->send;
1066 
1067 	ASSERT(mutex_owned(ngep->genlock));
1068 	mutex_enter(srp->tc_lock);
1069 	mutex_enter(srp->tx_lock);
1070 
1071 	nge_tx_recycle_all(ngep);
1072 	err = nge_reinit_ring(ngep);
1073 	if (err == DDI_FAILURE) {
1074 		mutex_exit(srp->tx_lock);
1075 		mutex_exit(srp->tc_lock);
1076 		return (err);
1077 	}
1078 	err = nge_chip_reset(ngep);
1079 	/*
1080 	 * Clear the Multicast mac address table
1081 	 */
1082 	nge_reg_put32(ngep, NGE_MUL_ADDR0, 0);
1083 	maddr1.addr_val = nge_reg_get32(ngep, NGE_MUL_ADDR1);
1084 	maddr1.addr_bits.addr = 0;
1085 	nge_reg_put32(ngep, NGE_MUL_ADDR1, maddr1.addr_val);
1086 
1087 	mutex_exit(srp->tx_lock);
1088 	mutex_exit(srp->tc_lock);
1089 	if (err == DDI_FAILURE)
1090 		return (err);
1091 	ngep->watchdog = 0;
1092 	ngep->resched_needed = B_FALSE;
1093 	ngep->promisc = B_FALSE;
1094 	ngep->param_loop_mode = NGE_LOOP_NONE;
1095 	ngep->factotum_flag = 0;
1096 	ngep->resched_needed = 0;
1097 	ngep->nge_mac_state = NGE_MAC_RESET;
1098 	ngep->max_sdu = ngep->default_mtu + ETHER_HEAD_LEN + ETHERFCSL;
1099 	ngep->max_sdu += VTAG_SIZE;
1100 	ngep->rx_def = 0x16;
1101 
1102 	/* Clear the software statistics */
1103 	sw_stp->recv_count = 0;
1104 	sw_stp->xmit_count = 0;
1105 	sw_stp->rbytes = 0;
1106 	sw_stp->obytes = 0;
1107 
1108 	return (DDI_SUCCESS);
1109 }
1110 
1111 static void
1112 nge_m_stop(void *arg)
1113 {
1114 	nge_t *ngep = arg;		/* private device info	*/
1115 
1116 	NGE_TRACE(("nge_m_stop($%p)", arg));
1117 
1118 	/*
1119 	 * Just stop processing, then record new MAC state
1120 	 */
1121 	mutex_enter(ngep->genlock);
1122 	/* If suspended, the adapter is already stopped, just return. */
1123 	if (ngep->suspended) {
1124 		ASSERT(ngep->nge_mac_state == NGE_MAC_STOPPED);
1125 		mutex_exit(ngep->genlock);
1126 		return;
1127 	}
1128 	rw_enter(ngep->rwlock, RW_WRITER);
1129 
1130 	(void) nge_chip_stop(ngep, B_FALSE);
1131 	ngep->nge_mac_state = NGE_MAC_STOPPED;
1132 
1133 	/* Recycle all the TX BD */
1134 	nge_tx_recycle_all(ngep);
1135 	nge_fini_rings(ngep);
1136 	nge_free_bufs(ngep);
1137 
1138 	NGE_DEBUG(("nge_m_stop($%p) done", arg));
1139 
1140 	rw_exit(ngep->rwlock);
1141 	mutex_exit(ngep->genlock);
1142 }
1143 
1144 static int
1145 nge_m_start(void *arg)
1146 {
1147 	int err;
1148 	nge_t *ngep = arg;
1149 
1150 	NGE_TRACE(("nge_m_start($%p)", arg));
1151 
1152 	/*
1153 	 * Start processing and record new MAC state
1154 	 */
1155 	mutex_enter(ngep->genlock);
1156 	/*
1157 	 * If suspended, don't start, as the resume processing
1158 	 * will recall this function with the suspended flag off.
1159 	 */
1160 	if (ngep->suspended) {
1161 		mutex_exit(ngep->genlock);
1162 		return (EIO);
1163 	}
1164 	rw_enter(ngep->rwlock, RW_WRITER);
1165 	err = nge_alloc_bufs(ngep);
1166 	if (err != DDI_SUCCESS) {
1167 		nge_problem(ngep, "nge_m_start: DMA buffer allocation failed");
1168 		goto finish;
1169 	}
1170 	err = nge_init_rings(ngep);
1171 	if (err != DDI_SUCCESS) {
1172 		nge_free_bufs(ngep);
1173 		nge_problem(ngep, "nge_init_rings() failed,err=%x", err);
1174 		goto finish;
1175 	}
1176 	err = nge_restart(ngep);
1177 
1178 	NGE_DEBUG(("nge_m_start($%p) done", arg));
1179 finish:
1180 	rw_exit(ngep->rwlock);
1181 	mutex_exit(ngep->genlock);
1182 
1183 	return (err == DDI_SUCCESS ? 0 : EIO);
1184 }
1185 
1186 static int
1187 nge_m_unicst(void *arg, const uint8_t *macaddr)
1188 {
1189 	nge_t *ngep = arg;
1190 
1191 	NGE_TRACE(("nge_m_unicst($%p)", arg));
1192 	/*
1193 	 * Remember the new current address in the driver state
1194 	 * Sync the chip's idea of the address too ...
1195 	 */
1196 	mutex_enter(ngep->genlock);
1197 
1198 	ethaddr_copy(macaddr, ngep->cur_uni_addr.addr);
1199 	ngep->cur_uni_addr.set = 1;
1200 
1201 	/*
1202 	 * If we are suspended, we want to quit now, and not update
1203 	 * the chip.  Doing so might put it in a bad state, but the
1204 	 * resume will get the unicast address installed.
1205 	 */
1206 	if (ngep->suspended) {
1207 		mutex_exit(ngep->genlock);
1208 		return (DDI_SUCCESS);
1209 	}
1210 	nge_chip_sync(ngep);
1211 
1212 	NGE_DEBUG(("nge_m_unicst($%p) done", arg));
1213 	mutex_exit(ngep->genlock);
1214 
1215 	return (0);
1216 }
1217 
1218 static int
1219 nge_m_promisc(void *arg, boolean_t on)
1220 {
1221 	nge_t *ngep = arg;
1222 
1223 	NGE_TRACE(("nge_m_promisc($%p)", arg));
1224 
1225 	/*
1226 	 * Store specified mode and pass to chip layer to update h/w
1227 	 */
1228 	mutex_enter(ngep->genlock);
1229 	/*
1230 	 * If suspended, there is no need to do anything, even
1231 	 * recording the promiscuious mode is not neccessary, as
1232 	 * it won't be properly set on resume.  Just return failing.
1233 	 */
1234 	if (ngep->suspended) {
1235 		mutex_exit(ngep->genlock);
1236 		return (DDI_FAILURE);
1237 	}
1238 	if (ngep->promisc == on) {
1239 		mutex_exit(ngep->genlock);
1240 		NGE_DEBUG(("nge_m_promisc($%p) done", arg));
1241 		return (0);
1242 	}
1243 	ngep->promisc = on;
1244 	ngep->record_promisc = ngep->promisc;
1245 	nge_chip_sync(ngep);
1246 	NGE_DEBUG(("nge_m_promisc($%p) done", arg));
1247 	mutex_exit(ngep->genlock);
1248 
1249 	return (0);
1250 }
1251 
1252 static void nge_mulparam(nge_t *ngep)
1253 {
1254 	uint8_t number;
1255 	ether_addr_t pand;
1256 	ether_addr_t por;
1257 	mul_item *plist;
1258 
1259 	for (number = 0; number < ETHERADDRL; number++) {
1260 		pand[number] = 0x00;
1261 		por[number] = 0x00;
1262 	}
1263 	for (plist = ngep->pcur_mulist; plist != NULL; plist = plist->next) {
1264 		for (number = 0; number < ETHERADDRL; number++) {
1265 			pand[number] &= plist->mul_addr[number];
1266 			por[number] |= plist->mul_addr[number];
1267 		}
1268 	}
1269 	for (number = 0; number < ETHERADDRL; number++) {
1270 		ngep->cur_mul_addr.addr[number]
1271 		    = pand[number] & por[number];
1272 		ngep->cur_mul_mask.addr[number]
1273 		    = pand [number] | (~por[number]);
1274 	}
1275 }
1276 static int
1277 nge_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
1278 {
1279 	boolean_t update;
1280 	boolean_t b_eq;
1281 	nge_t *ngep = arg;
1282 	mul_item *plist;
1283 	mul_item *plist_prev;
1284 	mul_item *pitem;
1285 
1286 	NGE_TRACE(("nge_m_multicst($%p, %s, %s)", arg,
1287 	    (add) ? "add" : "remove", ether_sprintf((void *)mca)));
1288 
1289 	update = B_FALSE;
1290 	plist = plist_prev = NULL;
1291 	mutex_enter(ngep->genlock);
1292 	if (add) {
1293 		if (ngep->pcur_mulist != NULL) {
1294 			for (plist = ngep->pcur_mulist; plist != NULL;
1295 			    plist = plist->next) {
1296 				b_eq = ether_eq(plist->mul_addr, mca);
1297 				if (b_eq) {
1298 					plist->ref_cnt++;
1299 					break;
1300 				}
1301 				plist_prev = plist;
1302 			}
1303 		}
1304 
1305 		if (plist == NULL) {
1306 			pitem = kmem_zalloc(sizeof (mul_item), KM_SLEEP);
1307 			ether_copy(mca, pitem->mul_addr);
1308 			pitem ->ref_cnt++;
1309 			pitem ->next = NULL;
1310 			if (plist_prev == NULL)
1311 				ngep->pcur_mulist = pitem;
1312 			else
1313 				plist_prev->next = pitem;
1314 			update = B_TRUE;
1315 		}
1316 	} else {
1317 		if (ngep->pcur_mulist != NULL) {
1318 			for (plist = ngep->pcur_mulist; plist != NULL;
1319 			    plist = plist->next) {
1320 				b_eq = ether_eq(plist->mul_addr, mca);
1321 				if (b_eq) {
1322 					update = B_TRUE;
1323 					break;
1324 				}
1325 				plist_prev = plist;
1326 			}
1327 
1328 			if (update) {
1329 				if ((plist_prev == NULL) &&
1330 				    (plist->next == NULL))
1331 					ngep->pcur_mulist = NULL;
1332 				else if ((plist_prev == NULL) &&
1333 				    (plist->next != NULL))
1334 					ngep->pcur_mulist = plist->next;
1335 				else
1336 					plist_prev->next = plist->next;
1337 				kmem_free(plist, sizeof (mul_item));
1338 			}
1339 		}
1340 	}
1341 
1342 	if (update && !ngep->suspended) {
1343 		nge_mulparam(ngep);
1344 		nge_chip_sync(ngep);
1345 	}
1346 	NGE_DEBUG(("nge_m_multicst($%p) done", arg));
1347 	mutex_exit(ngep->genlock);
1348 
1349 	return (0);
1350 }
1351 
1352 static void
1353 nge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp)
1354 {
1355 	int err;
1356 	int cmd;
1357 	nge_t *ngep = arg;
1358 	struct iocblk *iocp;
1359 	enum ioc_reply status;
1360 	boolean_t need_privilege;
1361 
1362 	/*
1363 	 * If suspended, we might actually be able to do some of
1364 	 * these ioctls, but it is harder to make sure they occur
1365 	 * without actually putting the hardware in an undesireable
1366 	 * state.  So just NAK it.
1367 	 */
1368 	mutex_enter(ngep->genlock);
1369 	if (ngep->suspended) {
1370 		miocnak(wq, mp, 0, EINVAL);
1371 		mutex_exit(ngep->genlock);
1372 		return;
1373 	}
1374 	mutex_exit(ngep->genlock);
1375 
1376 	/*
1377 	 * Validate the command before bothering with the mutex ...
1378 	 */
1379 	iocp = (struct iocblk *)mp->b_rptr;
1380 	iocp->ioc_error = 0;
1381 	need_privilege = B_TRUE;
1382 	cmd = iocp->ioc_cmd;
1383 
1384 	NGE_DEBUG(("nge_m_ioctl:  cmd 0x%x", cmd));
1385 	switch (cmd) {
1386 	default:
1387 		NGE_LDB(NGE_DBG_BADIOC,
1388 		    ("nge_m_ioctl: unknown cmd 0x%x", cmd));
1389 
1390 		miocnak(wq, mp, 0, EINVAL);
1391 		return;
1392 
1393 	case NGE_MII_READ:
1394 	case NGE_MII_WRITE:
1395 	case NGE_SEE_READ:
1396 	case NGE_SEE_WRITE:
1397 	case NGE_DIAG:
1398 	case NGE_PEEK:
1399 	case NGE_POKE:
1400 	case NGE_PHY_RESET:
1401 	case NGE_SOFT_RESET:
1402 	case NGE_HARD_RESET:
1403 		break;
1404 
1405 	case LB_GET_INFO_SIZE:
1406 	case LB_GET_INFO:
1407 	case LB_GET_MODE:
1408 		need_privilege = B_FALSE;
1409 		break;
1410 	case LB_SET_MODE:
1411 		break;
1412 	}
1413 
1414 	if (need_privilege) {
1415 		/*
1416 		 * Check for specific net_config privilege.
1417 		 */
1418 		err = secpolicy_net_config(iocp->ioc_cr, B_FALSE);
1419 		if (err != 0) {
1420 			NGE_DEBUG(("nge_m_ioctl: rejected cmd 0x%x, err %d",
1421 			    cmd, err));
1422 			miocnak(wq, mp, 0, err);
1423 			return;
1424 		}
1425 	}
1426 
1427 	mutex_enter(ngep->genlock);
1428 
1429 	switch (cmd) {
1430 	default:
1431 		_NOTE(NOTREACHED)
1432 		status = IOC_INVAL;
1433 	break;
1434 
1435 	case NGE_MII_READ:
1436 	case NGE_MII_WRITE:
1437 	case NGE_SEE_READ:
1438 	case NGE_SEE_WRITE:
1439 	case NGE_DIAG:
1440 	case NGE_PEEK:
1441 	case NGE_POKE:
1442 	case NGE_PHY_RESET:
1443 	case NGE_SOFT_RESET:
1444 	case NGE_HARD_RESET:
1445 		status = nge_chip_ioctl(ngep, mp, iocp);
1446 	break;
1447 
1448 	case LB_GET_INFO_SIZE:
1449 	case LB_GET_INFO:
1450 	case LB_GET_MODE:
1451 	case LB_SET_MODE:
1452 		status = nge_loop_ioctl(ngep, mp, iocp);
1453 	break;
1454 
1455 	}
1456 
1457 	/*
1458 	 * Do we need to reprogram the PHY and/or the MAC?
1459 	 * Do it now, while we still have the mutex.
1460 	 *
1461 	 * Note: update the PHY first, 'cos it controls the
1462 	 * speed/duplex parameters that the MAC code uses.
1463 	 */
1464 
1465 	NGE_DEBUG(("nge_m_ioctl: cmd 0x%x status %d", cmd, status));
1466 
1467 	switch (status) {
1468 	case IOC_RESTART_REPLY:
1469 	case IOC_RESTART_ACK:
1470 		(*ngep->physops->phys_update)(ngep);
1471 		nge_chip_sync(ngep);
1472 		break;
1473 
1474 	default:
1475 	break;
1476 	}
1477 
1478 	mutex_exit(ngep->genlock);
1479 
1480 	/*
1481 	 * Finally, decide how to reply
1482 	 */
1483 	switch (status) {
1484 
1485 	default:
1486 	case IOC_INVAL:
1487 		miocnak(wq, mp, 0, iocp->ioc_error == 0 ?
1488 		    EINVAL : iocp->ioc_error);
1489 		break;
1490 
1491 	case IOC_DONE:
1492 		break;
1493 
1494 	case IOC_RESTART_ACK:
1495 	case IOC_ACK:
1496 		miocack(wq, mp, 0, 0);
1497 		break;
1498 
1499 	case IOC_RESTART_REPLY:
1500 	case IOC_REPLY:
1501 		mp->b_datap->db_type = iocp->ioc_error == 0 ?
1502 		    M_IOCACK : M_IOCNAK;
1503 		qreply(wq, mp);
1504 		break;
1505 	}
1506 }
1507 
1508 static boolean_t
1509 nge_param_locked(mac_prop_id_t pr_num)
1510 {
1511 	/*
1512 	 * All adv_* parameters are locked (read-only) while
1513 	 * the device is in any sort of loopback mode ...
1514 	 */
1515 	switch (pr_num) {
1516 		case MAC_PROP_ADV_1000FDX_CAP:
1517 		case MAC_PROP_EN_1000FDX_CAP:
1518 		case MAC_PROP_ADV_1000HDX_CAP:
1519 		case MAC_PROP_EN_1000HDX_CAP:
1520 		case MAC_PROP_ADV_100FDX_CAP:
1521 		case MAC_PROP_EN_100FDX_CAP:
1522 		case MAC_PROP_ADV_100HDX_CAP:
1523 		case MAC_PROP_EN_100HDX_CAP:
1524 		case MAC_PROP_ADV_10FDX_CAP:
1525 		case MAC_PROP_EN_10FDX_CAP:
1526 		case MAC_PROP_ADV_10HDX_CAP:
1527 		case MAC_PROP_EN_10HDX_CAP:
1528 		case MAC_PROP_AUTONEG:
1529 		case MAC_PROP_FLOWCTRL:
1530 			return (B_TRUE);
1531 	}
1532 	return (B_FALSE);
1533 }
1534 
1535 /*
1536  * callback functions for set/get of properties
1537  */
1538 static int
1539 nge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
1540     uint_t pr_valsize, const void *pr_val)
1541 {
1542 	nge_t *ngep = barg;
1543 	int err = 0;
1544 	uint32_t cur_mtu, new_mtu;
1545 	link_flowctrl_t fl;
1546 
1547 	mutex_enter(ngep->genlock);
1548 	if (ngep->param_loop_mode != NGE_LOOP_NONE &&
1549 	    nge_param_locked(pr_num)) {
1550 		/*
1551 		 * All adv_* parameters are locked (read-only)
1552 		 * while the device is in any sort of loopback mode.
1553 		 */
1554 		mutex_exit(ngep->genlock);
1555 		return (EBUSY);
1556 	}
1557 	switch (pr_num) {
1558 		case MAC_PROP_EN_1000FDX_CAP:
1559 			ngep->param_en_1000fdx = *(uint8_t *)pr_val;
1560 			ngep->param_adv_1000fdx = *(uint8_t *)pr_val;
1561 			goto reprogram;
1562 		case MAC_PROP_EN_100FDX_CAP:
1563 			ngep->param_en_100fdx = *(uint8_t *)pr_val;
1564 			ngep->param_adv_100fdx = *(uint8_t *)pr_val;
1565 			goto reprogram;
1566 		case MAC_PROP_EN_100HDX_CAP:
1567 			ngep->param_en_100hdx = *(uint8_t *)pr_val;
1568 			ngep->param_adv_100hdx = *(uint8_t *)pr_val;
1569 			goto reprogram;
1570 		case MAC_PROP_EN_10FDX_CAP:
1571 			ngep->param_en_10fdx = *(uint8_t *)pr_val;
1572 			ngep->param_adv_10fdx = *(uint8_t *)pr_val;
1573 			goto reprogram;
1574 		case MAC_PROP_EN_10HDX_CAP:
1575 			ngep->param_en_10hdx = *(uint8_t *)pr_val;
1576 			ngep->param_adv_10hdx = *(uint8_t *)pr_val;
1577 reprogram:
1578 		(*ngep->physops->phys_update)(ngep);
1579 		nge_chip_sync(ngep);
1580 		break;
1581 
1582 		case MAC_PROP_ADV_1000FDX_CAP:
1583 		case MAC_PROP_ADV_1000HDX_CAP:
1584 		case MAC_PROP_ADV_100FDX_CAP:
1585 		case MAC_PROP_ADV_100HDX_CAP:
1586 		case MAC_PROP_ADV_10FDX_CAP:
1587 		case MAC_PROP_ADV_10HDX_CAP:
1588 		case MAC_PROP_STATUS:
1589 		case MAC_PROP_SPEED:
1590 		case MAC_PROP_DUPLEX:
1591 		case MAC_PROP_EN_1000HDX_CAP:
1592 			err = ENOTSUP; /* read-only prop. Can't set this */
1593 			break;
1594 		case MAC_PROP_AUTONEG:
1595 			ngep->param_adv_autoneg = *(uint8_t *)pr_val;
1596 			(*ngep->physops->phys_update)(ngep);
1597 			nge_chip_sync(ngep);
1598 			break;
1599 		case MAC_PROP_MTU:
1600 			cur_mtu = ngep->default_mtu;
1601 			bcopy(pr_val, &new_mtu, sizeof (new_mtu));
1602 			if (new_mtu == cur_mtu) {
1603 				err = 0;
1604 				break;
1605 			}
1606 			if (new_mtu < ETHERMTU ||
1607 			    new_mtu > NGE_MAX_MTU) {
1608 				err = EINVAL;
1609 				break;
1610 			}
1611 			if ((new_mtu > ETHERMTU) &&
1612 			    (!ngep->dev_spec_param.jumbo)) {
1613 				err = EINVAL;
1614 				break;
1615 			}
1616 			if (ngep->nge_mac_state == NGE_MAC_STARTED) {
1617 				err = EBUSY;
1618 				break;
1619 			}
1620 
1621 			ngep->default_mtu = new_mtu;
1622 			if (ngep->default_mtu > ETHERMTU &&
1623 			    ngep->default_mtu <= NGE_MTU_2500) {
1624 				ngep->buf_size = NGE_JB2500_BUFSZ;
1625 				ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC;
1626 				ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC;
1627 				ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2;
1628 				ngep->nge_split = NGE_SPLIT_256;
1629 			} else if (ngep->default_mtu > NGE_MTU_2500 &&
1630 			    ngep->default_mtu <= NGE_MTU_4500) {
1631 				ngep->buf_size = NGE_JB4500_BUFSZ;
1632 				ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC;
1633 				ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC;
1634 				ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2;
1635 				ngep->nge_split = NGE_SPLIT_256;
1636 			} else if (ngep->default_mtu > NGE_MTU_4500 &&
1637 			    ngep->default_mtu <= NGE_MAX_MTU) {
1638 				ngep->buf_size = NGE_JB9000_BUFSZ;
1639 				ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC;
1640 				ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC;
1641 				ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2;
1642 				ngep->nge_split = NGE_SPLIT_256;
1643 			} else if (ngep->default_mtu > NGE_MAX_MTU) {
1644 				ngep->default_mtu = NGE_MAX_MTU;
1645 				ngep->buf_size = NGE_JB9000_BUFSZ;
1646 				ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC;
1647 				ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC;
1648 				ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2;
1649 				ngep->nge_split = NGE_SPLIT_256;
1650 			} else if (ngep->lowmem_mode != 0) {
1651 				ngep->default_mtu = ETHERMTU;
1652 				ngep->buf_size = NGE_STD_BUFSZ;
1653 				ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC;
1654 				ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC;
1655 				ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2;
1656 				ngep->nge_split = NGE_SPLIT_32;
1657 			} else {
1658 				ngep->default_mtu = ETHERMTU;
1659 				ngep->buf_size = NGE_STD_BUFSZ;
1660 				ngep->tx_desc =
1661 				    ngep->dev_spec_param.tx_desc_num;
1662 				ngep->rx_desc =
1663 				    ngep->dev_spec_param.rx_desc_num;
1664 				ngep->rx_buf =
1665 				    ngep->dev_spec_param.rx_desc_num * 2;
1666 				ngep->nge_split =
1667 				    ngep->dev_spec_param.nge_split;
1668 			}
1669 
1670 			err = mac_maxsdu_update(ngep->mh, ngep->default_mtu);
1671 
1672 			break;
1673 		case MAC_PROP_FLOWCTRL:
1674 			bcopy(pr_val, &fl, sizeof (fl));
1675 			switch (fl) {
1676 			default:
1677 				err = ENOTSUP;
1678 				break;
1679 			case LINK_FLOWCTRL_NONE:
1680 				ngep->param_adv_pause = 0;
1681 				ngep->param_adv_asym_pause = 0;
1682 
1683 				ngep->param_link_rx_pause = B_FALSE;
1684 				ngep->param_link_tx_pause = B_FALSE;
1685 				break;
1686 			case LINK_FLOWCTRL_RX:
1687 				if (!((ngep->param_lp_pause == 0) &&
1688 				    (ngep->param_lp_asym_pause == 1))) {
1689 					err = EINVAL;
1690 					break;
1691 				}
1692 				ngep->param_adv_pause = 1;
1693 				ngep->param_adv_asym_pause = 1;
1694 
1695 				ngep->param_link_rx_pause = B_TRUE;
1696 				ngep->param_link_tx_pause = B_FALSE;
1697 				break;
1698 			case LINK_FLOWCTRL_TX:
1699 				if (!((ngep->param_lp_pause == 1) &&
1700 				    (ngep->param_lp_asym_pause == 1))) {
1701 					err = EINVAL;
1702 					break;
1703 				}
1704 				ngep->param_adv_pause = 0;
1705 				ngep->param_adv_asym_pause = 1;
1706 
1707 				ngep->param_link_rx_pause = B_FALSE;
1708 				ngep->param_link_tx_pause = B_TRUE;
1709 				break;
1710 			case LINK_FLOWCTRL_BI:
1711 				if (ngep->param_lp_pause != 1) {
1712 					err = EINVAL;
1713 					break;
1714 				}
1715 				ngep->param_adv_pause = 1;
1716 
1717 				ngep->param_link_rx_pause = B_TRUE;
1718 				ngep->param_link_tx_pause = B_TRUE;
1719 				break;
1720 			}
1721 
1722 			if (err == 0) {
1723 				(*ngep->physops->phys_update)(ngep);
1724 				nge_chip_sync(ngep);
1725 			}
1726 
1727 			break;
1728 		case MAC_PROP_PRIVATE:
1729 			err = nge_set_priv_prop(ngep, pr_name, pr_valsize,
1730 			    pr_val);
1731 			if (err == 0) {
1732 				(*ngep->physops->phys_update)(ngep);
1733 				nge_chip_sync(ngep);
1734 			}
1735 			break;
1736 		default:
1737 			err = ENOTSUP;
1738 	}
1739 	mutex_exit(ngep->genlock);
1740 	return (err);
1741 }
1742 
1743 static int
1744 nge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
1745     uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm)
1746 {
1747 	nge_t *ngep = barg;
1748 	int err = 0;
1749 	link_flowctrl_t fl;
1750 	uint64_t speed;
1751 	boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT);
1752 
1753 	if (pr_valsize == 0)
1754 		return (EINVAL);
1755 
1756 	*perm = MAC_PROP_PERM_RW;
1757 
1758 	bzero(pr_val, pr_valsize);
1759 
1760 	switch (pr_num) {
1761 		case MAC_PROP_DUPLEX:
1762 			*perm = MAC_PROP_PERM_READ;
1763 			if (pr_valsize >= sizeof (link_duplex_t)) {
1764 				bcopy(&ngep->param_link_duplex, pr_val,
1765 				    sizeof (link_duplex_t));
1766 			} else
1767 				err = EINVAL;
1768 			break;
1769 		case MAC_PROP_SPEED:
1770 			*perm = MAC_PROP_PERM_READ;
1771 			if (pr_valsize >= sizeof (uint64_t)) {
1772 				speed = ngep->param_link_speed * 1000000ull;
1773 				bcopy(&speed, pr_val, sizeof (speed));
1774 			} else
1775 				err = EINVAL;
1776 			break;
1777 		case MAC_PROP_AUTONEG:
1778 			if (is_default) {
1779 				*(uint8_t *)pr_val = 1;
1780 			} else {
1781 				*(uint8_t *)pr_val = ngep->param_adv_autoneg;
1782 			}
1783 			break;
1784 		case MAC_PROP_FLOWCTRL:
1785 			if (pr_valsize >= sizeof (link_flowctrl_t)) {
1786 				if (pr_flags & MAC_PROP_DEFAULT) {
1787 					fl = LINK_FLOWCTRL_BI;
1788 					bcopy(&fl, pr_val, sizeof (fl));
1789 					break;
1790 				}
1791 				if (ngep->param_link_rx_pause &&
1792 				    !ngep->param_link_tx_pause)
1793 					fl = LINK_FLOWCTRL_RX;
1794 
1795 				if (!ngep->param_link_rx_pause &&
1796 				    !ngep->param_link_tx_pause)
1797 					fl = LINK_FLOWCTRL_NONE;
1798 
1799 				if (!ngep->param_link_rx_pause &&
1800 				    ngep->param_link_tx_pause)
1801 					fl = LINK_FLOWCTRL_TX;
1802 
1803 				if (ngep->param_link_rx_pause &&
1804 				    ngep->param_link_tx_pause)
1805 					fl = LINK_FLOWCTRL_BI;
1806 				bcopy(&fl, pr_val, sizeof (fl));
1807 			} else
1808 				err = EINVAL;
1809 			break;
1810 		case MAC_PROP_ADV_1000FDX_CAP:
1811 			*perm = MAC_PROP_PERM_READ;
1812 			if (is_default) {
1813 				*(uint8_t *)pr_val = 1;
1814 			} else {
1815 				*(uint8_t *)pr_val = ngep->param_adv_1000fdx;
1816 			}
1817 			break;
1818 		case MAC_PROP_EN_1000FDX_CAP:
1819 			if (is_default) {
1820 				*(uint8_t *)pr_val = 1;
1821 			} else {
1822 				*(uint8_t *)pr_val = ngep->param_en_1000fdx;
1823 			}
1824 			break;
1825 		case MAC_PROP_ADV_1000HDX_CAP:
1826 			*perm = MAC_PROP_PERM_READ;
1827 			if (is_default) {
1828 				*(uint8_t *)pr_val = 0;
1829 			} else {
1830 				*(uint8_t *)pr_val = ngep->param_adv_1000hdx;
1831 			}
1832 			break;
1833 		case MAC_PROP_EN_1000HDX_CAP:
1834 			*perm = MAC_PROP_PERM_READ;
1835 			if (is_default) {
1836 				*(uint8_t *)pr_val = 0;
1837 			} else {
1838 				*(uint8_t *)pr_val = ngep->param_en_1000hdx;
1839 			}
1840 			break;
1841 		case MAC_PROP_ADV_100FDX_CAP:
1842 			*perm = MAC_PROP_PERM_READ;
1843 			if (is_default) {
1844 				*(uint8_t *)pr_val = 1;
1845 			} else {
1846 				*(uint8_t *)pr_val = ngep->param_adv_100fdx;
1847 			}
1848 			break;
1849 		case MAC_PROP_EN_100FDX_CAP:
1850 			if (is_default) {
1851 				*(uint8_t *)pr_val = 1;
1852 			} else {
1853 				*(uint8_t *)pr_val = ngep->param_en_100fdx;
1854 			}
1855 			break;
1856 		case MAC_PROP_ADV_100HDX_CAP:
1857 			*perm = MAC_PROP_PERM_READ;
1858 			if (is_default) {
1859 				*(uint8_t *)pr_val = 1;
1860 			} else {
1861 				*(uint8_t *)pr_val = ngep->param_adv_100hdx;
1862 			}
1863 			break;
1864 		case MAC_PROP_EN_100HDX_CAP:
1865 			if (is_default) {
1866 				*(uint8_t *)pr_val = 1;
1867 			} else {
1868 				*(uint8_t *)pr_val = ngep->param_en_100hdx;
1869 			}
1870 			break;
1871 		case MAC_PROP_ADV_10FDX_CAP:
1872 			*perm = MAC_PROP_PERM_READ;
1873 			if (is_default) {
1874 				*(uint8_t *)pr_val = 1;
1875 			} else {
1876 				*(uint8_t *)pr_val = ngep->param_adv_10fdx;
1877 			}
1878 			break;
1879 		case MAC_PROP_EN_10FDX_CAP:
1880 			if (is_default) {
1881 				*(uint8_t *)pr_val = 1;
1882 			} else {
1883 				*(uint8_t *)pr_val = ngep->param_en_10fdx;
1884 			}
1885 			break;
1886 		case MAC_PROP_ADV_10HDX_CAP:
1887 			*perm = MAC_PROP_PERM_READ;
1888 			if (is_default) {
1889 				*(uint8_t *)pr_val = 1;
1890 			} else {
1891 				*(uint8_t *)pr_val = ngep->param_adv_10hdx;
1892 			}
1893 			break;
1894 		case MAC_PROP_EN_10HDX_CAP:
1895 			if (is_default) {
1896 				*(uint8_t *)pr_val = 1;
1897 			} else {
1898 				*(uint8_t *)pr_val = ngep->param_en_10hdx;
1899 			}
1900 			break;
1901 		case MAC_PROP_ADV_100T4_CAP:
1902 		case MAC_PROP_EN_100T4_CAP:
1903 			*perm = MAC_PROP_PERM_READ;
1904 			*(uint8_t *)pr_val = 0;
1905 			break;
1906 		case MAC_PROP_PRIVATE:
1907 			err = nge_get_priv_prop(ngep, pr_name, pr_flags,
1908 			    pr_valsize, pr_val);
1909 			break;
1910 		default:
1911 			err = ENOTSUP;
1912 	}
1913 	return (err);
1914 }
1915 
1916 /* ARGSUSED */
1917 static int
1918 nge_set_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_valsize,
1919     const void *pr_val)
1920 {
1921 	int err = 0;
1922 	long result;
1923 
1924 	if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
1925 		if (pr_val == NULL) {
1926 			err = EINVAL;
1927 			return (err);
1928 		}
1929 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1930 		if (result < 0 || result > NGE_MAX_SDU) {
1931 			err = EINVAL;
1932 		} else {
1933 			ngep->param_txbcopy_threshold = (uint32_t)result;
1934 			goto reprogram;
1935 		}
1936 		return (err);
1937 	}
1938 	if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
1939 		if (pr_val == NULL) {
1940 			err = EINVAL;
1941 			return (err);
1942 		}
1943 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1944 		if (result < 0 || result > NGE_MAX_SDU) {
1945 			err = EINVAL;
1946 		} else {
1947 			ngep->param_rxbcopy_threshold = (uint32_t)result;
1948 			goto reprogram;
1949 		}
1950 		return (err);
1951 	}
1952 	if (strcmp(pr_name, "_recv_max_packet") == 0) {
1953 		if (pr_val == NULL) {
1954 			err = EINVAL;
1955 			return (err);
1956 		}
1957 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1958 		if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) {
1959 			err = EINVAL;
1960 		} else {
1961 			ngep->param_recv_max_packet = (uint32_t)result;
1962 			goto reprogram;
1963 		}
1964 		return (err);
1965 	}
1966 	if (strcmp(pr_name, "_poll_quiet_time") == 0) {
1967 		if (pr_val == NULL) {
1968 			err = EINVAL;
1969 			return (err);
1970 		}
1971 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1972 		if (result < 0 || result > 10000) {
1973 			err = EINVAL;
1974 		} else {
1975 			ngep->param_poll_quiet_time = (uint32_t)result;
1976 			goto reprogram;
1977 		}
1978 		return (err);
1979 	}
1980 	if (strcmp(pr_name, "_poll_busy_time") == 0) {
1981 		if (pr_val == NULL) {
1982 			err = EINVAL;
1983 			return (err);
1984 		}
1985 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1986 		if (result < 0 || result > 10000) {
1987 			err = EINVAL;
1988 		} else {
1989 			ngep->param_poll_busy_time = (uint32_t)result;
1990 			goto reprogram;
1991 		}
1992 		return (err);
1993 	}
1994 	if (strcmp(pr_name, "_rx_intr_hwater") == 0) {
1995 		if (pr_val == NULL) {
1996 			err = EINVAL;
1997 			return (err);
1998 		}
1999 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
2000 		if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) {
2001 			err = EINVAL;
2002 		} else {
2003 			ngep->param_rx_intr_hwater = (uint32_t)result;
2004 			goto reprogram;
2005 		}
2006 		return (err);
2007 	}
2008 	if (strcmp(pr_name, "_rx_intr_lwater") == 0) {
2009 		if (pr_val == NULL) {
2010 			err = EINVAL;
2011 			return (err);
2012 		}
2013 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
2014 		if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) {
2015 			err = EINVAL;
2016 		} else {
2017 			ngep->param_rx_intr_lwater = (uint32_t)result;
2018 			goto reprogram;
2019 		}
2020 		return (err);
2021 	}
2022 	if (strcmp(pr_name, "_tx_n_intr") == 0) {
2023 		if (pr_val == NULL) {
2024 			err = EINVAL;
2025 			return (err);
2026 		}
2027 		(void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
2028 		if (result < 1 || result > 10000) {
2029 			err = EINVAL;
2030 		} else {
2031 			ngep->param_tx_n_intr = (uint32_t)result;
2032 			goto reprogram;
2033 		}
2034 		return (err);
2035 	}
2036 
2037 	err = ENOTSUP;
2038 	return (err);
2039 
2040 reprogram:
2041 	if (err == 0) {
2042 		(*ngep->physops->phys_update)(ngep);
2043 		nge_chip_sync(ngep);
2044 	}
2045 
2046 	return (err);
2047 }
2048 
2049 static int
2050 nge_get_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_flags,
2051     uint_t pr_valsize, void *pr_val)
2052 {
2053 	int err = ENOTSUP;
2054 	boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT);
2055 	int value;
2056 
2057 	if (strcmp(pr_name, "_adv_pause_cap") == 0) {
2058 		value = (is_default ? 1 : ngep->param_adv_pause);
2059 		err = 0;
2060 		goto done;
2061 	}
2062 	if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
2063 		value = (is_default ? 1 : ngep->param_adv_asym_pause);
2064 		err = 0;
2065 		goto done;
2066 	}
2067 	if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) {
2068 		value = (is_default ? NGE_TX_COPY_SIZE :
2069 		    ngep->param_txbcopy_threshold);
2070 		err = 0;
2071 		goto done;
2072 	}
2073 	if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) {
2074 		value = (is_default ? NGE_RX_COPY_SIZE :
2075 		    ngep->param_rxbcopy_threshold);
2076 		err = 0;
2077 		goto done;
2078 	}
2079 	if (strcmp(pr_name, "_recv_max_packet") == 0) {
2080 		value = (is_default ? 128 : ngep->param_recv_max_packet);
2081 		err = 0;
2082 		goto done;
2083 	}
2084 	if (strcmp(pr_name, "_poll_quiet_time") == 0) {
2085 		value = (is_default ? NGE_POLL_QUIET_TIME :
2086 		    ngep->param_poll_quiet_time);
2087 		err = 0;
2088 		goto done;
2089 	}
2090 	if (strcmp(pr_name, "_poll_busy_time") == 0) {
2091 		value = (is_default ? NGE_POLL_BUSY_TIME :
2092 		    ngep->param_poll_busy_time);
2093 		err = 0;
2094 		goto done;
2095 	}
2096 	if (strcmp(pr_name, "_rx_intr_hwater") == 0) {
2097 		value = (is_default ? 1 : ngep->param_rx_intr_hwater);
2098 		err = 0;
2099 		goto done;
2100 	}
2101 	if (strcmp(pr_name, "_rx_intr_lwater") == 0) {
2102 		value = (is_default ? 8 : ngep->param_rx_intr_lwater);
2103 		err = 0;
2104 		goto done;
2105 	}
2106 	if (strcmp(pr_name, "_tx_n_intr") == 0) {
2107 		value = (is_default ? NGE_TX_N_INTR :
2108 		    ngep->param_tx_n_intr);
2109 		err = 0;
2110 		goto done;
2111 	}
2112 
2113 done:
2114 	if (err == 0) {
2115 		(void) snprintf(pr_val, pr_valsize, "%d", value);
2116 	}
2117 	return (err);
2118 }
2119 
2120 /* ARGSUSED */
2121 static boolean_t
2122 nge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
2123 {
2124 	nge_t	*ngep = arg;
2125 	nge_dev_spec_param_t *dev_param_p;
2126 
2127 	dev_param_p = &ngep->dev_spec_param;
2128 
2129 	switch (cap) {
2130 	case MAC_CAPAB_HCKSUM: {
2131 		uint32_t *hcksum_txflags = cap_data;
2132 
2133 		if (dev_param_p->tx_hw_checksum) {
2134 			*hcksum_txflags = dev_param_p->tx_hw_checksum;
2135 		} else
2136 			return (B_FALSE);
2137 		break;
2138 	}
2139 	default:
2140 		return (B_FALSE);
2141 	}
2142 	return (B_TRUE);
2143 }
2144 
2145 #undef	NGE_DBG
2146 #define	NGE_DBG	NGE_DBG_INIT	/* debug flag for this code	*/
2147 int
2148 nge_restart(nge_t *ngep)
2149 {
2150 	int err = 0;
2151 	err = nge_reset_dev(ngep);
2152 	/* write back the promisc setting */
2153 	ngep->promisc = ngep->record_promisc;
2154 	nge_chip_sync(ngep);
2155 	if (!err)
2156 		err = nge_chip_start(ngep);
2157 
2158 	if (err) {
2159 		ngep->nge_mac_state = NGE_MAC_STOPPED;
2160 		return (DDI_FAILURE);
2161 	} else {
2162 		ngep->nge_mac_state = NGE_MAC_STARTED;
2163 		return (DDI_SUCCESS);
2164 	}
2165 }
2166 
2167 void
2168 nge_wake_factotum(nge_t *ngep)
2169 {
2170 	mutex_enter(ngep->softlock);
2171 	if (ngep->factotum_flag == 0) {
2172 		ngep->factotum_flag = 1;
2173 		(void) ddi_intr_trigger_softint(ngep->factotum_hdl, NULL);
2174 	}
2175 	mutex_exit(ngep->softlock);
2176 }
2177 
2178 /*
2179  * High-level cyclic handler
2180  *
2181  * This routine schedules a (low-level) softint callback to the
2182  * factotum.
2183  */
2184 
2185 static void
2186 nge_chip_cyclic(void *arg)
2187 {
2188 	nge_t *ngep;
2189 
2190 	ngep = (nge_t *)arg;
2191 
2192 	switch (ngep->nge_chip_state) {
2193 	default:
2194 		return;
2195 
2196 	case NGE_CHIP_RUNNING:
2197 		break;
2198 
2199 	case NGE_CHIP_FAULT:
2200 	case NGE_CHIP_ERROR:
2201 		break;
2202 	}
2203 
2204 	nge_wake_factotum(ngep);
2205 }
2206 
2207 static void
2208 nge_unattach(nge_t *ngep)
2209 {
2210 	send_ring_t *srp;
2211 	buff_ring_t *brp;
2212 
2213 	srp = ngep->send;
2214 	brp = ngep->buff;
2215 	NGE_TRACE(("nge_unattach($%p)", (void *)ngep));
2216 
2217 	/*
2218 	 * Flag that no more activity may be initiated
2219 	 */
2220 	ngep->progress &= ~PROGRESS_READY;
2221 	ngep->nge_mac_state = NGE_MAC_UNATTACH;
2222 
2223 	/*
2224 	 * Quiesce the PHY and MAC (leave it reset but still powered).
2225 	 * Clean up and free all NGE data structures
2226 	 */
2227 	if (ngep->periodic_id != NULL) {
2228 		ddi_periodic_delete(ngep->periodic_id);
2229 		ngep->periodic_id = NULL;
2230 	}
2231 
2232 	if (ngep->progress & PROGRESS_KSTATS)
2233 		nge_fini_kstats(ngep);
2234 
2235 	if (ngep->progress & PROGRESS_HWINT) {
2236 		mutex_enter(ngep->genlock);
2237 		nge_restore_mac_addr(ngep);
2238 		(void) nge_chip_stop(ngep, B_FALSE);
2239 		mutex_exit(ngep->genlock);
2240 	}
2241 
2242 	if (ngep->progress & PROGRESS_SWINT)
2243 		nge_rem_intrs(ngep);
2244 
2245 	if (ngep->progress & PROGRESS_FACTOTUM)
2246 		(void) ddi_intr_remove_softint(ngep->factotum_hdl);
2247 
2248 	if (ngep->progress & PROGRESS_RESCHED)
2249 		(void) ddi_intr_remove_softint(ngep->resched_hdl);
2250 
2251 	if (ngep->progress & PROGRESS_INTR) {
2252 		mutex_destroy(srp->tx_lock);
2253 		mutex_destroy(srp->tc_lock);
2254 		mutex_destroy(&srp->dmah_lock);
2255 		mutex_destroy(brp->recycle_lock);
2256 
2257 		mutex_destroy(ngep->genlock);
2258 		mutex_destroy(ngep->softlock);
2259 		rw_destroy(ngep->rwlock);
2260 	}
2261 
2262 	if (ngep->progress & PROGRESS_REGS)
2263 		ddi_regs_map_free(&ngep->io_handle);
2264 
2265 	if (ngep->progress & PROGRESS_CFG)
2266 		pci_config_teardown(&ngep->cfg_handle);
2267 
2268 	ddi_remove_minor_node(ngep->devinfo, NULL);
2269 
2270 	kmem_free(ngep, sizeof (*ngep));
2271 }
2272 
2273 static int
2274 nge_resume(dev_info_t *devinfo)
2275 {
2276 	nge_t		*ngep;
2277 	chip_info_t	*infop;
2278 	int 		err;
2279 
2280 	ASSERT(devinfo != NULL);
2281 
2282 	ngep = ddi_get_driver_private(devinfo);
2283 	err = 0;
2284 
2285 	/*
2286 	 * If there are state inconsistancies, this is bad.  Returning
2287 	 * DDI_FAILURE here will eventually cause the machine to panic,
2288 	 * so it is best done here so that there is a possibility of
2289 	 * debugging the problem.
2290 	 */
2291 	if (ngep == NULL)
2292 		cmn_err(CE_PANIC,
2293 		    "nge: ngep returned from ddi_get_driver_private was NULL");
2294 	infop = (chip_info_t *)&ngep->chipinfo;
2295 
2296 	if (ngep->devinfo != devinfo)
2297 		cmn_err(CE_PANIC,
2298 		    "nge: passed devinfo not the same as saved devinfo");
2299 
2300 	mutex_enter(ngep->genlock);
2301 	rw_enter(ngep->rwlock, RW_WRITER);
2302 
2303 	/*
2304 	 * Fetch the config space.  Even though we have most of it cached,
2305 	 * some values *might* change across a suspend/resume.
2306 	 */
2307 	nge_chip_cfg_init(ngep, infop, B_FALSE);
2308 
2309 	/*
2310 	 * Only in one case, this conditional branch can be executed: the port
2311 	 * hasn't been plumbed.
2312 	 */
2313 	if (ngep->suspended == B_FALSE) {
2314 		rw_exit(ngep->rwlock);
2315 		mutex_exit(ngep->genlock);
2316 		return (DDI_SUCCESS);
2317 	}
2318 
2319 	nge_tx_recycle_all(ngep);
2320 	err = nge_reinit_ring(ngep);
2321 	if (!err) {
2322 		err = nge_chip_reset(ngep);
2323 		if (!err)
2324 			err = nge_chip_start(ngep);
2325 	}
2326 
2327 	if (err) {
2328 		/*
2329 		 * We note the failure, but return success, as the
2330 		 * system is still usable without this controller.
2331 		 */
2332 		cmn_err(CE_WARN, "nge: resume: failed to restart controller");
2333 	} else {
2334 		ngep->nge_mac_state = NGE_MAC_STARTED;
2335 	}
2336 	ngep->suspended = B_FALSE;
2337 
2338 	rw_exit(ngep->rwlock);
2339 	mutex_exit(ngep->genlock);
2340 
2341 	return (DDI_SUCCESS);
2342 }
2343 
2344 /*
2345  * attach(9E) -- Attach a device to the system
2346  *
2347  * Called once for each board successfully probed.
2348  */
2349 static int
2350 nge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2351 {
2352 	int		err;
2353 	int		i;
2354 	int		instance;
2355 	caddr_t		regs;
2356 	nge_t		*ngep;
2357 	chip_info_t	*infop;
2358 	mac_register_t	*macp;
2359 
2360 	switch (cmd) {
2361 	default:
2362 		return (DDI_FAILURE);
2363 
2364 	case DDI_RESUME:
2365 		return (nge_resume(devinfo));
2366 
2367 	case DDI_ATTACH:
2368 		break;
2369 	}
2370 
2371 	ngep = kmem_zalloc(sizeof (*ngep), KM_SLEEP);
2372 	instance = ddi_get_instance(devinfo);
2373 	ddi_set_driver_private(devinfo, ngep);
2374 	ngep->devinfo = devinfo;
2375 
2376 	(void) snprintf(ngep->ifname, sizeof (ngep->ifname), "%s%d",
2377 	    NGE_DRIVER_NAME, instance);
2378 	err = pci_config_setup(devinfo, &ngep->cfg_handle);
2379 	if (err != DDI_SUCCESS) {
2380 		nge_problem(ngep, "nge_attach: pci_config_setup() failed");
2381 		goto attach_fail;
2382 	}
2383 	/*
2384 	 * param_txbcopy_threshold and param_rxbcopy_threshold are tx/rx bcopy
2385 	 * thresholds. Bounds: min 0, max NGE_MAX_SDU
2386 	 */
2387 	ngep->param_txbcopy_threshold = NGE_TX_COPY_SIZE;
2388 	ngep->param_rxbcopy_threshold = NGE_RX_COPY_SIZE;
2389 
2390 	/*
2391 	 * param_recv_max_packet is max packet received per interupt.
2392 	 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024
2393 	 */
2394 	ngep->param_recv_max_packet = 128;
2395 
2396 	/*
2397 	 * param_poll_quiet_time and param_poll_busy_time are quiet/busy time
2398 	 * switch from per packet interrupt to polling interrupt.
2399 	 * Bounds: min 0, max 10000
2400 	 */
2401 	ngep->param_poll_quiet_time = NGE_POLL_QUIET_TIME;
2402 	ngep->param_poll_busy_time = NGE_POLL_BUSY_TIME;
2403 
2404 	/*
2405 	 * param_rx_intr_hwater/param_rx_intr_lwater: ackets received
2406 	 * to trigger the poll_quiet_time/poll_busy_time counter.
2407 	 * Bounds: min 0, max  NGE_RECV_SLOTS_DESC_1024.
2408 	 */
2409 	ngep->param_rx_intr_hwater = 1;
2410 	ngep->param_rx_intr_lwater = 8;
2411 
2412 	/*
2413 	 * param_tx_n_intr: Per N tx packets to do tx recycle in poll mode.
2414 	 * Bounds: min 1, max 10000.
2415 	 */
2416 	ngep->param_tx_n_intr = NGE_TX_N_INTR;
2417 
2418 	infop = (chip_info_t *)&ngep->chipinfo;
2419 	nge_chip_cfg_init(ngep, infop, B_FALSE);
2420 	nge_init_dev_spec_param(ngep);
2421 	nge_get_props(ngep);
2422 	ngep->progress |= PROGRESS_CFG;
2423 
2424 	err = ddi_regs_map_setup(devinfo, NGE_PCI_OPREGS_RNUMBER,
2425 	    &regs, 0, 0, &nge_reg_accattr, &ngep->io_handle);
2426 	if (err != DDI_SUCCESS) {
2427 		nge_problem(ngep, "nge_attach: ddi_regs_map_setup() failed");
2428 		goto attach_fail;
2429 	}
2430 	ngep->io_regs = regs;
2431 	ngep->progress |= PROGRESS_REGS;
2432 
2433 	err = nge_register_intrs_and_init_locks(ngep);
2434 	if (err != DDI_SUCCESS) {
2435 		nge_problem(ngep, "nge_attach:"
2436 		    " register intrs and init locks failed");
2437 		goto attach_fail;
2438 	}
2439 	nge_init_ring_param_lock(ngep);
2440 	ngep->progress |= PROGRESS_INTR;
2441 
2442 	mutex_enter(ngep->genlock);
2443 
2444 	/*
2445 	 * Initialise link state variables
2446 	 * Stop, reset & reinitialise the chip.
2447 	 * Initialise the (internal) PHY.
2448 	 */
2449 	nge_phys_init(ngep);
2450 	ngep->nge_chip_state = NGE_CHIP_INITIAL;
2451 	err = nge_chip_reset(ngep);
2452 	if (err != DDI_SUCCESS) {
2453 		nge_problem(ngep, "nge_attach: nge_chip_reset() failed");
2454 		mutex_exit(ngep->genlock);
2455 		goto attach_fail;
2456 	}
2457 	nge_chip_sync(ngep);
2458 
2459 	/*
2460 	 * Now that mutex locks are initialized, enable interrupts.
2461 	 */
2462 	if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) {
2463 		/* Call ddi_intr_block_enable() for MSI interrupts */
2464 		(void) ddi_intr_block_enable(ngep->htable,
2465 		    ngep->intr_actual_cnt);
2466 	} else {
2467 		/* Call ddi_intr_enable for MSI or FIXED interrupts */
2468 		for (i = 0; i < ngep->intr_actual_cnt; i++) {
2469 			(void) ddi_intr_enable(ngep->htable[i]);
2470 		}
2471 	}
2472 
2473 	ngep->link_state = LINK_STATE_UNKNOWN;
2474 	ngep->progress |= PROGRESS_HWINT;
2475 
2476 	/*
2477 	 * Register NDD-tweakable parameters
2478 	 */
2479 	if (nge_nd_init(ngep)) {
2480 		nge_problem(ngep, "nge_attach: nge_nd_init() failed");
2481 		mutex_exit(ngep->genlock);
2482 		goto attach_fail;
2483 	}
2484 	ngep->progress |= PROGRESS_NDD;
2485 
2486 	/*
2487 	 * Create & initialise named kstats
2488 	 */
2489 	nge_init_kstats(ngep, instance);
2490 	ngep->progress |= PROGRESS_KSTATS;
2491 
2492 	mutex_exit(ngep->genlock);
2493 
2494 	if ((macp = mac_alloc(MAC_VERSION)) == NULL)
2495 		goto attach_fail;
2496 	macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
2497 	macp->m_driver = ngep;
2498 	macp->m_dip = devinfo;
2499 	macp->m_src_addr = infop->vendor_addr.addr;
2500 	macp->m_callbacks = &nge_m_callbacks;
2501 	macp->m_min_sdu = 0;
2502 	macp->m_max_sdu = ngep->default_mtu;
2503 	macp->m_margin = VTAG_SIZE;
2504 	macp->m_priv_props = nge_priv_props;
2505 	macp->m_priv_prop_count = NGE_MAX_PRIV_PROPS;
2506 	/*
2507 	 * Finally, we're ready to register ourselves with the mac
2508 	 * interface; if this succeeds, we're all ready to start()
2509 	 */
2510 	err = mac_register(macp, &ngep->mh);
2511 	mac_free(macp);
2512 	if (err != 0)
2513 		goto attach_fail;
2514 
2515 	/*
2516 	 * Register a periodical handler.
2517 	 * nge_chip_cyclic() is invoked in kernel context.
2518 	 */
2519 	ngep->periodic_id = ddi_periodic_add(nge_chip_cyclic, ngep,
2520 	    NGE_CYCLIC_PERIOD, DDI_IPL_0);
2521 
2522 	ngep->progress |= PROGRESS_READY;
2523 	return (DDI_SUCCESS);
2524 
2525 attach_fail:
2526 	nge_unattach(ngep);
2527 	return (DDI_FAILURE);
2528 }
2529 
2530 static int
2531 nge_suspend(nge_t *ngep)
2532 {
2533 	mutex_enter(ngep->genlock);
2534 	rw_enter(ngep->rwlock, RW_WRITER);
2535 
2536 	/* if the port hasn't been plumbed, just return */
2537 	if (ngep->nge_mac_state != NGE_MAC_STARTED) {
2538 		rw_exit(ngep->rwlock);
2539 		mutex_exit(ngep->genlock);
2540 		return (DDI_SUCCESS);
2541 	}
2542 	ngep->suspended = B_TRUE;
2543 	(void) nge_chip_stop(ngep, B_FALSE);
2544 	ngep->nge_mac_state = NGE_MAC_STOPPED;
2545 
2546 	rw_exit(ngep->rwlock);
2547 	mutex_exit(ngep->genlock);
2548 	return (DDI_SUCCESS);
2549 }
2550 
2551 /*
2552  * detach(9E) -- Detach a device from the system
2553  */
2554 static int
2555 nge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
2556 {
2557 	int i;
2558 	nge_t *ngep;
2559 	mul_item *p, *nextp;
2560 	buff_ring_t *brp;
2561 
2562 	NGE_GTRACE(("nge_detach($%p, %d)", (void *)devinfo, cmd));
2563 
2564 	ngep = ddi_get_driver_private(devinfo);
2565 	brp = ngep->buff;
2566 
2567 	switch (cmd) {
2568 	default:
2569 		return (DDI_FAILURE);
2570 
2571 	case DDI_SUSPEND:
2572 		/*
2573 		 * Stop the NIC
2574 		 * Note: This driver doesn't currently support WOL, but
2575 		 *	should it in the future, it is important to
2576 		 *	make sure the PHY remains powered so that the
2577 		 *	wakeup packet can actually be recieved.
2578 		 */
2579 		return (nge_suspend(ngep));
2580 
2581 	case DDI_DETACH:
2582 		break;
2583 	}
2584 
2585 	/* Try to wait all the buffer post to upper layer be released */
2586 	for (i = 0; i < 1000; i++) {
2587 		if (brp->rx_hold == 0)
2588 			break;
2589 		drv_usecwait(1000);
2590 	}
2591 
2592 	/* If there is any posted buffer, reject to detach */
2593 	if (brp->rx_hold != 0)
2594 		return (DDI_FAILURE);
2595 
2596 	/*
2597 	 * Unregister from the GLD subsystem.  This can fail, in
2598 	 * particular if there are DLPI style-2 streams still open -
2599 	 * in which case we just return failure without shutting
2600 	 * down chip operations.
2601 	 */
2602 	if (mac_unregister(ngep->mh) != DDI_SUCCESS)
2603 		return (DDI_FAILURE);
2604 
2605 	/*
2606 	 * Recycle the multicast table. mac_unregister() should be called
2607 	 * before it to ensure the multicast table can be used even if
2608 	 * mac_unregister() fails.
2609 	 */
2610 	for (p = ngep->pcur_mulist; p != NULL; p = nextp) {
2611 		nextp = p->next;
2612 		kmem_free(p, sizeof (mul_item));
2613 	}
2614 	ngep->pcur_mulist = NULL;
2615 
2616 	/*
2617 	 * All activity stopped, so we can clean up & exit
2618 	 */
2619 	nge_unattach(ngep);
2620 	return (DDI_SUCCESS);
2621 }
2622 
2623 /*
2624  * quiesce(9E) entry point.
2625  *
2626  * This function is called when the system is single-threaded at high
2627  * PIL with preemption disabled. Therefore, this function must not be
2628  * blocked.
2629  *
2630  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
2631  * DDI_FAILURE indicates an error condition and should almost never happen.
2632  */
2633 static int
2634 nge_quiesce(dev_info_t *devinfo)
2635 {
2636 	nge_t *ngep;
2637 
2638 	ngep = ddi_get_driver_private(devinfo);
2639 
2640 	if (ngep == NULL)
2641 		return (DDI_FAILURE);
2642 
2643 	/*
2644 	 * Turn off debug tracing
2645 	 */
2646 	nge_debug = 0;
2647 	ngep->debug = 0;
2648 
2649 	nge_restore_mac_addr(ngep);
2650 	(void) nge_chip_stop(ngep, B_FALSE);
2651 
2652 	return (DDI_SUCCESS);
2653 }
2654 
2655 
2656 
2657 /*
2658  * ========== Module Loading Data & Entry Points ==========
2659  */
2660 
2661 DDI_DEFINE_STREAM_OPS(nge_dev_ops, nulldev, nulldev, nge_attach, nge_detach,
2662     NULL, NULL, D_MP, NULL, nge_quiesce);
2663 
2664 
2665 static struct modldrv nge_modldrv = {
2666 	&mod_driverops,		/* Type of module.  This one is a driver */
2667 	nge_ident,		/* short description */
2668 	&nge_dev_ops		/* driver specific ops */
2669 };
2670 
2671 static struct modlinkage modlinkage = {
2672 	MODREV_1, (void *)&nge_modldrv, NULL
2673 };
2674 
2675 
2676 int
2677 _info(struct modinfo *modinfop)
2678 {
2679 	return (mod_info(&modlinkage, modinfop));
2680 }
2681 
2682 int
2683 _init(void)
2684 {
2685 	int status;
2686 
2687 	mac_init_ops(&nge_dev_ops, "nge");
2688 	status = mod_install(&modlinkage);
2689 	if (status != DDI_SUCCESS)
2690 		mac_fini_ops(&nge_dev_ops);
2691 	else
2692 		mutex_init(nge_log_mutex, NULL, MUTEX_DRIVER, NULL);
2693 
2694 	return (status);
2695 }
2696 
2697 int
2698 _fini(void)
2699 {
2700 	int status;
2701 
2702 	status = mod_remove(&modlinkage);
2703 	if (status == DDI_SUCCESS) {
2704 		mac_fini_ops(&nge_dev_ops);
2705 		mutex_destroy(nge_log_mutex);
2706 	}
2707 
2708 	return (status);
2709 }
2710 
2711 /*
2712  * ============ Init MSI/Fixed/SoftInterrupt routines ==============
2713  */
2714 
2715 /*
2716  * Register interrupts and initialize each mutex and condition variables
2717  */
2718 
2719 static int
2720 nge_register_intrs_and_init_locks(nge_t *ngep)
2721 {
2722 	int		err;
2723 	int		intr_types;
2724 	uint_t		soft_prip;
2725 	nge_msi_mask	msi_mask;
2726 	nge_msi_map0_vec map0_vec;
2727 	nge_msi_map1_vec map1_vec;
2728 
2729 	/*
2730 	 * Add the softint handlers:
2731 	 *
2732 	 * Both of these handlers are used to avoid restrictions on the
2733 	 * context and/or mutexes required for some operations.  In
2734 	 * particular, the hardware interrupt handler and its subfunctions
2735 	 * can detect a number of conditions that we don't want to handle
2736 	 * in that context or with that set of mutexes held.  So, these
2737 	 * softints are triggered instead:
2738 	 *
2739 	 * the <resched> softint is triggered if if we have previously
2740 	 * had to refuse to send a packet because of resource shortage
2741 	 * (we've run out of transmit buffers), but the send completion
2742 	 * interrupt handler has now detected that more buffers have
2743 	 * become available.  Its only purpose is to call gld_sched()
2744 	 * to retry the pending transmits (we're not allowed to hold
2745 	 * driver-defined mutexes across gld_sched()).
2746 	 *
2747 	 * the <factotum> is triggered if the h/w interrupt handler
2748 	 * sees the <link state changed> or <error> bits in the status
2749 	 * block.  It's also triggered periodically to poll the link
2750 	 * state, just in case we aren't getting link status change
2751 	 * interrupts ...
2752 	 */
2753 	err = ddi_intr_add_softint(ngep->devinfo, &ngep->resched_hdl,
2754 	    DDI_INTR_SOFTPRI_MIN, nge_reschedule, (caddr_t)ngep);
2755 	if (err != DDI_SUCCESS) {
2756 		nge_problem(ngep,
2757 		    "nge_attach: add nge_reschedule softintr failed");
2758 
2759 		return (DDI_FAILURE);
2760 	}
2761 	ngep->progress |= PROGRESS_RESCHED;
2762 	err = ddi_intr_add_softint(ngep->devinfo, &ngep->factotum_hdl,
2763 	    DDI_INTR_SOFTPRI_MIN, nge_chip_factotum, (caddr_t)ngep);
2764 	if (err != DDI_SUCCESS) {
2765 		nge_problem(ngep,
2766 		    "nge_attach: add nge_chip_factotum softintr failed!");
2767 
2768 		return (DDI_FAILURE);
2769 	}
2770 	if (ddi_intr_get_softint_pri(ngep->factotum_hdl, &soft_prip)
2771 	    != DDI_SUCCESS) {
2772 		nge_problem(ngep, "nge_attach: get softintr priority failed\n");
2773 
2774 		return (DDI_FAILURE);
2775 	}
2776 	ngep->soft_pri = soft_prip;
2777 
2778 	ngep->progress |= PROGRESS_FACTOTUM;
2779 	/* Get supported interrupt types */
2780 	if (ddi_intr_get_supported_types(ngep->devinfo, &intr_types)
2781 	    != DDI_SUCCESS) {
2782 		nge_error(ngep, "ddi_intr_get_supported_types failed\n");
2783 
2784 		return (DDI_FAILURE);
2785 	}
2786 
2787 	NGE_DEBUG(("ddi_intr_get_supported_types() returned: %x",
2788 	    intr_types));
2789 
2790 	if ((intr_types & DDI_INTR_TYPE_MSI) && nge_enable_msi) {
2791 
2792 		/* MSI Configurations for mcp55 chipset */
2793 		if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
2794 		    ngep->chipinfo.device == DEVICE_ID_MCP55_372) {
2795 
2796 
2797 			/* Enable the 8 vectors */
2798 			msi_mask.msi_mask_val =
2799 			    nge_reg_get32(ngep, NGE_MSI_MASK);
2800 			msi_mask.msi_msk_bits.vec0 = NGE_SET;
2801 			msi_mask.msi_msk_bits.vec1 = NGE_SET;
2802 			msi_mask.msi_msk_bits.vec2 = NGE_SET;
2803 			msi_mask.msi_msk_bits.vec3 = NGE_SET;
2804 			msi_mask.msi_msk_bits.vec4 = NGE_SET;
2805 			msi_mask.msi_msk_bits.vec5 = NGE_SET;
2806 			msi_mask.msi_msk_bits.vec6 = NGE_SET;
2807 			msi_mask.msi_msk_bits.vec7 = NGE_SET;
2808 			nge_reg_put32(ngep, NGE_MSI_MASK,
2809 			    msi_mask.msi_mask_val);
2810 
2811 			/*
2812 			 * Remapping the MSI MAP0 and MAP1. MCP55
2813 			 * is default mapping all the interrupt to 0 vector.
2814 			 * Software needs to remapping this.
2815 			 * This mapping is same as CK804.
2816 			 */
2817 			map0_vec.msi_map0_val =
2818 			    nge_reg_get32(ngep, NGE_MSI_MAP0);
2819 			map1_vec.msi_map1_val =
2820 			    nge_reg_get32(ngep, NGE_MSI_MAP1);
2821 			map0_vec.vecs_bits.reint_vec = 0;
2822 			map0_vec.vecs_bits.rcint_vec = 0;
2823 			map0_vec.vecs_bits.miss_vec = 3;
2824 			map0_vec.vecs_bits.teint_vec = 5;
2825 			map0_vec.vecs_bits.tcint_vec = 5;
2826 			map0_vec.vecs_bits.stint_vec = 2;
2827 			map0_vec.vecs_bits.mint_vec = 6;
2828 			map0_vec.vecs_bits.rfint_vec = 0;
2829 			map1_vec.vecs_bits.tfint_vec = 5;
2830 			map1_vec.vecs_bits.feint_vec = 6;
2831 			map1_vec.vecs_bits.resv8_11 = 3;
2832 			map1_vec.vecs_bits.resv12_15 = 1;
2833 			map1_vec.vecs_bits.resv16_19 = 0;
2834 			map1_vec.vecs_bits.resv20_23 = 7;
2835 			map1_vec.vecs_bits.resv24_31 = 0xff;
2836 			nge_reg_put32(ngep, NGE_MSI_MAP0,
2837 			    map0_vec.msi_map0_val);
2838 			nge_reg_put32(ngep, NGE_MSI_MAP1,
2839 			    map1_vec.msi_map1_val);
2840 		}
2841 		if (nge_add_intrs(ngep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) {
2842 			NGE_DEBUG(("MSI registration failed, "
2843 			    "trying FIXED interrupt type\n"));
2844 		} else {
2845 			nge_log(ngep, "Using MSI interrupt type\n");
2846 
2847 			ngep->intr_type = DDI_INTR_TYPE_MSI;
2848 			ngep->progress |= PROGRESS_SWINT;
2849 		}
2850 	}
2851 
2852 	if (!(ngep->progress & PROGRESS_SWINT) &&
2853 	    (intr_types & DDI_INTR_TYPE_FIXED)) {
2854 		if (nge_add_intrs(ngep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) {
2855 			nge_error(ngep, "FIXED interrupt "
2856 			    "registration failed\n");
2857 
2858 			return (DDI_FAILURE);
2859 		}
2860 
2861 		nge_log(ngep, "Using FIXED interrupt type\n");
2862 
2863 		ngep->intr_type = DDI_INTR_TYPE_FIXED;
2864 		ngep->progress |= PROGRESS_SWINT;
2865 	}
2866 
2867 
2868 	if (!(ngep->progress & PROGRESS_SWINT)) {
2869 		nge_error(ngep, "No interrupts registered\n");
2870 
2871 		return (DDI_FAILURE);
2872 	}
2873 	mutex_init(ngep->genlock, NULL, MUTEX_DRIVER,
2874 	    DDI_INTR_PRI(ngep->intr_pri));
2875 	mutex_init(ngep->softlock, NULL, MUTEX_DRIVER,
2876 	    DDI_INTR_PRI(ngep->soft_pri));
2877 	rw_init(ngep->rwlock, NULL, RW_DRIVER,
2878 	    DDI_INTR_PRI(ngep->intr_pri));
2879 
2880 	return (DDI_SUCCESS);
2881 }
2882 
2883 /*
2884  * nge_add_intrs:
2885  *
2886  * Register FIXED or MSI interrupts.
2887  */
2888 static int
2889 nge_add_intrs(nge_t *ngep, int	intr_type)
2890 {
2891 	dev_info_t	*dip = ngep->devinfo;
2892 	int		avail, actual, intr_size, count = 0;
2893 	int		i, flag, ret;
2894 
2895 	NGE_DEBUG(("nge_add_intrs: interrupt type 0x%x\n", intr_type));
2896 
2897 	/* Get number of interrupts */
2898 	ret = ddi_intr_get_nintrs(dip, intr_type, &count);
2899 	if ((ret != DDI_SUCCESS) || (count == 0)) {
2900 		nge_error(ngep, "ddi_intr_get_nintrs() failure, ret: %d, "
2901 		    "count: %d", ret, count);
2902 
2903 		return (DDI_FAILURE);
2904 	}
2905 
2906 	/* Get number of available interrupts */
2907 	ret = ddi_intr_get_navail(dip, intr_type, &avail);
2908 	if ((ret != DDI_SUCCESS) || (avail == 0)) {
2909 		nge_error(ngep, "ddi_intr_get_navail() failure, "
2910 		    "ret: %d, avail: %d\n", ret, avail);
2911 
2912 		return (DDI_FAILURE);
2913 	}
2914 
2915 	if (avail < count) {
2916 		NGE_DEBUG(("nitrs() returned %d, navail returned %d\n",
2917 		    count, avail));
2918 	}
2919 	flag = DDI_INTR_ALLOC_NORMAL;
2920 
2921 	/* Allocate an array of interrupt handles */
2922 	intr_size = count * sizeof (ddi_intr_handle_t);
2923 	ngep->htable = kmem_alloc(intr_size, KM_SLEEP);
2924 
2925 	/* Call ddi_intr_alloc() */
2926 	ret = ddi_intr_alloc(dip, ngep->htable, intr_type, 0,
2927 	    count, &actual, flag);
2928 
2929 	if ((ret != DDI_SUCCESS) || (actual == 0)) {
2930 		nge_error(ngep, "ddi_intr_alloc() failed %d\n", ret);
2931 
2932 		kmem_free(ngep->htable, intr_size);
2933 		return (DDI_FAILURE);
2934 	}
2935 
2936 	if (actual < count) {
2937 		NGE_DEBUG(("Requested: %d, Received: %d\n",
2938 		    count, actual));
2939 	}
2940 
2941 	ngep->intr_actual_cnt = actual;
2942 	ngep->intr_req_cnt = count;
2943 
2944 	/*
2945 	 * Get priority for first msi, assume remaining are all the same
2946 	 */
2947 	if ((ret = ddi_intr_get_pri(ngep->htable[0], &ngep->intr_pri)) !=
2948 	    DDI_SUCCESS) {
2949 		nge_error(ngep, "ddi_intr_get_pri() failed %d\n", ret);
2950 
2951 		/* Free already allocated intr */
2952 		for (i = 0; i < actual; i++) {
2953 			(void) ddi_intr_free(ngep->htable[i]);
2954 		}
2955 
2956 		kmem_free(ngep->htable, intr_size);
2957 
2958 		return (DDI_FAILURE);
2959 	}
2960 	/* Test for high level mutex */
2961 	if (ngep->intr_pri >= ddi_intr_get_hilevel_pri()) {
2962 		nge_error(ngep, "nge_add_intrs:"
2963 		    "Hi level interrupt not supported");
2964 
2965 		for (i = 0; i < actual; i++)
2966 			(void) ddi_intr_free(ngep->htable[i]);
2967 
2968 		kmem_free(ngep->htable, intr_size);
2969 
2970 		return (DDI_FAILURE);
2971 	}
2972 
2973 
2974 	/* Call ddi_intr_add_handler() */
2975 	for (i = 0; i < actual; i++) {
2976 		if ((ret = ddi_intr_add_handler(ngep->htable[i], nge_chip_intr,
2977 		    (caddr_t)ngep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
2978 			nge_error(ngep, "ddi_intr_add_handler() "
2979 			    "failed %d\n", ret);
2980 
2981 			/* Free already allocated intr */
2982 			for (i = 0; i < actual; i++) {
2983 				(void) ddi_intr_free(ngep->htable[i]);
2984 			}
2985 
2986 			kmem_free(ngep->htable, intr_size);
2987 
2988 			return (DDI_FAILURE);
2989 		}
2990 	}
2991 
2992 	if ((ret = ddi_intr_get_cap(ngep->htable[0], &ngep->intr_cap))
2993 	    != DDI_SUCCESS) {
2994 		nge_error(ngep, "ddi_intr_get_cap() failed %d\n", ret);
2995 
2996 		for (i = 0; i < actual; i++) {
2997 			(void) ddi_intr_remove_handler(ngep->htable[i]);
2998 			(void) ddi_intr_free(ngep->htable[i]);
2999 		}
3000 
3001 		kmem_free(ngep->htable, intr_size);
3002 
3003 		return (DDI_FAILURE);
3004 	}
3005 
3006 	return (DDI_SUCCESS);
3007 }
3008 
3009 /*
3010  * nge_rem_intrs:
3011  *
3012  * Unregister FIXED or MSI interrupts
3013  */
3014 static void
3015 nge_rem_intrs(nge_t *ngep)
3016 {
3017 	int	i;
3018 
3019 	NGE_DEBUG(("nge_rem_intrs\n"));
3020 
3021 	/* Disable all interrupts */
3022 	if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) {
3023 		/* Call ddi_intr_block_disable() */
3024 		(void) ddi_intr_block_disable(ngep->htable,
3025 		    ngep->intr_actual_cnt);
3026 	} else {
3027 		for (i = 0; i < ngep->intr_actual_cnt; i++) {
3028 			(void) ddi_intr_disable(ngep->htable[i]);
3029 		}
3030 	}
3031 
3032 	/* Call ddi_intr_remove_handler() */
3033 	for (i = 0; i < ngep->intr_actual_cnt; i++) {
3034 		(void) ddi_intr_remove_handler(ngep->htable[i]);
3035 		(void) ddi_intr_free(ngep->htable[i]);
3036 	}
3037 
3038 	kmem_free(ngep->htable,
3039 	    ngep->intr_req_cnt * sizeof (ddi_intr_handle_t));
3040 }
3041