1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "nge.h" 28 static uint32_t nge_watchdog_count = 1 << 29; 29 extern boolean_t nge_enable_msi; 30 static void nge_sync_mac_modes(nge_t *); 31 32 #undef NGE_DBG 33 #define NGE_DBG NGE_DBG_CHIP 34 35 /* 36 * Operating register get/set access routines 37 */ 38 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 39 #pragma inline(nge_reg_get8) 40 41 uint8_t 42 nge_reg_get8(nge_t *ngep, nge_regno_t regno) 43 { 44 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno)); 45 46 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno))); 47 } 48 49 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 50 #pragma inline(nge_reg_put8) 51 52 void 53 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data) 54 { 55 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)", 56 (void *)ngep, regno, data)); 57 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data); 58 59 } 60 61 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 62 #pragma inline(nge_reg_get16) 63 64 uint16_t 65 nge_reg_get16(nge_t *ngep, nge_regno_t regno) 66 { 67 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno)); 68 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno))); 69 } 70 71 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 72 #pragma inline(nge_reg_put16) 73 74 void 75 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data) 76 { 77 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)", 78 (void *)ngep, regno, data)); 79 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data); 80 81 } 82 83 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 84 #pragma inline(nge_reg_get32) 85 86 uint32_t 87 nge_reg_get32(nge_t *ngep, nge_regno_t regno) 88 { 89 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno)); 90 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno))); 91 } 92 93 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 94 #pragma inline(nge_reg_put32) 95 96 void 97 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data) 98 { 99 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)", 100 (void *)ngep, regno, data)); 101 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data); 102 103 } 104 105 106 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 107 #pragma no_inline(nge_chip_peek_cfg) 108 109 static int 110 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 111 { 112 int err; 113 uint64_t regval; 114 uint64_t regno; 115 116 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)", 117 (void *)ngep, (void *)ppd)); 118 119 err = DDI_SUCCESS; 120 regno = ppd->pp_acc_offset; 121 122 switch (ppd->pp_acc_size) { 123 case 1: 124 regval = pci_config_get8(ngep->cfg_handle, regno); 125 break; 126 127 case 2: 128 regval = pci_config_get16(ngep->cfg_handle, regno); 129 break; 130 131 case 4: 132 regval = pci_config_get32(ngep->cfg_handle, regno); 133 break; 134 135 case 8: 136 regval = pci_config_get64(ngep->cfg_handle, regno); 137 break; 138 } 139 ppd->pp_acc_data = regval; 140 return (err); 141 } 142 143 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 144 145 static int 146 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 147 { 148 int err; 149 uint64_t regval; 150 uint64_t regno; 151 152 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)", 153 (void *)ngep, (void *)ppd)); 154 155 err = DDI_SUCCESS; 156 regno = ppd->pp_acc_offset; 157 regval = ppd->pp_acc_data; 158 159 switch (ppd->pp_acc_size) { 160 case 1: 161 pci_config_put8(ngep->cfg_handle, regno, regval); 162 break; 163 164 case 2: 165 pci_config_put16(ngep->cfg_handle, regno, regval); 166 break; 167 168 case 4: 169 pci_config_put32(ngep->cfg_handle, regno, regval); 170 break; 171 172 case 8: 173 pci_config_put64(ngep->cfg_handle, regno, regval); 174 break; 175 } 176 177 return (err); 178 179 } 180 181 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd); 182 183 static int 184 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd) 185 { 186 int err; 187 uint64_t regval; 188 void *regaddr; 189 190 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)", 191 (void *)ngep, (void *)ppd)); 192 193 err = DDI_SUCCESS; 194 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 195 196 switch (ppd->pp_acc_size) { 197 case 1: 198 regval = ddi_get8(ngep->io_handle, regaddr); 199 break; 200 201 case 2: 202 regval = ddi_get16(ngep->io_handle, regaddr); 203 break; 204 205 case 4: 206 regval = ddi_get32(ngep->io_handle, regaddr); 207 break; 208 209 case 8: 210 regval = ddi_get64(ngep->io_handle, regaddr); 211 break; 212 213 default: 214 regval = 0x0ull; 215 break; 216 } 217 ppd->pp_acc_data = regval; 218 return (err); 219 } 220 221 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd); 222 223 static int 224 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd) 225 { 226 int err; 227 uint64_t regval; 228 void *regaddr; 229 230 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)", 231 (void *)ngep, (void *)ppd)); 232 233 err = DDI_SUCCESS; 234 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 235 regval = ppd->pp_acc_data; 236 237 switch (ppd->pp_acc_size) { 238 case 1: 239 ddi_put8(ngep->io_handle, regaddr, regval); 240 break; 241 242 case 2: 243 ddi_put16(ngep->io_handle, regaddr, regval); 244 break; 245 246 case 4: 247 ddi_put32(ngep->io_handle, regaddr, regval); 248 break; 249 250 case 8: 251 ddi_put64(ngep->io_handle, regaddr, regval); 252 break; 253 } 254 return (err); 255 } 256 257 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd); 258 #pragma no_inline(nge_chip_peek_mii) 259 260 static int 261 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd) 262 { 263 int err; 264 265 err = DDI_SUCCESS; 266 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2); 267 return (err); 268 } 269 270 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd); 271 #pragma no_inline(nge_chip_poke_mii) 272 273 static int 274 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd) 275 { 276 int err; 277 err = DDI_SUCCESS; 278 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 279 return (err); 280 } 281 282 /* 283 * Basic SEEPROM get/set access routine 284 * 285 * This uses the chip's SEEPROM auto-access method, controlled by the 286 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU 287 * doesn't have to fiddle with the individual bits. 288 * 289 * The caller should hold <genlock> and *also* have already acquired 290 * the right to access the SEEPROM. 291 * 292 * Return value: 293 * 0 on success, 294 * ENODATA on access timeout (maybe retryable: device may just be busy) 295 * EPROTO on other h/w or s/w errors. 296 * 297 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 298 * from a (successful) SEEPROM_ACCESS_READ. 299 */ 300 301 static int 302 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp) 303 { 304 uint32_t tries; 305 nge_ep_cmd cmd_reg; 306 nge_ep_data data_reg; 307 308 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)", 309 (void *)ngep, cmd, addr, (void *)dp)); 310 311 ASSERT(mutex_owned(ngep->genlock)); 312 313 /* 314 * Check there's no command in progress. 315 * 316 * Note: this *shouldn't* ever find that there is a command 317 * in progress, because we already hold the <genlock> mutex. 318 * Also, to ensure we don't have a conflict with the chip's 319 * internal firmware or a process accessing the same (shared) 320 * So this is just a final consistency check: we shouldn't 321 * see EITHER the START bit (command started but not complete) 322 * OR the COMPLETE bit (command completed but not cleared). 323 */ 324 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 325 for (tries = 0; tries < 30; tries++) { 326 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 327 break; 328 drv_usecwait(10); 329 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 330 } 331 332 /* 333 * This should not happen. If so, we have to restart eeprom 334 * state machine 335 */ 336 if (tries == 30) { 337 cmd_reg.cmd_bits.sts = SEEPROM_READY; 338 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 339 drv_usecwait(10); 340 /* 341 * Polling the status bit to make assure the eeprom is ready 342 */ 343 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 344 for (tries = 0; tries < 30; tries++) { 345 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 346 break; 347 drv_usecwait(10); 348 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 349 } 350 } 351 352 /* 353 * Assemble the command ... 354 */ 355 cmd_reg.cmd_bits.addr = (uint32_t)addr; 356 cmd_reg.cmd_bits.cmd = cmd; 357 cmd_reg.cmd_bits.sts = 0; 358 359 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 360 361 /* 362 * Polling whether the access is successful. 363 * 364 */ 365 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 366 for (tries = 0; tries < 30; tries++) { 367 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 368 break; 369 drv_usecwait(10); 370 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 371 } 372 373 if (tries == 30) { 374 nge_report(ngep, NGE_HW_ROM); 375 return (DDI_FAILURE); 376 } 377 switch (cmd) { 378 default: 379 case SEEPROM_CMD_WRITE_ENABLE: 380 case SEEPROM_CMD_ERASE: 381 case SEEPROM_CMD_ERALSE_ALL: 382 case SEEPROM_CMD_WRITE_DIS: 383 break; 384 385 case SEEPROM_CMD_READ: 386 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 387 *dp = data_reg.data_bits.data; 388 break; 389 390 case SEEPROM_CMD_WRITE: 391 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 392 data_reg.data_bits.data = *dp; 393 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val); 394 break; 395 } 396 397 return (DDI_SUCCESS); 398 } 399 400 401 static int 402 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 403 { 404 uint16_t data; 405 int err; 406 407 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ, 408 ppd->pp_acc_offset, &data); 409 ppd->pp_acc_data = data; 410 return (err); 411 } 412 413 static int 414 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 415 { 416 uint16_t data; 417 int err; 418 419 data = ppd->pp_acc_data; 420 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE, 421 ppd->pp_acc_offset, &data); 422 return (err); 423 } 424 425 void 426 nge_init_dev_spec_param(nge_t *ngep) 427 { 428 nge_dev_spec_param_t *dev_param_p; 429 chip_info_t *infop; 430 431 dev_param_p = &ngep->dev_spec_param; 432 infop = (chip_info_t *)&ngep->chipinfo; 433 434 switch (infop->device) { 435 case DEVICE_ID_NF3_E6: 436 case DEVICE_ID_NF3_DF: 437 case DEVICE_ID_MCP04_37: 438 case DEVICE_ID_MCP04_38: 439 dev_param_p->msi = B_FALSE; 440 dev_param_p->msi_x = B_FALSE; 441 dev_param_p->vlan = B_FALSE; 442 dev_param_p->advanced_pm = B_FALSE; 443 dev_param_p->mac_addr_order = B_FALSE; 444 dev_param_p->tx_pause_frame = B_FALSE; 445 dev_param_p->rx_pause_frame = B_FALSE; 446 dev_param_p->jumbo = B_FALSE; 447 dev_param_p->tx_rx_64byte = B_FALSE; 448 dev_param_p->rx_hw_checksum = B_FALSE; 449 dev_param_p->tx_hw_checksum = 0; 450 dev_param_p->desc_type = DESC_OFFLOAD; 451 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 452 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 453 dev_param_p->nge_split = NGE_SPLIT_32; 454 break; 455 456 case DEVICE_ID_CK804_56: 457 case DEVICE_ID_CK804_57: 458 dev_param_p->msi = B_TRUE; 459 dev_param_p->msi_x = B_TRUE; 460 dev_param_p->vlan = B_FALSE; 461 dev_param_p->advanced_pm = B_FALSE; 462 dev_param_p->mac_addr_order = B_FALSE; 463 dev_param_p->tx_pause_frame = B_FALSE; 464 dev_param_p->rx_pause_frame = B_TRUE; 465 dev_param_p->jumbo = B_TRUE; 466 dev_param_p->tx_rx_64byte = B_FALSE; 467 dev_param_p->rx_hw_checksum = B_TRUE; 468 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 469 dev_param_p->desc_type = DESC_HOT; 470 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 471 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 472 dev_param_p->nge_split = NGE_SPLIT_96; 473 break; 474 475 case DEVICE_ID_MCP51_268: 476 case DEVICE_ID_MCP51_269: 477 dev_param_p->msi = B_FALSE; 478 dev_param_p->msi_x = B_FALSE; 479 dev_param_p->vlan = B_FALSE; 480 dev_param_p->advanced_pm = B_TRUE; 481 dev_param_p->mac_addr_order = B_FALSE; 482 dev_param_p->tx_pause_frame = B_FALSE; 483 dev_param_p->rx_pause_frame = B_FALSE; 484 dev_param_p->jumbo = B_FALSE; 485 dev_param_p->tx_rx_64byte = B_TRUE; 486 dev_param_p->rx_hw_checksum = B_FALSE; 487 dev_param_p->tx_hw_checksum = 0; 488 dev_param_p->desc_type = DESC_OFFLOAD; 489 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 490 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 491 dev_param_p->nge_split = NGE_SPLIT_32; 492 break; 493 494 case DEVICE_ID_MCP55_372: 495 case DEVICE_ID_MCP55_373: 496 dev_param_p->msi = B_TRUE; 497 dev_param_p->msi_x = B_TRUE; 498 dev_param_p->vlan = B_TRUE; 499 dev_param_p->advanced_pm = B_TRUE; 500 dev_param_p->mac_addr_order = B_FALSE; 501 dev_param_p->tx_pause_frame = B_TRUE; 502 dev_param_p->rx_pause_frame = B_TRUE; 503 dev_param_p->jumbo = B_TRUE; 504 dev_param_p->tx_rx_64byte = B_TRUE; 505 dev_param_p->rx_hw_checksum = B_TRUE; 506 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 507 dev_param_p->desc_type = DESC_HOT; 508 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 509 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 510 dev_param_p->nge_split = NGE_SPLIT_96; 511 break; 512 513 case DEVICE_ID_MCP61_3EE: 514 case DEVICE_ID_MCP61_3EF: 515 dev_param_p->msi = B_FALSE; 516 dev_param_p->msi_x = B_FALSE; 517 dev_param_p->vlan = B_FALSE; 518 dev_param_p->advanced_pm = B_TRUE; 519 dev_param_p->mac_addr_order = B_TRUE; 520 dev_param_p->tx_pause_frame = B_FALSE; 521 dev_param_p->rx_pause_frame = B_FALSE; 522 dev_param_p->jumbo = B_FALSE; 523 dev_param_p->tx_rx_64byte = B_TRUE; 524 dev_param_p->rx_hw_checksum = B_FALSE; 525 dev_param_p->tx_hw_checksum = 0; 526 dev_param_p->desc_type = DESC_OFFLOAD; 527 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 528 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 529 dev_param_p->nge_split = NGE_SPLIT_32; 530 break; 531 532 case DEVICE_ID_MCP77_760: 533 dev_param_p->msi = B_FALSE; 534 dev_param_p->msi_x = B_FALSE; 535 dev_param_p->vlan = B_FALSE; 536 dev_param_p->advanced_pm = B_TRUE; 537 dev_param_p->mac_addr_order = B_TRUE; 538 dev_param_p->tx_pause_frame = B_FALSE; 539 dev_param_p->rx_pause_frame = B_FALSE; 540 dev_param_p->jumbo = B_FALSE; 541 dev_param_p->tx_rx_64byte = B_TRUE; 542 dev_param_p->rx_hw_checksum = B_FALSE; 543 dev_param_p->tx_hw_checksum = 0; 544 dev_param_p->desc_type = DESC_HOT; 545 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 546 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 547 dev_param_p->nge_split = NGE_SPLIT_32; 548 break; 549 550 default: 551 dev_param_p->msi = B_FALSE; 552 dev_param_p->msi_x = B_FALSE; 553 dev_param_p->vlan = B_FALSE; 554 dev_param_p->advanced_pm = B_FALSE; 555 dev_param_p->mac_addr_order = B_FALSE; 556 dev_param_p->tx_pause_frame = B_FALSE; 557 dev_param_p->rx_pause_frame = B_FALSE; 558 dev_param_p->jumbo = B_FALSE; 559 dev_param_p->tx_rx_64byte = B_FALSE; 560 dev_param_p->rx_hw_checksum = B_FALSE; 561 dev_param_p->tx_hw_checksum = 0; 562 dev_param_p->desc_type = DESC_OFFLOAD; 563 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 564 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 565 dev_param_p->nge_split = NGE_SPLIT_32; 566 return; 567 } 568 } 569 /* 570 * Perform first-stage chip (re-)initialisation, using only config-space 571 * accesses: 572 * 573 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 574 * returning the data in the structure pointed to by <infop>. 575 */ 576 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 577 #pragma no_inline(nge_chip_cfg_init) 578 579 void 580 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset) 581 { 582 uint16_t command; 583 ddi_acc_handle_t handle; 584 nge_interbus_conf interbus_conf; 585 nge_msi_mask_conf msi_mask_conf; 586 nge_msi_map_cap_conf cap_conf; 587 588 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)", 589 (void *)ngep, (void *)infop, reset)); 590 591 /* 592 * save PCI cache line size and subsystem vendor ID 593 * 594 * Read all the config-space registers that characterise the 595 * chip, specifically vendor/device/revision/subsystem vendor 596 * and subsystem device id. We expect (but don't check) that 597 */ 598 handle = ngep->cfg_handle; 599 /* reading the vendor information once */ 600 if (reset == B_FALSE) { 601 infop->command = pci_config_get16(handle, 602 PCI_CONF_COMM); 603 infop->vendor = pci_config_get16(handle, 604 PCI_CONF_VENID); 605 infop->device = pci_config_get16(handle, 606 PCI_CONF_DEVID); 607 infop->subven = pci_config_get16(handle, 608 PCI_CONF_SUBVENID); 609 infop->subdev = pci_config_get16(handle, 610 PCI_CONF_SUBSYSID); 611 infop->class_code = pci_config_get8(handle, 612 PCI_CONF_BASCLASS); 613 infop->revision = pci_config_get8(handle, 614 PCI_CONF_REVID); 615 infop->clsize = pci_config_get8(handle, 616 PCI_CONF_CACHE_LINESZ); 617 infop->latency = pci_config_get8(handle, 618 PCI_CONF_LATENCY_TIMER); 619 } 620 if (nge_enable_msi) { 621 /* Disable the hidden for MSI support */ 622 interbus_conf.conf_val = pci_config_get32(handle, 623 PCI_CONF_HT_INTERNAL); 624 if ((infop->device == DEVICE_ID_MCP55_373) || 625 (infop->device == DEVICE_ID_MCP55_372)) 626 interbus_conf.conf_bits.msix_off = NGE_SET; 627 interbus_conf.conf_bits.msi_off = NGE_CLEAR; 628 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 629 interbus_conf.conf_val); 630 631 if ((infop->device == DEVICE_ID_MCP55_373) || 632 (infop->device == DEVICE_ID_MCP55_372)) { 633 634 /* Disable the vector off for mcp55 */ 635 msi_mask_conf.msi_mask_conf_val = 636 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK); 637 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR; 638 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR; 639 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR; 640 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR; 641 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR; 642 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR; 643 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR; 644 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR; 645 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, 646 msi_mask_conf.msi_mask_conf_val); 647 648 /* Enable the MSI mapping */ 649 cap_conf.msi_map_cap_conf_val = 650 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP); 651 cap_conf.map_cap_conf_bits.map_en = NGE_SET; 652 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, 653 cap_conf.msi_map_cap_conf_val); 654 } 655 } else { 656 interbus_conf.conf_val = pci_config_get32(handle, 657 PCI_CONF_HT_INTERNAL); 658 interbus_conf.conf_bits.msi_off = NGE_SET; 659 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 660 interbus_conf.conf_val); 661 } 662 command = infop->command | PCI_COMM_MAE; 663 command &= ~PCI_COMM_MEMWR_INVAL; 664 command |= PCI_COMM_ME; 665 pci_config_put16(handle, PCI_CONF_COMM, command); 666 pci_config_put16(handle, PCI_CONF_STAT, ~0); 667 668 } 669 670 int 671 nge_chip_stop(nge_t *ngep, boolean_t fault) 672 { 673 int err; 674 uint32_t reg_val; 675 uint32_t tries; 676 nge_mintr_src mintr_src; 677 nge_mii_cs mii_cs; 678 nge_rx_poll rx_poll; 679 nge_tx_poll tx_poll; 680 nge_rx_en rx_en; 681 nge_tx_en tx_en; 682 nge_tx_sta tx_sta; 683 nge_rx_sta rx_sta; 684 nge_mode_cntl mode; 685 nge_pmu_cntl2 pmu_cntl2; 686 687 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault)); 688 689 err = DDI_SUCCESS; 690 691 /* Clear any pending PHY interrupt */ 692 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC); 693 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val); 694 695 /* Mask all interrupts */ 696 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK); 697 reg_val &= ~NGE_INTR_ALL_EN; 698 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val); 699 700 /* Disable auto-polling of phy */ 701 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 702 mii_cs.cs_bits.ap_en = NGE_CLEAR; 703 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 704 705 /* Reset buffer management & DMA */ 706 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 707 mode.mode_bits.dma_dis = NGE_SET; 708 mode.mode_bits.desc_type = ngep->desc_mode; 709 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 710 711 for (tries = 0; tries < 10000; tries++) { 712 drv_usecwait(10); 713 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 714 if (mode.mode_bits.dma_status == NGE_SET) 715 break; 716 } 717 if (tries == 10000) { 718 ngep->nge_chip_state = NGE_CHIP_ERROR; 719 return (DDI_FAILURE); 720 } 721 722 /* Disable rx's machine */ 723 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 724 rx_en.bits.rx_en = NGE_CLEAR; 725 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 726 727 /* Disable tx's machine */ 728 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 729 tx_en.bits.tx_en = NGE_CLEAR; 730 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 731 732 /* 733 * Clean the status of tx's state machine 734 * and Make assure the tx's channel is idle 735 */ 736 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 737 for (tries = 0; tries < 1000; tries++) { 738 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR) 739 break; 740 drv_usecwait(10); 741 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 742 } 743 if (tries == 1000) { 744 ngep->nge_chip_state = NGE_CHIP_ERROR; 745 return (DDI_FAILURE); 746 } 747 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val); 748 749 /* 750 * Clean the status of rx's state machine 751 * and Make assure the tx's channel is idle 752 */ 753 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 754 for (tries = 0; tries < 1000; tries++) { 755 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR) 756 break; 757 drv_usecwait(10); 758 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 759 } 760 if (tries == 1000) { 761 ngep->nge_chip_state = NGE_CHIP_ERROR; 762 return (DDI_FAILURE); 763 } 764 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val); 765 766 /* Disable auto-poll of rx's state machine */ 767 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 768 rx_poll.poll_bits.rpen = NGE_CLEAR; 769 rx_poll.poll_bits.rpi = NGE_CLEAR; 770 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 771 772 /* Disable auto-polling of tx's state machine */ 773 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL); 774 tx_poll.poll_bits.tpen = NGE_CLEAR; 775 tx_poll.poll_bits.tpi = NGE_CLEAR; 776 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val); 777 778 /* Restore buffer management */ 779 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 780 mode.mode_bits.bm_reset = NGE_SET; 781 mode.mode_bits.tx_rcom_en = NGE_SET; 782 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 783 784 if (ngep->dev_spec_param.advanced_pm) { 785 786 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0); 787 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0); 788 789 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 790 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR; 791 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR; 792 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 793 } 794 if (fault) 795 ngep->nge_chip_state = NGE_CHIP_FAULT; 796 else 797 ngep->nge_chip_state = NGE_CHIP_STOPPED; 798 799 return (err); 800 } 801 802 static void 803 nge_rx_setup(nge_t *ngep) 804 { 805 uint64_t desc_addr; 806 nge_rxtx_dlen dlen; 807 nge_rx_poll rx_poll; 808 809 /* 810 * Filling the address and length of rx's descriptors 811 */ 812 desc_addr = ngep->recv->desc.cookie.dmac_laddress; 813 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr); 814 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32); 815 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 816 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1; 817 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 818 819 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 820 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G; 821 rx_poll.poll_bits.rpen = NGE_SET; 822 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 823 } 824 825 static void 826 nge_tx_setup(nge_t *ngep) 827 { 828 uint64_t desc_addr; 829 nge_rxtx_dlen dlen; 830 831 /* 832 * Filling the address and length of tx's descriptors 833 */ 834 desc_addr = ngep->send->desc.cookie.dmac_laddress; 835 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr); 836 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32); 837 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 838 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1; 839 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 840 } 841 842 static int 843 nge_buff_setup(nge_t *ngep) 844 { 845 nge_mode_cntl mode_cntl; 846 nge_dev_spec_param_t *dev_param_p; 847 848 dev_param_p = &ngep->dev_spec_param; 849 850 /* 851 * Configure Rx&Tx's buffer 852 */ 853 nge_rx_setup(ngep); 854 nge_tx_setup(ngep); 855 856 /* 857 * Configure buffer attribute 858 */ 859 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 860 861 /* 862 * Enable Dma access request 863 */ 864 mode_cntl.mode_bits.dma_dis = NGE_CLEAR; 865 866 /* 867 * Enbale Buffer management 868 */ 869 mode_cntl.mode_bits.bm_reset = NGE_CLEAR; 870 871 /* 872 * Support Standoffload Descriptor 873 */ 874 mode_cntl.mode_bits.desc_type = ngep->desc_mode; 875 876 /* 877 * Support receive hardware checksum 878 */ 879 if (dev_param_p->rx_hw_checksum) { 880 mode_cntl.mode_bits.rx_sum_en = NGE_SET; 881 } else 882 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR; 883 884 /* 885 * Disable Tx PRD coarse update 886 */ 887 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR; 888 889 /* 890 * Disable 64-byte access 891 */ 892 mode_cntl.mode_bits.w64_dis = NGE_SET; 893 894 /* 895 * Skip Rx Error Frame is not supported and if 896 * enable it, jumbo frame does not work any more. 897 */ 898 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR; 899 900 /* 901 * Can not support hot mode now 902 */ 903 mode_cntl.mode_bits.resv15 = NGE_CLEAR; 904 905 if (dev_param_p->vlan) { 906 /* Disable the vlan strip for devices which support vlan */ 907 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR; 908 909 /* Disable the vlan insert for devices which supprot vlan */ 910 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR; 911 } 912 913 if (dev_param_p->tx_rx_64byte) { 914 915 /* Set the maximum TX PRD fetch size to 64 bytes */ 916 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET; 917 918 /* Set the maximum RX PRD fetch size to 64 bytes */ 919 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET; 920 } 921 /* 922 * Upload Rx data as it arrives, rather than waiting for full frame 923 */ 924 mode_cntl.mode_bits.resv16 = NGE_CLEAR; 925 926 /* 927 * Normal HOT table accesses 928 */ 929 mode_cntl.mode_bits.resv17 = NGE_CLEAR; 930 931 /* 932 * Normal HOT buffer requesting 933 */ 934 mode_cntl.mode_bits.resv18 = NGE_CLEAR; 935 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 936 937 /* 938 * Signal controller to check for new Rx descriptors 939 */ 940 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 941 mode_cntl.mode_bits.rxdm = NGE_SET; 942 mode_cntl.mode_bits.tx_rcom_en = NGE_SET; 943 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 944 945 946 return (DDI_SUCCESS); 947 } 948 949 /* 950 * When chipset resets, the chipset can not restore the orignial 951 * mac address to the mac address registers. 952 * 953 * When the driver is dettached, the function will write the orignial 954 * mac address to the mac address registers. 955 */ 956 957 void 958 nge_restore_mac_addr(nge_t *ngep) 959 { 960 uint32_t mac_addr; 961 962 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr; 963 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr); 964 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32); 965 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr); 966 } 967 968 int 969 nge_chip_reset(nge_t *ngep) 970 { 971 int err; 972 uint8_t i; 973 uint32_t regno; 974 uint64_t mac = 0; 975 nge_uni_addr1 uaddr1; 976 nge_cp_cntl ee_cntl; 977 nge_soft_misc soft_misc; 978 nge_pmu_cntl0 pmu_cntl0; 979 nge_pmu_cntl2 pmu_cntl2; 980 nge_pm_cntl2 pm_cntl2; 981 const nge_ksindex_t *ksip; 982 983 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep)); 984 985 /* 986 * Clear the statistics by reading the statistics register 987 */ 988 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) { 989 regno = KS_BASE + ksip->index * sizeof (uint32_t); 990 (void) nge_reg_get32(ngep, regno); 991 } 992 993 /* 994 * Setup seeprom control 995 */ 996 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL); 997 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV; 998 ee_cntl.cntl_bits.rom_size = EEPROM_32K; 999 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT; 1000 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK; 1001 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val); 1002 1003 /* 1004 * Reading the unicast mac address table 1005 */ 1006 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) { 1007 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1008 mac = uaddr1.addr_bits.addr; 1009 mac <<= 32; 1010 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0); 1011 ngep->chipinfo.hw_mac_addr = mac; 1012 if (ngep->dev_spec_param.mac_addr_order) { 1013 for (i = 0; i < ETHERADDRL; i++) { 1014 ngep->chipinfo.vendor_addr.addr[i] = 1015 (uchar_t)mac; 1016 ngep->cur_uni_addr.addr[i] = 1017 (uchar_t)mac; 1018 mac >>= 8; 1019 } 1020 } else { 1021 for (i = ETHERADDRL; i-- != 0; ) { 1022 ngep->chipinfo.vendor_addr.addr[i] = 1023 (uchar_t)mac; 1024 ngep->cur_uni_addr.addr[i] = 1025 (uchar_t)mac; 1026 mac >>= 8; 1027 } 1028 } 1029 ngep->chipinfo.vendor_addr.set = 1; 1030 } 1031 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, 1032 ngep->chipinfo.clsize); 1033 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER, 1034 ngep->chipinfo.latency); 1035 1036 1037 if (ngep->dev_spec_param.advanced_pm) { 1038 1039 /* Program software misc register */ 1040 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1041 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET; 1042 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET; 1043 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET; 1044 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET; 1045 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET; 1046 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET; 1047 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET; 1048 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET; 1049 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1050 1051 /* wait for 32 us */ 1052 drv_usecwait(32); 1053 1054 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1055 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR; 1056 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR; 1057 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR; 1058 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR; 1059 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR; 1060 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR; 1061 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR; 1062 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR; 1063 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1064 1065 /* Program PMU registers */ 1066 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0); 1067 pmu_cntl0.cntl0_bits.core_spd10_fp = 1068 NGE_PMU_CORE_SPD10_BUSY; 1069 pmu_cntl0.cntl0_bits.core_spd10_idle = 1070 NGE_PMU_CORE_SPD10_IDLE; 1071 pmu_cntl0.cntl0_bits.core_spd100_fp = 1072 NGE_PMU_CORE_SPD100_BUSY; 1073 pmu_cntl0.cntl0_bits.core_spd100_idle = 1074 NGE_PMU_CORE_SPD100_IDLE; 1075 pmu_cntl0.cntl0_bits.core_spd1000_fp = 1076 NGE_PMU_CORE_SPD1000_BUSY; 1077 pmu_cntl0.cntl0_bits.core_spd1000_idle = 1078 NGE_PMU_CORE_SPD100_IDLE; 1079 pmu_cntl0.cntl0_bits.core_spd10_idle = 1080 NGE_PMU_CORE_SPD10_IDLE; 1081 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val); 1082 1083 /* Set the core idle limit value */ 1084 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 1085 NGE_PMU_CIDLE_LIMIT_DEF); 1086 1087 /* Set the device idle limit value */ 1088 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 1089 NGE_PMU_DIDLE_LIMIT_DEF); 1090 1091 /* Enable the core/device idle timer in PMU control 2 */ 1092 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 1093 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET; 1094 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET; 1095 pmu_cntl2.cntl2_bits.core_enable = NGE_SET; 1096 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET; 1097 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 1098 } 1099 /* 1100 * Stop the chipset and clear buffer management 1101 */ 1102 err = nge_chip_stop(ngep, B_FALSE); 1103 if (err == DDI_FAILURE) 1104 return (err); 1105 /* 1106 * Clear the power state bits for phy since interface no longer 1107 * works after rebooting from Windows on a multi-boot machine 1108 */ 1109 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 || 1110 ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1111 ngep->chipinfo.device == DEVICE_ID_MCP55_372 || 1112 ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1113 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE || 1114 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF || 1115 ngep->chipinfo.device == DEVICE_ID_MCP77_760) { 1116 1117 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2); 1118 /* bring phy out of coma mode */ 1119 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR; 1120 /* disable auto reset coma bits */ 1121 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR; 1122 /* restore power to gated clocks */ 1123 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR; 1124 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val); 1125 } 1126 1127 /* 1128 * Reset the external phy 1129 */ 1130 if (!nge_phy_reset(ngep)) 1131 return (DDI_FAILURE); 1132 ngep->nge_chip_state = NGE_CHIP_RESET; 1133 return (DDI_SUCCESS); 1134 } 1135 1136 int 1137 nge_chip_start(nge_t *ngep) 1138 { 1139 int err; 1140 nge_itc itc; 1141 nge_tx_cntl tx_cntl; 1142 nge_rx_cntrl0 rx_cntl0; 1143 nge_rx_cntl1 rx_cntl1; 1144 nge_tx_en tx_en; 1145 nge_rx_en rx_en; 1146 nge_mii_cs mii_cs; 1147 nge_swtr_cntl swtr_cntl; 1148 nge_rx_fifo_wm rx_fifo; 1149 nge_intr_mask intr_mask; 1150 nge_mintr_mask mintr_mask; 1151 nge_dev_spec_param_t *dev_param_p; 1152 1153 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep)); 1154 1155 /* 1156 * Setup buffer management 1157 */ 1158 err = nge_buff_setup(ngep); 1159 if (err == DDI_FAILURE) 1160 return (err); 1161 1162 dev_param_p = &ngep->dev_spec_param; 1163 1164 /* 1165 * Enable polling attribute 1166 */ 1167 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 1168 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr; 1169 mii_cs.cs_bits.ap_en = NGE_SET; 1170 mii_cs.cs_bits.ap_intv = MII_POLL_INTV; 1171 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 1172 1173 /* 1174 * Setup link 1175 */ 1176 (*ngep->physops->phys_update)(ngep); 1177 1178 /* 1179 * Configure the tx's parameters 1180 */ 1181 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1182 if (dev_param_p->tx_pause_frame) 1183 tx_cntl.cntl_bits.paen = NGE_SET; 1184 else 1185 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1186 tx_cntl.cntl_bits.retry_en = NGE_SET; 1187 tx_cntl.cntl_bits.pad_en = NGE_SET; 1188 tx_cntl.cntl_bits.fappend_en = NGE_SET; 1189 tx_cntl.cntl_bits.two_def_en = NGE_SET; 1190 tx_cntl.cntl_bits.max_retry = 15; 1191 tx_cntl.cntl_bits.burst_en = NGE_CLEAR; 1192 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR; 1193 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR; 1194 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR; 1195 tx_cntl.cntl_bits.def_mask = NGE_CLEAR; 1196 tx_cntl.cntl_bits.exdef_mask = NGE_SET; 1197 tx_cntl.cntl_bits.lcar_mask = NGE_SET; 1198 tx_cntl.cntl_bits.tlcol_mask = NGE_SET; 1199 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET; 1200 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR; 1201 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1202 1203 1204 /* 1205 * Configure the parameters of Rx's state machine 1206 * Enabe the parameters: 1207 * 1). Pad Strip 1208 * 2). FCS Relay 1209 * 3). Pause 1210 * 4). Address filter 1211 * 5). Runt Packet receive 1212 * 6). Broadcast 1213 * 7). Receive Deferral 1214 * 1215 * Disable the following parameters for decreasing 1216 * the number of interrupts: 1217 * 1). Runt Inerrupt. 1218 * 2). Rx's Late Collision interrupt. 1219 * 3). Rx's Max length Error Interrupt. 1220 * 4). Rx's Length Field error Interrupt. 1221 * 5). Rx's FCS error interrupt. 1222 * 6). Rx's overflow error interrupt. 1223 * 7). Rx's Frame alignment error interrupt. 1224 */ 1225 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1226 rx_cntl0.cntl_bits.padsen = NGE_CLEAR; 1227 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR; 1228 if (dev_param_p->rx_pause_frame) 1229 rx_cntl0.cntl_bits.paen = NGE_SET; 1230 else 1231 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1232 rx_cntl0.cntl_bits.lben = NGE_CLEAR; 1233 rx_cntl0.cntl_bits.afen = NGE_SET; 1234 rx_cntl0.cntl_bits.runten = NGE_CLEAR; 1235 rx_cntl0.cntl_bits.brdis = NGE_CLEAR; 1236 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR; 1237 rx_cntl0.cntl_bits.runtm = NGE_CLEAR; 1238 rx_cntl0.cntl_bits.slfb = NGE_CLEAR; 1239 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR; 1240 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR; 1241 rx_cntl0.cntl_bits.lferm = NGE_CLEAR; 1242 rx_cntl0.cntl_bits.crcm = NGE_CLEAR; 1243 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR; 1244 rx_cntl0.cntl_bits.framerm = NGE_CLEAR; 1245 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1246 1247 /* 1248 * Configure the watermark for the rx's statemachine 1249 */ 1250 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM); 1251 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm; 1252 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm; 1253 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm; 1254 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val); 1255 1256 /* 1257 * Configure the deffer time slot for rx's state machine 1258 */ 1259 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def); 1260 1261 /* 1262 * Configure the length of rx's packet 1263 */ 1264 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1); 1265 rx_cntl1.cntl_bits.length = ngep->max_sdu; 1266 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val); 1267 /* 1268 * Enable Tx's state machine 1269 */ 1270 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 1271 tx_en.bits.tx_en = NGE_SET; 1272 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 1273 1274 /* 1275 * Enable Rx's state machine 1276 */ 1277 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 1278 rx_en.bits.rx_en = NGE_SET; 1279 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 1280 1281 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC); 1282 itc.itc_bits.sw_intv = ngep->sw_intr_intv; 1283 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val); 1284 1285 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL); 1286 swtr_cntl.cntl_bits.sten = NGE_SET; 1287 swtr_cntl.cntl_bits.stren = NGE_SET; 1288 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val); 1289 1290 /* 1291 * Disable all mii read/write operation Interrupt 1292 */ 1293 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK); 1294 mintr_mask.mask_bits.mrei = NGE_CLEAR; 1295 mintr_mask.mask_bits.mcc2 = NGE_CLEAR; 1296 mintr_mask.mask_bits.mcc1 = NGE_CLEAR; 1297 mintr_mask.mask_bits.mapi = NGE_SET; 1298 mintr_mask.mask_bits.mpdi = NGE_SET; 1299 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val); 1300 1301 /* 1302 * Enable all interrupt event 1303 */ 1304 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1305 intr_mask.mask_bits.reint = NGE_SET; 1306 intr_mask.mask_bits.rcint = NGE_SET; 1307 intr_mask.mask_bits.miss = NGE_SET; 1308 intr_mask.mask_bits.teint = NGE_CLEAR; 1309 intr_mask.mask_bits.tcint = NGE_SET; 1310 intr_mask.mask_bits.stint = NGE_CLEAR; 1311 intr_mask.mask_bits.mint = NGE_CLEAR; 1312 intr_mask.mask_bits.rfint = NGE_CLEAR; 1313 intr_mask.mask_bits.tfint = NGE_CLEAR; 1314 intr_mask.mask_bits.feint = NGE_SET; 1315 intr_mask.mask_bits.resv10 = NGE_CLEAR; 1316 intr_mask.mask_bits.resv11 = NGE_CLEAR; 1317 intr_mask.mask_bits.resv12 = NGE_CLEAR; 1318 intr_mask.mask_bits.resv13 = NGE_CLEAR; 1319 intr_mask.mask_bits.phyint = NGE_CLEAR; 1320 ngep->intr_masks = intr_mask.mask_val; 1321 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1322 ngep->nge_chip_state = NGE_CHIP_RUNNING; 1323 return (DDI_SUCCESS); 1324 } 1325 1326 /* 1327 * nge_chip_sync() -- program the chip with the unicast MAC address, 1328 * the multicast hash table, the required level of promiscuity. 1329 */ 1330 void 1331 nge_chip_sync(nge_t *ngep) 1332 { 1333 uint8_t i; 1334 uint64_t macaddr; 1335 uint64_t mul_addr; 1336 uint64_t mul_mask; 1337 nge_rx_cntrl0 rx_cntl; 1338 nge_uni_addr1 uni_adr1; 1339 1340 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep)); 1341 1342 macaddr = 0x0ull; 1343 mul_addr = 0x0ull; 1344 mul_mask = 0x0ull; 1345 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1346 1347 if (ngep->promisc) { 1348 rx_cntl.cntl_bits.afen = NGE_CLEAR; 1349 rx_cntl.cntl_bits.brdis = NGE_SET; 1350 } else { 1351 rx_cntl.cntl_bits.afen = NGE_SET; 1352 rx_cntl.cntl_bits.brdis = NGE_CLEAR; 1353 } 1354 1355 /* 1356 * Transform the MAC address from host to chip format, the unicast 1357 * MAC address(es) ... 1358 */ 1359 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) { 1360 macaddr |= ngep->cur_uni_addr.addr[i-1]; 1361 macaddr <<= (i > 1) ? 8 : 0; 1362 } 1363 1364 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr); 1365 macaddr = macaddr >>32; 1366 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1367 uni_adr1.addr_bits.addr = (uint16_t)macaddr; 1368 uni_adr1.addr_bits.resv16_31 = (uint16_t)0; 1369 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val); 1370 1371 /* 1372 * Reprogram the multicast address table ... 1373 */ 1374 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) { 1375 mul_addr |= ngep->cur_mul_addr.addr[i-1]; 1376 mul_addr <<= (i > 1) ? 8 : 0; 1377 mul_mask |= ngep->cur_mul_mask.addr[i-1]; 1378 mul_mask <<= (i > 1) ? 8 : 0; 1379 } 1380 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr); 1381 mul_addr >>= 32; 1382 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr); 1383 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask); 1384 mul_mask >>= 32; 1385 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask); 1386 /* 1387 * Set or clear the PROMISCUOUS mode bit 1388 */ 1389 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val); 1390 /* 1391 * For internal PHY loopback, the link will 1392 * not be up, so it need to sync mac modes directly. 1393 */ 1394 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY) 1395 nge_sync_mac_modes(ngep); 1396 } 1397 1398 static void 1399 nge_chip_err(nge_t *ngep) 1400 { 1401 nge_reg010 reg010_ins; 1402 nge_sw_statistics_t *psw_stat; 1403 nge_intr_mask intr_mask; 1404 1405 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep)); 1406 1407 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics; 1408 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010); 1409 if (reg010_ins.reg010_bits.resv0) 1410 psw_stat->fe_err.tso_err_mss ++; 1411 1412 if (reg010_ins.reg010_bits.resv1) 1413 psw_stat->fe_err.tso_dis ++; 1414 1415 if (reg010_ins.reg010_bits.resv2) 1416 psw_stat->fe_err.tso_err_nosum ++; 1417 1418 if (reg010_ins.reg010_bits.resv3) 1419 psw_stat->fe_err.tso_err_hov ++; 1420 1421 if (reg010_ins.reg010_bits.resv4) 1422 psw_stat->fe_err.tso_err_huf ++; 1423 1424 if (reg010_ins.reg010_bits.resv5) 1425 psw_stat->fe_err.tso_err_l2 ++; 1426 1427 if (reg010_ins.reg010_bits.resv6) 1428 psw_stat->fe_err.tso_err_ip ++; 1429 1430 if (reg010_ins.reg010_bits.resv7) 1431 psw_stat->fe_err.tso_err_l4 ++; 1432 1433 if (reg010_ins.reg010_bits.resv8) 1434 psw_stat->fe_err.tso_err_tcp ++; 1435 1436 if (reg010_ins.reg010_bits.resv9) 1437 psw_stat->fe_err.hsum_err_ip ++; 1438 1439 if (reg010_ins.reg010_bits.resv10) 1440 psw_stat->fe_err.hsum_err_l4 ++; 1441 1442 if (reg010_ins.reg010_val != 0) { 1443 1444 /* 1445 * Fatal error is triggered by malformed driver commands. 1446 * Disable unless debugging. 1447 */ 1448 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1449 intr_mask.mask_bits.feint = NGE_CLEAR; 1450 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1451 ngep->intr_masks = intr_mask.mask_val; 1452 1453 } 1454 } 1455 1456 static void 1457 nge_sync_mac_modes(nge_t *ngep) 1458 { 1459 nge_tx_def tx_def; 1460 nge_tx_fifo_wm tx_fifo; 1461 nge_bkoff_cntl bk_cntl; 1462 nge_mac2phy m2p; 1463 nge_rx_cntrl0 rx_cntl0; 1464 nge_dev_spec_param_t *dev_param_p; 1465 1466 dev_param_p = &ngep->dev_spec_param; 1467 1468 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF); 1469 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY); 1470 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM); 1471 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL); 1472 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED; 1473 switch (ngep->param_link_speed) { 1474 case 10: 1475 m2p.m2p_bits.speed = low_speed; 1476 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1477 if (ngep->phy_mode == RGMII_IN) { 1478 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1479 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1480 } else { 1481 tx_def.def_bits.if_def = TX_TIFG_MII; 1482 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1483 } 1484 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1485 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1486 break; 1487 1488 case 100: 1489 m2p.m2p_bits.speed = fast_speed; 1490 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1491 if (ngep->phy_mode == RGMII_IN) { 1492 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1493 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1494 } else { 1495 tx_def.def_bits.if_def = TX_TIFG_MII; 1496 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1497 } 1498 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1499 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1500 break; 1501 1502 case 1000: 1503 m2p.m2p_bits.speed = giga_speed; 1504 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1505 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) { 1506 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1507 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD; 1508 } else { 1509 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1510 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1511 } 1512 1513 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII; 1514 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII; 1515 break; 1516 } 1517 1518 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1519 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 1520 m2p.m2p_bits.phyintr = NGE_CLEAR; 1521 m2p.m2p_bits.phyintrlvl = NGE_CLEAR; 1522 } 1523 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) { 1524 m2p.m2p_bits.hdup_en = NGE_SET; 1525 } 1526 else 1527 m2p.m2p_bits.hdup_en = NGE_CLEAR; 1528 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val); 1529 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val); 1530 1531 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM; 1532 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM; 1533 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM; 1534 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW; 1535 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val); 1536 1537 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val); 1538 1539 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1540 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) 1541 rx_cntl0.cntl_bits.paen = NGE_SET; 1542 else 1543 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1544 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1545 } 1546 1547 /* 1548 * Handler for hardware link state change. 1549 * 1550 * When this routine is called, the hardware link state has changed 1551 * and the new state is reflected in the param_* variables. Here 1552 * we must update the softstate, reprogram the MAC to match, and 1553 * record the change in the log and/or on the console. 1554 */ 1555 static void 1556 nge_factotum_link_handler(nge_t *ngep) 1557 { 1558 /* 1559 * Update the s/w link_state 1560 */ 1561 if (ngep->param_link_up) 1562 ngep->link_state = LINK_STATE_UP; 1563 else 1564 ngep->link_state = LINK_STATE_DOWN; 1565 1566 /* 1567 * Reprogram the MAC modes to match 1568 */ 1569 nge_sync_mac_modes(ngep); 1570 } 1571 1572 static boolean_t 1573 nge_factotum_link_check(nge_t *ngep) 1574 { 1575 boolean_t lchg; 1576 boolean_t check; 1577 1578 ASSERT(mutex_owned(ngep->genlock)); 1579 1580 (*ngep->physops->phys_check)(ngep); 1581 switch (ngep->link_state) { 1582 case LINK_STATE_UP: 1583 lchg = (ngep->param_link_up == B_FALSE); 1584 check = (ngep->param_link_up == B_FALSE); 1585 break; 1586 1587 case LINK_STATE_DOWN: 1588 lchg = (ngep->param_link_up == B_TRUE); 1589 check = (ngep->param_link_up == B_TRUE); 1590 break; 1591 1592 default: 1593 check = B_TRUE; 1594 break; 1595 } 1596 1597 /* 1598 * If <check> is false, we're sure the link hasn't changed. 1599 * If true, however, it's not yet definitive; we have to call 1600 * nge_phys_check() to determine whether the link has settled 1601 * into a new state yet ... and if it has, then call the link 1602 * state change handler.But when the chip is 5700 in Dell 6650 1603 * ,even if check is false, the link may have changed.So we 1604 * have to call nge_phys_check() to determine the link state. 1605 */ 1606 if (check) 1607 nge_factotum_link_handler(ngep); 1608 1609 return (lchg); 1610 } 1611 1612 /* 1613 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1614 */ 1615 static boolean_t nge_factotum_stall_check(nge_t *ngep); 1616 1617 static boolean_t 1618 nge_factotum_stall_check(nge_t *ngep) 1619 { 1620 uint32_t dogval; 1621 /* 1622 * Specific check for Tx stall ... 1623 * 1624 * The 'watchdog' counter is incremented whenever a packet 1625 * is queued, reset to 1 when some (but not all) buffers 1626 * are reclaimed, reset to 0 (disabled) when all buffers 1627 * are reclaimed, and shifted left here. If it exceeds the 1628 * threshold value, the chip is assumed to have stalled and 1629 * is put into the ERROR state. The factotum will then reset 1630 * it on the next pass. 1631 * 1632 * All of which should ensure that we don't get into a state 1633 * where packets are left pending indefinitely! 1634 */ 1635 dogval = nge_atomic_shl32(&ngep->watchdog, 1); 1636 if (dogval < nge_watchdog_count) { 1637 ngep->stall_cknum = 0; 1638 } else { 1639 ngep->stall_cknum++; 1640 } 1641 if (ngep->stall_cknum < 16) { 1642 return (B_FALSE); 1643 } else { 1644 ngep->stall_cknum = 0; 1645 ngep->statistics.sw_statistics.tx_stall++; 1646 return (B_TRUE); 1647 } 1648 } 1649 1650 1651 1652 /* 1653 * The factotum is woken up when there's something to do that we'd rather 1654 * not do from inside a hardware interrupt handler or high-level cyclic. 1655 * Its two main tasks are: 1656 * reset & restart the chip after an error 1657 * check the link status whenever necessary 1658 */ 1659 /* ARGSUSED */ 1660 uint_t 1661 nge_chip_factotum(caddr_t args1, caddr_t args2) 1662 { 1663 uint_t result; 1664 nge_t *ngep; 1665 boolean_t err; 1666 boolean_t linkchg; 1667 1668 ngep = (nge_t *)args1; 1669 1670 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep)); 1671 1672 mutex_enter(ngep->softlock); 1673 if (ngep->factotum_flag == 0) { 1674 mutex_exit(ngep->softlock); 1675 return (DDI_INTR_UNCLAIMED); 1676 } 1677 ngep->factotum_flag = 0; 1678 mutex_exit(ngep->softlock); 1679 err = B_FALSE; 1680 linkchg = B_FALSE; 1681 result = DDI_INTR_CLAIMED; 1682 1683 mutex_enter(ngep->genlock); 1684 switch (ngep->nge_chip_state) { 1685 default: 1686 break; 1687 1688 case NGE_CHIP_RUNNING: 1689 linkchg = nge_factotum_link_check(ngep); 1690 err = nge_factotum_stall_check(ngep); 1691 break; 1692 1693 case NGE_CHIP_FAULT: 1694 (void) nge_restart(ngep); 1695 NGE_REPORT((ngep, "automatic recovery activated")); 1696 break; 1697 } 1698 1699 if (err) 1700 (void) nge_chip_stop(ngep, B_TRUE); 1701 mutex_exit(ngep->genlock); 1702 1703 /* 1704 * If the link state changed, tell the world about it (if 1705 * this version of MAC supports link state notification). 1706 * Note: can't do this while still holding the mutex. 1707 */ 1708 if (linkchg) 1709 mac_link_update(ngep->mh, ngep->link_state); 1710 1711 return (result); 1712 1713 } 1714 1715 static void 1716 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src) 1717 { 1718 boolean_t brx; 1719 boolean_t btx; 1720 nge_mintr_src mintr_src; 1721 1722 brx = B_FALSE; 1723 btx = B_FALSE; 1724 ngep->statistics.sw_statistics.intr_count++; 1725 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val; 1726 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss 1727 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint) 1728 != 0 ? B_TRUE : B_FALSE; 1729 if (pintr_src->int_bits.reint) 1730 ngep->statistics.sw_statistics.rx_err++; 1731 if (pintr_src->int_bits.miss) 1732 ngep->statistics.sw_statistics.rx_nobuffer++; 1733 1734 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tcint) 1735 != 0 ? B_TRUE : B_FALSE; 1736 if (pintr_src->int_bits.stint && ngep->poll) 1737 ngep->stint_count ++; 1738 if (ngep->poll && (ngep->stint_count % ngep->param_tx_n_intr == 0)) 1739 btx = B_TRUE; 1740 if (btx) 1741 nge_tx_recycle(ngep, B_TRUE); 1742 if (brx) 1743 nge_receive(ngep); 1744 if (pintr_src->int_bits.teint) 1745 ngep->statistics.sw_statistics.tx_stop_err++; 1746 if (ngep->intr_moderation && brx) { 1747 if (ngep->poll) { 1748 if (ngep->recv_count < ngep->param_rx_intr_hwater) { 1749 ngep->quiet_time++; 1750 if (ngep->quiet_time == 1751 ngep->param_poll_quiet_time) { 1752 ngep->poll = B_FALSE; 1753 ngep->quiet_time = 0; 1754 ngep->stint_count = 0; 1755 nge_tx_recycle(ngep, B_TRUE); 1756 } 1757 } else 1758 ngep->quiet_time = 0; 1759 } else { 1760 if (ngep->recv_count > ngep->param_rx_intr_lwater) { 1761 ngep->busy_time++; 1762 if (ngep->busy_time == 1763 ngep->param_poll_busy_time) { 1764 ngep->poll = B_TRUE; 1765 ngep->busy_time = 0; 1766 } 1767 } else 1768 ngep->busy_time = 0; 1769 } 1770 } 1771 ngep->recv_count = 0; 1772 if (pintr_src->int_bits.feint) 1773 nge_chip_err(ngep); 1774 /* link interrupt, check the link state */ 1775 if (pintr_src->int_bits.mint) { 1776 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC); 1777 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val); 1778 nge_wake_factotum(ngep); 1779 } 1780 } 1781 1782 /* 1783 * nge_chip_intr() -- handle chip interrupts 1784 */ 1785 /* ARGSUSED */ 1786 uint_t 1787 nge_chip_intr(caddr_t arg1, caddr_t arg2) 1788 { 1789 nge_t *ngep = (nge_t *)arg1; 1790 nge_intr_src intr_src; 1791 nge_intr_mask intr_mask; 1792 1793 mutex_enter(ngep->genlock); 1794 1795 if (ngep->suspended) { 1796 mutex_exit(ngep->genlock); 1797 return (DDI_INTR_UNCLAIMED); 1798 } 1799 1800 /* 1801 * Check whether chip's says it's asserting #INTA; 1802 * if not, don't process or claim the interrupt. 1803 */ 1804 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 1805 if (intr_src.intr_val == 0) { 1806 mutex_exit(ngep->genlock); 1807 return (DDI_INTR_UNCLAIMED); 1808 } 1809 /* 1810 * Ack the interrupt 1811 */ 1812 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 1813 1814 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) { 1815 mutex_exit(ngep->genlock); 1816 return (DDI_INTR_CLAIMED); 1817 } 1818 nge_intr_handle(ngep, &intr_src); 1819 if (ngep->poll && !ngep->ch_intr_mode) { 1820 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1821 intr_mask.mask_bits.stint = NGE_SET; 1822 intr_mask.mask_bits.rcint = NGE_CLEAR; 1823 intr_mask.mask_bits.reint = NGE_CLEAR; 1824 intr_mask.mask_bits.tcint = NGE_CLEAR; 1825 intr_mask.mask_bits.teint = NGE_CLEAR; 1826 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1827 ngep->ch_intr_mode = B_TRUE; 1828 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) { 1829 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks); 1830 ngep->ch_intr_mode = B_FALSE; 1831 } 1832 mutex_exit(ngep->genlock); 1833 return (DDI_INTR_CLAIMED); 1834 } 1835 1836 static enum ioc_reply 1837 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1838 { 1839 int err; 1840 uint64_t sizemask; 1841 uint64_t mem_va; 1842 uint64_t maxoff; 1843 boolean_t peek; 1844 nge_peekpoke_t *ppd; 1845 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd); 1846 1847 switch (cmd) { 1848 default: 1849 return (IOC_INVAL); 1850 1851 case NGE_PEEK: 1852 peek = B_TRUE; 1853 break; 1854 1855 case NGE_POKE: 1856 peek = B_FALSE; 1857 break; 1858 } 1859 1860 /* 1861 * Validate format of ioctl 1862 */ 1863 if (iocp->ioc_count != sizeof (nge_peekpoke_t)) 1864 return (IOC_INVAL); 1865 if (mp->b_cont == NULL) 1866 return (IOC_INVAL); 1867 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr; 1868 1869 /* 1870 * Validate request parameters 1871 */ 1872 switch (ppd->pp_acc_space) { 1873 default: 1874 return (IOC_INVAL); 1875 1876 case NGE_PP_SPACE_CFG: 1877 /* 1878 * Config space 1879 */ 1880 sizemask = 8|4|2|1; 1881 mem_va = 0; 1882 maxoff = PCI_CONF_HDR_SIZE; 1883 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg; 1884 break; 1885 1886 case NGE_PP_SPACE_REG: 1887 /* 1888 * Memory-mapped I/O space 1889 */ 1890 sizemask = 8|4|2|1; 1891 mem_va = 0; 1892 maxoff = NGE_REG_SIZE; 1893 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg; 1894 break; 1895 1896 case NGE_PP_SPACE_MII: 1897 sizemask = 4|2|1; 1898 mem_va = 0; 1899 maxoff = NGE_MII_SIZE; 1900 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii; 1901 break; 1902 1903 case NGE_PP_SPACE_SEEPROM: 1904 sizemask = 4|2|1; 1905 mem_va = 0; 1906 maxoff = NGE_SEEROM_SIZE; 1907 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom; 1908 break; 1909 } 1910 1911 switch (ppd->pp_acc_size) { 1912 default: 1913 return (IOC_INVAL); 1914 1915 case 8: 1916 case 4: 1917 case 2: 1918 case 1: 1919 if ((ppd->pp_acc_size & sizemask) == 0) 1920 return (IOC_INVAL); 1921 break; 1922 } 1923 1924 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1925 return (IOC_INVAL); 1926 1927 if (ppd->pp_acc_offset >= maxoff) 1928 return (IOC_INVAL); 1929 1930 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1931 return (IOC_INVAL); 1932 1933 /* 1934 * All OK - go do it! 1935 */ 1936 ppd->pp_acc_offset += mem_va; 1937 if (ppfn) 1938 err = (*ppfn)(ngep, ppd); 1939 if (err != DDI_SUCCESS) 1940 return (IOC_INVAL); 1941 return (peek ? IOC_REPLY : IOC_ACK); 1942 } 1943 1944 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, 1945 struct iocblk *iocp); 1946 #pragma no_inline(nge_diag_ioctl) 1947 1948 static enum ioc_reply 1949 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1950 { 1951 ASSERT(mutex_owned(ngep->genlock)); 1952 1953 switch (cmd) { 1954 default: 1955 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd); 1956 return (IOC_INVAL); 1957 1958 case NGE_DIAG: 1959 return (IOC_ACK); 1960 1961 case NGE_PEEK: 1962 case NGE_POKE: 1963 return (nge_pp_ioctl(ngep, cmd, mp, iocp)); 1964 1965 case NGE_PHY_RESET: 1966 return (IOC_RESTART_ACK); 1967 1968 case NGE_SOFT_RESET: 1969 case NGE_HARD_RESET: 1970 return (IOC_ACK); 1971 } 1972 1973 /* NOTREACHED */ 1974 } 1975 1976 enum ioc_reply 1977 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 1978 { 1979 int cmd; 1980 1981 ASSERT(mutex_owned(ngep->genlock)); 1982 1983 cmd = iocp->ioc_cmd; 1984 1985 switch (cmd) { 1986 default: 1987 return (IOC_INVAL); 1988 1989 case NGE_DIAG: 1990 case NGE_PEEK: 1991 case NGE_POKE: 1992 case NGE_PHY_RESET: 1993 case NGE_SOFT_RESET: 1994 case NGE_HARD_RESET: 1995 #if NGE_DEBUGGING 1996 return (nge_diag_ioctl(ngep, cmd, mp, iocp)); 1997 #else 1998 return (IOC_INVAL); 1999 #endif 2000 2001 case NGE_MII_READ: 2002 case NGE_MII_WRITE: 2003 return (IOC_INVAL); 2004 2005 #if NGE_SEE_IO32 2006 case NGE_SEE_READ: 2007 case NGE_SEE_WRITE: 2008 return (IOC_INVAL); 2009 #endif 2010 2011 #if NGE_FLASH_IO32 2012 case NGE_FLASH_READ: 2013 case NGE_FLASH_WRITE: 2014 return (IOC_INVAL); 2015 #endif 2016 } 2017 } 2018