1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * MII overrides for Cicada (now Vitesse) PHYs. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/mii.h> 34 #include <sys/miiregs.h> 35 #include "miipriv.h" 36 37 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 38 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 39 40 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 41 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 42 43 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 44 #define MII_CICADA_MODE_SELECT_BITS 0xf000 45 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 46 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 47 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 48 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 49 50 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 51 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 52 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 53 54 /* 55 * The nge driver seems to do some rather specialized programming of 56 * this PHY. Specifically, it appears that the PHY is programmed for 57 * 2.5 RGMII operation and the PIN_PRIOITY_SETTING is set for RGMII 58 * interfaces. For MII interfaces, the echo mode is disabled and the 59 * 125MHz clock is disabled. 60 * 61 * It isn't immediately clear to me how to cleanly do this. One could 62 * probably argue that this particular PHY would never ever be used in 63 * a strict MII setting, but I hate to make an incorrect assumption. 64 * 65 * For now, absent data sheets on this part, we're going just leave 66 * the code for this in nge. 67 * 68 * If someone has data sheets and can "prove" that the architecture 69 * works portably across drivers, revisiting this logic and adding code 70 * to handle these PHYs would be cleaner. 71 */ 72 boolean_t 73 phy_cicada_probe(phy_handle_t *ph) 74 { 75 switch (MII_PHY_MFG(ph->phy_id)) { 76 case MII_OUI_CICADA: 77 case MII_OUI_CICADA_2: 78 switch (MII_PHY_MODEL(ph->phy_id)) { 79 case MII_MODEL_CICADA_CS8201: 80 case MII_MODEL_CICADA_CS8201A: 81 case MII_MODEL_CICADA_CS8201B: 82 ph->phy_vendor = "Cicada"; 83 ph->phy_model = "CS8201"; 84 return (B_TRUE); 85 default: 86 break; 87 } 88 break; 89 90 default: 91 break; 92 } 93 94 return (B_FALSE); 95 } 96