1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #include "ixgbe_sw.h" 29 30 static int ixgbe_tx_copy(ixgbe_tx_ring_t *, tx_control_block_t *, mblk_t *, 31 uint32_t, boolean_t); 32 static int ixgbe_tx_bind(ixgbe_tx_ring_t *, tx_control_block_t *, mblk_t *, 33 uint32_t); 34 static int ixgbe_tx_fill_ring(ixgbe_tx_ring_t *, link_list_t *, 35 ixgbe_tx_context_t *, size_t); 36 static void ixgbe_save_desc(tx_control_block_t *, uint64_t, size_t); 37 static tx_control_block_t *ixgbe_get_free_list(ixgbe_tx_ring_t *); 38 39 static int ixgbe_get_context(mblk_t *, ixgbe_tx_context_t *); 40 static boolean_t ixgbe_check_context(ixgbe_tx_ring_t *, 41 ixgbe_tx_context_t *); 42 static void ixgbe_fill_context(struct ixgbe_adv_tx_context_desc *, 43 ixgbe_tx_context_t *); 44 45 #ifndef IXGBE_DEBUG 46 #pragma inline(ixgbe_save_desc) 47 #pragma inline(ixgbe_get_context) 48 #pragma inline(ixgbe_check_context) 49 #pragma inline(ixgbe_fill_context) 50 #endif 51 52 /* 53 * ixgbe_ring_tx 54 * 55 * To transmit one mblk through one specified ring. 56 * 57 * One mblk can consist of several fragments, each fragment 58 * will be processed with different methods based on the size. 59 * For the fragments with size less than the bcopy threshold, 60 * they will be processed by using bcopy; otherwise, they will 61 * be processed by using DMA binding. 62 * 63 * To process the mblk, a tx control block is got from the 64 * free list. One tx control block contains one tx buffer, which 65 * is used to copy mblk fragments' data; and one tx DMA handle, 66 * which is used to bind a mblk fragment with DMA resource. 67 * 68 * Several small mblk fragments can be copied into one tx control 69 * block's buffer, and then the buffer will be transmitted with 70 * one tx descriptor. 71 * 72 * A large fragment only binds with one tx control block's DMA 73 * handle, and it can span several tx descriptors for transmitting. 74 * 75 * So to transmit a packet (mblk), several tx control blocks can 76 * be used. After the processing, those tx control blocks will 77 * be put to the work list. 78 */ 79 mblk_t * 80 ixgbe_ring_tx(void *arg, mblk_t *mp) 81 { 82 ixgbe_tx_ring_t *tx_ring = (ixgbe_tx_ring_t *)arg; 83 ixgbe_t *ixgbe = tx_ring->ixgbe; 84 tx_type_t current_flag, next_flag; 85 uint32_t current_len, next_len; 86 uint32_t desc_total; 87 size_t mbsize; 88 int desc_num; 89 boolean_t copy_done, eop; 90 mblk_t *current_mp, *next_mp, *nmp, *pull_mp = NULL; 91 tx_control_block_t *tcb; 92 ixgbe_tx_context_t tx_context, *ctx; 93 link_list_t pending_list; 94 uint32_t len, hdr_frag_len, hdr_len; 95 uint32_t copy_thresh; 96 mblk_t *hdr_new_mp = NULL; 97 mblk_t *hdr_pre_mp = NULL; 98 mblk_t *hdr_nmp = NULL; 99 100 ASSERT(mp->b_next == NULL); 101 102 if ((ixgbe->ixgbe_state & IXGBE_SUSPENDED) || 103 (ixgbe->ixgbe_state & IXGBE_ERROR) || 104 !(ixgbe->ixgbe_state & IXGBE_STARTED)) { 105 return (mp); 106 } 107 108 copy_thresh = ixgbe->tx_copy_thresh; 109 110 /* Get the mblk size */ 111 mbsize = 0; 112 for (nmp = mp; nmp != NULL; nmp = nmp->b_cont) { 113 mbsize += MBLKL(nmp); 114 } 115 116 if (ixgbe->tx_hcksum_enable) { 117 /* 118 * Retrieve checksum context information from the mblk 119 * that will be used to decide whether/how to fill the 120 * context descriptor. 121 */ 122 ctx = &tx_context; 123 if (ixgbe_get_context(mp, ctx) < 0) { 124 freemsg(mp); 125 return (NULL); 126 } 127 128 /* 129 * If the mblk size exceeds the max size ixgbe could 130 * process, then discard this mblk, and return NULL. 131 */ 132 if ((ctx->lso_flag && 133 ((mbsize - ctx->mac_hdr_len) > IXGBE_LSO_MAXLEN)) || 134 (!ctx->lso_flag && 135 (mbsize > (ixgbe->max_frame_size - ETHERFCSL)))) { 136 freemsg(mp); 137 IXGBE_DEBUGLOG_0(ixgbe, "ixgbe_tx: packet oversize"); 138 return (NULL); 139 } 140 } else { 141 ctx = NULL; 142 } 143 144 /* 145 * Check and recycle tx descriptors. 146 * The recycle threshold here should be selected carefully 147 */ 148 if (tx_ring->tbd_free < ixgbe->tx_recycle_thresh) { 149 tx_ring->tx_recycle(tx_ring); 150 } 151 152 /* 153 * After the recycling, if the tbd_free is less than the 154 * overload_threshold, assert overload, return mp; 155 * and we need to re-schedule the tx again. 156 */ 157 if (tx_ring->tbd_free < ixgbe->tx_overload_thresh) { 158 tx_ring->reschedule = B_TRUE; 159 IXGBE_DEBUG_STAT(tx_ring->stat_overload); 160 return (mp); 161 } 162 163 /* 164 * The pending_list is a linked list that is used to save 165 * the tx control blocks that have packet data processed 166 * but have not put the data to the tx descriptor ring. 167 * It is used to reduce the lock contention of the tx_lock. 168 */ 169 LINK_LIST_INIT(&pending_list); 170 desc_num = 0; 171 desc_total = 0; 172 173 /* 174 * The software should guarantee LSO packet header(MAC+IP+TCP) 175 * to be within one descriptor. Here we reallocate and refill the 176 * the header if it's physical memory non-contiguous. 177 */ 178 if ((ctx != NULL) && ctx->lso_flag) { 179 /* find the last fragment of the header */ 180 len = MBLKL(mp); 181 ASSERT(len > 0); 182 hdr_nmp = mp; 183 hdr_len = ctx->ip_hdr_len + ctx->mac_hdr_len + ctx->l4_hdr_len; 184 while (len < hdr_len) { 185 hdr_pre_mp = hdr_nmp; 186 hdr_nmp = hdr_nmp->b_cont; 187 len += MBLKL(hdr_nmp); 188 } 189 /* 190 * If the header and the payload are in different mblks, 191 * we simply force the header to be copied into pre-allocated 192 * page-aligned buffer. 193 */ 194 if (len == hdr_len) 195 goto adjust_threshold; 196 197 hdr_frag_len = hdr_len - (len - MBLKL(hdr_nmp)); 198 /* 199 * There are two cases we need to reallocate a mblk for the 200 * last header fragment: 201 * 1. the header is in multiple mblks and the last fragment 202 * share the same mblk with the payload 203 * 2. the header is in a single mblk shared with the payload 204 * and the header is physical memory non-contiguous 205 */ 206 if ((hdr_nmp != mp) || 207 (P2NPHASE((uintptr_t)hdr_nmp->b_rptr, ixgbe->sys_page_size) 208 < hdr_len)) { 209 IXGBE_DEBUG_STAT(tx_ring->stat_lso_header_fail); 210 /* 211 * reallocate the mblk for the last header fragment, 212 * expect to bcopy into pre-allocated page-aligned 213 * buffer 214 */ 215 hdr_new_mp = allocb(hdr_frag_len, NULL); 216 if (!hdr_new_mp) 217 return (mp); 218 bcopy(hdr_nmp->b_rptr, hdr_new_mp->b_rptr, 219 hdr_frag_len); 220 /* link the new header fragment with the other parts */ 221 hdr_new_mp->b_wptr = hdr_new_mp->b_rptr + hdr_frag_len; 222 hdr_new_mp->b_cont = hdr_nmp; 223 if (hdr_pre_mp) 224 hdr_pre_mp->b_cont = hdr_new_mp; 225 else 226 mp = hdr_new_mp; 227 hdr_nmp->b_rptr += hdr_frag_len; 228 } 229 adjust_threshold: 230 /* 231 * adjust the bcopy threshhold to guarantee 232 * the header to use bcopy way 233 */ 234 if (copy_thresh < hdr_len) 235 copy_thresh = hdr_len; 236 } 237 238 current_mp = mp; 239 current_len = MBLKL(current_mp); 240 /* 241 * Decide which method to use for the first fragment 242 */ 243 current_flag = (current_len <= copy_thresh) ? 244 USE_COPY : USE_DMA; 245 /* 246 * If the mblk includes several contiguous small fragments, 247 * they may be copied into one buffer. This flag is used to 248 * indicate whether there are pending fragments that need to 249 * be copied to the current tx buffer. 250 * 251 * If this flag is B_TRUE, it indicates that a new tx control 252 * block is needed to process the next fragment using either 253 * copy or DMA binding. 254 * 255 * Otherwise, it indicates that the next fragment will be 256 * copied to the current tx buffer that is maintained by the 257 * current tx control block. No new tx control block is needed. 258 */ 259 copy_done = B_TRUE; 260 while (current_mp) { 261 next_mp = current_mp->b_cont; 262 eop = (next_mp == NULL); /* Last fragment of the packet? */ 263 next_len = eop ? 0: MBLKL(next_mp); 264 265 /* 266 * When the current fragment is an empty fragment, if 267 * the next fragment will still be copied to the current 268 * tx buffer, we cannot skip this fragment here. Because 269 * the copy processing is pending for completion. We have 270 * to process this empty fragment in the tx_copy routine. 271 * 272 * If the copy processing is completed or a DMA binding 273 * processing is just completed, we can just skip this 274 * empty fragment. 275 */ 276 if ((current_len == 0) && (copy_done)) { 277 current_mp = next_mp; 278 current_len = next_len; 279 current_flag = (current_len <= copy_thresh) ? 280 USE_COPY : USE_DMA; 281 continue; 282 } 283 284 if (copy_done) { 285 /* 286 * Get a new tx control block from the free list 287 */ 288 tcb = ixgbe_get_free_list(tx_ring); 289 290 if (tcb == NULL) { 291 IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tcb); 292 goto tx_failure; 293 } 294 295 /* 296 * Push the tx control block to the pending list 297 * to avoid using lock too early 298 */ 299 LIST_PUSH_TAIL(&pending_list, &tcb->link); 300 } 301 302 if (current_flag == USE_COPY) { 303 /* 304 * Check whether to use bcopy or DMA binding to process 305 * the next fragment, and if using bcopy, whether we 306 * need to continue copying the next fragment into the 307 * current tx buffer. 308 */ 309 ASSERT((tcb->tx_buf.len + current_len) <= 310 tcb->tx_buf.size); 311 312 if (eop) { 313 /* 314 * This is the last fragment of the packet, so 315 * the copy processing will be completed with 316 * this fragment. 317 */ 318 next_flag = USE_NONE; 319 copy_done = B_TRUE; 320 } else if ((tcb->tx_buf.len + current_len + next_len) > 321 tcb->tx_buf.size) { 322 /* 323 * If the next fragment is too large to be 324 * copied to the current tx buffer, we need 325 * to complete the current copy processing. 326 */ 327 next_flag = (next_len > copy_thresh) ? 328 USE_DMA: USE_COPY; 329 copy_done = B_TRUE; 330 } else if (next_len > copy_thresh) { 331 /* 332 * The next fragment needs to be processed with 333 * DMA binding. So the copy prcessing will be 334 * completed with the current fragment. 335 */ 336 next_flag = USE_DMA; 337 copy_done = B_TRUE; 338 } else { 339 /* 340 * Continue to copy the next fragment to the 341 * current tx buffer. 342 */ 343 next_flag = USE_COPY; 344 copy_done = B_FALSE; 345 } 346 347 desc_num = ixgbe_tx_copy(tx_ring, tcb, current_mp, 348 current_len, copy_done); 349 } else { 350 /* 351 * Check whether to use bcopy or DMA binding to process 352 * the next fragment. 353 */ 354 next_flag = (next_len > copy_thresh) ? 355 USE_DMA: USE_COPY; 356 ASSERT(copy_done == B_TRUE); 357 358 desc_num = ixgbe_tx_bind(tx_ring, tcb, current_mp, 359 current_len); 360 } 361 362 if (desc_num > 0) 363 desc_total += desc_num; 364 else if (desc_num < 0) 365 goto tx_failure; 366 367 current_mp = next_mp; 368 current_len = next_len; 369 current_flag = next_flag; 370 } 371 372 /* 373 * Attach the mblk to the last tx control block 374 */ 375 ASSERT(tcb); 376 ASSERT(tcb->mp == NULL); 377 tcb->mp = mp; 378 379 /* 380 * 82598/82599 chipset has a limitation that no more than 32 tx 381 * descriptors can be transmited out at one time. 382 * 383 * Here is a workaround for it: pull up the mblk then send it 384 * out with bind way. By doing so, no more than MAX_COOKIE (18) 385 * descriptors is needed. 386 */ 387 if (desc_total + 1 > IXGBE_TX_DESC_LIMIT) { 388 IXGBE_DEBUG_STAT(tx_ring->stat_break_tbd_limit); 389 390 /* 391 * Discard the mblk and free the used resources 392 */ 393 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 394 while (tcb) { 395 tcb->mp = NULL; 396 ixgbe_free_tcb(tcb); 397 tcb = (tx_control_block_t *) 398 LIST_GET_NEXT(&pending_list, &tcb->link); 399 } 400 401 /* 402 * Return the tx control blocks in the pending list to 403 * the free list. 404 */ 405 ixgbe_put_free_list(tx_ring, &pending_list); 406 407 /* 408 * pull up the mblk and send it out with bind way 409 */ 410 if ((pull_mp = msgpullup(mp, -1)) == NULL) { 411 tx_ring->reschedule = B_TRUE; 412 413 /* 414 * If new mblk has been allocted for the last header 415 * fragment of a LSO packet, we should restore the 416 * modified mp. 417 */ 418 if (hdr_new_mp) { 419 hdr_new_mp->b_cont = NULL; 420 freeb(hdr_new_mp); 421 hdr_nmp->b_rptr -= hdr_frag_len; 422 if (hdr_pre_mp) 423 hdr_pre_mp->b_cont = hdr_nmp; 424 else 425 mp = hdr_nmp; 426 } 427 return (mp); 428 } 429 430 LINK_LIST_INIT(&pending_list); 431 desc_total = 0; 432 433 /* 434 * if the packet is a LSO packet, we simply 435 * transmit the header in one descriptor using the copy way 436 */ 437 if ((ctx != NULL) && ctx->lso_flag) { 438 hdr_len = ctx->ip_hdr_len + ctx->mac_hdr_len + 439 ctx->l4_hdr_len; 440 441 tcb = ixgbe_get_free_list(tx_ring); 442 if (tcb == NULL) { 443 IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tcb); 444 goto tx_failure; 445 } 446 desc_num = ixgbe_tx_copy(tx_ring, tcb, pull_mp, 447 hdr_len, B_TRUE); 448 LIST_PUSH_TAIL(&pending_list, &tcb->link); 449 desc_total += desc_num; 450 451 pull_mp->b_rptr += hdr_len; 452 } 453 454 tcb = ixgbe_get_free_list(tx_ring); 455 if (tcb == NULL) { 456 IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tcb); 457 goto tx_failure; 458 } 459 if ((ctx != NULL) && ctx->lso_flag) { 460 desc_num = ixgbe_tx_bind(tx_ring, tcb, pull_mp, 461 mbsize - hdr_len); 462 } else { 463 desc_num = ixgbe_tx_bind(tx_ring, tcb, pull_mp, 464 mbsize); 465 } 466 if (desc_num < 0) { 467 goto tx_failure; 468 } 469 LIST_PUSH_TAIL(&pending_list, &tcb->link); 470 471 desc_total += desc_num; 472 tcb->mp = pull_mp; 473 } 474 475 /* 476 * Before fill the tx descriptor ring with the data, we need to 477 * ensure there are adequate free descriptors for transmit 478 * (including one context descriptor). 479 */ 480 if (tx_ring->tbd_free < (desc_total + 1)) { 481 tx_ring->tx_recycle(tx_ring); 482 } 483 484 mutex_enter(&tx_ring->tx_lock); 485 /* 486 * If the number of free tx descriptors is not enough for transmit 487 * then return mp. 488 * 489 * Note: we must put this check under the mutex protection to 490 * ensure the correctness when multiple threads access it in 491 * parallel. 492 */ 493 if (tx_ring->tbd_free < (desc_total + 1)) { 494 IXGBE_DEBUG_STAT(tx_ring->stat_fail_no_tbd); 495 mutex_exit(&tx_ring->tx_lock); 496 goto tx_failure; 497 } 498 499 desc_num = ixgbe_tx_fill_ring(tx_ring, &pending_list, ctx, 500 mbsize); 501 502 ASSERT((desc_num == desc_total) || (desc_num == (desc_total + 1))); 503 504 mutex_exit(&tx_ring->tx_lock); 505 506 /* 507 * now that the transmission succeeds, need to free the original 508 * mp if we used the pulling up mblk for transmission. 509 */ 510 if (pull_mp) { 511 freemsg(mp); 512 } 513 514 return (NULL); 515 516 tx_failure: 517 /* 518 * If transmission fails, need to free the pulling up mblk. 519 */ 520 if (pull_mp) { 521 freemsg(pull_mp); 522 } 523 524 /* 525 * If new mblk has been allocted for the last header 526 * fragment of a LSO packet, we should restore the 527 * modified mp. 528 */ 529 if (hdr_new_mp) { 530 hdr_new_mp->b_cont = NULL; 531 freeb(hdr_new_mp); 532 hdr_nmp->b_rptr -= hdr_frag_len; 533 if (hdr_pre_mp) 534 hdr_pre_mp->b_cont = hdr_nmp; 535 else 536 mp = hdr_nmp; 537 } 538 /* 539 * Discard the mblk and free the used resources 540 */ 541 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 542 while (tcb) { 543 tcb->mp = NULL; 544 545 ixgbe_free_tcb(tcb); 546 547 tcb = (tx_control_block_t *) 548 LIST_GET_NEXT(&pending_list, &tcb->link); 549 } 550 551 /* 552 * Return the tx control blocks in the pending list to the free list. 553 */ 554 ixgbe_put_free_list(tx_ring, &pending_list); 555 556 /* Transmit failed, do not drop the mblk, rechedule the transmit */ 557 tx_ring->reschedule = B_TRUE; 558 559 return (mp); 560 } 561 562 /* 563 * ixgbe_tx_copy 564 * 565 * Copy the mblk fragment to the pre-allocated tx buffer 566 */ 567 static int 568 ixgbe_tx_copy(ixgbe_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 569 uint32_t len, boolean_t copy_done) 570 { 571 dma_buffer_t *tx_buf; 572 uint32_t desc_num; 573 _NOTE(ARGUNUSED(tx_ring)); 574 575 tx_buf = &tcb->tx_buf; 576 577 /* 578 * Copy the packet data of the mblk fragment into the 579 * pre-allocated tx buffer, which is maintained by the 580 * tx control block. 581 * 582 * Several mblk fragments can be copied into one tx buffer. 583 * The destination address of the current copied fragment in 584 * the tx buffer is next to the end of the previous copied 585 * fragment. 586 */ 587 if (len > 0) { 588 bcopy(mp->b_rptr, tx_buf->address + tx_buf->len, len); 589 590 tx_buf->len += len; 591 tcb->frag_num++; 592 } 593 594 desc_num = 0; 595 596 /* 597 * If it is the last fragment copied to the current tx buffer, 598 * in other words, if there's no remaining fragment or the remaining 599 * fragment requires a new tx control block to process, we need to 600 * complete the current copy processing by syncing up the current 601 * DMA buffer and saving the descriptor data. 602 */ 603 if (copy_done) { 604 /* 605 * Sync the DMA buffer of the packet data 606 */ 607 DMA_SYNC(tx_buf, DDI_DMA_SYNC_FORDEV); 608 609 tcb->tx_type = USE_COPY; 610 611 /* 612 * Save the address and length to the private data structure 613 * of the tx control block, which will be used to fill the 614 * tx descriptor ring after all the fragments are processed. 615 */ 616 ixgbe_save_desc(tcb, tx_buf->dma_address, tx_buf->len); 617 desc_num++; 618 } 619 620 return (desc_num); 621 } 622 623 /* 624 * ixgbe_tx_bind 625 * 626 * Bind the mblk fragment with DMA 627 */ 628 static int 629 ixgbe_tx_bind(ixgbe_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 630 uint32_t len) 631 { 632 int status, i; 633 ddi_dma_cookie_t dma_cookie; 634 uint_t ncookies; 635 int desc_num; 636 637 /* 638 * Use DMA binding to process the mblk fragment 639 */ 640 status = ddi_dma_addr_bind_handle(tcb->tx_dma_handle, NULL, 641 (caddr_t)mp->b_rptr, len, 642 DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, 643 0, &dma_cookie, &ncookies); 644 645 if (status != DDI_DMA_MAPPED) { 646 IXGBE_DEBUG_STAT(tx_ring->stat_fail_dma_bind); 647 return (-1); 648 } 649 650 tcb->frag_num++; 651 tcb->tx_type = USE_DMA; 652 /* 653 * Each fragment can span several cookies. One cookie will have 654 * one tx descriptor to transmit. 655 */ 656 desc_num = 0; 657 for (i = ncookies; i > 0; i--) { 658 /* 659 * Save the address and length to the private data structure 660 * of the tx control block, which will be used to fill the 661 * tx descriptor ring after all the fragments are processed. 662 */ 663 ixgbe_save_desc(tcb, 664 dma_cookie.dmac_laddress, 665 dma_cookie.dmac_size); 666 667 desc_num++; 668 669 if (i > 1) 670 ddi_dma_nextcookie(tcb->tx_dma_handle, &dma_cookie); 671 } 672 673 return (desc_num); 674 } 675 676 /* 677 * ixgbe_get_context 678 * 679 * Get the context information from the mblk 680 */ 681 static int 682 ixgbe_get_context(mblk_t *mp, ixgbe_tx_context_t *ctx) 683 { 684 uint32_t start; 685 uint32_t hckflags; 686 uint32_t lsoflags; 687 uint32_t mss; 688 uint32_t len; 689 uint32_t size; 690 uint32_t offset; 691 unsigned char *pos; 692 ushort_t etype; 693 uint32_t mac_hdr_len; 694 uint32_t l4_proto; 695 uint32_t l4_hdr_len; 696 697 ASSERT(mp != NULL); 698 699 hcksum_retrieve(mp, NULL, NULL, &start, NULL, NULL, NULL, &hckflags); 700 bzero(ctx, sizeof (ixgbe_tx_context_t)); 701 702 if (hckflags == 0) { 703 return (0); 704 } 705 706 ctx->hcksum_flags = hckflags; 707 708 lso_info_get(mp, &mss, &lsoflags); 709 ctx->mss = mss; 710 ctx->lso_flag = (lsoflags == HW_LSO); 711 712 /* 713 * LSO relies on tx h/w checksum, so here will drop the package 714 * if h/w checksum flag is not declared. 715 */ 716 if (ctx->lso_flag) { 717 if (!((ctx->hcksum_flags & HCK_PARTIALCKSUM) && 718 (ctx->hcksum_flags & HCK_IPV4_HDRCKSUM))) { 719 IXGBE_DEBUGLOG_0(NULL, "ixgbe_tx: h/w " 720 "checksum flags are not specified when doing LSO"); 721 return (-1); 722 } 723 } 724 725 etype = 0; 726 mac_hdr_len = 0; 727 l4_proto = 0; 728 729 /* 730 * Firstly get the position of the ether_type/ether_tpid. 731 * Here we don't assume the ether (VLAN) header is fully included 732 * in one mblk fragment, so we go thourgh the fragments to parse 733 * the ether type. 734 */ 735 size = len = MBLKL(mp); 736 offset = offsetof(struct ether_header, ether_type); 737 while (size <= offset) { 738 mp = mp->b_cont; 739 ASSERT(mp != NULL); 740 len = MBLKL(mp); 741 size += len; 742 } 743 pos = mp->b_rptr + offset + len - size; 744 745 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 746 if (etype == ETHERTYPE_VLAN) { 747 /* 748 * Get the position of the ether_type in VLAN header 749 */ 750 offset = offsetof(struct ether_vlan_header, ether_type); 751 while (size <= offset) { 752 mp = mp->b_cont; 753 ASSERT(mp != NULL); 754 len = MBLKL(mp); 755 size += len; 756 } 757 pos = mp->b_rptr + offset + len - size; 758 759 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 760 mac_hdr_len = sizeof (struct ether_vlan_header); 761 } else { 762 mac_hdr_len = sizeof (struct ether_header); 763 } 764 765 /* 766 * Here we don't assume the IP(V6) header is fully included in 767 * one mblk fragment. 768 */ 769 switch (etype) { 770 case ETHERTYPE_IP: 771 if (ctx->lso_flag) { 772 offset = offsetof(ipha_t, ipha_length) + mac_hdr_len; 773 while (size <= offset) { 774 mp = mp->b_cont; 775 ASSERT(mp != NULL); 776 len = MBLKL(mp); 777 size += len; 778 } 779 pos = mp->b_rptr + offset + len - size; 780 *((uint16_t *)(uintptr_t)(pos)) = 0; 781 782 offset = offsetof(ipha_t, ipha_hdr_checksum) + 783 mac_hdr_len; 784 while (size <= offset) { 785 mp = mp->b_cont; 786 ASSERT(mp != NULL); 787 len = MBLKL(mp); 788 size += len; 789 } 790 pos = mp->b_rptr + offset + len - size; 791 *((uint16_t *)(uintptr_t)(pos)) = 0; 792 793 /* 794 * To perform ixgbe LSO, here also need to fill 795 * the tcp checksum field of the packet with the 796 * following pseudo-header checksum: 797 * (ip_source_addr, ip_destination_addr, l4_proto) 798 * Currently the tcp/ip stack has done it. 799 */ 800 } 801 802 offset = offsetof(ipha_t, ipha_protocol) + mac_hdr_len; 803 while (size <= offset) { 804 mp = mp->b_cont; 805 ASSERT(mp != NULL); 806 len = MBLKL(mp); 807 size += len; 808 } 809 pos = mp->b_rptr + offset + len - size; 810 811 l4_proto = *(uint8_t *)pos; 812 break; 813 case ETHERTYPE_IPV6: 814 offset = offsetof(ip6_t, ip6_nxt) + mac_hdr_len; 815 while (size <= offset) { 816 mp = mp->b_cont; 817 ASSERT(mp != NULL); 818 len = MBLKL(mp); 819 size += len; 820 } 821 pos = mp->b_rptr + offset + len - size; 822 823 l4_proto = *(uint8_t *)pos; 824 break; 825 default: 826 /* Unrecoverable error */ 827 IXGBE_DEBUGLOG_0(NULL, "Ether type error with tx hcksum"); 828 return (-2); 829 } 830 831 if (ctx->lso_flag) { 832 offset = mac_hdr_len + start; 833 while (size <= offset) { 834 mp = mp->b_cont; 835 ASSERT(mp != NULL); 836 len = MBLKL(mp); 837 size += len; 838 } 839 pos = mp->b_rptr + offset + len - size; 840 841 l4_hdr_len = TCP_HDR_LENGTH((tcph_t *)pos); 842 } else { 843 /* 844 * l4 header length is only required for LSO 845 */ 846 l4_hdr_len = 0; 847 } 848 849 ctx->mac_hdr_len = mac_hdr_len; 850 ctx->ip_hdr_len = start; 851 ctx->l4_proto = l4_proto; 852 ctx->l4_hdr_len = l4_hdr_len; 853 854 return (0); 855 } 856 857 /* 858 * ixgbe_check_context 859 * 860 * Check if a new context descriptor is needed 861 */ 862 static boolean_t 863 ixgbe_check_context(ixgbe_tx_ring_t *tx_ring, ixgbe_tx_context_t *ctx) 864 { 865 ixgbe_tx_context_t *last; 866 867 if (ctx == NULL) 868 return (B_FALSE); 869 870 /* 871 * Compare the context data retrieved from the mblk and the 872 * stored data of the last context descriptor. The data need 873 * to be checked are: 874 * hcksum_flags 875 * l4_proto 876 * mac_hdr_len 877 * ip_hdr_len 878 * lso_flag 879 * mss (only checked for LSO) 880 * l4_hr_len (only checked for LSO) 881 * Either one of the above data is changed, a new context descriptor 882 * will be needed. 883 */ 884 last = &tx_ring->tx_context; 885 886 if ((ctx->hcksum_flags != last->hcksum_flags) || 887 (ctx->l4_proto != last->l4_proto) || 888 (ctx->mac_hdr_len != last->mac_hdr_len) || 889 (ctx->ip_hdr_len != last->ip_hdr_len) || 890 (ctx->lso_flag != last->lso_flag) || 891 (ctx->lso_flag && ((ctx->mss != last->mss) || 892 (ctx->l4_hdr_len != last->l4_hdr_len)))) { 893 return (B_TRUE); 894 } 895 896 return (B_FALSE); 897 } 898 899 /* 900 * ixgbe_fill_context 901 * 902 * Fill the context descriptor with hardware checksum informations 903 */ 904 static void 905 ixgbe_fill_context(struct ixgbe_adv_tx_context_desc *ctx_tbd, 906 ixgbe_tx_context_t *ctx) 907 { 908 /* 909 * Fill the context descriptor with the checksum 910 * context information we've got. 911 */ 912 ctx_tbd->vlan_macip_lens = ctx->ip_hdr_len; 913 ctx_tbd->vlan_macip_lens |= ctx->mac_hdr_len << 914 IXGBE_ADVTXD_MACLEN_SHIFT; 915 916 ctx_tbd->type_tucmd_mlhl = 917 IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 918 919 if (ctx->hcksum_flags & HCK_IPV4_HDRCKSUM) 920 ctx_tbd->type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; 921 922 if (ctx->hcksum_flags & HCK_PARTIALCKSUM) { 923 switch (ctx->l4_proto) { 924 case IPPROTO_TCP: 925 ctx_tbd->type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 926 break; 927 case IPPROTO_UDP: 928 /* 929 * We don't have to explicitly set: 930 * ctx_tbd->type_tucmd_mlhl |= 931 * IXGBE_ADVTXD_TUCMD_L4T_UDP; 932 * Because IXGBE_ADVTXD_TUCMD_L4T_UDP == 0b 933 */ 934 break; 935 default: 936 /* Unrecoverable error */ 937 IXGBE_DEBUGLOG_0(NULL, "L4 type error with tx hcksum"); 938 break; 939 } 940 } 941 942 ctx_tbd->seqnum_seed = 0; 943 944 if (ctx->lso_flag) { 945 ctx_tbd->mss_l4len_idx = 946 (ctx->l4_hdr_len << IXGBE_ADVTXD_L4LEN_SHIFT) | 947 (ctx->mss << IXGBE_ADVTXD_MSS_SHIFT); 948 } else { 949 ctx_tbd->mss_l4len_idx = 0; 950 } 951 } 952 953 /* 954 * ixgbe_tx_fill_ring 955 * 956 * Fill the tx descriptor ring with the data 957 */ 958 static int 959 ixgbe_tx_fill_ring(ixgbe_tx_ring_t *tx_ring, link_list_t *pending_list, 960 ixgbe_tx_context_t *ctx, size_t mbsize) 961 { 962 struct ixgbe_hw *hw = &tx_ring->ixgbe->hw; 963 boolean_t load_context; 964 uint32_t index, tcb_index, desc_num; 965 union ixgbe_adv_tx_desc *tbd, *first_tbd; 966 tx_control_block_t *tcb, *first_tcb; 967 uint32_t hcksum_flags; 968 int i; 969 970 ASSERT(mutex_owned(&tx_ring->tx_lock)); 971 972 tbd = NULL; 973 first_tbd = NULL; 974 first_tcb = NULL; 975 desc_num = 0; 976 hcksum_flags = 0; 977 load_context = B_FALSE; 978 979 /* 980 * Get the index of the first tx descriptor that will be filled, 981 * and the index of the first work list item that will be attached 982 * with the first used tx control block in the pending list. 983 * Note: the two indexes are the same. 984 */ 985 index = tx_ring->tbd_tail; 986 tcb_index = tx_ring->tbd_tail; 987 988 if (ctx != NULL) { 989 hcksum_flags = ctx->hcksum_flags; 990 991 /* 992 * Check if a new context descriptor is needed for this packet 993 */ 994 load_context = ixgbe_check_context(tx_ring, ctx); 995 996 if (load_context) { 997 tbd = &tx_ring->tbd_ring[index]; 998 999 /* 1000 * Fill the context descriptor with the 1001 * hardware checksum offload informations. 1002 */ 1003 ixgbe_fill_context( 1004 (struct ixgbe_adv_tx_context_desc *)tbd, ctx); 1005 1006 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 1007 desc_num++; 1008 1009 /* 1010 * Store the checksum context data if 1011 * a new context descriptor is added 1012 */ 1013 tx_ring->tx_context = *ctx; 1014 } 1015 } 1016 1017 first_tbd = &tx_ring->tbd_ring[index]; 1018 1019 /* 1020 * Fill tx data descriptors with the data saved in the pending list. 1021 * The tx control blocks in the pending list are added to the work list 1022 * at the same time. 1023 * 1024 * The work list is strictly 1:1 corresponding to the descriptor ring. 1025 * One item of the work list corresponds to one tx descriptor. Because 1026 * one tx control block can span multiple tx descriptors, the tx 1027 * control block will be added to the first work list item that 1028 * corresponds to the first tx descriptor generated from that tx 1029 * control block. 1030 */ 1031 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1032 first_tcb = tcb; 1033 while (tcb != NULL) { 1034 1035 for (i = 0; i < tcb->desc_num; i++) { 1036 tbd = &tx_ring->tbd_ring[index]; 1037 1038 tbd->read.buffer_addr = tcb->desc[i].address; 1039 tbd->read.cmd_type_len = tcb->desc[i].length; 1040 1041 tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_DEXT 1042 | IXGBE_ADVTXD_DTYP_DATA; 1043 1044 tbd->read.olinfo_status = 0; 1045 1046 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 1047 desc_num++; 1048 } 1049 1050 /* 1051 * Add the tx control block to the work list 1052 */ 1053 ASSERT(tx_ring->work_list[tcb_index] == NULL); 1054 tx_ring->work_list[tcb_index] = tcb; 1055 1056 tcb_index = index; 1057 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1058 } 1059 1060 if (load_context) { 1061 /* 1062 * Count the context descriptor for 1063 * the first tx control block. 1064 */ 1065 first_tcb->desc_num++; 1066 } 1067 first_tcb->last_index = PREV_INDEX(index, 1, tx_ring->ring_size); 1068 1069 /* 1070 * The Insert Ethernet CRC (IFCS) bit and the checksum fields are only 1071 * valid in the first descriptor of the packet. 1072 * Setting paylen in every first_tbd for all parts. 1073 * 82599 requires the packet length in paylen field with or without 1074 * LSO and 82598 will ignore it in non-LSO mode. 1075 */ 1076 ASSERT(first_tbd != NULL); 1077 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS; 1078 1079 switch (hw->mac.type) { 1080 case ixgbe_mac_82599EB: 1081 if (ctx != NULL && ctx->lso_flag) { 1082 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; 1083 first_tbd->read.olinfo_status |= 1084 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len 1085 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT; 1086 } else { 1087 first_tbd->read.olinfo_status |= 1088 (mbsize << IXGBE_ADVTXD_PAYLEN_SHIFT); 1089 } 1090 break; 1091 case ixgbe_mac_82598EB: 1092 if (ctx != NULL && ctx->lso_flag) { 1093 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; 1094 first_tbd->read.olinfo_status |= 1095 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len 1096 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT; 1097 } 1098 break; 1099 default: 1100 break; 1101 } 1102 1103 /* Set hardware checksum bits */ 1104 if (hcksum_flags != 0) { 1105 if (hcksum_flags & HCK_IPV4_HDRCKSUM) 1106 first_tbd->read.olinfo_status |= 1107 IXGBE_ADVTXD_POPTS_IXSM; 1108 if (hcksum_flags & HCK_PARTIALCKSUM) 1109 first_tbd->read.olinfo_status |= 1110 IXGBE_ADVTXD_POPTS_TXSM; 1111 } 1112 1113 /* 1114 * The last descriptor of packet needs End Of Packet (EOP), 1115 * and Report Status (RS) bits set 1116 */ 1117 ASSERT(tbd != NULL); 1118 tbd->read.cmd_type_len |= 1119 IXGBE_ADVTXD_DCMD_EOP | IXGBE_ADVTXD_DCMD_RS; 1120 1121 /* 1122 * Sync the DMA buffer of the tx descriptor ring 1123 */ 1124 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORDEV); 1125 1126 /* 1127 * Update the number of the free tx descriptors. 1128 * The mutual exclusion between the transmission and the recycling 1129 * (for the tx descriptor ring and the work list) is implemented 1130 * with the atomic operation on the number of the free tx descriptors. 1131 * 1132 * Note: we should always decrement the counter tbd_free before 1133 * advancing the hardware TDT pointer to avoid the race condition - 1134 * before the counter tbd_free is decremented, the transmit of the 1135 * tx descriptors has done and the counter tbd_free is increased by 1136 * the tx recycling. 1137 */ 1138 i = ixgbe_atomic_reserve(&tx_ring->tbd_free, desc_num); 1139 ASSERT(i >= 0); 1140 1141 tx_ring->tbd_tail = index; 1142 1143 /* 1144 * Advance the hardware TDT pointer of the tx descriptor ring 1145 */ 1146 IXGBE_WRITE_REG(hw, IXGBE_TDT(tx_ring->index), index); 1147 1148 if (ixgbe_check_acc_handle(tx_ring->ixgbe->osdep.reg_handle) != 1149 DDI_FM_OK) { 1150 ddi_fm_service_impact(tx_ring->ixgbe->dip, 1151 DDI_SERVICE_DEGRADED); 1152 atomic_or_32(&tx_ring->ixgbe->ixgbe_state, IXGBE_ERROR); 1153 } 1154 1155 return (desc_num); 1156 } 1157 1158 /* 1159 * ixgbe_save_desc 1160 * 1161 * Save the address/length pair to the private array 1162 * of the tx control block. The address/length pairs 1163 * will be filled into the tx descriptor ring later. 1164 */ 1165 static void 1166 ixgbe_save_desc(tx_control_block_t *tcb, uint64_t address, size_t length) 1167 { 1168 sw_desc_t *desc; 1169 1170 desc = &tcb->desc[tcb->desc_num]; 1171 desc->address = address; 1172 desc->length = length; 1173 1174 tcb->desc_num++; 1175 } 1176 1177 /* 1178 * ixgbe_tx_recycle_legacy 1179 * 1180 * Recycle the tx descriptors and tx control blocks. 1181 * 1182 * The work list is traversed to check if the corresponding 1183 * tx descriptors have been transmitted. If so, the resources 1184 * bound to the tx control blocks will be freed, and those 1185 * tx control blocks will be returned to the free list. 1186 */ 1187 uint32_t 1188 ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *tx_ring) 1189 { 1190 uint32_t index, last_index, prev_index; 1191 int desc_num; 1192 boolean_t desc_done; 1193 tx_control_block_t *tcb; 1194 link_list_t pending_list; 1195 ixgbe_t *ixgbe = tx_ring->ixgbe; 1196 1197 mutex_enter(&tx_ring->recycle_lock); 1198 1199 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 1200 1201 if (tx_ring->tbd_free == tx_ring->ring_size) { 1202 tx_ring->recycle_fail = 0; 1203 tx_ring->stall_watchdog = 0; 1204 if (tx_ring->reschedule) { 1205 tx_ring->reschedule = B_FALSE; 1206 mac_tx_ring_update(ixgbe->mac_hdl, 1207 tx_ring->ring_handle); 1208 } 1209 mutex_exit(&tx_ring->recycle_lock); 1210 return (0); 1211 } 1212 1213 /* 1214 * Sync the DMA buffer of the tx descriptor ring 1215 */ 1216 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 1217 1218 if (ixgbe_check_dma_handle(tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 1219 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED); 1220 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR); 1221 return (0); 1222 } 1223 1224 LINK_LIST_INIT(&pending_list); 1225 desc_num = 0; 1226 index = tx_ring->tbd_head; /* Index of next tbd/tcb to recycle */ 1227 1228 tcb = tx_ring->work_list[index]; 1229 ASSERT(tcb != NULL); 1230 1231 while (tcb != NULL) { 1232 /* 1233 * Get the last tx descriptor of this packet. 1234 * If the last tx descriptor is done, then 1235 * we can recycle all descriptors of a packet 1236 * which usually includes several tx control blocks. 1237 * For 82599, LSO descriptors can not be recycled 1238 * unless the whole packet's transmission is done. 1239 * That's why packet level recycling is used here. 1240 * For 82598, there's not such limit. 1241 */ 1242 last_index = tcb->last_index; 1243 /* 1244 * MAX_TX_RING_SIZE is used to judge whether 1245 * the index is a valid value or not. 1246 */ 1247 if (last_index == MAX_TX_RING_SIZE) 1248 break; 1249 1250 /* 1251 * Check if the Descriptor Done bit is set 1252 */ 1253 desc_done = tx_ring->tbd_ring[last_index].wb.status & 1254 IXGBE_TXD_STAT_DD; 1255 if (desc_done) { 1256 /* 1257 * recycle all descriptors of the packet 1258 */ 1259 while (tcb != NULL) { 1260 /* 1261 * Strip off the tx control block from 1262 * the work list, and add it to the 1263 * pending list. 1264 */ 1265 tx_ring->work_list[index] = NULL; 1266 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1267 1268 /* 1269 * Count the total number of the tx 1270 * descriptors recycled 1271 */ 1272 desc_num += tcb->desc_num; 1273 1274 index = NEXT_INDEX(index, tcb->desc_num, 1275 tx_ring->ring_size); 1276 1277 tcb = tx_ring->work_list[index]; 1278 1279 prev_index = PREV_INDEX(index, 1, 1280 tx_ring->ring_size); 1281 if (prev_index == last_index) 1282 break; 1283 } 1284 } else { 1285 break; 1286 } 1287 } 1288 1289 /* 1290 * If no tx descriptors are recycled, no need to do more processing 1291 */ 1292 if (desc_num == 0) { 1293 tx_ring->recycle_fail++; 1294 mutex_exit(&tx_ring->recycle_lock); 1295 return (0); 1296 } 1297 1298 tx_ring->recycle_fail = 0; 1299 tx_ring->stall_watchdog = 0; 1300 1301 /* 1302 * Update the head index of the tx descriptor ring 1303 */ 1304 tx_ring->tbd_head = index; 1305 1306 /* 1307 * Update the number of the free tx descriptors with atomic operations 1308 */ 1309 atomic_add_32(&tx_ring->tbd_free, desc_num); 1310 1311 if ((tx_ring->tbd_free >= ixgbe->tx_resched_thresh) && 1312 (tx_ring->reschedule)) { 1313 tx_ring->reschedule = B_FALSE; 1314 mac_tx_ring_update(ixgbe->mac_hdl, 1315 tx_ring->ring_handle); 1316 } 1317 mutex_exit(&tx_ring->recycle_lock); 1318 1319 /* 1320 * Free the resources used by the tx control blocks 1321 * in the pending list 1322 */ 1323 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 1324 while (tcb != NULL) { 1325 /* 1326 * Release the resources occupied by the tx control block 1327 */ 1328 ixgbe_free_tcb(tcb); 1329 1330 tcb = (tx_control_block_t *) 1331 LIST_GET_NEXT(&pending_list, &tcb->link); 1332 } 1333 1334 /* 1335 * Add the tx control blocks in the pending list to the free list. 1336 */ 1337 ixgbe_put_free_list(tx_ring, &pending_list); 1338 1339 return (desc_num); 1340 } 1341 1342 /* 1343 * ixgbe_tx_recycle_head_wb 1344 * 1345 * Check the head write-back, and recycle all the transmitted 1346 * tx descriptors and tx control blocks. 1347 */ 1348 uint32_t 1349 ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *tx_ring) 1350 { 1351 uint32_t index; 1352 uint32_t head_wb; 1353 int desc_num; 1354 tx_control_block_t *tcb; 1355 link_list_t pending_list; 1356 ixgbe_t *ixgbe = tx_ring->ixgbe; 1357 1358 mutex_enter(&tx_ring->recycle_lock); 1359 1360 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 1361 1362 if (tx_ring->tbd_free == tx_ring->ring_size) { 1363 tx_ring->recycle_fail = 0; 1364 tx_ring->stall_watchdog = 0; 1365 if (tx_ring->reschedule) { 1366 tx_ring->reschedule = B_FALSE; 1367 mac_tx_ring_update(ixgbe->mac_hdl, 1368 tx_ring->ring_handle); 1369 } 1370 mutex_exit(&tx_ring->recycle_lock); 1371 return (0); 1372 } 1373 1374 /* 1375 * Sync the DMA buffer of the tx descriptor ring 1376 * 1377 * Note: For head write-back mode, the tx descriptors will not 1378 * be written back, but the head write-back value is stored at 1379 * the last extra tbd at the end of the DMA area, we still need 1380 * to sync the head write-back value for kernel. 1381 * 1382 * DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 1383 */ 1384 (void) ddi_dma_sync(tx_ring->tbd_area.dma_handle, 1385 sizeof (union ixgbe_adv_tx_desc) * tx_ring->ring_size, 1386 sizeof (uint32_t), 1387 DDI_DMA_SYNC_FORKERNEL); 1388 1389 if (ixgbe_check_dma_handle(tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 1390 ddi_fm_service_impact(ixgbe->dip, 1391 DDI_SERVICE_DEGRADED); 1392 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR); 1393 return (0); 1394 } 1395 1396 LINK_LIST_INIT(&pending_list); 1397 desc_num = 0; 1398 index = tx_ring->tbd_head; /* Next index to clean */ 1399 1400 /* 1401 * Get the value of head write-back 1402 */ 1403 head_wb = *tx_ring->tbd_head_wb; 1404 while (index != head_wb) { 1405 tcb = tx_ring->work_list[index]; 1406 ASSERT(tcb != NULL); 1407 1408 if (OFFSET(index, head_wb, tx_ring->ring_size) < 1409 tcb->desc_num) { 1410 /* 1411 * The current tx control block is not 1412 * completely transmitted, stop recycling 1413 */ 1414 break; 1415 } 1416 1417 /* 1418 * Strip off the tx control block from the work list, 1419 * and add it to the pending list. 1420 */ 1421 tx_ring->work_list[index] = NULL; 1422 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1423 1424 /* 1425 * Advance the index of the tx descriptor ring 1426 */ 1427 index = NEXT_INDEX(index, tcb->desc_num, tx_ring->ring_size); 1428 1429 /* 1430 * Count the total number of the tx descriptors recycled 1431 */ 1432 desc_num += tcb->desc_num; 1433 } 1434 1435 /* 1436 * If no tx descriptors are recycled, no need to do more processing 1437 */ 1438 if (desc_num == 0) { 1439 tx_ring->recycle_fail++; 1440 mutex_exit(&tx_ring->recycle_lock); 1441 return (0); 1442 } 1443 1444 tx_ring->recycle_fail = 0; 1445 tx_ring->stall_watchdog = 0; 1446 1447 /* 1448 * Update the head index of the tx descriptor ring 1449 */ 1450 tx_ring->tbd_head = index; 1451 1452 /* 1453 * Update the number of the free tx descriptors with atomic operations 1454 */ 1455 atomic_add_32(&tx_ring->tbd_free, desc_num); 1456 1457 if ((tx_ring->tbd_free >= ixgbe->tx_resched_thresh) && 1458 (tx_ring->reschedule)) { 1459 tx_ring->reschedule = B_FALSE; 1460 mac_tx_ring_update(ixgbe->mac_hdl, 1461 tx_ring->ring_handle); 1462 } 1463 mutex_exit(&tx_ring->recycle_lock); 1464 1465 /* 1466 * Free the resources used by the tx control blocks 1467 * in the pending list 1468 */ 1469 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 1470 while (tcb) { 1471 /* 1472 * Release the resources occupied by the tx control block 1473 */ 1474 ixgbe_free_tcb(tcb); 1475 1476 tcb = (tx_control_block_t *) 1477 LIST_GET_NEXT(&pending_list, &tcb->link); 1478 } 1479 1480 /* 1481 * Add the tx control blocks in the pending list to the free list. 1482 */ 1483 ixgbe_put_free_list(tx_ring, &pending_list); 1484 1485 return (desc_num); 1486 } 1487 1488 /* 1489 * ixgbe_free_tcb - free up the tx control block 1490 * 1491 * Free the resources of the tx control block, including 1492 * unbind the previously bound DMA handle, and reset other 1493 * control fields. 1494 */ 1495 void 1496 ixgbe_free_tcb(tx_control_block_t *tcb) 1497 { 1498 switch (tcb->tx_type) { 1499 case USE_COPY: 1500 /* 1501 * Reset the buffer length that is used for copy 1502 */ 1503 tcb->tx_buf.len = 0; 1504 break; 1505 case USE_DMA: 1506 /* 1507 * Release the DMA resource that is used for 1508 * DMA binding. 1509 */ 1510 (void) ddi_dma_unbind_handle(tcb->tx_dma_handle); 1511 break; 1512 default: 1513 break; 1514 } 1515 1516 /* 1517 * Free the mblk 1518 */ 1519 if (tcb->mp != NULL) { 1520 freemsg(tcb->mp); 1521 tcb->mp = NULL; 1522 } 1523 1524 tcb->tx_type = USE_NONE; 1525 tcb->last_index = MAX_TX_RING_SIZE; 1526 tcb->frag_num = 0; 1527 tcb->desc_num = 0; 1528 } 1529 1530 /* 1531 * ixgbe_get_free_list - Get a free tx control block from the free list 1532 * 1533 * The atomic operation on the number of the available tx control block 1534 * in the free list is used to keep this routine mutual exclusive with 1535 * the routine ixgbe_put_check_list. 1536 */ 1537 static tx_control_block_t * 1538 ixgbe_get_free_list(ixgbe_tx_ring_t *tx_ring) 1539 { 1540 tx_control_block_t *tcb; 1541 1542 /* 1543 * Check and update the number of the free tx control block 1544 * in the free list. 1545 */ 1546 if (ixgbe_atomic_reserve(&tx_ring->tcb_free, 1) < 0) 1547 return (NULL); 1548 1549 mutex_enter(&tx_ring->tcb_head_lock); 1550 1551 tcb = tx_ring->free_list[tx_ring->tcb_head]; 1552 ASSERT(tcb != NULL); 1553 tx_ring->free_list[tx_ring->tcb_head] = NULL; 1554 tx_ring->tcb_head = NEXT_INDEX(tx_ring->tcb_head, 1, 1555 tx_ring->free_list_size); 1556 1557 mutex_exit(&tx_ring->tcb_head_lock); 1558 1559 return (tcb); 1560 } 1561 1562 /* 1563 * ixgbe_put_free_list 1564 * 1565 * Put a list of used tx control blocks back to the free list 1566 * 1567 * A mutex is used here to ensure the serialization. The mutual exclusion 1568 * between ixgbe_get_free_list and ixgbe_put_free_list is implemented with 1569 * the atomic operation on the counter tcb_free. 1570 */ 1571 void 1572 ixgbe_put_free_list(ixgbe_tx_ring_t *tx_ring, link_list_t *pending_list) 1573 { 1574 uint32_t index; 1575 int tcb_num; 1576 tx_control_block_t *tcb; 1577 1578 mutex_enter(&tx_ring->tcb_tail_lock); 1579 1580 index = tx_ring->tcb_tail; 1581 1582 tcb_num = 0; 1583 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1584 while (tcb != NULL) { 1585 ASSERT(tx_ring->free_list[index] == NULL); 1586 tx_ring->free_list[index] = tcb; 1587 1588 tcb_num++; 1589 1590 index = NEXT_INDEX(index, 1, tx_ring->free_list_size); 1591 1592 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1593 } 1594 1595 tx_ring->tcb_tail = index; 1596 1597 /* 1598 * Update the number of the free tx control block 1599 * in the free list. This operation must be placed 1600 * under the protection of the lock. 1601 */ 1602 atomic_add_32(&tx_ring->tcb_free, tcb_num); 1603 1604 mutex_exit(&tx_ring->tcb_tail_lock); 1605 } 1606