1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_SW_H 29 #define _IXGBE_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/bitmap.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/disp.h> 71 #include <sys/fm/io/ddi.h> 72 #include "ixgbe_api.h" 73 74 #define MODULE_NAME "ixgbe" /* module name */ 75 76 #define IXGBE_FAILURE DDI_FAILURE 77 78 #define IXGBE_UNKNOWN 0x00 79 #define IXGBE_INITIALIZED 0x01 80 #define IXGBE_STARTED 0x02 81 #define IXGBE_SUSPENDED 0x04 82 #define IXGBE_STALL 0x08 83 #define IXGBE_ERROR 0x80 84 85 #define MAX_NUM_UNICAST_ADDRESSES 0x10 86 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 87 #define IXGBE_INTR_NONE 0 88 #define IXGBE_INTR_MSIX 1 89 #define IXGBE_INTR_MSI 2 90 #define IXGBE_INTR_LEGACY 3 91 92 #define IXGBE_POLL_NULL -1 93 94 #define MAX_COOKIE 18 95 #define MIN_NUM_TX_DESC 2 96 97 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 98 99 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 100 101 #define IXGBE_RX_STOPPED 0x1 102 103 #define IXGBE_PKG_BUF_16k 16384 104 105 /* 106 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 107 * supported silicon types. 108 */ 109 #define MAX_TX_QUEUE_NUM 128 110 #define MAX_RX_QUEUE_NUM 128 111 #define MAX_INTR_VECTOR 64 112 113 /* 114 * Maximum values for user configurable parameters 115 */ 116 #define MAX_RX_GROUP_NUM 1 117 #define MAX_TX_RING_SIZE 4096 118 #define MAX_RX_RING_SIZE 4096 119 120 #define MAX_RX_LIMIT_PER_INTR 4096 121 122 #define MAX_RX_COPY_THRESHOLD 9216 123 #define MAX_TX_COPY_THRESHOLD 9216 124 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 127 128 /* 129 * Minimum values for user configurable parameters 130 */ 131 #define MIN_RX_GROUP_NUM 1 132 #define MIN_TX_RING_SIZE 64 133 #define MIN_RX_RING_SIZE 64 134 135 #define MIN_MTU ETHERMIN 136 #define MIN_RX_LIMIT_PER_INTR 16 137 #define MIN_TX_COPY_THRESHOLD 0 138 #define MIN_RX_COPY_THRESHOLD 0 139 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 140 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 141 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 142 143 /* 144 * Default values for user configurable parameters 145 */ 146 #define DEFAULT_RX_GROUP_NUM 1 147 #define DEFAULT_TX_RING_SIZE 1024 148 #define DEFAULT_RX_RING_SIZE 1024 149 150 #define DEFAULT_MTU ETHERMTU 151 #define DEFAULT_RX_LIMIT_PER_INTR 256 152 #define DEFAULT_RX_COPY_THRESHOLD 128 153 #define DEFAULT_TX_COPY_THRESHOLD 512 154 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 155 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 156 #define DEFAULT_TX_RESCHED_THRESHOLD 128 157 #define DEFAULT_FCRTH 0x20000 158 #define DEFAULT_FCRTL 0x10000 159 #define DEFAULT_FCPAUSE 0xFFFF 160 161 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 162 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 163 #define DEFAULT_LSO_ENABLE B_TRUE 164 #define DEFAULT_LRO_ENABLE B_FALSE 165 #define DEFAULT_MR_ENABLE B_TRUE 166 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 167 168 #define IXGBE_LSO_MAXLEN 65535 169 170 #define TX_DRAIN_TIME 200 171 #define RX_DRAIN_TIME 200 172 173 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 174 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 175 176 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 177 178 /* 179 * Extra register bit masks for 82598 180 */ 181 #define IXGBE_PCS1GANA_FDC 0x20 182 #define IXGBE_PCS1GANLP_LPFD 0x20 183 #define IXGBE_PCS1GANLP_LPHD 0x40 184 185 /* 186 * Defined for IP header alignment. 187 */ 188 #define IPHDR_ALIGN_ROOM 2 189 190 /* 191 * Bit flags for attach_progress 192 */ 193 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 194 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 195 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 196 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 197 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 198 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 199 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 200 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 201 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 202 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 203 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 204 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 205 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 206 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 207 208 #define PROP_DEFAULT_MTU "default_mtu" 209 #define PROP_FLOW_CONTROL "flow_control" 210 #define PROP_TX_QUEUE_NUM "tx_queue_number" 211 #define PROP_TX_RING_SIZE "tx_ring_size" 212 #define PROP_RX_QUEUE_NUM "rx_queue_number" 213 #define PROP_RX_RING_SIZE "rx_ring_size" 214 #define PROP_RX_GROUP_NUM "rx_group_number" 215 216 #define PROP_INTR_FORCE "intr_force" 217 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 218 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 219 #define PROP_LSO_ENABLE "lso_enable" 220 #define PROP_LRO_ENABLE "lro_enable" 221 #define PROP_MR_ENABLE "mr_enable" 222 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 223 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 224 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 225 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 226 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 227 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 228 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 229 #define PROP_INTR_THROTTLING "intr_throttling" 230 #define PROP_FM_CAPABLE "fm_capable" 231 232 #define IXGBE_LB_NONE 0 233 #define IXGBE_LB_EXTERNAL 1 234 #define IXGBE_LB_INTERNAL_MAC 2 235 #define IXGBE_LB_INTERNAL_PHY 3 236 #define IXGBE_LB_INTERNAL_SERDES 4 237 238 /* 239 * capability/feature flags 240 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 241 * Separately, the flag named _ENABLED is set when the feature is enabled. 242 */ 243 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 244 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 245 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 246 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 247 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 248 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 249 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 250 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 251 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 252 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 253 254 /* adapter-specific info for each supported device type */ 255 typedef struct adapter_info { 256 uint32_t max_rx_que_num; /* maximum number of rx queues */ 257 uint32_t min_rx_que_num; /* minimum number of rx queues */ 258 uint32_t def_rx_que_num; /* default number of rx queues */ 259 uint32_t max_tx_que_num; /* maximum number of tx queues */ 260 uint32_t min_tx_que_num; /* minimum number of tx queues */ 261 uint32_t def_tx_que_num; /* default number of tx queues */ 262 uint32_t max_mtu; /* maximum MTU size */ 263 /* 264 * Interrupt throttling is in unit of 256 nsec 265 */ 266 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 267 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 268 uint32_t def_intr_throttle; /* default interrupt throttle */ 269 270 uint32_t max_msix_vect; /* maximum total msix vectors */ 271 uint32_t max_ring_vect; /* maximum number of ring vectors */ 272 uint32_t max_other_vect; /* maximum number of other vectors */ 273 uint32_t other_intr; /* "other" interrupt types handled */ 274 uint32_t flags; /* capability flags */ 275 } adapter_info_t; 276 277 /* bits representing all interrupt types other than tx & rx */ 278 #define IXGBE_OTHER_INTR 0x3ff00000 279 #define IXGBE_82599_OTHER_INTR 0x86100000 280 281 enum ioc_reply { 282 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 283 IOC_DONE, /* OK, reply sent */ 284 IOC_ACK, /* OK, just send ACK */ 285 IOC_REPLY /* OK, just send reply */ 286 }; 287 288 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 289 0, 0, (flag))) 290 291 /* 292 * Defined for ring index operations 293 * ASSERT(index < limit) 294 * ASSERT(step < limit) 295 * ASSERT(index1 < limit) 296 * ASSERT(index2 < limit) 297 */ 298 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 299 (index) + (step) : (index) + (step) - (limit)) 300 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 301 (index) - (step) : (index) + (limit) - (step)) 302 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 303 (index2) - (index1) : (index2) + (limit) - (index1)) 304 305 #define LINK_LIST_INIT(_LH) \ 306 (_LH)->head = (_LH)->tail = NULL 307 308 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 309 310 #define LIST_POP_HEAD(_LH) \ 311 (single_link_t *)(_LH)->head; \ 312 { \ 313 if ((_LH)->head != NULL) { \ 314 (_LH)->head = (_LH)->head->link; \ 315 if ((_LH)->head == NULL) \ 316 (_LH)->tail = NULL; \ 317 } \ 318 } 319 320 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 321 322 #define LIST_PUSH_TAIL(_LH, _E) \ 323 if ((_LH)->tail != NULL) { \ 324 (_LH)->tail->link = (single_link_t *)(_E); \ 325 (_LH)->tail = (single_link_t *)(_E); \ 326 } else { \ 327 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 328 } \ 329 (_E)->link = NULL; 330 331 #define LIST_GET_NEXT(_LH, _E) \ 332 (((_LH)->tail == (single_link_t *)(_E)) ? \ 333 NULL : ((single_link_t *)(_E))->link) 334 335 336 typedef struct single_link { 337 struct single_link *link; 338 } single_link_t; 339 340 typedef struct link_list { 341 single_link_t *head; 342 single_link_t *tail; 343 } link_list_t; 344 345 /* 346 * Property lookups 347 */ 348 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 349 DDI_PROP_DONTPASS, (n)) 350 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 351 DDI_PROP_DONTPASS, (n), -1) 352 353 354 typedef union ixgbe_ether_addr { 355 struct { 356 uint32_t high; 357 uint32_t low; 358 } reg; 359 struct { 360 uint8_t set; 361 uint8_t redundant; 362 uint8_t addr[ETHERADDRL]; 363 } mac; 364 } ixgbe_ether_addr_t; 365 366 typedef enum { 367 USE_NONE, 368 USE_COPY, 369 USE_DMA 370 } tx_type_t; 371 372 typedef struct ixgbe_tx_context { 373 uint32_t hcksum_flags; 374 uint32_t ip_hdr_len; 375 uint32_t mac_hdr_len; 376 uint32_t l4_proto; 377 uint32_t mss; 378 uint32_t l4_hdr_len; 379 boolean_t lso_flag; 380 } ixgbe_tx_context_t; 381 382 /* 383 * Hold address/length of each DMA segment 384 */ 385 typedef struct sw_desc { 386 uint64_t address; 387 size_t length; 388 } sw_desc_t; 389 390 /* 391 * Handles and addresses of DMA buffer 392 */ 393 typedef struct dma_buffer { 394 caddr_t address; /* Virtual address */ 395 uint64_t dma_address; /* DMA (Hardware) address */ 396 ddi_acc_handle_t acc_handle; /* Data access handle */ 397 ddi_dma_handle_t dma_handle; /* DMA handle */ 398 size_t size; /* Buffer size */ 399 size_t len; /* Data length in the buffer */ 400 } dma_buffer_t; 401 402 /* 403 * Tx Control Block 404 */ 405 typedef struct tx_control_block { 406 single_link_t link; 407 uint32_t last_index; /* last descriptor of the pkt */ 408 uint32_t frag_num; 409 uint32_t desc_num; 410 mblk_t *mp; 411 tx_type_t tx_type; 412 ddi_dma_handle_t tx_dma_handle; 413 dma_buffer_t tx_buf; 414 sw_desc_t desc[MAX_COOKIE]; 415 } tx_control_block_t; 416 417 /* 418 * RX Control Block 419 */ 420 typedef struct rx_control_block { 421 mblk_t *mp; 422 uint32_t ref_cnt; 423 dma_buffer_t rx_buf; 424 frtn_t free_rtn; 425 struct ixgbe_rx_data *rx_data; 426 int lro_next; /* Index of next rcb */ 427 int lro_prev; /* Index of previous rcb */ 428 boolean_t lro_pkt; /* Flag for LRO rcb */ 429 } rx_control_block_t; 430 431 /* 432 * Software Data Structure for Tx Ring 433 */ 434 typedef struct ixgbe_tx_ring { 435 uint32_t index; /* Ring index */ 436 uint32_t intr_vector; /* Interrupt vector index */ 437 uint32_t vect_bit; /* vector's bit in register */ 438 439 /* 440 * Mutexes 441 */ 442 kmutex_t tx_lock; 443 kmutex_t recycle_lock; 444 kmutex_t tcb_head_lock; 445 kmutex_t tcb_tail_lock; 446 447 /* 448 * Tx descriptor ring definitions 449 */ 450 dma_buffer_t tbd_area; 451 union ixgbe_adv_tx_desc *tbd_ring; 452 uint32_t tbd_head; /* Index of next tbd to recycle */ 453 uint32_t tbd_tail; /* Index of next tbd to transmit */ 454 uint32_t tbd_free; /* Number of free tbd */ 455 456 /* 457 * Tx control block list definitions 458 */ 459 tx_control_block_t *tcb_area; 460 tx_control_block_t **work_list; 461 tx_control_block_t **free_list; 462 uint32_t tcb_head; /* Head index of free list */ 463 uint32_t tcb_tail; /* Tail index of free list */ 464 uint32_t tcb_free; /* Number of free tcb in free list */ 465 466 uint32_t *tbd_head_wb; /* Head write-back */ 467 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 468 469 /* 470 * s/w context structure for TCP/UDP checksum offload 471 * and LSO. 472 */ 473 ixgbe_tx_context_t tx_context; 474 475 /* 476 * Tx ring settings and status 477 */ 478 uint32_t ring_size; /* Tx descriptor ring size */ 479 uint32_t free_list_size; /* Tx free list size */ 480 481 boolean_t reschedule; 482 uint32_t recycle_fail; 483 uint32_t stall_watchdog; 484 485 #ifdef IXGBE_DEBUG 486 /* 487 * Debug statistics 488 */ 489 uint32_t stat_overload; 490 uint32_t stat_fail_no_tbd; 491 uint32_t stat_fail_no_tcb; 492 uint32_t stat_fail_dma_bind; 493 uint32_t stat_reschedule; 494 uint32_t stat_break_tbd_limit; 495 uint32_t stat_lso_header_fail; 496 #endif 497 498 mac_ring_handle_t ring_handle; 499 500 /* 501 * Pointer to the ixgbe struct 502 */ 503 struct ixgbe *ixgbe; 504 } ixgbe_tx_ring_t; 505 506 /* 507 * Software Receive Ring 508 */ 509 typedef struct ixgbe_rx_data { 510 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 511 512 /* 513 * Rx descriptor ring definitions 514 */ 515 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 516 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 517 uint32_t rbd_next; /* Index of next rx desc */ 518 519 /* 520 * Rx control block list definitions 521 */ 522 rx_control_block_t *rcb_area; 523 rx_control_block_t **work_list; /* Work list of rcbs */ 524 rx_control_block_t **free_list; /* Free list of rcbs */ 525 uint32_t rcb_head; /* Index of next free rcb */ 526 uint32_t rcb_tail; /* Index to put recycled rcb */ 527 uint32_t rcb_free; /* Number of free rcbs */ 528 529 /* 530 * Rx sw ring settings and status 531 */ 532 uint32_t ring_size; /* Rx descriptor ring size */ 533 uint32_t free_list_size; /* Rx free list size */ 534 535 uint32_t rcb_pending; 536 uint32_t flag; 537 538 uint32_t lro_num; /* Number of rcbs of one LRO */ 539 uint32_t lro_first; /* Index of first LRO rcb */ 540 541 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 542 } ixgbe_rx_data_t; 543 544 /* 545 * Software Data Structure for Rx Ring 546 */ 547 typedef struct ixgbe_rx_ring { 548 uint32_t index; /* Ring index */ 549 uint32_t intr_vector; /* Interrupt vector index */ 550 uint32_t vect_bit; /* vector's bit in register */ 551 552 ixgbe_rx_data_t *rx_data; /* Rx software ring */ 553 554 kmutex_t rx_lock; /* Rx access lock */ 555 556 #ifdef IXGBE_DEBUG 557 /* 558 * Debug statistics 559 */ 560 uint32_t stat_frame_error; 561 uint32_t stat_cksum_error; 562 uint32_t stat_exceed_pkt; 563 #endif 564 565 mac_ring_handle_t ring_handle; 566 uint64_t ring_gen_num; 567 568 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 569 } ixgbe_rx_ring_t; 570 /* 571 * Software Receive Ring Group 572 */ 573 typedef struct ixgbe_rx_group { 574 uint32_t index; /* Group index */ 575 mac_group_handle_t group_handle; /* call back group handle */ 576 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 577 } ixgbe_rx_group_t; 578 579 /* 580 * structure to map interrupt cleanup to msi-x vector 581 */ 582 typedef struct ixgbe_intr_vector { 583 struct ixgbe *ixgbe; /* point to my adapter */ 584 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 585 int rxr_cnt; /* count rx rings */ 586 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 587 int txr_cnt; /* count tx rings */ 588 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 589 int other_cnt; /* count other interrupt */ 590 } ixgbe_intr_vector_t; 591 592 /* 593 * Software adapter state 594 */ 595 typedef struct ixgbe { 596 int instance; 597 mac_handle_t mac_hdl; 598 dev_info_t *dip; 599 struct ixgbe_hw hw; 600 struct ixgbe_osdep osdep; 601 602 adapter_info_t *capab; /* adapter hardware capabilities */ 603 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 604 uint32_t eims; /* interrupt mask setting */ 605 uint32_t eimc; /* interrupt mask clear */ 606 uint32_t eicr; /* interrupt cause reg */ 607 608 uint32_t ixgbe_state; 609 link_state_t link_state; 610 uint32_t link_speed; 611 uint32_t link_duplex; 612 613 uint32_t reset_count; 614 uint32_t attach_progress; 615 uint32_t loopback_mode; 616 uint32_t default_mtu; 617 uint32_t max_frame_size; 618 619 uint32_t rcb_pending; 620 621 /* 622 * Each msi-x vector: map vector to interrupt cleanup 623 */ 624 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 625 626 /* 627 * Receive Rings 628 */ 629 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 630 uint32_t num_rx_rings; /* Number of rx rings in use */ 631 uint32_t rx_ring_size; /* Rx descriptor ring size */ 632 uint32_t rx_buf_size; /* Rx buffer size */ 633 boolean_t lro_enable; /* Large Receive Offload */ 634 uint64_t lro_pkt_count; /* LRO packet count */ 635 /* 636 * Receive Groups 637 */ 638 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 639 uint32_t num_rx_groups; /* Number of rx groups in use */ 640 641 /* 642 * Transmit Rings 643 */ 644 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 645 uint32_t num_tx_rings; /* Number of tx rings in use */ 646 uint32_t tx_ring_size; /* Tx descriptor ring size */ 647 uint32_t tx_buf_size; /* Tx buffer size */ 648 649 boolean_t tx_ring_init; 650 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 651 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 652 boolean_t lso_enable; /* Large Segment Offload */ 653 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 654 uint32_t tx_copy_thresh; /* Tx copy threshold */ 655 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 656 uint32_t tx_overload_thresh; /* Tx overload threshold */ 657 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 658 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 659 uint32_t rx_copy_thresh; /* Rx copy threshold */ 660 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 661 uint32_t intr_throttling[MAX_INTR_VECTOR]; 662 uint32_t intr_force; 663 int fm_capabilities; /* FMA capabilities */ 664 665 int intr_type; 666 int intr_cnt; 667 int intr_cap; 668 size_t intr_size; 669 uint_t intr_pri; 670 ddi_intr_handle_t *htable; 671 uint32_t eims_mask; 672 673 kmutex_t gen_lock; /* General lock for device access */ 674 kmutex_t watchdog_lock; 675 kmutex_t rx_pending_lock; 676 677 boolean_t watchdog_enable; 678 boolean_t watchdog_start; 679 timeout_id_t watchdog_tid; 680 681 boolean_t unicst_init; 682 uint32_t unicst_avail; 683 uint32_t unicst_total; 684 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 685 uint32_t mcast_count; 686 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 687 688 ulong_t sys_page_size; 689 690 boolean_t link_check_complete; 691 hrtime_t link_check_hrtime; 692 ddi_periodic_t periodic_id; /* for link check timer func */ 693 694 /* 695 * Kstat definitions 696 */ 697 kstat_t *ixgbe_ks; 698 699 uint32_t param_en_10000fdx_cap:1, 700 param_en_1000fdx_cap:1, 701 param_en_100fdx_cap:1, 702 param_adv_10000fdx_cap:1, 703 param_adv_1000fdx_cap:1, 704 param_adv_100fdx_cap:1, 705 param_pause_cap:1, 706 param_asym_pause_cap:1, 707 param_rem_fault:1, 708 param_adv_autoneg_cap:1, 709 param_adv_pause_cap:1, 710 param_adv_asym_pause_cap:1, 711 param_adv_rem_fault:1, 712 param_lp_10000fdx_cap:1, 713 param_lp_1000fdx_cap:1, 714 param_lp_100fdx_cap:1, 715 param_lp_autoneg_cap:1, 716 param_lp_pause_cap:1, 717 param_lp_asym_pause_cap:1, 718 param_lp_rem_fault:1, 719 param_pad_to_32:12; 720 } ixgbe_t; 721 722 typedef struct ixgbe_stat { 723 kstat_named_t link_speed; /* Link Speed */ 724 725 kstat_named_t reset_count; /* Reset Count */ 726 727 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 728 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 729 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 730 731 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 732 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 733 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 734 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 735 kstat_named_t tx_reschedule; /* Tx Reschedule */ 736 737 kstat_named_t gprc; /* Good Packets Received Count */ 738 kstat_named_t gptc; /* Good Packets Xmitted Count */ 739 kstat_named_t gor; /* Good Octets Received Count */ 740 kstat_named_t got; /* Good Octets Xmitd Count */ 741 kstat_named_t prc64; /* Packets Received - 64b */ 742 kstat_named_t prc127; /* Packets Received - 65-127b */ 743 kstat_named_t prc255; /* Packets Received - 127-255b */ 744 kstat_named_t prc511; /* Packets Received - 256-511b */ 745 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 746 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 747 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 748 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 749 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 750 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 751 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 752 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 753 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 754 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 755 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 756 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 757 758 kstat_named_t crcerrs; /* CRC Error Count */ 759 kstat_named_t illerrc; /* Illegal Byte Error Count */ 760 kstat_named_t errbc; /* Error Byte Count */ 761 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 762 kstat_named_t mpc; /* Missed Packets Count */ 763 kstat_named_t mlfc; /* MAC Local Fault Count */ 764 kstat_named_t mrfc; /* MAC Remote Fault Count */ 765 kstat_named_t rlec; /* Receive Length Error Count */ 766 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 767 kstat_named_t lxonrxc; /* Link XON Received Count */ 768 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 769 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 770 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 771 kstat_named_t mprc; /* Multicast Pkts Received Count */ 772 kstat_named_t rnbc; /* Receive No Buffers Count */ 773 kstat_named_t ruc; /* Receive Undersize Count */ 774 kstat_named_t rfc; /* Receive Frag Count */ 775 kstat_named_t roc; /* Receive Oversize Count */ 776 kstat_named_t rjc; /* Receive Jabber Count */ 777 kstat_named_t tor; /* Total Octets Recvd Count */ 778 kstat_named_t tot; /* Total Octets Xmitted Count */ 779 kstat_named_t tpr; /* Total Packets Received */ 780 kstat_named_t tpt; /* Total Packets Xmitted */ 781 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 782 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 783 kstat_named_t lroc; /* LRO Packets Received Count */ 784 } ixgbe_stat_t; 785 786 /* 787 * Function prototypes in ixgbe_buf.c 788 */ 789 int ixgbe_alloc_dma(ixgbe_t *); 790 void ixgbe_free_dma(ixgbe_t *); 791 void ixgbe_set_fma_flags(int); 792 void ixgbe_free_dma_buffer(dma_buffer_t *); 793 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 794 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 795 796 /* 797 * Function prototypes in ixgbe_main.c 798 */ 799 int ixgbe_start(ixgbe_t *, boolean_t); 800 void ixgbe_stop(ixgbe_t *, boolean_t); 801 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 802 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 803 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 804 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 805 806 void ixgbe_enable_watchdog_timer(ixgbe_t *); 807 void ixgbe_disable_watchdog_timer(ixgbe_t *); 808 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 809 810 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 811 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 812 void ixgbe_fm_ereport(ixgbe_t *, char *); 813 814 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 815 mac_ring_info_t *, mac_ring_handle_t); 816 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 817 mac_group_info_t *, mac_group_handle_t); 818 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 819 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 820 821 /* 822 * Function prototypes in ixgbe_gld.c 823 */ 824 int ixgbe_m_start(void *); 825 void ixgbe_m_stop(void *); 826 int ixgbe_m_promisc(void *, boolean_t); 827 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 828 int ixgbe_m_stat(void *, uint_t, uint64_t *); 829 void ixgbe_m_resources(void *); 830 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 831 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 832 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 833 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, 834 uint_t, uint_t, void *, uint_t *); 835 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 836 int ixgbe_get_priv_prop(ixgbe_t *, const char *, 837 uint_t, uint_t, void *, uint_t *); 838 boolean_t ixgbe_param_locked(mac_prop_id_t); 839 840 /* 841 * Function prototypes in ixgbe_rx.c 842 */ 843 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 844 void ixgbe_rx_recycle(caddr_t arg); 845 mblk_t *ixgbe_ring_rx_poll(void *, int); 846 847 /* 848 * Function prototypes in ixgbe_tx.c 849 */ 850 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 851 void ixgbe_free_tcb(tx_control_block_t *); 852 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 853 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 854 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 855 856 /* 857 * Function prototypes in ixgbe_log.c 858 */ 859 void ixgbe_notice(void *, const char *, ...); 860 void ixgbe_log(void *, const char *, ...); 861 void ixgbe_error(void *, const char *, ...); 862 863 /* 864 * Function prototypes in ixgbe_stat.c 865 */ 866 int ixgbe_init_stats(ixgbe_t *); 867 868 #ifdef __cplusplus 869 } 870 #endif 871 872 #endif /* _IXGBE_SW_H */ 873