1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_SW_H 29 #define _IXGBE_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/bitmap.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/disp.h> 71 #include <sys/fm/io/ddi.h> 72 #include "ixgbe_api.h" 73 74 #define MODULE_NAME "ixgbe" /* module name */ 75 76 #define IXGBE_FAILURE DDI_FAILURE 77 78 #define IXGBE_UNKNOWN 0x00 79 #define IXGBE_INITIALIZED 0x01 80 #define IXGBE_STARTED 0x02 81 #define IXGBE_SUSPENDED 0x04 82 #define IXGBE_STALL 0x08 83 #define IXGBE_INTR_ADJUST 0x40 84 #define IXGBE_ERROR 0x80 85 86 #define MAX_NUM_UNICAST_ADDRESSES 0x80 87 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 88 #define IXGBE_INTR_NONE 0 89 #define IXGBE_INTR_MSIX 1 90 #define IXGBE_INTR_MSI 2 91 #define IXGBE_INTR_LEGACY 3 92 93 #define IXGBE_POLL_NULL -1 94 95 #define MAX_COOKIE 18 96 #define MIN_NUM_TX_DESC 2 97 98 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 99 100 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 101 102 #define IXGBE_RX_STOPPED 0x1 103 104 #define IXGBE_PKG_BUF_16k 16384 105 106 /* 107 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 108 * supported silicon types. 109 */ 110 #define MAX_TX_QUEUE_NUM 128 111 #define MAX_RX_QUEUE_NUM 128 112 #define MAX_INTR_VECTOR 64 113 #define MAX_RX_GROUP_NUM 64 114 115 /* 116 * Maximum values for user configurable parameters 117 */ 118 #define MAX_TX_RING_SIZE 4096 119 #define MAX_RX_RING_SIZE 4096 120 121 #define MAX_RX_LIMIT_PER_INTR 4096 122 123 #define MAX_RX_COPY_THRESHOLD 9216 124 #define MAX_TX_COPY_THRESHOLD 9216 125 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 127 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 128 129 /* 130 * Minimum values for user configurable parameters 131 */ 132 #define MIN_TX_RING_SIZE 64 133 #define MIN_RX_RING_SIZE 64 134 135 #define MIN_MTU ETHERMIN 136 #define MIN_RX_LIMIT_PER_INTR 16 137 #define MIN_TX_COPY_THRESHOLD 0 138 #define MIN_RX_COPY_THRESHOLD 0 139 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 140 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 141 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 142 143 /* 144 * Default values for user configurable parameters 145 */ 146 #define DEFAULT_TX_RING_SIZE 1024 147 #define DEFAULT_RX_RING_SIZE 1024 148 149 #define DEFAULT_MTU ETHERMTU 150 #define DEFAULT_RX_LIMIT_PER_INTR 256 151 #define DEFAULT_RX_COPY_THRESHOLD 128 152 #define DEFAULT_TX_COPY_THRESHOLD 512 153 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 154 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 155 #define DEFAULT_TX_RESCHED_THRESHOLD 128 156 #define DEFAULT_FCRTH 0x20000 157 #define DEFAULT_FCRTL 0x10000 158 #define DEFAULT_FCPAUSE 0xFFFF 159 160 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 161 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 162 #define DEFAULT_LSO_ENABLE B_TRUE 163 #define DEFAULT_LRO_ENABLE B_FALSE 164 #define DEFAULT_MR_ENABLE B_TRUE 165 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 166 167 #define IXGBE_LSO_MAXLEN 65535 168 169 #define TX_DRAIN_TIME 200 170 #define RX_DRAIN_TIME 200 171 172 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 173 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 174 175 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 176 177 /* 178 * Extra register bit masks for 82598 179 */ 180 #define IXGBE_PCS1GANA_FDC 0x20 181 #define IXGBE_PCS1GANLP_LPFD 0x20 182 #define IXGBE_PCS1GANLP_LPHD 0x40 183 184 /* 185 * Defined for IP header alignment. 186 */ 187 #define IPHDR_ALIGN_ROOM 2 188 189 /* 190 * Bit flags for attach_progress 191 */ 192 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 193 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 194 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 195 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 196 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 197 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 198 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 199 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 200 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 201 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 202 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 203 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 204 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 205 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 206 207 #define PROP_DEFAULT_MTU "default_mtu" 208 #define PROP_FLOW_CONTROL "flow_control" 209 #define PROP_TX_QUEUE_NUM "tx_queue_number" 210 #define PROP_TX_RING_SIZE "tx_ring_size" 211 #define PROP_RX_QUEUE_NUM "rx_queue_number" 212 #define PROP_RX_RING_SIZE "rx_ring_size" 213 #define PROP_RX_GROUP_NUM "rx_group_number" 214 215 #define PROP_INTR_FORCE "intr_force" 216 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 217 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 218 #define PROP_LSO_ENABLE "lso_enable" 219 #define PROP_LRO_ENABLE "lro_enable" 220 #define PROP_MR_ENABLE "mr_enable" 221 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 222 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 223 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 224 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 225 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 226 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 227 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 228 #define PROP_INTR_THROTTLING "intr_throttling" 229 #define PROP_FM_CAPABLE "fm_capable" 230 231 #define IXGBE_LB_NONE 0 232 #define IXGBE_LB_EXTERNAL 1 233 #define IXGBE_LB_INTERNAL_MAC 2 234 #define IXGBE_LB_INTERNAL_PHY 3 235 #define IXGBE_LB_INTERNAL_SERDES 4 236 237 /* 238 * capability/feature flags 239 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 240 * Separately, the flag named _ENABLED is set when the feature is enabled. 241 */ 242 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 243 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 244 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 245 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 246 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 247 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 248 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 249 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 250 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 251 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 252 253 /* 254 * Classification mode 255 */ 256 #define IXGBE_CLASSIFY_NONE 0 257 #define IXGBE_CLASSIFY_RSS 1 258 #define IXGBE_CLASSIFY_VMDQ 2 259 #define IXGBE_CLASSIFY_VMDQ_RSS 3 260 261 /* adapter-specific info for each supported device type */ 262 typedef struct adapter_info { 263 uint32_t max_rx_que_num; /* maximum number of rx queues */ 264 uint32_t min_rx_que_num; /* minimum number of rx queues */ 265 uint32_t def_rx_que_num; /* default number of rx queues */ 266 uint32_t max_rx_grp_num; /* maximum number of rx groups */ 267 uint32_t min_rx_grp_num; /* minimum number of rx groups */ 268 uint32_t def_rx_grp_num; /* default number of rx groups */ 269 uint32_t max_tx_que_num; /* maximum number of tx queues */ 270 uint32_t min_tx_que_num; /* minimum number of tx queues */ 271 uint32_t def_tx_que_num; /* default number of tx queues */ 272 uint32_t max_mtu; /* maximum MTU size */ 273 /* 274 * Interrupt throttling is in unit of 256 nsec 275 */ 276 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 277 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 278 uint32_t def_intr_throttle; /* default interrupt throttle */ 279 280 uint32_t max_msix_vect; /* maximum total msix vectors */ 281 uint32_t max_ring_vect; /* maximum number of ring vectors */ 282 uint32_t max_other_vect; /* maximum number of other vectors */ 283 uint32_t other_intr; /* "other" interrupt types handled */ 284 uint32_t flags; /* capability flags */ 285 } adapter_info_t; 286 287 /* bits representing all interrupt types other than tx & rx */ 288 #define IXGBE_OTHER_INTR 0x3ff00000 289 #define IXGBE_82599_OTHER_INTR 0x86100000 290 291 enum ioc_reply { 292 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 293 IOC_DONE, /* OK, reply sent */ 294 IOC_ACK, /* OK, just send ACK */ 295 IOC_REPLY /* OK, just send reply */ 296 }; 297 298 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 299 0, 0, (flag))) 300 301 /* 302 * Defined for ring index operations 303 * ASSERT(index < limit) 304 * ASSERT(step < limit) 305 * ASSERT(index1 < limit) 306 * ASSERT(index2 < limit) 307 */ 308 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 309 (index) + (step) : (index) + (step) - (limit)) 310 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 311 (index) - (step) : (index) + (limit) - (step)) 312 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 313 (index2) - (index1) : (index2) + (limit) - (index1)) 314 315 #define LINK_LIST_INIT(_LH) \ 316 (_LH)->head = (_LH)->tail = NULL 317 318 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 319 320 #define LIST_POP_HEAD(_LH) \ 321 (single_link_t *)(_LH)->head; \ 322 { \ 323 if ((_LH)->head != NULL) { \ 324 (_LH)->head = (_LH)->head->link; \ 325 if ((_LH)->head == NULL) \ 326 (_LH)->tail = NULL; \ 327 } \ 328 } 329 330 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 331 332 #define LIST_PUSH_TAIL(_LH, _E) \ 333 if ((_LH)->tail != NULL) { \ 334 (_LH)->tail->link = (single_link_t *)(_E); \ 335 (_LH)->tail = (single_link_t *)(_E); \ 336 } else { \ 337 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 338 } \ 339 (_E)->link = NULL; 340 341 #define LIST_GET_NEXT(_LH, _E) \ 342 (((_LH)->tail == (single_link_t *)(_E)) ? \ 343 NULL : ((single_link_t *)(_E))->link) 344 345 346 typedef struct single_link { 347 struct single_link *link; 348 } single_link_t; 349 350 typedef struct link_list { 351 single_link_t *head; 352 single_link_t *tail; 353 } link_list_t; 354 355 /* 356 * Property lookups 357 */ 358 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 359 DDI_PROP_DONTPASS, (n)) 360 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 361 DDI_PROP_DONTPASS, (n), -1) 362 363 364 typedef union ixgbe_ether_addr { 365 struct { 366 uint32_t high; 367 uint32_t low; 368 } reg; 369 struct { 370 uint8_t set; 371 uint8_t group_index; 372 uint8_t addr[ETHERADDRL]; 373 } mac; 374 } ixgbe_ether_addr_t; 375 376 typedef enum { 377 USE_NONE, 378 USE_COPY, 379 USE_DMA 380 } tx_type_t; 381 382 typedef struct ixgbe_tx_context { 383 uint32_t hcksum_flags; 384 uint32_t ip_hdr_len; 385 uint32_t mac_hdr_len; 386 uint32_t l4_proto; 387 uint32_t mss; 388 uint32_t l4_hdr_len; 389 boolean_t lso_flag; 390 } ixgbe_tx_context_t; 391 392 /* 393 * Hold address/length of each DMA segment 394 */ 395 typedef struct sw_desc { 396 uint64_t address; 397 size_t length; 398 } sw_desc_t; 399 400 /* 401 * Handles and addresses of DMA buffer 402 */ 403 typedef struct dma_buffer { 404 caddr_t address; /* Virtual address */ 405 uint64_t dma_address; /* DMA (Hardware) address */ 406 ddi_acc_handle_t acc_handle; /* Data access handle */ 407 ddi_dma_handle_t dma_handle; /* DMA handle */ 408 size_t size; /* Buffer size */ 409 size_t len; /* Data length in the buffer */ 410 } dma_buffer_t; 411 412 /* 413 * Tx Control Block 414 */ 415 typedef struct tx_control_block { 416 single_link_t link; 417 uint32_t last_index; /* last descriptor of the pkt */ 418 uint32_t frag_num; 419 uint32_t desc_num; 420 mblk_t *mp; 421 tx_type_t tx_type; 422 ddi_dma_handle_t tx_dma_handle; 423 dma_buffer_t tx_buf; 424 sw_desc_t desc[MAX_COOKIE]; 425 } tx_control_block_t; 426 427 /* 428 * RX Control Block 429 */ 430 typedef struct rx_control_block { 431 mblk_t *mp; 432 uint32_t ref_cnt; 433 dma_buffer_t rx_buf; 434 frtn_t free_rtn; 435 struct ixgbe_rx_data *rx_data; 436 int lro_next; /* Index of next rcb */ 437 int lro_prev; /* Index of previous rcb */ 438 boolean_t lro_pkt; /* Flag for LRO rcb */ 439 } rx_control_block_t; 440 441 /* 442 * Software Data Structure for Tx Ring 443 */ 444 typedef struct ixgbe_tx_ring { 445 uint32_t index; /* Ring index */ 446 uint32_t intr_vector; /* Interrupt vector index */ 447 uint32_t vect_bit; /* vector's bit in register */ 448 449 /* 450 * Mutexes 451 */ 452 kmutex_t tx_lock; 453 kmutex_t recycle_lock; 454 kmutex_t tcb_head_lock; 455 kmutex_t tcb_tail_lock; 456 457 /* 458 * Tx descriptor ring definitions 459 */ 460 dma_buffer_t tbd_area; 461 union ixgbe_adv_tx_desc *tbd_ring; 462 uint32_t tbd_head; /* Index of next tbd to recycle */ 463 uint32_t tbd_tail; /* Index of next tbd to transmit */ 464 uint32_t tbd_free; /* Number of free tbd */ 465 466 /* 467 * Tx control block list definitions 468 */ 469 tx_control_block_t *tcb_area; 470 tx_control_block_t **work_list; 471 tx_control_block_t **free_list; 472 uint32_t tcb_head; /* Head index of free list */ 473 uint32_t tcb_tail; /* Tail index of free list */ 474 uint32_t tcb_free; /* Number of free tcb in free list */ 475 476 uint32_t *tbd_head_wb; /* Head write-back */ 477 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 478 479 /* 480 * s/w context structure for TCP/UDP checksum offload 481 * and LSO. 482 */ 483 ixgbe_tx_context_t tx_context; 484 485 /* 486 * Tx ring settings and status 487 */ 488 uint32_t ring_size; /* Tx descriptor ring size */ 489 uint32_t free_list_size; /* Tx free list size */ 490 491 boolean_t reschedule; 492 uint32_t recycle_fail; 493 uint32_t stall_watchdog; 494 495 #ifdef IXGBE_DEBUG 496 /* 497 * Debug statistics 498 */ 499 uint32_t stat_overload; 500 uint32_t stat_fail_no_tbd; 501 uint32_t stat_fail_no_tcb; 502 uint32_t stat_fail_dma_bind; 503 uint32_t stat_reschedule; 504 uint32_t stat_break_tbd_limit; 505 uint32_t stat_lso_header_fail; 506 #endif 507 uint64_t stat_obytes; 508 uint64_t stat_opackets; 509 510 mac_ring_handle_t ring_handle; 511 512 /* 513 * Pointer to the ixgbe struct 514 */ 515 struct ixgbe *ixgbe; 516 } ixgbe_tx_ring_t; 517 518 /* 519 * Software Receive Ring 520 */ 521 typedef struct ixgbe_rx_data { 522 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 523 524 /* 525 * Rx descriptor ring definitions 526 */ 527 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 528 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 529 uint32_t rbd_next; /* Index of next rx desc */ 530 531 /* 532 * Rx control block list definitions 533 */ 534 rx_control_block_t *rcb_area; 535 rx_control_block_t **work_list; /* Work list of rcbs */ 536 rx_control_block_t **free_list; /* Free list of rcbs */ 537 uint32_t rcb_head; /* Index of next free rcb */ 538 uint32_t rcb_tail; /* Index to put recycled rcb */ 539 uint32_t rcb_free; /* Number of free rcbs */ 540 541 /* 542 * Rx sw ring settings and status 543 */ 544 uint32_t ring_size; /* Rx descriptor ring size */ 545 uint32_t free_list_size; /* Rx free list size */ 546 547 uint32_t rcb_pending; 548 uint32_t flag; 549 550 uint32_t lro_num; /* Number of rcbs of one LRO */ 551 uint32_t lro_first; /* Index of first LRO rcb */ 552 553 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 554 } ixgbe_rx_data_t; 555 556 /* 557 * Software Data Structure for Rx Ring 558 */ 559 typedef struct ixgbe_rx_ring { 560 uint32_t index; /* Ring index */ 561 uint32_t group_index; /* Group index */ 562 uint32_t hw_index; /* h/w ring index */ 563 uint32_t intr_vector; /* Interrupt vector index */ 564 uint32_t vect_bit; /* vector's bit in register */ 565 566 ixgbe_rx_data_t *rx_data; /* Rx software ring */ 567 568 kmutex_t rx_lock; /* Rx access lock */ 569 570 #ifdef IXGBE_DEBUG 571 /* 572 * Debug statistics 573 */ 574 uint32_t stat_frame_error; 575 uint32_t stat_cksum_error; 576 uint32_t stat_exceed_pkt; 577 #endif 578 uint64_t stat_rbytes; 579 uint64_t stat_ipackets; 580 581 mac_ring_handle_t ring_handle; 582 uint64_t ring_gen_num; 583 584 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 585 } ixgbe_rx_ring_t; 586 /* 587 * Software Receive Ring Group 588 */ 589 typedef struct ixgbe_rx_group { 590 uint32_t index; /* Group index */ 591 mac_group_handle_t group_handle; /* call back group handle */ 592 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 593 } ixgbe_rx_group_t; 594 595 /* 596 * structure to map interrupt cleanup to msi-x vector 597 */ 598 typedef struct ixgbe_intr_vector { 599 struct ixgbe *ixgbe; /* point to my adapter */ 600 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 601 int rxr_cnt; /* count rx rings */ 602 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 603 int txr_cnt; /* count tx rings */ 604 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 605 int other_cnt; /* count other interrupt */ 606 } ixgbe_intr_vector_t; 607 608 /* 609 * Software adapter state 610 */ 611 typedef struct ixgbe { 612 int instance; 613 mac_handle_t mac_hdl; 614 dev_info_t *dip; 615 struct ixgbe_hw hw; 616 struct ixgbe_osdep osdep; 617 618 adapter_info_t *capab; /* adapter hardware capabilities */ 619 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 620 uint32_t eims; /* interrupt mask setting */ 621 uint32_t eimc; /* interrupt mask clear */ 622 uint32_t eicr; /* interrupt cause reg */ 623 624 uint32_t ixgbe_state; 625 link_state_t link_state; 626 uint32_t link_speed; 627 uint32_t link_duplex; 628 629 uint32_t reset_count; 630 uint32_t attach_progress; 631 uint32_t loopback_mode; 632 uint32_t default_mtu; 633 uint32_t max_frame_size; 634 635 uint32_t rcb_pending; 636 637 /* 638 * Each msi-x vector: map vector to interrupt cleanup 639 */ 640 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 641 642 /* 643 * Receive Rings 644 */ 645 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 646 uint32_t num_rx_rings; /* Number of rx rings in use */ 647 uint32_t rx_ring_size; /* Rx descriptor ring size */ 648 uint32_t rx_buf_size; /* Rx buffer size */ 649 boolean_t lro_enable; /* Large Receive Offload */ 650 uint64_t lro_pkt_count; /* LRO packet count */ 651 /* 652 * Receive Groups 653 */ 654 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 655 uint32_t num_rx_groups; /* Number of rx groups in use */ 656 657 /* 658 * Transmit Rings 659 */ 660 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 661 uint32_t num_tx_rings; /* Number of tx rings in use */ 662 uint32_t tx_ring_size; /* Tx descriptor ring size */ 663 uint32_t tx_buf_size; /* Tx buffer size */ 664 665 boolean_t tx_ring_init; 666 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 667 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 668 boolean_t lso_enable; /* Large Segment Offload */ 669 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 670 uint32_t classify_mode; /* Classification mode */ 671 uint32_t tx_copy_thresh; /* Tx copy threshold */ 672 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 673 uint32_t tx_overload_thresh; /* Tx overload threshold */ 674 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 675 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 676 uint32_t rx_copy_thresh; /* Rx copy threshold */ 677 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 678 uint32_t intr_throttling[MAX_INTR_VECTOR]; 679 uint32_t intr_force; 680 int fm_capabilities; /* FMA capabilities */ 681 682 int intr_type; 683 int intr_cnt; 684 uint32_t intr_cnt_max; 685 uint32_t intr_cnt_min; 686 int intr_cap; 687 size_t intr_size; 688 uint_t intr_pri; 689 ddi_intr_handle_t *htable; 690 uint32_t eims_mask; 691 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */ 692 693 kmutex_t gen_lock; /* General lock for device access */ 694 kmutex_t watchdog_lock; 695 kmutex_t rx_pending_lock; 696 697 boolean_t watchdog_enable; 698 boolean_t watchdog_start; 699 timeout_id_t watchdog_tid; 700 701 boolean_t unicst_init; 702 uint32_t unicst_avail; 703 uint32_t unicst_total; 704 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 705 uint32_t mcast_count; 706 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 707 708 ulong_t sys_page_size; 709 710 boolean_t link_check_complete; 711 hrtime_t link_check_hrtime; 712 ddi_periodic_t periodic_id; /* for link check timer func */ 713 714 /* 715 * Kstat definitions 716 */ 717 kstat_t *ixgbe_ks; 718 719 uint32_t param_en_10000fdx_cap:1, 720 param_en_1000fdx_cap:1, 721 param_en_100fdx_cap:1, 722 param_adv_10000fdx_cap:1, 723 param_adv_1000fdx_cap:1, 724 param_adv_100fdx_cap:1, 725 param_pause_cap:1, 726 param_asym_pause_cap:1, 727 param_rem_fault:1, 728 param_adv_autoneg_cap:1, 729 param_adv_pause_cap:1, 730 param_adv_asym_pause_cap:1, 731 param_adv_rem_fault:1, 732 param_lp_10000fdx_cap:1, 733 param_lp_1000fdx_cap:1, 734 param_lp_100fdx_cap:1, 735 param_lp_autoneg_cap:1, 736 param_lp_pause_cap:1, 737 param_lp_asym_pause_cap:1, 738 param_lp_rem_fault:1, 739 param_pad_to_32:12; 740 } ixgbe_t; 741 742 typedef struct ixgbe_stat { 743 kstat_named_t link_speed; /* Link Speed */ 744 745 kstat_named_t reset_count; /* Reset Count */ 746 747 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 748 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 749 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 750 751 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 752 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 753 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 754 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 755 kstat_named_t tx_reschedule; /* Tx Reschedule */ 756 757 kstat_named_t gprc; /* Good Packets Received Count */ 758 kstat_named_t gptc; /* Good Packets Xmitted Count */ 759 kstat_named_t gor; /* Good Octets Received Count */ 760 kstat_named_t got; /* Good Octets Xmitd Count */ 761 kstat_named_t prc64; /* Packets Received - 64b */ 762 kstat_named_t prc127; /* Packets Received - 65-127b */ 763 kstat_named_t prc255; /* Packets Received - 127-255b */ 764 kstat_named_t prc511; /* Packets Received - 256-511b */ 765 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 766 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 767 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 768 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 769 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 770 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 771 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 772 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 773 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 774 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 775 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 776 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 777 778 kstat_named_t crcerrs; /* CRC Error Count */ 779 kstat_named_t illerrc; /* Illegal Byte Error Count */ 780 kstat_named_t errbc; /* Error Byte Count */ 781 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 782 kstat_named_t mpc; /* Missed Packets Count */ 783 kstat_named_t mlfc; /* MAC Local Fault Count */ 784 kstat_named_t mrfc; /* MAC Remote Fault Count */ 785 kstat_named_t rlec; /* Receive Length Error Count */ 786 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 787 kstat_named_t lxonrxc; /* Link XON Received Count */ 788 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 789 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 790 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 791 kstat_named_t mprc; /* Multicast Pkts Received Count */ 792 kstat_named_t rnbc; /* Receive No Buffers Count */ 793 kstat_named_t ruc; /* Receive Undersize Count */ 794 kstat_named_t rfc; /* Receive Frag Count */ 795 kstat_named_t roc; /* Receive Oversize Count */ 796 kstat_named_t rjc; /* Receive Jabber Count */ 797 kstat_named_t tor; /* Total Octets Recvd Count */ 798 kstat_named_t tot; /* Total Octets Xmitted Count */ 799 kstat_named_t tpr; /* Total Packets Received */ 800 kstat_named_t tpt; /* Total Packets Xmitted */ 801 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 802 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 803 kstat_named_t lroc; /* LRO Packets Received Count */ 804 } ixgbe_stat_t; 805 806 /* 807 * Function prototypes in ixgbe_buf.c 808 */ 809 int ixgbe_alloc_dma(ixgbe_t *); 810 void ixgbe_free_dma(ixgbe_t *); 811 void ixgbe_set_fma_flags(int); 812 void ixgbe_free_dma_buffer(dma_buffer_t *); 813 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 814 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 815 816 /* 817 * Function prototypes in ixgbe_main.c 818 */ 819 int ixgbe_start(ixgbe_t *, boolean_t); 820 void ixgbe_stop(ixgbe_t *, boolean_t); 821 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 822 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 823 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 824 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 825 826 void ixgbe_enable_watchdog_timer(ixgbe_t *); 827 void ixgbe_disable_watchdog_timer(ixgbe_t *); 828 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 829 830 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 831 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 832 void ixgbe_fm_ereport(ixgbe_t *, char *); 833 834 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 835 mac_ring_info_t *, mac_ring_handle_t); 836 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 837 mac_group_info_t *, mac_group_handle_t); 838 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 839 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 840 841 /* 842 * Function prototypes in ixgbe_gld.c 843 */ 844 int ixgbe_m_start(void *); 845 void ixgbe_m_stop(void *); 846 int ixgbe_m_promisc(void *, boolean_t); 847 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 848 void ixgbe_m_resources(void *); 849 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 850 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 851 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 852 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 853 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t, 854 mac_prop_info_handle_t); 855 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 856 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *); 857 boolean_t ixgbe_param_locked(mac_prop_id_t); 858 859 /* 860 * Function prototypes in ixgbe_rx.c 861 */ 862 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 863 void ixgbe_rx_recycle(caddr_t arg); 864 mblk_t *ixgbe_ring_rx_poll(void *, int); 865 866 /* 867 * Function prototypes in ixgbe_tx.c 868 */ 869 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 870 void ixgbe_free_tcb(tx_control_block_t *); 871 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 872 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 873 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 874 875 /* 876 * Function prototypes in ixgbe_log.c 877 */ 878 void ixgbe_notice(void *, const char *, ...); 879 void ixgbe_log(void *, const char *, ...); 880 void ixgbe_error(void *, const char *, ...); 881 882 /* 883 * Function prototypes in ixgbe_stat.c 884 */ 885 int ixgbe_init_stats(ixgbe_t *); 886 int ixgbe_m_stat(void *, uint_t, uint64_t *); 887 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 888 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 889 890 #ifdef __cplusplus 891 } 892 #endif 893 894 #endif /* _IXGBE_SW_H */ 895