1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IXGBE_SW_H 30 #define _IXGBE_SW_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include <sys/bitmap.h> 69 #include <sys/ddifm.h> 70 #include <sys/fm/protocol.h> 71 #include <sys/fm/util.h> 72 #include <sys/fm/io/ddi.h> 73 #include "ixgbe_api.h" 74 75 #define MODULE_NAME "ixgbe" /* module name */ 76 77 #define IXGBE_FAILURE DDI_FAILURE 78 79 #define IXGBE_UNKNOWN 0x00 80 #define IXGBE_INITIALIZED 0x01 81 #define IXGBE_STARTED 0x02 82 #define IXGBE_SUSPENDED 0x04 83 84 #define MAX_NUM_UNICAST_ADDRESSES 0x10 85 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 86 #define IXGBE_INTR_NONE 0 87 #define IXGBE_INTR_MSIX 1 88 #define IXGBE_INTR_MSI 2 89 #define IXGBE_INTR_LEGACY 3 90 91 #define MAX_COOKIE 16 92 #define MIN_NUM_TX_DESC 2 93 94 /* 95 * Maximum values for user configurable parameters 96 */ 97 98 /* 99 * MAX_xx_QUEUE_NUM values need to be the maximum of all supported 100 * silicon types. 101 */ 102 #define MAX_TX_QUEUE_NUM 32 103 #define MAX_RX_QUEUE_NUM 64 104 105 #define MAX_TX_RING_SIZE 4096 106 #define MAX_RX_RING_SIZE 4096 107 108 #define MAX_MTU 16366 109 #define MAX_RX_LIMIT_PER_INTR 4096 110 #define MAX_INTR_THROTTLING 65535 111 112 #define MAX_RX_COPY_THRESHOLD 9216 113 #define MAX_TX_COPY_THRESHOLD 9216 114 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 115 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 116 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 117 118 /* 119 * Minimum values for user configurable parameters 120 */ 121 #define MIN_TX_QUEUE_NUM 1 122 #define MIN_RX_QUEUE_NUM 1 123 #define MIN_TX_RING_SIZE 64 124 #define MIN_RX_RING_SIZE 64 125 126 #define MIN_MTU ETHERMIN 127 #define MIN_RX_LIMIT_PER_INTR 16 128 #define MIN_INTR_THROTTLING 0 129 #define MIN_TX_COPY_THRESHOLD 0 130 #define MIN_RX_COPY_THRESHOLD 0 131 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 132 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 133 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 134 135 /* 136 * Default values for user configurable parameters 137 */ 138 #define DEFAULT_TX_QUEUE_NUM 1 139 #define DEFAULT_RX_QUEUE_NUM 1 140 #define DEFAULT_TX_RING_SIZE 512 141 #define DEFAULT_RX_RING_SIZE 512 142 143 #define DEFAULT_MTU ETHERMTU 144 #define DEFAULT_RX_LIMIT_PER_INTR 256 145 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 146 #define DEFAULT_RX_COPY_THRESHOLD 128 147 #define DEFAULT_TX_COPY_THRESHOLD 512 148 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 149 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 150 #define DEFAULT_TX_RESCHED_THRESHOLD 128 151 #define DEFAULT_FCRTH 0x20000 152 #define DEFAULT_FCRTL 0x10000 153 #define DEFAULT_FCPAUSE 0xFFFF 154 155 #define TX_DRAIN_TIME 200 156 #define RX_DRAIN_TIME 200 157 158 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 159 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 160 161 /* 162 * limits on msi-x vectors for 82598 163 */ 164 #define IXGBE_MAX_INTR_VECTOR 18 165 #define IXGBE_MAX_OTHER_VECTOR 2 166 #define IXGBE_MAX_RING_VECTOR (IXGBE_MAX_INTR_VECTOR - IXGBE_MAX_OTHER_VECTOR) 167 168 /* 169 * Extra register bit masks for 82598 170 */ 171 #define IXGBE_PCS1GANA_FDC 0x20 172 #define IXGBE_PCS1GANLP_LPFD 0x20 173 #define IXGBE_PCS1GANLP_LPHD 0x40 174 175 176 /* 177 * Defined for IP header alignment. 178 */ 179 #define IPHDR_ALIGN_ROOM 2 180 181 /* 182 * Bit flags for attach_progress 183 */ 184 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 185 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 186 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 187 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 188 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 189 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 190 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 191 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 192 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 193 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 194 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 195 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 196 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 197 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 198 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_QUEUE_NUM "tx_queue_number" 202 #define PROP_TX_RING_SIZE "tx_ring_size" 203 #define PROP_RX_QUEUE_NUM "rx_queue_number" 204 #define PROP_RX_RING_SIZE "rx_ring_size" 205 206 #define PROP_INTR_FORCE "intr_force" 207 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209 #define PROP_LSO_ENABLE "lso_enable" 210 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217 #define PROP_INTR_THROTTLING "intr_throttling" 218 #define PROP_FM_CAPABLE "fm_capable" 219 220 #define IXGBE_LB_NONE 0 221 #define IXGBE_LB_EXTERNAL 1 222 #define IXGBE_LB_INTERNAL_MAC 2 223 #define IXGBE_LB_INTERNAL_PHY 3 224 #define IXGBE_LB_INTERNAL_SERDES 4 225 226 /* 227 * Shorthand for the NDD parameters 228 */ 229 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 230 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 231 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 232 #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 233 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 234 #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 235 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 236 237 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 238 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 239 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 240 #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 241 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 242 #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 243 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 244 245 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 246 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 247 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 248 #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 249 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 250 #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 251 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 252 253 enum ioc_reply { 254 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 255 IOC_DONE, /* OK, reply sent */ 256 IOC_ACK, /* OK, just send ACK */ 257 IOC_REPLY /* OK, just send reply */ 258 }; 259 260 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 261 (uintptr_t)(mp)->b_rptr) 262 263 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 264 0, 0, (flag))) 265 266 /* 267 * Defined for ring index operations 268 * ASSERT(index < limit) 269 * ASSERT(step < limit) 270 * ASSERT(index1 < limit) 271 * ASSERT(index2 < limit) 272 */ 273 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 274 (index) + (step) : (index) + (step) - (limit)) 275 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 276 (index) - (step) : (index) + (limit) - (step)) 277 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 278 (index2) - (index1) : (index2) + (limit) - (index1)) 279 280 #define LINK_LIST_INIT(_LH) \ 281 (_LH)->head = (_LH)->tail = NULL 282 283 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 284 285 #define LIST_POP_HEAD(_LH) \ 286 (single_link_t *)(_LH)->head; \ 287 { \ 288 if ((_LH)->head != NULL) { \ 289 (_LH)->head = (_LH)->head->link; \ 290 if ((_LH)->head == NULL) \ 291 (_LH)->tail = NULL; \ 292 } \ 293 } 294 295 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 296 297 #define LIST_PUSH_TAIL(_LH, _E) \ 298 if ((_LH)->tail != NULL) { \ 299 (_LH)->tail->link = (single_link_t *)(_E); \ 300 (_LH)->tail = (single_link_t *)(_E); \ 301 } else { \ 302 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 303 } \ 304 (_E)->link = NULL; 305 306 #define LIST_GET_NEXT(_LH, _E) \ 307 (((_LH)->tail == (single_link_t *)(_E)) ? \ 308 NULL : ((single_link_t *)(_E))->link) 309 310 311 typedef struct single_link { 312 struct single_link *link; 313 } single_link_t; 314 315 typedef struct link_list { 316 single_link_t *head; 317 single_link_t *tail; 318 } link_list_t; 319 320 /* 321 * Property lookups 322 */ 323 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 324 DDI_PROP_DONTPASS, (n)) 325 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 326 DDI_PROP_DONTPASS, (n), -1) 327 328 329 /* 330 * Named Data (ND) Parameter Management Structure 331 */ 332 typedef struct { 333 struct ixgbe *private; 334 uint32_t info; 335 uint32_t min; 336 uint32_t max; 337 uint32_t val; 338 char *name; 339 } nd_param_t; 340 341 /* 342 * NDD parameter indexes, divided into: 343 * 344 * read-only parameters describing the hardware's capabilities 345 * read-write parameters controlling the advertised capabilities 346 * read-only parameters describing the partner's capabilities 347 * read-write parameters controlling the force speed and duplex 348 * read-only parameters describing the link state 349 * read-only parameters describing the driver properties 350 * read-write parameters controlling the driver properties 351 */ 352 enum { 353 PARAM_AUTONEG_CAP, 354 PARAM_PAUSE_CAP, 355 PARAM_ASYM_PAUSE_CAP, 356 PARAM_10000FDX_CAP, 357 PARAM_1000FDX_CAP, 358 PARAM_100FDX_CAP, 359 PARAM_REM_FAULT, 360 361 PARAM_ADV_AUTONEG_CAP, 362 PARAM_ADV_PAUSE_CAP, 363 PARAM_ADV_ASYM_PAUSE_CAP, 364 PARAM_ADV_10000FDX_CAP, 365 PARAM_ADV_1000FDX_CAP, 366 PARAM_ADV_100FDX_CAP, 367 PARAM_ADV_REM_FAULT, 368 369 PARAM_LP_AUTONEG_CAP, 370 PARAM_LP_PAUSE_CAP, 371 PARAM_LP_ASYM_PAUSE_CAP, 372 PARAM_LP_10000FDX_CAP, 373 PARAM_LP_1000FDX_CAP, 374 PARAM_LP_100FDX_CAP, 375 PARAM_LP_REM_FAULT, 376 377 PARAM_LINK_STATUS, 378 PARAM_LINK_SPEED, 379 PARAM_LINK_DUPLEX, 380 381 PARAM_COUNT 382 }; 383 384 typedef union ixgbe_ether_addr { 385 struct { 386 uint32_t high; 387 uint32_t low; 388 } reg; 389 struct { 390 uint8_t set; 391 uint8_t redundant; 392 uint8_t addr[ETHERADDRL]; 393 } mac; 394 } ixgbe_ether_addr_t; 395 396 typedef enum { 397 USE_NONE, 398 USE_COPY, 399 USE_DMA 400 } tx_type_t; 401 402 typedef enum { 403 RCB_FREE, 404 RCB_SENDUP 405 } rcb_state_t; 406 407 typedef struct hcksum_context { 408 uint32_t hcksum_flags; 409 uint32_t ip_hdr_len; 410 uint32_t mac_hdr_len; 411 uint32_t l4_proto; 412 } hcksum_context_t; 413 414 /* 415 * Hold address/length of each DMA segment 416 */ 417 typedef struct sw_desc { 418 uint64_t address; 419 size_t length; 420 } sw_desc_t; 421 422 /* 423 * Handles and addresses of DMA buffer 424 */ 425 typedef struct dma_buffer { 426 caddr_t address; /* Virtual address */ 427 uint64_t dma_address; /* DMA (Hardware) address */ 428 ddi_acc_handle_t acc_handle; /* Data access handle */ 429 ddi_dma_handle_t dma_handle; /* DMA handle */ 430 size_t size; /* Buffer size */ 431 size_t len; /* Data length in the buffer */ 432 } dma_buffer_t; 433 434 /* 435 * Tx Control Block 436 */ 437 typedef struct tx_control_block { 438 single_link_t link; 439 uint32_t frag_num; 440 uint32_t desc_num; 441 mblk_t *mp; 442 tx_type_t tx_type; 443 ddi_dma_handle_t tx_dma_handle; 444 dma_buffer_t tx_buf; 445 sw_desc_t desc[MAX_COOKIE]; 446 } tx_control_block_t; 447 448 /* 449 * RX Control Block 450 */ 451 typedef struct rx_control_block { 452 mblk_t *mp; 453 rcb_state_t state; 454 dma_buffer_t rx_buf; 455 frtn_t free_rtn; 456 struct ixgbe_rx_ring *rx_ring; 457 } rx_control_block_t; 458 459 /* 460 * Software Data Structure for Tx Ring 461 */ 462 typedef struct ixgbe_tx_ring { 463 uint32_t index; /* Ring index */ 464 uint32_t intr_vector; /* Interrupt vector index */ 465 uint32_t vect_bit; /* vector's bit in register */ 466 467 /* 468 * Mutexes 469 */ 470 kmutex_t tx_lock; 471 kmutex_t recycle_lock; 472 kmutex_t tcb_head_lock; 473 kmutex_t tcb_tail_lock; 474 475 /* 476 * Tx descriptor ring definitions 477 */ 478 dma_buffer_t tbd_area; 479 union ixgbe_adv_tx_desc *tbd_ring; 480 uint32_t tbd_head; /* Index of next tbd to recycle */ 481 uint32_t tbd_tail; /* Index of next tbd to transmit */ 482 uint32_t tbd_free; /* Number of free tbd */ 483 484 /* 485 * Tx control block list definitions 486 */ 487 tx_control_block_t *tcb_area; 488 tx_control_block_t **work_list; 489 tx_control_block_t **free_list; 490 uint32_t tcb_head; /* Head index of free list */ 491 uint32_t tcb_tail; /* Tail index of free list */ 492 uint32_t tcb_free; /* Number of free tcb in free list */ 493 494 uint32_t *tbd_head_wb; /* Head write-back */ 495 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 496 497 /* 498 * TCP/UDP checksum offload 499 */ 500 hcksum_context_t hcksum_context; 501 502 /* 503 * Tx ring settings and status 504 */ 505 uint32_t ring_size; /* Tx descriptor ring size */ 506 uint32_t free_list_size; /* Tx free list size */ 507 uint32_t copy_thresh; 508 uint32_t recycle_thresh; 509 uint32_t overload_thresh; 510 uint32_t resched_thresh; 511 512 boolean_t reschedule; 513 uint32_t recycle_fail; 514 uint32_t stall_watchdog; 515 516 #ifdef IXGBE_DEBUG 517 /* 518 * Debug statistics 519 */ 520 uint32_t stat_overload; 521 uint32_t stat_fail_no_tbd; 522 uint32_t stat_fail_no_tcb; 523 uint32_t stat_fail_dma_bind; 524 uint32_t stat_reschedule; 525 #endif 526 527 /* 528 * Pointer to the ixgbe struct 529 */ 530 struct ixgbe *ixgbe; 531 532 } ixgbe_tx_ring_t; 533 534 /* 535 * Software Receive Ring 536 */ 537 typedef struct ixgbe_rx_ring { 538 uint32_t index; /* Ring index */ 539 uint32_t intr_vector; /* Interrupt vector index */ 540 uint32_t vect_bit; /* vector's bit in register */ 541 542 /* 543 * Mutexes 544 */ 545 kmutex_t rx_lock; /* Rx access lock */ 546 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 547 548 /* 549 * Rx descriptor ring definitions 550 */ 551 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 552 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 553 uint32_t rbd_next; /* Index of next rx desc */ 554 555 /* 556 * Rx control block list definitions 557 */ 558 rx_control_block_t *rcb_area; 559 rx_control_block_t **work_list; /* Work list of rcbs */ 560 rx_control_block_t **free_list; /* Free list of rcbs */ 561 uint32_t rcb_head; /* Index of next free rcb */ 562 uint32_t rcb_tail; /* Index to put recycled rcb */ 563 uint32_t rcb_free; /* Number of free rcbs */ 564 565 /* 566 * Rx ring settings and status 567 */ 568 uint32_t ring_size; /* Rx descriptor ring size */ 569 uint32_t free_list_size; /* Rx free list size */ 570 uint32_t limit_per_intr; /* Max packets per interrupt */ 571 uint32_t copy_thresh; 572 573 #ifdef IXGBE_DEBUG 574 /* 575 * Debug statistics 576 */ 577 uint32_t stat_frame_error; 578 uint32_t stat_cksum_error; 579 uint32_t stat_exceed_pkt; 580 #endif 581 582 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 583 584 } ixgbe_rx_ring_t; 585 586 /* 587 * structure to map ring cleanup to msi-x vector 588 */ 589 typedef struct ixgbe_ring_vector { 590 struct ixgbe *ixgbe; /* point to my adapter */ 591 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 592 int rxr_cnt; /* count rx rings */ 593 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 594 int txr_cnt; /* count tx rings */ 595 } ixgbe_ring_vector_t; 596 597 /* 598 * Software adapter state 599 */ 600 typedef struct ixgbe { 601 int instance; 602 mac_handle_t mac_hdl; 603 dev_info_t *dip; 604 struct ixgbe_hw hw; 605 struct ixgbe_osdep osdep; 606 607 uint32_t ixgbe_state; 608 link_state_t link_state; 609 uint32_t link_speed; 610 uint32_t link_duplex; 611 uint32_t link_down_timeout; 612 613 uint32_t reset_count; 614 uint32_t attach_progress; 615 uint32_t loopback_mode; 616 uint32_t default_mtu; 617 uint32_t max_frame_size; 618 619 /* 620 * Each msi-x vector: map vector to ring cleanup 621 */ 622 ixgbe_ring_vector_t vect_map[IXGBE_MAX_RING_VECTOR]; 623 624 /* 625 * Receive Rings 626 */ 627 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 628 uint32_t num_rx_rings; /* Number of rx rings in use */ 629 uint32_t rx_ring_size; /* Rx descriptor ring size */ 630 uint32_t rx_buf_size; /* Rx buffer size */ 631 632 /* 633 * Transmit Rings 634 */ 635 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 636 uint32_t num_tx_rings; /* Number of tx rings in use */ 637 uint32_t tx_ring_size; /* Tx descriptor ring size */ 638 uint32_t tx_buf_size; /* Tx buffer size */ 639 640 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 641 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 642 boolean_t lso_enable; /* Large Segment Offload */ 643 uint32_t tx_copy_thresh; /* Tx copy threshold */ 644 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 645 uint32_t tx_overload_thresh; /* Tx overload threshold */ 646 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 647 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 648 uint32_t rx_copy_thresh; /* Rx copy threshold */ 649 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 650 uint32_t intr_throttling[IXGBE_MAX_RING_VECTOR]; 651 uint32_t intr_force; 652 int fm_capabilities; /* FMA capabilities */ 653 654 int intr_type; 655 int intr_cnt; 656 int intr_cap; 657 size_t intr_size; 658 uint_t intr_pri; 659 ddi_intr_handle_t *htable; 660 uint32_t eims_mask; 661 662 kmutex_t gen_lock; /* General lock for device access */ 663 kmutex_t watchdog_lock; 664 665 boolean_t watchdog_enable; 666 boolean_t watchdog_start; 667 timeout_id_t watchdog_tid; 668 669 boolean_t unicst_init; 670 uint32_t unicst_avail; 671 uint32_t unicst_total; 672 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 673 uint32_t mcast_count; 674 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 675 676 /* 677 * Kstat definitions 678 */ 679 kstat_t *ixgbe_ks; 680 681 /* 682 * NDD definitions 683 */ 684 caddr_t nd_data; 685 nd_param_t nd_params[PARAM_COUNT]; 686 687 } ixgbe_t; 688 689 typedef struct ixgbe_stat { 690 691 kstat_named_t link_speed; /* Link Speed */ 692 #ifdef IXGBE_DEBUG 693 kstat_named_t reset_count; /* Reset Count */ 694 695 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 696 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 697 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 698 699 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 700 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 701 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 702 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 703 kstat_named_t tx_reschedule; /* Tx Reschedule */ 704 705 kstat_named_t gprc; /* Good Packets Received Count */ 706 kstat_named_t gptc; /* Good Packets Xmitted Count */ 707 kstat_named_t gor; /* Good Octets Received Count */ 708 kstat_named_t got; /* Good Octets Xmitd Count */ 709 kstat_named_t prc64; /* Packets Received - 64b */ 710 kstat_named_t prc127; /* Packets Received - 65-127b */ 711 kstat_named_t prc255; /* Packets Received - 127-255b */ 712 kstat_named_t prc511; /* Packets Received - 256-511b */ 713 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 714 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 715 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 716 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 717 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 718 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 719 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 720 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 721 #endif 722 kstat_named_t crcerrs; /* CRC Error Count */ 723 kstat_named_t illerrc; /* Illegal Byte Error Count */ 724 kstat_named_t errbc; /* Error Byte Count */ 725 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 726 kstat_named_t mpc; /* Missed Packets Count */ 727 kstat_named_t mlfc; /* MAC Local Fault Count */ 728 kstat_named_t mrfc; /* MAC Remote Fault Count */ 729 kstat_named_t rlec; /* Receive Length Error Count */ 730 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 731 kstat_named_t lxonrxc; /* Link XON Received Count */ 732 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 733 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 734 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 735 kstat_named_t mprc; /* Multicast Pkts Received Count */ 736 kstat_named_t rnbc; /* Receive No Buffers Count */ 737 kstat_named_t ruc; /* Receive Undersize Count */ 738 kstat_named_t rfc; /* Receive Frag Count */ 739 kstat_named_t roc; /* Receive Oversize Count */ 740 kstat_named_t rjc; /* Receive Jabber Count */ 741 kstat_named_t tor; /* Total Octets Recvd Count */ 742 kstat_named_t tpr; /* Total Packets Received */ 743 kstat_named_t tpt; /* Total Packets Xmitted */ 744 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 745 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 746 } ixgbe_stat_t; 747 748 /* 749 * Function prototypes in ixgbe_buf.c 750 */ 751 int ixgbe_alloc_dma(ixgbe_t *); 752 void ixgbe_free_dma(ixgbe_t *); 753 void ixgbe_set_fma_flags(int, int); 754 755 /* 756 * Function prototypes in ixgbe_main.c 757 */ 758 int ixgbe_start(ixgbe_t *); 759 void ixgbe_stop(ixgbe_t *); 760 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 761 int ixgbe_unicst_set(ixgbe_t *, const uint8_t *, mac_addr_slot_t); 762 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 763 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 764 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 765 766 void ixgbe_enable_watchdog_timer(ixgbe_t *); 767 void ixgbe_disable_watchdog_timer(ixgbe_t *); 768 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 769 770 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 771 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 772 void ixgbe_fm_ereport(ixgbe_t *, char *); 773 774 /* 775 * Function prototypes in ixgbe_gld.c 776 */ 777 int ixgbe_m_start(void *); 778 void ixgbe_m_stop(void *); 779 int ixgbe_m_promisc(void *, boolean_t); 780 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 781 int ixgbe_m_unicst(void *, const uint8_t *); 782 int ixgbe_m_stat(void *, uint_t, uint64_t *); 783 void ixgbe_m_resources(void *); 784 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 785 int ixgbe_m_unicst_add(void *, mac_multi_addr_t *); 786 int ixgbe_m_unicst_remove(void *, mac_addr_slot_t); 787 int ixgbe_m_unicst_modify(void *, mac_multi_addr_t *); 788 int ixgbe_m_unicst_get(void *, mac_multi_addr_t *); 789 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 790 791 /* 792 * Function prototypes in ixgbe_rx.c 793 */ 794 mblk_t *ixgbe_rx(ixgbe_rx_ring_t *); 795 void ixgbe_rx_recycle(caddr_t arg); 796 797 /* 798 * Function prototypes in ixgbe_tx.c 799 */ 800 mblk_t *ixgbe_m_tx(void *, mblk_t *); 801 void ixgbe_free_tcb(tx_control_block_t *); 802 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 803 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 804 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 805 806 /* 807 * Function prototypes in ixgbe_log.c 808 */ 809 void ixgbe_notice(void *, const char *, ...); 810 void ixgbe_log(void *, const char *, ...); 811 void ixgbe_error(void *, const char *, ...); 812 813 /* 814 * Function prototypes in ixgbe_ndd.c 815 */ 816 int ixgbe_nd_init(ixgbe_t *); 817 void ixgbe_nd_cleanup(ixgbe_t *); 818 enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 819 820 /* 821 * Function prototypes in ixgbe_stat.c 822 */ 823 int ixgbe_init_stats(ixgbe_t *); 824 825 826 #ifdef __cplusplus 827 } 828 #endif 829 830 #endif /* _IXGBE_SW_H */ 831