1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30 #ifndef _IXGBE_SW_H 31 #define _IXGBE_SW_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/types.h> 38 #include <sys/conf.h> 39 #include <sys/debug.h> 40 #include <sys/stropts.h> 41 #include <sys/stream.h> 42 #include <sys/strsun.h> 43 #include <sys/strlog.h> 44 #include <sys/kmem.h> 45 #include <sys/stat.h> 46 #include <sys/kstat.h> 47 #include <sys/modctl.h> 48 #include <sys/errno.h> 49 #include <sys/dlpi.h> 50 #include <sys/mac_provider.h> 51 #include <sys/mac_ether.h> 52 #include <sys/vlan.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 #include <sys/pci.h> 56 #include <sys/pcie.h> 57 #include <sys/sdt.h> 58 #include <sys/ethernet.h> 59 #include <sys/pattr.h> 60 #include <sys/strsubr.h> 61 #include <sys/netlb.h> 62 #include <sys/random.h> 63 #include <inet/common.h> 64 #include <inet/tcp.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include <sys/bitmap.h> 69 #include <sys/ddifm.h> 70 #include <sys/fm/protocol.h> 71 #include <sys/fm/util.h> 72 #include <sys/disp.h> 73 #include <sys/fm/io/ddi.h> 74 #include "ixgbe_api.h" 75 76 #define MODULE_NAME "ixgbe" /* module name */ 77 78 #define IXGBE_FAILURE DDI_FAILURE 79 80 #define IXGBE_UNKNOWN 0x00 81 #define IXGBE_INITIALIZED 0x01 82 #define IXGBE_STARTED 0x02 83 #define IXGBE_SUSPENDED 0x04 84 #define IXGBE_STALL 0x08 85 #define IXGBE_OVERTEMP 0x20 86 #define IXGBE_INTR_ADJUST 0x40 87 #define IXGBE_ERROR 0x80 88 89 #define MAX_NUM_UNICAST_ADDRESSES 0x80 90 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 91 #define IXGBE_INTR_NONE 0 92 #define IXGBE_INTR_MSIX 1 93 #define IXGBE_INTR_MSI 2 94 #define IXGBE_INTR_LEGACY 3 95 96 #define IXGBE_POLL_NULL -1 97 98 #define MAX_COOKIE 18 99 #define MIN_NUM_TX_DESC 2 100 101 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 102 103 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 104 105 #define IXGBE_RX_STOPPED 0x1 106 107 #define IXGBE_PKG_BUF_16k 16384 108 109 /* 110 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 111 * supported silicon types. 112 */ 113 #define MAX_TX_QUEUE_NUM 128 114 #define MAX_RX_QUEUE_NUM 128 115 #define MAX_INTR_VECTOR 64 116 117 /* 118 * Maximum values for user configurable parameters 119 */ 120 #define MAX_TX_RING_SIZE 4096 121 #define MAX_RX_RING_SIZE 4096 122 123 #define MAX_RX_LIMIT_PER_INTR 4096 124 125 #define MAX_RX_COPY_THRESHOLD 9216 126 #define MAX_TX_COPY_THRESHOLD 9216 127 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 128 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 129 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 130 131 /* 132 * Minimum values for user configurable parameters 133 */ 134 #define MIN_TX_RING_SIZE 64 135 #define MIN_RX_RING_SIZE 64 136 137 #define MIN_MTU ETHERMIN 138 #define MIN_RX_LIMIT_PER_INTR 16 139 #define MIN_TX_COPY_THRESHOLD 0 140 #define MIN_RX_COPY_THRESHOLD 0 141 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 142 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 143 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 144 145 /* 146 * Default values for user configurable parameters 147 */ 148 #define DEFAULT_TX_RING_SIZE 1024 149 #define DEFAULT_RX_RING_SIZE 1024 150 151 #define DEFAULT_MTU ETHERMTU 152 #define DEFAULT_RX_LIMIT_PER_INTR 256 153 #define DEFAULT_RX_COPY_THRESHOLD 128 154 #define DEFAULT_TX_COPY_THRESHOLD 512 155 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 156 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 157 #define DEFAULT_TX_RESCHED_THRESHOLD 128 158 #define DEFAULT_FCRTH 0x20000 159 #define DEFAULT_FCRTL 0x10000 160 #define DEFAULT_FCPAUSE 0xFFFF 161 162 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 163 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 164 #define DEFAULT_LSO_ENABLE B_TRUE 165 #define DEFAULT_LRO_ENABLE B_FALSE 166 #define DEFAULT_MR_ENABLE B_TRUE 167 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 168 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE 169 170 #define IXGBE_LSO_MAXLEN 65535 171 172 #define TX_DRAIN_TIME 200 173 #define RX_DRAIN_TIME 200 174 175 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 176 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 177 178 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 179 180 /* 181 * Extra register bit masks for 82598 182 */ 183 #define IXGBE_PCS1GANA_FDC 0x20 184 #define IXGBE_PCS1GANLP_LPFD 0x20 185 #define IXGBE_PCS1GANLP_LPHD 0x40 186 187 /* 188 * Defined for IP header alignment. 189 */ 190 #define IPHDR_ALIGN_ROOM 2 191 192 /* 193 * Bit flags for attach_progress 194 */ 195 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 196 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 197 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 198 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 199 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 200 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 201 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 202 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 203 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 204 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 205 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 206 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 207 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 208 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 209 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */ 210 211 #define PROP_DEFAULT_MTU "default_mtu" 212 #define PROP_FLOW_CONTROL "flow_control" 213 #define PROP_TX_QUEUE_NUM "tx_queue_number" 214 #define PROP_TX_RING_SIZE "tx_ring_size" 215 #define PROP_RX_QUEUE_NUM "rx_queue_number" 216 #define PROP_RX_RING_SIZE "rx_ring_size" 217 #define PROP_RX_GROUP_NUM "rx_group_number" 218 219 #define PROP_INTR_FORCE "intr_force" 220 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 221 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 222 #define PROP_LSO_ENABLE "lso_enable" 223 #define PROP_LRO_ENABLE "lro_enable" 224 #define PROP_MR_ENABLE "mr_enable" 225 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable" 226 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 227 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 228 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 229 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 230 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 231 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 232 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 233 #define PROP_INTR_THROTTLING "intr_throttling" 234 #define PROP_FM_CAPABLE "fm_capable" 235 236 #define IXGBE_LB_NONE 0 237 #define IXGBE_LB_EXTERNAL 1 238 #define IXGBE_LB_INTERNAL_MAC 2 239 #define IXGBE_LB_INTERNAL_PHY 3 240 #define IXGBE_LB_INTERNAL_SERDES 4 241 242 /* 243 * capability/feature flags 244 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 245 * Separately, the flag named _ENABLED is set when the feature is enabled. 246 */ 247 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 248 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 249 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 250 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 251 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 252 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 253 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 254 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 255 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 256 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9) 257 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10) 258 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11) 259 260 /* 261 * Classification mode 262 */ 263 #define IXGBE_CLASSIFY_NONE 0 264 #define IXGBE_CLASSIFY_RSS 1 265 #define IXGBE_CLASSIFY_VMDQ 2 266 #define IXGBE_CLASSIFY_VMDQ_RSS 3 267 268 /* adapter-specific info for each supported device type */ 269 typedef struct adapter_info { 270 uint32_t max_rx_que_num; /* maximum number of rx queues */ 271 uint32_t min_rx_que_num; /* minimum number of rx queues */ 272 uint32_t def_rx_que_num; /* default number of rx queues */ 273 uint32_t max_rx_grp_num; /* maximum number of rx groups */ 274 uint32_t min_rx_grp_num; /* minimum number of rx groups */ 275 uint32_t def_rx_grp_num; /* default number of rx groups */ 276 uint32_t max_tx_que_num; /* maximum number of tx queues */ 277 uint32_t min_tx_que_num; /* minimum number of tx queues */ 278 uint32_t def_tx_que_num; /* default number of tx queues */ 279 uint32_t max_mtu; /* maximum MTU size */ 280 /* 281 * Interrupt throttling is in unit of 256 nsec 282 */ 283 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 284 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 285 uint32_t def_intr_throttle; /* default interrupt throttle */ 286 287 uint32_t max_msix_vect; /* maximum total msix vectors */ 288 uint32_t max_ring_vect; /* maximum number of ring vectors */ 289 uint32_t max_other_vect; /* maximum number of other vectors */ 290 uint32_t other_intr; /* "other" interrupt types handled */ 291 uint32_t other_gpie; /* "other" interrupt types enabling */ 292 uint32_t flags; /* capability flags */ 293 } adapter_info_t; 294 295 /* bits representing all interrupt types other than tx & rx */ 296 #define IXGBE_OTHER_INTR 0x3ff00000 297 #define IXGBE_82599_OTHER_INTR 0x86100000 298 299 enum ioc_reply { 300 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 301 IOC_DONE, /* OK, reply sent */ 302 IOC_ACK, /* OK, just send ACK */ 303 IOC_REPLY /* OK, just send reply */ 304 }; 305 306 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 307 0, 0, (flag))) 308 309 /* 310 * Defined for ring index operations 311 * ASSERT(index < limit) 312 * ASSERT(step < limit) 313 * ASSERT(index1 < limit) 314 * ASSERT(index2 < limit) 315 */ 316 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 317 (index) + (step) : (index) + (step) - (limit)) 318 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 319 (index) - (step) : (index) + (limit) - (step)) 320 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 321 (index2) - (index1) : (index2) + (limit) - (index1)) 322 323 #define LINK_LIST_INIT(_LH) \ 324 (_LH)->head = (_LH)->tail = NULL 325 326 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 327 328 #define LIST_POP_HEAD(_LH) \ 329 (single_link_t *)(_LH)->head; \ 330 { \ 331 if ((_LH)->head != NULL) { \ 332 (_LH)->head = (_LH)->head->link; \ 333 if ((_LH)->head == NULL) \ 334 (_LH)->tail = NULL; \ 335 } \ 336 } 337 338 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 339 340 #define LIST_PUSH_TAIL(_LH, _E) \ 341 if ((_LH)->tail != NULL) { \ 342 (_LH)->tail->link = (single_link_t *)(_E); \ 343 (_LH)->tail = (single_link_t *)(_E); \ 344 } else { \ 345 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 346 } \ 347 (_E)->link = NULL; 348 349 #define LIST_GET_NEXT(_LH, _E) \ 350 (((_LH)->tail == (single_link_t *)(_E)) ? \ 351 NULL : ((single_link_t *)(_E))->link) 352 353 354 typedef struct single_link { 355 struct single_link *link; 356 } single_link_t; 357 358 typedef struct link_list { 359 single_link_t *head; 360 single_link_t *tail; 361 } link_list_t; 362 363 /* 364 * Property lookups 365 */ 366 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 367 DDI_PROP_DONTPASS, (n)) 368 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 369 DDI_PROP_DONTPASS, (n), -1) 370 371 372 typedef union ixgbe_ether_addr { 373 struct { 374 uint32_t high; 375 uint32_t low; 376 } reg; 377 struct { 378 uint8_t set; 379 uint8_t group_index; 380 uint8_t addr[ETHERADDRL]; 381 } mac; 382 } ixgbe_ether_addr_t; 383 384 typedef enum { 385 USE_NONE, 386 USE_COPY, 387 USE_DMA 388 } tx_type_t; 389 390 typedef struct ixgbe_tx_context { 391 uint32_t hcksum_flags; 392 uint32_t ip_hdr_len; 393 uint32_t mac_hdr_len; 394 uint32_t l4_proto; 395 uint32_t mss; 396 uint32_t l4_hdr_len; 397 boolean_t lso_flag; 398 } ixgbe_tx_context_t; 399 400 /* 401 * Hold address/length of each DMA segment 402 */ 403 typedef struct sw_desc { 404 uint64_t address; 405 size_t length; 406 } sw_desc_t; 407 408 /* 409 * Handles and addresses of DMA buffer 410 */ 411 typedef struct dma_buffer { 412 caddr_t address; /* Virtual address */ 413 uint64_t dma_address; /* DMA (Hardware) address */ 414 ddi_acc_handle_t acc_handle; /* Data access handle */ 415 ddi_dma_handle_t dma_handle; /* DMA handle */ 416 size_t size; /* Buffer size */ 417 size_t len; /* Data length in the buffer */ 418 } dma_buffer_t; 419 420 /* 421 * Tx Control Block 422 */ 423 typedef struct tx_control_block { 424 single_link_t link; 425 uint32_t last_index; /* last descriptor of the pkt */ 426 uint32_t frag_num; 427 uint32_t desc_num; 428 mblk_t *mp; 429 tx_type_t tx_type; 430 ddi_dma_handle_t tx_dma_handle; 431 dma_buffer_t tx_buf; 432 sw_desc_t desc[MAX_COOKIE]; 433 } tx_control_block_t; 434 435 /* 436 * RX Control Block 437 */ 438 typedef struct rx_control_block { 439 mblk_t *mp; 440 uint32_t ref_cnt; 441 dma_buffer_t rx_buf; 442 frtn_t free_rtn; 443 struct ixgbe_rx_data *rx_data; 444 int lro_next; /* Index of next rcb */ 445 int lro_prev; /* Index of previous rcb */ 446 boolean_t lro_pkt; /* Flag for LRO rcb */ 447 } rx_control_block_t; 448 449 /* 450 * Software Data Structure for Tx Ring 451 */ 452 typedef struct ixgbe_tx_ring { 453 uint32_t index; /* Ring index */ 454 uint32_t intr_vector; /* Interrupt vector index */ 455 uint32_t vect_bit; /* vector's bit in register */ 456 457 /* 458 * Mutexes 459 */ 460 kmutex_t tx_lock; 461 kmutex_t recycle_lock; 462 kmutex_t tcb_head_lock; 463 kmutex_t tcb_tail_lock; 464 465 /* 466 * Tx descriptor ring definitions 467 */ 468 dma_buffer_t tbd_area; 469 union ixgbe_adv_tx_desc *tbd_ring; 470 uint32_t tbd_head; /* Index of next tbd to recycle */ 471 uint32_t tbd_tail; /* Index of next tbd to transmit */ 472 uint32_t tbd_free; /* Number of free tbd */ 473 474 /* 475 * Tx control block list definitions 476 */ 477 tx_control_block_t *tcb_area; 478 tx_control_block_t **work_list; 479 tx_control_block_t **free_list; 480 uint32_t tcb_head; /* Head index of free list */ 481 uint32_t tcb_tail; /* Tail index of free list */ 482 uint32_t tcb_free; /* Number of free tcb in free list */ 483 484 uint32_t *tbd_head_wb; /* Head write-back */ 485 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 486 487 /* 488 * s/w context structure for TCP/UDP checksum offload 489 * and LSO. 490 */ 491 ixgbe_tx_context_t tx_context; 492 493 /* 494 * Tx ring settings and status 495 */ 496 uint32_t ring_size; /* Tx descriptor ring size */ 497 uint32_t free_list_size; /* Tx free list size */ 498 499 boolean_t reschedule; 500 uint32_t recycle_fail; 501 uint32_t stall_watchdog; 502 503 #ifdef IXGBE_DEBUG 504 /* 505 * Debug statistics 506 */ 507 uint32_t stat_overload; 508 uint32_t stat_fail_no_tbd; 509 uint32_t stat_fail_no_tcb; 510 uint32_t stat_fail_dma_bind; 511 uint32_t stat_reschedule; 512 uint32_t stat_break_tbd_limit; 513 uint32_t stat_lso_header_fail; 514 #endif 515 uint64_t stat_obytes; 516 uint64_t stat_opackets; 517 518 mac_ring_handle_t ring_handle; 519 520 /* 521 * Pointer to the ixgbe struct 522 */ 523 struct ixgbe *ixgbe; 524 } ixgbe_tx_ring_t; 525 526 /* 527 * Software Receive Ring 528 */ 529 typedef struct ixgbe_rx_data { 530 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 531 532 /* 533 * Rx descriptor ring definitions 534 */ 535 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 536 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 537 uint32_t rbd_next; /* Index of next rx desc */ 538 539 /* 540 * Rx control block list definitions 541 */ 542 rx_control_block_t *rcb_area; 543 rx_control_block_t **work_list; /* Work list of rcbs */ 544 rx_control_block_t **free_list; /* Free list of rcbs */ 545 uint32_t rcb_head; /* Index of next free rcb */ 546 uint32_t rcb_tail; /* Index to put recycled rcb */ 547 uint32_t rcb_free; /* Number of free rcbs */ 548 549 /* 550 * Rx sw ring settings and status 551 */ 552 uint32_t ring_size; /* Rx descriptor ring size */ 553 uint32_t free_list_size; /* Rx free list size */ 554 555 uint32_t rcb_pending; 556 uint32_t flag; 557 558 uint32_t lro_num; /* Number of rcbs of one LRO */ 559 uint32_t lro_first; /* Index of first LRO rcb */ 560 561 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 562 } ixgbe_rx_data_t; 563 564 /* 565 * Software Data Structure for Rx Ring 566 */ 567 typedef struct ixgbe_rx_ring { 568 uint32_t index; /* Ring index */ 569 uint32_t group_index; /* Group index */ 570 uint32_t hw_index; /* h/w ring index */ 571 uint32_t intr_vector; /* Interrupt vector index */ 572 uint32_t vect_bit; /* vector's bit in register */ 573 574 ixgbe_rx_data_t *rx_data; /* Rx software ring */ 575 576 kmutex_t rx_lock; /* Rx access lock */ 577 578 #ifdef IXGBE_DEBUG 579 /* 580 * Debug statistics 581 */ 582 uint32_t stat_frame_error; 583 uint32_t stat_cksum_error; 584 uint32_t stat_exceed_pkt; 585 #endif 586 uint64_t stat_rbytes; 587 uint64_t stat_ipackets; 588 589 mac_ring_handle_t ring_handle; 590 uint64_t ring_gen_num; 591 592 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 593 } ixgbe_rx_ring_t; 594 /* 595 * Software Receive Ring Group 596 */ 597 typedef struct ixgbe_rx_group { 598 uint32_t index; /* Group index */ 599 mac_group_handle_t group_handle; /* call back group handle */ 600 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 601 } ixgbe_rx_group_t; 602 603 /* 604 * structure to map interrupt cleanup to msi-x vector 605 */ 606 typedef struct ixgbe_intr_vector { 607 struct ixgbe *ixgbe; /* point to my adapter */ 608 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 609 int rxr_cnt; /* count rx rings */ 610 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 611 int txr_cnt; /* count tx rings */ 612 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 613 int other_cnt; /* count other interrupt */ 614 } ixgbe_intr_vector_t; 615 616 /* 617 * Software adapter state 618 */ 619 typedef struct ixgbe { 620 int instance; 621 mac_handle_t mac_hdl; 622 dev_info_t *dip; 623 struct ixgbe_hw hw; 624 struct ixgbe_osdep osdep; 625 626 adapter_info_t *capab; /* adapter hardware capabilities */ 627 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 628 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */ 629 uint32_t eims; /* interrupt mask setting */ 630 uint32_t eimc; /* interrupt mask clear */ 631 uint32_t eicr; /* interrupt cause reg */ 632 633 uint32_t ixgbe_state; 634 link_state_t link_state; 635 uint32_t link_speed; 636 uint32_t link_duplex; 637 638 uint32_t reset_count; 639 uint32_t attach_progress; 640 uint32_t loopback_mode; 641 uint32_t default_mtu; 642 uint32_t max_frame_size; 643 644 uint32_t rcb_pending; 645 646 /* 647 * Each msi-x vector: map vector to interrupt cleanup 648 */ 649 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 650 651 /* 652 * Receive Rings 653 */ 654 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 655 uint32_t num_rx_rings; /* Number of rx rings in use */ 656 uint32_t rx_ring_size; /* Rx descriptor ring size */ 657 uint32_t rx_buf_size; /* Rx buffer size */ 658 boolean_t lro_enable; /* Large Receive Offload */ 659 uint64_t lro_pkt_count; /* LRO packet count */ 660 /* 661 * Receive Groups 662 */ 663 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 664 uint32_t num_rx_groups; /* Number of rx groups in use */ 665 666 /* 667 * Transmit Rings 668 */ 669 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 670 uint32_t num_tx_rings; /* Number of tx rings in use */ 671 uint32_t tx_ring_size; /* Tx descriptor ring size */ 672 uint32_t tx_buf_size; /* Tx buffer size */ 673 674 boolean_t tx_ring_init; 675 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 676 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 677 boolean_t lso_enable; /* Large Segment Offload */ 678 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 679 boolean_t relax_order_enable; /* Relax Order */ 680 uint32_t classify_mode; /* Classification mode */ 681 uint32_t tx_copy_thresh; /* Tx copy threshold */ 682 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 683 uint32_t tx_overload_thresh; /* Tx overload threshold */ 684 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 685 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 686 uint32_t rx_copy_thresh; /* Rx copy threshold */ 687 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 688 uint32_t intr_throttling[MAX_INTR_VECTOR]; 689 uint32_t intr_force; 690 int fm_capabilities; /* FMA capabilities */ 691 692 int intr_type; 693 int intr_cnt; 694 uint32_t intr_cnt_max; 695 uint32_t intr_cnt_min; 696 int intr_cap; 697 size_t intr_size; 698 uint_t intr_pri; 699 ddi_intr_handle_t *htable; 700 uint32_t eims_mask; 701 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */ 702 703 kmutex_t gen_lock; /* General lock for device access */ 704 kmutex_t watchdog_lock; 705 kmutex_t rx_pending_lock; 706 707 boolean_t watchdog_enable; 708 boolean_t watchdog_start; 709 timeout_id_t watchdog_tid; 710 711 boolean_t unicst_init; 712 uint32_t unicst_avail; 713 uint32_t unicst_total; 714 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 715 uint32_t mcast_count; 716 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 717 718 ulong_t sys_page_size; 719 720 boolean_t link_check_complete; 721 hrtime_t link_check_hrtime; 722 ddi_periodic_t periodic_id; /* for link check timer func */ 723 724 /* 725 * Kstat definitions 726 */ 727 kstat_t *ixgbe_ks; 728 729 uint32_t param_en_10000fdx_cap:1, 730 param_en_1000fdx_cap:1, 731 param_en_100fdx_cap:1, 732 param_adv_10000fdx_cap:1, 733 param_adv_1000fdx_cap:1, 734 param_adv_100fdx_cap:1, 735 param_pause_cap:1, 736 param_asym_pause_cap:1, 737 param_rem_fault:1, 738 param_adv_autoneg_cap:1, 739 param_adv_pause_cap:1, 740 param_adv_asym_pause_cap:1, 741 param_adv_rem_fault:1, 742 param_lp_10000fdx_cap:1, 743 param_lp_1000fdx_cap:1, 744 param_lp_100fdx_cap:1, 745 param_lp_autoneg_cap:1, 746 param_lp_pause_cap:1, 747 param_lp_asym_pause_cap:1, 748 param_lp_rem_fault:1, 749 param_pad_to_32:12; 750 } ixgbe_t; 751 752 typedef struct ixgbe_stat { 753 kstat_named_t link_speed; /* Link Speed */ 754 755 kstat_named_t reset_count; /* Reset Count */ 756 757 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 758 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 759 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 760 761 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 762 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 763 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 764 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 765 kstat_named_t tx_reschedule; /* Tx Reschedule */ 766 767 kstat_named_t gprc; /* Good Packets Received Count */ 768 kstat_named_t gptc; /* Good Packets Xmitted Count */ 769 kstat_named_t gor; /* Good Octets Received Count */ 770 kstat_named_t got; /* Good Octets Xmitd Count */ 771 kstat_named_t prc64; /* Packets Received - 64b */ 772 kstat_named_t prc127; /* Packets Received - 65-127b */ 773 kstat_named_t prc255; /* Packets Received - 127-255b */ 774 kstat_named_t prc511; /* Packets Received - 256-511b */ 775 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 776 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 777 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 778 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 779 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 780 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 781 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 782 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 783 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 784 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 785 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 786 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 787 788 kstat_named_t crcerrs; /* CRC Error Count */ 789 kstat_named_t illerrc; /* Illegal Byte Error Count */ 790 kstat_named_t errbc; /* Error Byte Count */ 791 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 792 kstat_named_t mpc; /* Missed Packets Count */ 793 kstat_named_t mlfc; /* MAC Local Fault Count */ 794 kstat_named_t mrfc; /* MAC Remote Fault Count */ 795 kstat_named_t rlec; /* Receive Length Error Count */ 796 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 797 kstat_named_t lxonrxc; /* Link XON Received Count */ 798 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 799 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 800 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 801 kstat_named_t mprc; /* Multicast Pkts Received Count */ 802 kstat_named_t rnbc; /* Receive No Buffers Count */ 803 kstat_named_t ruc; /* Receive Undersize Count */ 804 kstat_named_t rfc; /* Receive Frag Count */ 805 kstat_named_t roc; /* Receive Oversize Count */ 806 kstat_named_t rjc; /* Receive Jabber Count */ 807 kstat_named_t tor; /* Total Octets Recvd Count */ 808 kstat_named_t tot; /* Total Octets Xmitted Count */ 809 kstat_named_t tpr; /* Total Packets Received */ 810 kstat_named_t tpt; /* Total Packets Xmitted */ 811 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 812 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 813 kstat_named_t lroc; /* LRO Packets Received Count */ 814 } ixgbe_stat_t; 815 816 /* 817 * Function prototypes in ixgbe_buf.c 818 */ 819 int ixgbe_alloc_dma(ixgbe_t *); 820 void ixgbe_free_dma(ixgbe_t *); 821 void ixgbe_set_fma_flags(int); 822 void ixgbe_free_dma_buffer(dma_buffer_t *); 823 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 824 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 825 826 /* 827 * Function prototypes in ixgbe_main.c 828 */ 829 int ixgbe_start(ixgbe_t *, boolean_t); 830 void ixgbe_stop(ixgbe_t *, boolean_t); 831 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 832 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 833 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 834 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 835 836 void ixgbe_enable_watchdog_timer(ixgbe_t *); 837 void ixgbe_disable_watchdog_timer(ixgbe_t *); 838 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 839 840 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 841 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 842 void ixgbe_fm_ereport(ixgbe_t *, char *); 843 844 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 845 mac_ring_info_t *, mac_ring_handle_t); 846 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 847 mac_group_info_t *, mac_group_handle_t); 848 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 849 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 850 851 /* 852 * Function prototypes in ixgbe_gld.c 853 */ 854 int ixgbe_m_start(void *); 855 void ixgbe_m_stop(void *); 856 int ixgbe_m_promisc(void *, boolean_t); 857 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 858 void ixgbe_m_resources(void *); 859 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 860 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 861 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 862 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 863 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t, 864 mac_prop_info_handle_t); 865 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 866 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *); 867 boolean_t ixgbe_param_locked(mac_prop_id_t); 868 869 /* 870 * Function prototypes in ixgbe_rx.c 871 */ 872 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 873 void ixgbe_rx_recycle(caddr_t arg); 874 mblk_t *ixgbe_ring_rx_poll(void *, int); 875 876 /* 877 * Function prototypes in ixgbe_tx.c 878 */ 879 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 880 void ixgbe_free_tcb(tx_control_block_t *); 881 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 882 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 883 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 884 885 /* 886 * Function prototypes in ixgbe_log.c 887 */ 888 void ixgbe_notice(void *, const char *, ...); 889 void ixgbe_log(void *, const char *, ...); 890 void ixgbe_error(void *, const char *, ...); 891 892 /* 893 * Function prototypes in ixgbe_stat.c 894 */ 895 int ixgbe_init_stats(ixgbe_t *); 896 int ixgbe_m_stat(void *, uint_t, uint64_t *); 897 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 898 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 899 900 #ifdef __cplusplus 901 } 902 #endif 903 904 #endif /* _IXGBE_SW_H */ 905