1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at: 9 * http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When using or redistributing this file, you may do so under the 14 * License only. No other modification of this header is permitted. 15 * 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 29 */ 30 31 /* IntelVersion: 1.43 scm_061610_003709 */ 32 33 #ifndef _IXGBE_PHY_H 34 #define _IXGBE_PHY_H 35 36 #include "ixgbe_type.h" 37 38 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 39 40 /* EEPROM byte offsets */ 41 #define IXGBE_SFF_IDENTIFIER 0x0 42 #define IXGBE_SFF_IDENTIFIER_SFP 0x3 43 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 44 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 45 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 46 #define IXGBE_SFF_1GBE_COMP_CODES 0x6 47 #define IXGBE_SFF_10GBE_COMP_CODES 0x3 48 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 49 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 50 51 /* Bitmasks */ 52 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 53 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 54 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 55 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 56 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 57 #define IXGBE_SFF_1GBASET_CAPABLE 0x8 58 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 59 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 60 #define IXGBE_I2C_EEPROM_READ_MASK 0x100 61 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 62 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 63 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 64 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 65 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 66 67 /* Flow control defines */ 68 #define IXGBE_TAF_SYM_PAUSE 0x400 69 #define IXGBE_TAF_ASM_PAUSE 0x800 70 71 /* Bit-shift macros */ 72 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 73 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 74 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 75 76 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 77 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 78 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 79 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 80 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 81 82 /* I2C SDA and SCL timing parameters for standard mode */ 83 #define IXGBE_I2C_T_HD_STA 4 84 #define IXGBE_I2C_T_LOW 5 85 #define IXGBE_I2C_T_HIGH 4 86 #define IXGBE_I2C_T_SU_STA 5 87 #define IXGBE_I2C_T_HD_DATA 5 88 #define IXGBE_I2C_T_SU_DATA 1 89 #define IXGBE_I2C_T_RISE 1 90 #define IXGBE_I2C_T_FALL 1 91 #define IXGBE_I2C_T_SU_STO 4 92 #define IXGBE_I2C_T_BUF 5 93 94 #define IXGBE_TN_LASI_STATUS_REG 0x9005 95 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 96 97 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 98 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 99 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 100 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 101 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 102 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 103 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 104 u32 device_type, u16 *phy_data); 105 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 106 u32 device_type, u16 phy_data); 107 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 108 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 109 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 110 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 111 ixgbe_link_speed *speed, bool *autoneg); 112 113 /* PHY specific */ 114 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 115 ixgbe_link_speed *speed, bool *link_up); 116 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); 117 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 118 u16 *firmware_version); 119 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 120 u16 *firmware_version); 121 122 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 123 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 124 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 125 u16 *list_offset, u16 *data_offset); 126 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); 127 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 128 u8 dev_addr, u8 *data); 129 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 130 u8 dev_addr, u8 data); 131 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 132 u8 *eeprom_data); 133 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 134 u8 eeprom_data); 135 136 #endif /* _IXGBE_PHY_H */ 137