1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.27 v2008-09-12 */ 30 31 #ifndef _IXGBE_PHY_H 32 #define _IXGBE_PHY_H 33 34 #include "ixgbe_type.h" 35 36 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 37 38 /* EEPROM byte offsets */ 39 #define IXGBE_SFF_IDENTIFIER 0x0 40 #define IXGBE_SFF_IDENTIFIER_SFP 0x3 41 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 42 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 43 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 44 #define IXGBE_SFF_1GBE_COMP_CODES 0x6 45 #define IXGBE_SFF_10GBE_COMP_CODES 0x3 46 #define IXGBE_SFF_TRANSMISSION_MEDIA 0x9 47 48 /* Bitmasks */ 49 #define IXGBE_SFF_TWIN_AX_CAPABLE 0x80 50 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 51 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 52 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 53 #define IXGBE_I2C_EEPROM_READ_MASK 0x100 54 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 55 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 56 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 57 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 58 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 59 60 /* Bit-shift macros */ 61 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12 62 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8 63 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4 64 65 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 66 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 67 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 68 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 69 70 #ident "$Id: ixgbe_phy.h,v 1.27 2008/09/02 18:20:19 mrchilak Exp $" 71 72 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 73 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 74 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 75 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 76 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 77 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 78 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 79 u32 device_type, u16 *phy_data); 80 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 81 u32 device_type, u16 phy_data); 82 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 83 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 84 ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); 85 86 /* PHY specific */ 87 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 88 ixgbe_link_speed *speed, bool *link_up); 89 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 90 u16 *firmware_version); 91 92 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 93 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 94 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 95 u16 *list_offset, u16 *data_offset); 96 97 #endif /* _IXGBE_PHY_H */ 98