1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.60 v2008-09-12 */ 30 31 #include "ixgbe_api.h" 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 #ident "$Id: ixgbe_phy.c,v 1.60 2008/09/15 15:47:02 mrchilak Exp $" 35 36 /* 37 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 38 * @hw: pointer to the hardware structure 39 * 40 * Initialize the function pointers. 41 */ 42 s32 43 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 44 { 45 struct ixgbe_phy_info *phy = &hw->phy; 46 47 /* PHY */ 48 phy->ops.identify = &ixgbe_identify_phy_generic; 49 phy->ops.reset = &ixgbe_reset_phy_generic; 50 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 51 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 52 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 53 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 54 phy->ops.check_link = NULL; 55 phy->ops.get_firmware_version = NULL; 56 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 57 phy->sfp_type = ixgbe_sfp_type_unknown; 58 59 return (IXGBE_SUCCESS); 60 } 61 62 /* 63 * ixgbe_identify_phy_generic - Get physical layer module 64 * @hw: pointer to hardware structure 65 * 66 * Determines the physical layer module found on the current adapter. 67 */ 68 s32 69 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 70 { 71 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 72 u32 phy_addr; 73 74 if (hw->phy.type == ixgbe_phy_unknown) { 75 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 76 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 77 hw->phy.addr = phy_addr; 78 (void) ixgbe_get_phy_id(hw); 79 hw->phy.type = 80 ixgbe_get_phy_type_from_id(hw->phy.id); 81 status = IXGBE_SUCCESS; 82 break; 83 } 84 } 85 } else { 86 status = IXGBE_SUCCESS; 87 } 88 89 return (status); 90 } 91 92 /* 93 * ixgbe_validate_phy_addr - Determines phy address is valid 94 * @hw: pointer to hardware structure 95 * 96 */ 97 bool 98 ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 99 { 100 u16 phy_id = 0; 101 bool valid = false; 102 103 hw->phy.addr = phy_addr; 104 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 105 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 106 107 if (phy_id != 0xFFFF && phy_id != 0x0) 108 valid = true; 109 110 return (valid); 111 } 112 113 /* 114 * ixgbe_get_phy_id - Get the phy type 115 * @hw: pointer to hardware structure 116 * 117 */ 118 s32 119 ixgbe_get_phy_id(struct ixgbe_hw *hw) 120 { 121 u32 status; 122 u16 phy_id_high = 0; 123 u16 phy_id_low = 0; 124 125 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 126 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 127 &phy_id_high); 128 129 if (status == IXGBE_SUCCESS) { 130 hw->phy.id = (u32)(phy_id_high << 16); 131 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 132 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 133 &phy_id_low); 134 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 135 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 136 } 137 138 return (status); 139 } 140 141 /* 142 * ixgbe_get_phy_type_from_id - Get the phy type 143 * @hw: pointer to hardware structure 144 * 145 */ 146 enum ixgbe_phy_type 147 ixgbe_get_phy_type_from_id(u32 phy_id) 148 { 149 enum ixgbe_phy_type phy_type; 150 151 switch (phy_id) { 152 case TN1010_PHY_ID: 153 phy_type = ixgbe_phy_tn; 154 break; 155 case QT2022_PHY_ID: 156 phy_type = ixgbe_phy_qt; 157 break; 158 case ATH_PHY_ID: 159 phy_type = ixgbe_phy_nl; 160 break; 161 default: 162 phy_type = ixgbe_phy_unknown; 163 break; 164 } 165 166 DEBUGOUT1("phy type found is %d\n", phy_type); 167 168 return (phy_type); 169 } 170 171 /* 172 * ixgbe_reset_phy_generic - Performs a PHY reset 173 * @hw: pointer to hardware structure 174 */ 175 s32 176 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 177 { 178 /* 179 * Perform soft PHY reset to the PHY_XS. 180 * This will cause a soft reset to the PHY 181 */ 182 return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 183 IXGBE_MDIO_PHY_XS_DEV_TYPE, 184 IXGBE_MDIO_PHY_XS_RESET); 185 } 186 187 /* 188 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 189 * @hw: pointer to hardware structure 190 * @reg_addr: 32 bit address of PHY register to read 191 * @phy_data: Pointer to read data from PHY register 192 */ 193 s32 194 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 195 u32 device_type, u16 *phy_data) 196 { 197 u32 command; 198 u32 i; 199 u32 data; 200 s32 status = IXGBE_SUCCESS; 201 u16 gssr; 202 203 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 204 gssr = IXGBE_GSSR_PHY1_SM; 205 else 206 gssr = IXGBE_GSSR_PHY0_SM; 207 208 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 209 status = IXGBE_ERR_SWFW_SYNC; 210 211 if (status == IXGBE_SUCCESS) { 212 /* Setup and write the address cycle command */ 213 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 214 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 215 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 216 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 217 218 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 219 220 /* 221 * Check every 10 usec to see if the address cycle completed. 222 * The MDI Command bit will clear when the operation is 223 * complete 224 */ 225 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 226 usec_delay(10); 227 228 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 229 230 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 231 break; 232 } 233 } 234 235 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 236 DEBUGOUT("PHY address command did not complete.\n"); 237 status = IXGBE_ERR_PHY; 238 } 239 240 if (status == IXGBE_SUCCESS) { 241 /* 242 * Address cycle complete, setup and write the read 243 * command 244 */ 245 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 246 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 247 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 248 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 249 250 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 251 252 /* 253 * Check every 10 usec to see if the address cycle 254 * completed. The MDI Command bit will clear when the 255 * operation is complete 256 */ 257 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 258 usec_delay(10); 259 260 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 261 262 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 263 break; 264 } 265 266 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 267 DEBUGOUT("PHY read command didn't complete\n"); 268 status = IXGBE_ERR_PHY; 269 } else { 270 /* 271 * Read operation is complete. Get the data 272 * from MSRWD 273 */ 274 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 275 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 276 *phy_data = (u16)(data); 277 } 278 } 279 280 ixgbe_release_swfw_sync(hw, gssr); 281 } 282 283 return (status); 284 } 285 286 /* 287 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 288 * @hw: pointer to hardware structure 289 * @reg_addr: 32 bit PHY register to write 290 * @device_type: 5 bit device type 291 * @phy_data: Data to write to the PHY register 292 */ 293 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 294 u32 device_type, u16 phy_data) 295 { 296 u32 command; 297 u32 i; 298 s32 status = IXGBE_SUCCESS; 299 u16 gssr; 300 301 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 302 gssr = IXGBE_GSSR_PHY1_SM; 303 else 304 gssr = IXGBE_GSSR_PHY0_SM; 305 306 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 307 status = IXGBE_ERR_SWFW_SYNC; 308 309 if (status == IXGBE_SUCCESS) { 310 /* 311 * Put the data in the MDI single read and write data register 312 */ 313 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 314 315 /* Setup and write the address cycle command */ 316 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 317 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 318 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 319 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 320 321 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 322 323 /* 324 * Check every 10 usec to see if the address cycle completed. 325 * The MDI Command bit will clear when the operation is 326 * complete 327 */ 328 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 329 usec_delay(10); 330 331 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 332 333 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 334 break; 335 } 336 337 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 338 DEBUGOUT("PHY address cmd didn't complete\n"); 339 status = IXGBE_ERR_PHY; 340 } 341 342 if (status == IXGBE_SUCCESS) { 343 /* 344 * Address cycle complete, setup and write the write 345 * command 346 */ 347 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 348 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 350 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 351 352 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 353 354 /* 355 * Check every 10 usec to see if the address cycle 356 * completed. The MDI Command bit will clear when the 357 * operation is complete 358 */ 359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 360 usec_delay(10); 361 362 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 363 364 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 365 break; 366 } 367 368 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 369 DEBUGOUT("PHY address cmd didn't complete\n"); 370 status = IXGBE_ERR_PHY; 371 } 372 } 373 374 ixgbe_release_swfw_sync(hw, gssr); 375 } 376 377 return (status); 378 } 379 380 /* 381 * ixgbe_setup_phy_link_generic - Set and restart autoneg 382 * @hw: pointer to hardware structure 383 * 384 * Restart autonegotiation and PHY and waits for completion. 385 */ 386 s32 387 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 388 { 389 s32 status = IXGBE_NOT_IMPLEMENTED; 390 u32 time_out; 391 u32 max_time_out = 10; 392 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 393 394 /* 395 * Set advertisement settings in PHY based on autoneg_advertised 396 * settings. If autoneg_advertised = 0, then advertise default values 397 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 398 * for a 1G. 399 */ 400 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 401 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 402 403 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 404 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 405 else 406 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 407 408 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 409 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 410 411 /* Restart PHY autonegotiation and wait for completion */ 412 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 413 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 414 415 autoneg_reg |= IXGBE_MII_RESTART; 416 417 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 418 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 419 420 /* Wait for autonegotiation to finish */ 421 for (time_out = 0; time_out < max_time_out; time_out++) { 422 usec_delay(10); 423 /* Restart PHY autonegotiation and wait for completion */ 424 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 425 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 426 &autoneg_reg); 427 428 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 429 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 430 status = IXGBE_SUCCESS; 431 break; 432 } 433 } 434 435 if (time_out == max_time_out) 436 status = IXGBE_ERR_LINK_SETUP; 437 438 return (status); 439 } 440 441 /* 442 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 443 * @hw: pointer to hardware structure 444 * @speed: new link speed 445 * @autoneg: true if autonegotiation enabled 446 */ 447 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 448 ixgbe_link_speed speed, 449 bool autoneg, 450 bool autoneg_wait_to_complete) 451 { 452 UNREFERENCED_PARAMETER(autoneg); 453 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 454 455 /* 456 * Clear autoneg_advertised and set new values based on input link 457 * speed. 458 */ 459 hw->phy.autoneg_advertised = 0; 460 461 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 462 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 463 } 464 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 465 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 466 } 467 468 /* Setup link based on the new speed settings */ 469 hw->phy.ops.setup_link(hw); 470 471 return (IXGBE_SUCCESS); 472 } 473 474 /* 475 * ixgbe_check_phy_link_tnx - Determine link and speed status 476 * @hw: pointer to hardware structure 477 * 478 * Reads the VS1 register to determine if link is up and the current speed for 479 * the PHY. 480 */ 481 s32 482 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 483 bool *link_up) 484 { 485 s32 status = IXGBE_SUCCESS; 486 u32 time_out; 487 u32 max_time_out = 10; 488 u16 phy_link = 0; 489 u16 phy_speed = 0; 490 u16 phy_data = 0; 491 492 /* Initialize speed and link to default case */ 493 *link_up = false; 494 *speed = IXGBE_LINK_SPEED_10GB_FULL; 495 496 /* 497 * Check current speed and link status of the PHY register. 498 * This is a vendor specific register and may have to 499 * be changed for other copper PHYs. 500 */ 501 for (time_out = 0; time_out < max_time_out; time_out++) { 502 usec_delay(10); 503 status = hw->phy.ops.read_reg(hw, 504 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 505 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 506 &phy_data); 507 phy_link = phy_data & 508 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 509 phy_speed = phy_data & 510 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 511 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 512 *link_up = true; 513 if (phy_speed == 514 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 515 *speed = IXGBE_LINK_SPEED_1GB_FULL; 516 break; 517 } 518 } 519 520 return (status); 521 } 522 523 /* 524 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 525 * @hw: pointer to hardware structure 526 * @firmware_version: pointer to the PHY Firmware Version 527 */ 528 s32 529 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version) 530 { 531 s32 status = IXGBE_SUCCESS; 532 533 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 534 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 535 536 return (status); 537 } 538 539 /* 540 * ixgbe_reset_phy_nl - Performs a PHY reset 541 * @hw: pointer to hardware structure 542 */ 543 s32 544 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 545 { 546 u16 phy_offset, control, eword, edata, block_crc; 547 bool end_data = false; 548 u16 list_offset, data_offset; 549 u16 phy_data = 0; 550 s32 ret_val = IXGBE_SUCCESS; 551 u32 i; 552 553 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 554 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 555 556 /* reset the PHY and poll for completion */ 557 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 558 IXGBE_MDIO_PHY_XS_DEV_TYPE, 559 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 560 561 for (i = 0; i < 100; i++) { 562 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 563 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 564 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 565 break; 566 msec_delay(10); 567 } 568 569 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 570 DEBUGOUT("PHY reset did not complete.\n"); 571 ret_val = IXGBE_ERR_PHY; 572 goto out; 573 } 574 575 /* Get init offsets */ 576 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 577 &data_offset); 578 if (ret_val != IXGBE_SUCCESS) 579 goto out; 580 581 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 582 data_offset++; 583 while (!end_data) { 584 /* 585 * Read control word from PHY init contents offset 586 */ 587 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 588 control = (eword & IXGBE_CONTROL_MASK_NL) >> 589 IXGBE_CONTROL_SHIFT_NL; 590 edata = eword & IXGBE_DATA_MASK_NL; 591 switch (control) { 592 case IXGBE_DELAY_NL: 593 data_offset++; 594 DEBUGOUT1("DELAY: %d MS\n", edata); 595 msec_delay(edata); 596 break; 597 case IXGBE_DATA_NL: 598 DEBUGOUT("DATA: \n"); 599 data_offset++; 600 hw->eeprom.ops.read(hw, data_offset++, &phy_offset); 601 for (i = 0; i < edata; i++) { 602 hw->eeprom.ops.read(hw, data_offset, &eword); 603 hw->phy.ops.write_reg(hw, phy_offset, 604 IXGBE_TWINAX_DEV, eword); 605 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 606 phy_offset); 607 data_offset++; 608 phy_offset++; 609 } 610 break; 611 case IXGBE_CONTROL_NL: 612 data_offset++; 613 DEBUGOUT("CONTROL: \n"); 614 if (edata == IXGBE_CONTROL_EOL_NL) { 615 DEBUGOUT("EOL\n"); 616 end_data = true; 617 } else if (edata == IXGBE_CONTROL_SOL_NL) { 618 DEBUGOUT("SOL\n"); 619 } else { 620 DEBUGOUT("Bad control value\n"); 621 ret_val = IXGBE_ERR_PHY; 622 goto out; 623 } 624 break; 625 default: 626 DEBUGOUT("Bad control type\n"); 627 ret_val = IXGBE_ERR_PHY; 628 goto out; 629 } 630 } 631 632 out: 633 return (ret_val); 634 } 635 636 /* 637 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns 638 * the PHY type. 639 * @hw: pointer to hardware structure 640 * 641 * Searches for and identifies the SFP module. Assigns appropriate PHY type. 642 */ 643 s32 644 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 645 { 646 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 647 u32 vendor_oui = 0; 648 u8 identifier = 0; 649 u8 comp_codes_1g = 0; 650 u8 comp_codes_10g = 0; 651 u8 oui_bytes[4] = {0, 0, 0, 0}; 652 u8 transmission_media = 0; 653 654 status = hw->phy.ops.read_i2c_eeprom(hw, 655 IXGBE_SFF_IDENTIFIER, &identifier); 656 657 if (status == IXGBE_ERR_SFP_NOT_PRESENT) { 658 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 659 goto out; 660 } 661 662 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 663 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 664 &comp_codes_1g); 665 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 666 &comp_codes_10g); 667 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, 668 &transmission_media); 669 670 /* 671 * ID Module 672 * ============ 673 * 0 SFP_DA_CU 674 * 1 SFP_SR 675 * 2 SFP_LR 676 */ 677 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 678 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 679 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 680 hw->phy.sfp_type = ixgbe_sfp_type_sr; 681 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 682 hw->phy.sfp_type = ixgbe_sfp_type_lr; 683 else 684 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 685 686 /* Determine PHY vendor */ 687 if (hw->phy.type == ixgbe_phy_unknown) { 688 hw->phy.id = identifier; 689 hw->phy.ops.read_i2c_eeprom(hw, 690 IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 691 hw->phy.ops.read_i2c_eeprom(hw, 692 IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 693 hw->phy.ops.read_i2c_eeprom(hw, 694 IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 695 696 vendor_oui = 697 ((oui_bytes[0] << 698 IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 699 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 700 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 701 702 switch (vendor_oui) { 703 case IXGBE_SFF_VENDOR_OUI_TYCO: 704 if (transmission_media & 705 IXGBE_SFF_TWIN_AX_CAPABLE) 706 hw->phy.type = ixgbe_phy_tw_tyco; 707 break; 708 case IXGBE_SFF_VENDOR_OUI_FTL: 709 hw->phy.type = ixgbe_phy_sfp_ftl; 710 break; 711 case IXGBE_SFF_VENDOR_OUI_AVAGO: 712 hw->phy.type = ixgbe_phy_sfp_avago; 713 break; 714 default: 715 if (transmission_media & 716 IXGBE_SFF_TWIN_AX_CAPABLE) 717 hw->phy.type = ixgbe_phy_tw_unknown; 718 else 719 hw->phy.type = ixgbe_phy_sfp_unknown; 720 break; 721 } 722 } 723 status = IXGBE_SUCCESS; 724 } 725 726 out: 727 return (status); 728 } 729 730 731 /* 732 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see 733 * if it supports a given SFP+ module type, if so it returns the offsets to the 734 * phy init sequence block. 735 * @hw: pointer to hardware structure 736 * @list_offset: offset to the SFP ID list 737 * @data_offset: offset to the SFP data block 738 */ 739 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 740 u16 *list_offset, u16 *data_offset) 741 { 742 u16 sfp_id; 743 744 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 745 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 746 747 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 748 return (IXGBE_ERR_SFP_NOT_PRESENT); 749 750 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 751 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 752 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 753 754 /* Read offset to PHY init contents */ 755 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 756 757 if ((!*list_offset) || (*list_offset == 0xFFFF)) 758 return (IXGBE_ERR_PHY); 759 760 /* Shift offset to first ID word */ 761 (*list_offset)++; 762 763 /* 764 * Find the matching SFP ID in the EEPROM 765 * and program the init sequence 766 */ 767 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 768 769 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 770 if (sfp_id == hw->phy.sfp_type) { 771 (*list_offset)++; 772 hw->eeprom.ops.read(hw, *list_offset, data_offset); 773 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 774 DEBUGOUT("SFP+ module not supported\n"); 775 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 776 } else { 777 break; 778 } 779 } else { 780 (*list_offset) += 2; 781 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 782 return (IXGBE_ERR_PHY); 783 } 784 } 785 786 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 787 DEBUGOUT("No matching SFP+ module found\n"); 788 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 789 } 790 791 return (IXGBE_SUCCESS); 792 } 793