1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.94 v2-9-1-1_2009-6-10_NSW1 */ 30 31 #include "ixgbe_api.h" 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 35 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45 static bool ixgbe_get_i2c_data(u32 *i2cctl); 46 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 48 /* 49 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 50 * @hw: pointer to the hardware structure 51 * 52 * Initialize the function pointers. 53 */ 54 s32 55 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 56 { 57 struct ixgbe_phy_info *phy = &hw->phy; 58 59 /* PHY */ 60 phy->ops.identify = &ixgbe_identify_phy_generic; 61 phy->ops.reset = &ixgbe_reset_phy_generic; 62 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 63 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 64 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 65 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 66 phy->ops.check_link = NULL; 67 phy->ops.get_firmware_version = NULL; 68 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 69 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 70 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 71 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 72 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 73 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 74 phy->sfp_type = ixgbe_sfp_type_unknown; 75 76 return (IXGBE_SUCCESS); 77 } 78 79 /* 80 * ixgbe_identify_phy_generic - Get physical layer module 81 * @hw: pointer to hardware structure 82 * 83 * Determines the physical layer module found on the current adapter. 84 */ 85 s32 86 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 87 { 88 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 89 u32 phy_addr; 90 u16 ext_ability = 0; 91 92 if (hw->phy.type == ixgbe_phy_unknown) { 93 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 94 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 95 hw->phy.addr = phy_addr; 96 (void) ixgbe_get_phy_id(hw); 97 hw->phy.type = 98 ixgbe_get_phy_type_from_id(hw->phy.id); 99 100 if (hw->phy.type == ixgbe_phy_unknown) { 101 hw->phy.ops.read_reg(hw, 102 IXGBE_MDIO_PHY_EXT_ABILITY, 103 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 104 &ext_ability); 105 if (ext_ability & 106 IXGBE_MDIO_PHY_10GBASET_ABILITY || 107 ext_ability & 108 IXGBE_MDIO_PHY_1000BASET_ABILITY) 109 hw->phy.type = 110 ixgbe_phy_cu_unknown; 111 else 112 hw->phy.type = 113 ixgbe_phy_generic; 114 } 115 116 status = IXGBE_SUCCESS; 117 break; 118 } 119 } 120 if (status != IXGBE_SUCCESS) 121 hw->phy.addr = 0; 122 } else { 123 status = IXGBE_SUCCESS; 124 } 125 126 return (status); 127 } 128 129 /* 130 * ixgbe_validate_phy_addr - Determines phy address is valid 131 * @hw: pointer to hardware structure 132 * 133 */ 134 bool 135 ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 136 { 137 u16 phy_id = 0; 138 bool valid = false; 139 140 hw->phy.addr = phy_addr; 141 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 142 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 143 144 if (phy_id != 0xFFFF && phy_id != 0x0) 145 valid = true; 146 147 return (valid); 148 } 149 150 /* 151 * ixgbe_get_phy_id - Get the phy type 152 * @hw: pointer to hardware structure 153 * 154 */ 155 s32 156 ixgbe_get_phy_id(struct ixgbe_hw *hw) 157 { 158 u32 status; 159 u16 phy_id_high = 0; 160 u16 phy_id_low = 0; 161 162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 163 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 164 &phy_id_high); 165 166 if (status == IXGBE_SUCCESS) { 167 hw->phy.id = (u32)(phy_id_high << 16); 168 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 169 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 170 &phy_id_low); 171 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 172 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 173 } 174 175 return (status); 176 } 177 178 /* 179 * ixgbe_get_phy_type_from_id - Get the phy type 180 * @hw: pointer to hardware structure 181 * 182 */ 183 enum ixgbe_phy_type 184 ixgbe_get_phy_type_from_id(u32 phy_id) 185 { 186 enum ixgbe_phy_type phy_type; 187 188 switch (phy_id) { 189 case TN1010_PHY_ID: 190 phy_type = ixgbe_phy_tn; 191 break; 192 case AQ1002_PHY_ID: 193 phy_type = ixgbe_phy_aq; 194 break; 195 case QT2022_PHY_ID: 196 phy_type = ixgbe_phy_qt; 197 break; 198 case ATH_PHY_ID: 199 phy_type = ixgbe_phy_nl; 200 break; 201 default: 202 phy_type = ixgbe_phy_unknown; 203 break; 204 } 205 206 DEBUGOUT1("phy type found is %d\n", phy_type); 207 208 return (phy_type); 209 } 210 211 /* 212 * ixgbe_reset_phy_generic - Performs a PHY reset 213 * @hw: pointer to hardware structure 214 */ 215 s32 216 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 217 { 218 u32 i; 219 u16 ctrl = 0; 220 s32 status = IXGBE_SUCCESS; 221 222 if (hw->phy.type == ixgbe_phy_unknown) 223 status = ixgbe_identify_phy_generic(hw); 224 225 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 226 goto out; 227 228 /* 229 * Perform soft PHY reset to the PHY_XS. 230 * This will cause a soft reset to the PHY 231 */ 232 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 233 IXGBE_MDIO_PHY_XS_DEV_TYPE, 234 IXGBE_MDIO_PHY_XS_RESET); 235 236 /* Poll for reset bit to self-clear indicating reset is complete */ 237 for (i = 0; i < 500; i++) { 238 msec_delay(1); 239 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 240 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 241 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) 242 break; 243 } 244 245 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 246 status = IXGBE_ERR_RESET_FAILED; 247 DEBUGOUT("PHY reset polling failed to complete.\n"); 248 } 249 250 out: 251 return (status); 252 } 253 254 /* 255 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 256 * @hw: pointer to hardware structure 257 * @reg_addr: 32 bit address of PHY register to read 258 * @phy_data: Pointer to read data from PHY register 259 */ 260 s32 261 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 262 u32 device_type, u16 *phy_data) 263 { 264 u32 command; 265 u32 i; 266 u32 data; 267 s32 status = IXGBE_SUCCESS; 268 u16 gssr; 269 270 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 271 gssr = IXGBE_GSSR_PHY1_SM; 272 else 273 gssr = IXGBE_GSSR_PHY0_SM; 274 275 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 276 status = IXGBE_ERR_SWFW_SYNC; 277 278 if (status == IXGBE_SUCCESS) { 279 /* Setup and write the address cycle command */ 280 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 281 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 282 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 283 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 284 285 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 286 287 /* 288 * Check every 10 usec to see if the address cycle completed. 289 * The MDI Command bit will clear when the operation is 290 * complete 291 */ 292 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 293 usec_delay(10); 294 295 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 296 297 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 298 break; 299 } 300 } 301 302 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 303 DEBUGOUT("PHY address command did not complete.\n"); 304 status = IXGBE_ERR_PHY; 305 } 306 307 if (status == IXGBE_SUCCESS) { 308 /* 309 * Address cycle complete, setup and write the read 310 * command 311 */ 312 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 313 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 314 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 315 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 316 317 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 318 319 /* 320 * Check every 10 usec to see if the address cycle 321 * completed. The MDI Command bit will clear when the 322 * operation is complete 323 */ 324 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 325 usec_delay(10); 326 327 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 328 329 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 330 break; 331 } 332 333 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 334 DEBUGOUT("PHY read command didn't complete\n"); 335 status = IXGBE_ERR_PHY; 336 } else { 337 /* 338 * Read operation is complete. Get the data 339 * from MSRWD 340 */ 341 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 342 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 343 *phy_data = (u16)(data); 344 } 345 } 346 347 ixgbe_release_swfw_sync(hw, gssr); 348 } 349 350 return (status); 351 } 352 353 /* 354 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 355 * @hw: pointer to hardware structure 356 * @reg_addr: 32 bit PHY register to write 357 * @device_type: 5 bit device type 358 * @phy_data: Data to write to the PHY register 359 */ 360 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 361 u32 device_type, u16 phy_data) 362 { 363 u32 command; 364 u32 i; 365 s32 status = IXGBE_SUCCESS; 366 u16 gssr; 367 368 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 369 gssr = IXGBE_GSSR_PHY1_SM; 370 else 371 gssr = IXGBE_GSSR_PHY0_SM; 372 373 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 374 status = IXGBE_ERR_SWFW_SYNC; 375 376 if (status == IXGBE_SUCCESS) { 377 /* 378 * Put the data in the MDI single read and write data register 379 */ 380 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 381 382 /* Setup and write the address cycle command */ 383 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 384 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 385 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 386 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 387 388 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 389 390 /* 391 * Check every 10 usec to see if the address cycle completed. 392 * The MDI Command bit will clear when the operation is 393 * complete 394 */ 395 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 396 usec_delay(10); 397 398 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 399 400 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 401 break; 402 } 403 404 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 405 DEBUGOUT("PHY address cmd didn't complete\n"); 406 status = IXGBE_ERR_PHY; 407 } 408 409 if (status == IXGBE_SUCCESS) { 410 /* 411 * Address cycle complete, setup and write the write 412 * command 413 */ 414 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 415 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 416 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 417 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 418 419 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 420 421 /* 422 * Check every 10 usec to see if the address cycle 423 * completed. The MDI Command bit will clear when the 424 * operation is complete 425 */ 426 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 427 usec_delay(10); 428 429 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 430 431 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 432 break; 433 } 434 435 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 436 DEBUGOUT("PHY address cmd didn't complete\n"); 437 status = IXGBE_ERR_PHY; 438 } 439 } 440 441 ixgbe_release_swfw_sync(hw, gssr); 442 } 443 444 return (status); 445 } 446 447 /* 448 * ixgbe_setup_phy_link_generic - Set and restart autoneg 449 * @hw: pointer to hardware structure 450 * 451 * Restart autonegotiation and PHY and waits for completion. 452 */ 453 s32 454 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 455 { 456 s32 status = IXGBE_SUCCESS; 457 u32 time_out; 458 u32 max_time_out = 10; 459 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 460 461 /* 462 * Set advertisement settings in PHY based on autoneg_advertised 463 * settings. If autoneg_advertised = 0, then advertise default values 464 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 465 * for a 1G. 466 */ 467 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 468 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 469 470 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 471 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 472 else 473 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 474 475 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 476 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 477 478 /* Restart PHY autonegotiation and wait for completion */ 479 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 480 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 481 482 autoneg_reg |= IXGBE_MII_RESTART; 483 484 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 485 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 486 487 /* Wait for autonegotiation to finish */ 488 for (time_out = 0; time_out < max_time_out; time_out++) { 489 usec_delay(10); 490 /* Restart PHY autonegotiation and wait for completion */ 491 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 492 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 493 &autoneg_reg); 494 495 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 496 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 497 break; 498 } 499 } 500 501 if (time_out == max_time_out) 502 status = IXGBE_ERR_LINK_SETUP; 503 504 return (status); 505 } 506 507 /* 508 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 509 * @hw: pointer to hardware structure 510 * @speed: new link speed 511 * @autoneg: true if autonegotiation enabled 512 */ 513 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 514 ixgbe_link_speed speed, 515 bool autoneg, 516 bool autoneg_wait_to_complete) 517 { 518 UNREFERENCED_PARAMETER(autoneg); 519 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 520 521 /* 522 * Clear autoneg_advertised and set new values based on input link 523 * speed. 524 */ 525 hw->phy.autoneg_advertised = 0; 526 527 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 528 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 529 } 530 531 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 532 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 533 } 534 535 if (speed & IXGBE_LINK_SPEED_100_FULL) 536 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 537 538 /* Setup link based on the new speed settings */ 539 hw->phy.ops.setup_link(hw); 540 541 return (IXGBE_SUCCESS); 542 } 543 544 /* 545 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 546 * @hw: pointer to hardware structure 547 * @speed: pointer to link speed 548 * @autoneg: boolean auto-negotiation value 549 * 550 * Determines the link capabilities by reading the AUTOC register. 551 */ 552 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 553 ixgbe_link_speed *speed, bool *autoneg) 554 { 555 s32 status = IXGBE_ERR_LINK_SETUP; 556 u16 speed_ability; 557 558 *speed = 0; 559 *autoneg = true; 560 561 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 562 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability); 563 564 if (status == IXGBE_SUCCESS) { 565 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 566 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 567 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 568 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 569 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 570 *speed |= IXGBE_LINK_SPEED_100_FULL; 571 } 572 573 return (status); 574 } 575 576 /* 577 * ixgbe_check_phy_link_tnx - Determine link and speed status 578 * @hw: pointer to hardware structure 579 * 580 * Reads the VS1 register to determine if link is up and the current speed for 581 * the PHY. 582 */ 583 s32 584 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 585 bool *link_up) 586 { 587 s32 status = IXGBE_SUCCESS; 588 u32 time_out; 589 u32 max_time_out = 10; 590 u16 phy_link = 0; 591 u16 phy_speed = 0; 592 u16 phy_data = 0; 593 594 /* Initialize speed and link to default case */ 595 *link_up = false; 596 *speed = IXGBE_LINK_SPEED_10GB_FULL; 597 598 /* 599 * Check current speed and link status of the PHY register. 600 * This is a vendor specific register and may have to 601 * be changed for other copper PHYs. 602 */ 603 for (time_out = 0; time_out < max_time_out; time_out++) { 604 usec_delay(10); 605 status = hw->phy.ops.read_reg(hw, 606 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 607 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 608 &phy_data); 609 phy_link = phy_data & 610 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 611 phy_speed = phy_data & 612 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 613 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 614 *link_up = true; 615 if (phy_speed == 616 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 617 *speed = IXGBE_LINK_SPEED_1GB_FULL; 618 break; 619 } 620 } 621 622 return (status); 623 } 624 625 /* 626 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 627 * @hw: pointer to hardware structure 628 * @firmware_version: pointer to the PHY Firmware Version 629 */ 630 s32 631 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version) 632 { 633 s32 status = IXGBE_SUCCESS; 634 635 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 636 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 637 638 return (status); 639 } 640 641 /* 642 * ixgbe_get_phy_firmware_version_aq - Gets the PHY Firmware Version 643 * @hw: pointer to hardware structure 644 * @firmware_version: pointer to the PHY Firmware Version 645 */ 646 s32 647 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw, u16 *firmware_version) 648 { 649 s32 status = IXGBE_SUCCESS; 650 651 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 652 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 653 654 return (status); 655 } 656 657 /* 658 * ixgbe_reset_phy_nl - Performs a PHY reset 659 * @hw: pointer to hardware structure 660 */ 661 s32 662 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 663 { 664 u16 phy_offset, control, eword, edata, block_crc; 665 bool end_data = false; 666 u16 list_offset, data_offset; 667 u16 phy_data = 0; 668 s32 ret_val = IXGBE_SUCCESS; 669 u32 i; 670 671 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 672 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 673 674 /* reset the PHY and poll for completion */ 675 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 676 IXGBE_MDIO_PHY_XS_DEV_TYPE, 677 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 678 679 for (i = 0; i < 100; i++) { 680 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 681 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 682 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 683 break; 684 msec_delay(10); 685 } 686 687 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 688 DEBUGOUT("PHY reset did not complete.\n"); 689 ret_val = IXGBE_ERR_PHY; 690 goto out; 691 } 692 693 /* Get init offsets */ 694 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 695 &data_offset); 696 if (ret_val != IXGBE_SUCCESS) 697 goto out; 698 699 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 700 data_offset++; 701 while (!end_data) { 702 /* 703 * Read control word from PHY init contents offset 704 */ 705 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 706 control = (eword & IXGBE_CONTROL_MASK_NL) >> 707 IXGBE_CONTROL_SHIFT_NL; 708 edata = eword & IXGBE_DATA_MASK_NL; 709 switch (control) { 710 case IXGBE_DELAY_NL: 711 data_offset++; 712 DEBUGOUT1("DELAY: %d MS\n", edata); 713 msec_delay(edata); 714 break; 715 case IXGBE_DATA_NL: 716 DEBUGOUT("DATA: \n"); 717 data_offset++; 718 hw->eeprom.ops.read(hw, data_offset++, &phy_offset); 719 for (i = 0; i < edata; i++) { 720 hw->eeprom.ops.read(hw, data_offset, &eword); 721 hw->phy.ops.write_reg(hw, phy_offset, 722 IXGBE_TWINAX_DEV, eword); 723 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 724 phy_offset); 725 data_offset++; 726 phy_offset++; 727 } 728 break; 729 case IXGBE_CONTROL_NL: 730 data_offset++; 731 DEBUGOUT("CONTROL: \n"); 732 if (edata == IXGBE_CONTROL_EOL_NL) { 733 DEBUGOUT("EOL\n"); 734 end_data = true; 735 } else if (edata == IXGBE_CONTROL_SOL_NL) { 736 DEBUGOUT("SOL\n"); 737 } else { 738 DEBUGOUT("Bad control value\n"); 739 ret_val = IXGBE_ERR_PHY; 740 goto out; 741 } 742 break; 743 default: 744 DEBUGOUT("Bad control type\n"); 745 ret_val = IXGBE_ERR_PHY; 746 goto out; 747 } 748 } 749 750 out: 751 return (ret_val); 752 } 753 754 /* 755 * ixgbe_identify_sfp_module_generic - Identifies SFP module 756 * @hw: pointer to hardware structure 757 * 758 * Searches for and identifies the SFP module and assigns appropriate PHY type. 759 */ 760 s32 761 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 762 { 763 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 764 u32 vendor_oui = 0; 765 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 766 u8 identifier = 0; 767 u8 comp_codes_1g = 0; 768 u8 comp_codes_10g = 0; 769 u8 oui_bytes[3] = {0, 0, 0}; 770 u8 cable_tech = 0; 771 u16 enforce_sfp = 0; 772 773 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 774 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 775 status = IXGBE_ERR_SFP_NOT_PRESENT; 776 goto out; 777 } 778 779 status = hw->phy.ops.read_i2c_eeprom(hw, 780 IXGBE_SFF_IDENTIFIER, &identifier); 781 782 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 783 status = IXGBE_ERR_SFP_NOT_PRESENT; 784 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 785 if (hw->phy.type != ixgbe_phy_nl) { 786 hw->phy.id = 0; 787 hw->phy.type = ixgbe_phy_unknown; 788 } 789 goto out; 790 } 791 792 /* LAN ID is needed for sfp_type determination */ 793 hw->mac.ops.set_lan_id(hw); 794 795 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 796 hw->phy.type = ixgbe_phy_sfp_unsupported; 797 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 798 } else { 799 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 800 &comp_codes_1g); 801 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 802 &comp_codes_10g); 803 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 804 &cable_tech); 805 806 /* 807 * ID Module 808 * ============ 809 * 0 SFP_DA_CU 810 * 1 SFP_SR 811 * 2 SFP_LR 812 * 3 SFP_DA_CORE0 - 82599-specific 813 * 4 SFP_DA_CORE1 - 82599-specific 814 * 5 SFP_SR/LR_CORE0 - 82599-specific 815 * 6 SFP_SR/LR_CORE1 - 82599-specific 816 */ 817 if (hw->mac.type == ixgbe_mac_82598EB) { 818 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 819 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 820 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 821 hw->phy.sfp_type = ixgbe_sfp_type_sr; 822 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 823 hw->phy.sfp_type = ixgbe_sfp_type_lr; 824 else 825 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 826 } else if (hw->mac.type == ixgbe_mac_82599EB) { 827 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 828 if (hw->bus.lan_id == 0) 829 hw->phy.sfp_type = 830 ixgbe_sfp_type_da_cu_core0; 831 else 832 hw->phy.sfp_type = 833 ixgbe_sfp_type_da_cu_core1; 834 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 835 if (hw->bus.lan_id == 0) 836 hw->phy.sfp_type = 837 ixgbe_sfp_type_srlr_core0; 838 else 839 hw->phy.sfp_type = 840 ixgbe_sfp_type_srlr_core1; 841 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 842 if (hw->bus.lan_id == 0) 843 hw->phy.sfp_type = 844 ixgbe_sfp_type_srlr_core0; 845 else 846 hw->phy.sfp_type = 847 ixgbe_sfp_type_srlr_core1; 848 else 849 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 850 } 851 852 if (hw->phy.sfp_type != stored_sfp_type) 853 hw->phy.sfp_setup_needed = true; 854 855 /* Determine if the SFP+ PHY is dual speed or not. */ 856 hw->phy.multispeed_fiber = false; 857 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 858 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 859 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 860 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 861 hw->phy.multispeed_fiber = true; 862 863 /* Determine PHY vendor */ 864 if (hw->phy.type != ixgbe_phy_nl) { 865 hw->phy.id = identifier; 866 hw->phy.ops.read_i2c_eeprom(hw, 867 IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 868 hw->phy.ops.read_i2c_eeprom(hw, 869 IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 870 hw->phy.ops.read_i2c_eeprom(hw, 871 IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 872 873 vendor_oui = 874 ((oui_bytes[0] << 875 IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 876 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 877 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 878 879 switch (vendor_oui) { 880 case IXGBE_SFF_VENDOR_OUI_TYCO: 881 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 882 hw->phy.type = ixgbe_phy_tw_tyco; 883 break; 884 case IXGBE_SFF_VENDOR_OUI_FTL: 885 hw->phy.type = ixgbe_phy_sfp_ftl; 886 break; 887 case IXGBE_SFF_VENDOR_OUI_AVAGO: 888 hw->phy.type = ixgbe_phy_sfp_avago; 889 break; 890 case IXGBE_SFF_VENDOR_OUI_INTEL: 891 hw->phy.type = ixgbe_phy_sfp_intel; 892 break; 893 default: 894 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 895 hw->phy.type = ixgbe_phy_tw_unknown; 896 else 897 hw->phy.type = ixgbe_phy_sfp_unknown; 898 break; 899 } 900 } 901 902 /* All passive DA cables are supported */ 903 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 904 status = IXGBE_SUCCESS; 905 goto out; 906 } 907 908 /* 1G SFP modules are not supported */ 909 if (comp_codes_10g == 0) { 910 hw->phy.type = ixgbe_phy_sfp_unsupported; 911 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 912 goto out; 913 } 914 915 /* Anything else 82598-based is supported */ 916 if (hw->mac.type == ixgbe_mac_82598EB) { 917 status = IXGBE_SUCCESS; 918 goto out; 919 } 920 921 (void) ixgbe_get_device_caps(hw, &enforce_sfp); 922 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 923 /* Make sure we're a supported PHY type */ 924 if (hw->phy.type == ixgbe_phy_sfp_intel) { 925 status = IXGBE_SUCCESS; 926 } else { 927 DEBUGOUT("SFP+ module not supported\n"); 928 hw->phy.type = ixgbe_phy_sfp_unsupported; 929 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 930 } 931 } else { 932 status = IXGBE_SUCCESS; 933 } 934 } 935 936 out: 937 return (status); 938 } 939 940 941 /* 942 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 943 * @hw: pointer to hardware structure 944 * @list_offset: offset to the SFP ID list 945 * @data_offset: offset to the SFP data block 946 * 947 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 948 * so it returns the offsets to the phy init sequence block. 949 */ 950 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 951 u16 *list_offset, u16 *data_offset) 952 { 953 u16 sfp_id; 954 955 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 956 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 957 958 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 959 return (IXGBE_ERR_SFP_NOT_PRESENT); 960 961 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 962 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 963 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 964 965 /* Read offset to PHY init contents */ 966 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 967 968 if ((!*list_offset) || (*list_offset == 0xFFFF)) 969 return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT); 970 971 /* Shift offset to first ID word */ 972 (*list_offset)++; 973 974 /* 975 * Find the matching SFP ID in the EEPROM 976 * and program the init sequence 977 */ 978 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 979 980 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 981 if (sfp_id == hw->phy.sfp_type) { 982 (*list_offset)++; 983 hw->eeprom.ops.read(hw, *list_offset, data_offset); 984 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 985 DEBUGOUT("SFP+ module not supported\n"); 986 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 987 } else { 988 break; 989 } 990 } else { 991 (*list_offset) += 2; 992 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 993 return (IXGBE_ERR_PHY); 994 } 995 } 996 997 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 998 DEBUGOUT("No matching SFP+ module found\n"); 999 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1000 } 1001 1002 return (IXGBE_SUCCESS); 1003 } 1004 1005 /* 1006 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1007 * @hw: pointer to hardware structure 1008 * @byte_offset: EEPROM byte offset to read 1009 * @eeprom_data: value read 1010 * 1011 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1012 */ 1013 s32 1014 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1015 u8 *eeprom_data) 1016 { 1017 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1018 1019 return (hw->phy.ops.read_i2c_byte(hw, byte_offset, 1020 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1021 } 1022 1023 /* 1024 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1025 * @hw: pointer to hardware structure 1026 * @byte_offset: EEPROM byte offset to write 1027 * @eeprom_data: value to write 1028 * 1029 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1030 */ 1031 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1032 u8 eeprom_data) 1033 { 1034 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1035 1036 return (hw->phy.ops.write_i2c_byte(hw, byte_offset, 1037 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1038 } 1039 1040 /* 1041 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1042 * @hw: pointer to hardware structure 1043 * @byte_offset: byte offset to read 1044 * @data: value read 1045 * 1046 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1047 * a specified deivce address. 1048 */ 1049 s32 1050 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1051 u8 dev_addr, u8 *data) 1052 { 1053 s32 status = IXGBE_SUCCESS; 1054 u32 max_retry = 10; 1055 u32 retry = 0; 1056 u16 swfw_mask = 0; 1057 bool nack = 1; 1058 1059 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1060 1061 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1062 swfw_mask = IXGBE_GSSR_PHY1_SM; 1063 else 1064 swfw_mask = IXGBE_GSSR_PHY0_SM; 1065 1066 do { 1067 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1068 status = IXGBE_ERR_SWFW_SYNC; 1069 goto read_byte_out; 1070 } 1071 1072 ixgbe_i2c_start(hw); 1073 1074 /* Device Address and write indication */ 1075 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1076 if (status != IXGBE_SUCCESS) 1077 goto fail; 1078 1079 status = ixgbe_get_i2c_ack(hw); 1080 if (status != IXGBE_SUCCESS) 1081 goto fail; 1082 1083 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1084 if (status != IXGBE_SUCCESS) 1085 goto fail; 1086 1087 status = ixgbe_get_i2c_ack(hw); 1088 if (status != IXGBE_SUCCESS) 1089 goto fail; 1090 1091 ixgbe_i2c_start(hw); 1092 1093 /* Device Address and read indication */ 1094 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1095 if (status != IXGBE_SUCCESS) 1096 goto fail; 1097 1098 status = ixgbe_get_i2c_ack(hw); 1099 if (status != IXGBE_SUCCESS) 1100 goto fail; 1101 1102 status = ixgbe_clock_in_i2c_byte(hw, data); 1103 if (status != IXGBE_SUCCESS) 1104 goto fail; 1105 1106 status = ixgbe_clock_out_i2c_bit(hw, nack); 1107 if (status != IXGBE_SUCCESS) 1108 goto fail; 1109 1110 ixgbe_i2c_stop(hw); 1111 break; 1112 1113 fail: 1114 ixgbe_release_swfw_sync(hw, swfw_mask); 1115 msec_delay(100); 1116 ixgbe_i2c_bus_clear(hw); 1117 retry++; 1118 if (retry < max_retry) 1119 DEBUGOUT("I2C byte read error - Retrying.\n"); 1120 else 1121 DEBUGOUT("I2C byte read error.\n"); 1122 } while (retry < max_retry); 1123 1124 ixgbe_release_swfw_sync(hw, swfw_mask); 1125 1126 read_byte_out: 1127 return (status); 1128 } 1129 1130 /* 1131 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1132 * @hw: pointer to hardware structure 1133 * @byte_offset: byte offset to write 1134 * @data: value to write 1135 * 1136 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1137 * a specified device address. 1138 */ 1139 s32 1140 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1141 u8 dev_addr, u8 data) 1142 { 1143 s32 status = IXGBE_SUCCESS; 1144 u32 max_retry = 1; 1145 u32 retry = 0; 1146 u16 swfw_mask = 0; 1147 1148 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1149 1150 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1151 swfw_mask = IXGBE_GSSR_PHY1_SM; 1152 else 1153 swfw_mask = IXGBE_GSSR_PHY0_SM; 1154 1155 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1156 status = IXGBE_ERR_SWFW_SYNC; 1157 goto write_byte_out; 1158 } 1159 1160 do { 1161 ixgbe_i2c_start(hw); 1162 1163 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1164 if (status != IXGBE_SUCCESS) 1165 goto fail; 1166 1167 status = ixgbe_get_i2c_ack(hw); 1168 if (status != IXGBE_SUCCESS) 1169 goto fail; 1170 1171 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1172 if (status != IXGBE_SUCCESS) 1173 goto fail; 1174 1175 status = ixgbe_get_i2c_ack(hw); 1176 if (status != IXGBE_SUCCESS) 1177 goto fail; 1178 1179 status = ixgbe_clock_out_i2c_byte(hw, data); 1180 if (status != IXGBE_SUCCESS) 1181 goto fail; 1182 1183 status = ixgbe_get_i2c_ack(hw); 1184 if (status != IXGBE_SUCCESS) 1185 goto fail; 1186 1187 ixgbe_i2c_stop(hw); 1188 break; 1189 1190 fail: 1191 ixgbe_i2c_bus_clear(hw); 1192 retry++; 1193 if (retry < max_retry) 1194 DEBUGOUT("I2C byte write error - Retrying.\n"); 1195 else 1196 DEBUGOUT("I2C byte write error.\n"); 1197 } while (retry < max_retry); 1198 1199 ixgbe_release_swfw_sync(hw, swfw_mask); 1200 1201 write_byte_out: 1202 return (status); 1203 } 1204 1205 /* 1206 * ixgbe_i2c_start - Sets I2C start condition 1207 * @hw: pointer to hardware structure 1208 * 1209 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1210 */ 1211 static void 1212 ixgbe_i2c_start(struct ixgbe_hw *hw) 1213 { 1214 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1215 1216 DEBUGFUNC("ixgbe_i2c_start"); 1217 1218 /* Start condition must begin with data and clock high */ 1219 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1220 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1221 1222 /* Setup time for start condition (4.7us) */ 1223 usec_delay(IXGBE_I2C_T_SU_STA); 1224 1225 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1226 1227 /* Hold time for start condition (4us) */ 1228 usec_delay(IXGBE_I2C_T_HD_STA); 1229 1230 ixgbe_lower_i2c_clk(hw, &i2cctl); 1231 1232 /* Minimum low period of clock is 4.7 us */ 1233 usec_delay(IXGBE_I2C_T_LOW); 1234 } 1235 1236 /* 1237 * ixgbe_i2c_stop - Sets I2C stop condition 1238 * @hw: pointer to hardware structure 1239 * 1240 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1241 */ 1242 static void 1243 ixgbe_i2c_stop(struct ixgbe_hw *hw) 1244 { 1245 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1246 1247 DEBUGFUNC("ixgbe_i2c_stop"); 1248 1249 /* Stop condition must begin with data low and clock high */ 1250 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1251 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1252 1253 /* Setup time for stop condition (4us) */ 1254 usec_delay(IXGBE_I2C_T_SU_STO); 1255 1256 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1257 1258 /* bus free time between stop and start (4.7us) */ 1259 usec_delay(IXGBE_I2C_T_BUF); 1260 } 1261 1262 /* 1263 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1264 * @hw: pointer to hardware structure 1265 * @data: data byte to clock in 1266 * 1267 * Clocks in one byte data via I2C data/clock 1268 */ 1269 static s32 1270 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1271 { 1272 s32 status = IXGBE_SUCCESS; 1273 s32 i; 1274 bool bit = 0; 1275 1276 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1277 1278 for (i = 7; i >= 0; i--) { 1279 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1280 *data |= bit<<i; 1281 1282 if (status != IXGBE_SUCCESS) 1283 break; 1284 } 1285 1286 return (status); 1287 } 1288 1289 /* 1290 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1291 * @hw: pointer to hardware structure 1292 * @data: data byte clocked out 1293 * 1294 * Clocks out one byte data via I2C data/clock 1295 */ 1296 static s32 1297 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1298 { 1299 s32 status = IXGBE_SUCCESS; 1300 s32 i; 1301 u32 i2cctl; 1302 bool bit = 0; 1303 1304 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1305 1306 for (i = 7; i >= 0; i--) { 1307 bit = (data >> i) & 0x1; 1308 status = ixgbe_clock_out_i2c_bit(hw, bit); 1309 1310 if (status != IXGBE_SUCCESS) 1311 break; 1312 } 1313 1314 /* Release SDA line (set high) */ 1315 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1316 i2cctl |= IXGBE_I2C_DATA_OUT; 1317 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1318 1319 return (status); 1320 } 1321 1322 /* 1323 * ixgbe_get_i2c_ack - Polls for I2C ACK 1324 * @hw: pointer to hardware structure 1325 * 1326 * Clocks in/out one bit via I2C data/clock 1327 */ 1328 static s32 1329 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1330 { 1331 s32 status; 1332 u32 i = 0; 1333 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1334 u32 timeout = 10; 1335 bool ack = 1; 1336 1337 DEBUGFUNC("ixgbe_get_i2c_ack"); 1338 1339 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1340 1341 if (status != IXGBE_SUCCESS) 1342 goto out; 1343 1344 /* Minimum high period of clock is 4us */ 1345 usec_delay(IXGBE_I2C_T_HIGH); 1346 1347 /* 1348 * Poll for ACK. Note that ACK in I2C spec is 1349 * transition from 1 to 0 1350 */ 1351 for (i = 0; i < timeout; i++) { 1352 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1353 ack = ixgbe_get_i2c_data(&i2cctl); 1354 1355 usec_delay(1); 1356 if (ack == 0) 1357 break; 1358 } 1359 1360 if (ack == 1) { 1361 DEBUGOUT("I2C ack was not received.\n"); 1362 status = IXGBE_ERR_I2C; 1363 } 1364 1365 ixgbe_lower_i2c_clk(hw, &i2cctl); 1366 1367 /* Minimum low period of clock is 4.7 us */ 1368 usec_delay(IXGBE_I2C_T_LOW); 1369 1370 out: 1371 return (status); 1372 } 1373 1374 /* 1375 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1376 * @hw: pointer to hardware structure 1377 * @data: read data value 1378 * 1379 * Clocks in one bit via I2C data/clock 1380 */ 1381 static s32 1382 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1383 { 1384 s32 status; 1385 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1386 1387 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1388 1389 /* Minimum high period of clock is 4us */ 1390 usec_delay(IXGBE_I2C_T_HIGH); 1391 1392 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1393 *data = ixgbe_get_i2c_data(&i2cctl); 1394 1395 ixgbe_lower_i2c_clk(hw, &i2cctl); 1396 1397 /* Minimum low period of clock is 4.7 us */ 1398 usec_delay(IXGBE_I2C_T_LOW); 1399 1400 return (status); 1401 } 1402 1403 /* 1404 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1405 * @hw: pointer to hardware structure 1406 * @data: data value to write 1407 * 1408 * Clocks out one bit via I2C data/clock 1409 */ 1410 static s32 1411 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1412 { 1413 s32 status; 1414 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1415 1416 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1417 if (status == IXGBE_SUCCESS) { 1418 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1419 1420 /* Minimum high period of clock is 4us */ 1421 usec_delay(IXGBE_I2C_T_HIGH); 1422 1423 ixgbe_lower_i2c_clk(hw, &i2cctl); 1424 1425 /* 1426 * Minimum low period of clock is 4.7 us. 1427 * This also takes care of the data hold time. 1428 */ 1429 usec_delay(IXGBE_I2C_T_LOW); 1430 } else { 1431 status = IXGBE_ERR_I2C; 1432 DEBUGOUT1("I2C data was not set to %X\n", data); 1433 } 1434 1435 return (status); 1436 } 1437 1438 /* 1439 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1440 * @hw: pointer to hardware structure 1441 * @i2cctl: Current value of I2CCTL register 1442 * 1443 * Raises the I2C clock line '0'->'1' 1444 */ 1445 static s32 1446 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1447 { 1448 s32 status = IXGBE_SUCCESS; 1449 1450 *i2cctl |= IXGBE_I2C_CLK_OUT; 1451 1452 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1453 1454 /* SCL rise time (1000ns) */ 1455 usec_delay(IXGBE_I2C_T_RISE); 1456 1457 return (status); 1458 } 1459 1460 /* 1461 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1462 * @hw: pointer to hardware structure 1463 * @i2cctl: Current value of I2CCTL register 1464 * 1465 * Lowers the I2C clock line '1'->'0' 1466 */ 1467 static void 1468 ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1469 { 1470 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1471 1472 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1473 1474 /* SCL fall time (300ns) */ 1475 usec_delay(IXGBE_I2C_T_FALL); 1476 } 1477 1478 /* 1479 * ixgbe_set_i2c_data - Sets the I2C data bit 1480 * @hw: pointer to hardware structure 1481 * @i2cctl: Current value of I2CCTL register 1482 * @data: I2C data value (0 or 1) to set 1483 * 1484 * Sets the I2C data bit 1485 */ 1486 static s32 1487 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1488 { 1489 s32 status = IXGBE_SUCCESS; 1490 1491 if (data) 1492 *i2cctl |= IXGBE_I2C_DATA_OUT; 1493 else 1494 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1495 1496 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1497 1498 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1499 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1500 1501 /* Verify data was set correctly */ 1502 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1503 if (data != ixgbe_get_i2c_data(i2cctl)) { 1504 status = IXGBE_ERR_I2C; 1505 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1506 } 1507 1508 return (status); 1509 } 1510 1511 /* 1512 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1513 * @hw: pointer to hardware structure 1514 * @i2cctl: Current value of I2CCTL register 1515 * 1516 * Returns the I2C data bit value 1517 */ 1518 static bool 1519 ixgbe_get_i2c_data(u32 *i2cctl) 1520 { 1521 bool data; 1522 1523 if (*i2cctl & IXGBE_I2C_DATA_IN) 1524 data = 1; 1525 else 1526 data = 0; 1527 1528 return (data); 1529 } 1530 1531 /* 1532 * ixgbe_i2c_bus_clear - Clears the I2C bus 1533 * @hw: pointer to hardware structure 1534 * 1535 * Clears the I2C bus by sending nine clock pulses. 1536 * Used when data line is stuck low. 1537 */ 1538 void 1539 ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1540 { 1541 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1542 u32 i; 1543 1544 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1545 1546 ixgbe_i2c_start(hw); 1547 1548 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1549 1550 for (i = 0; i < 9; i++) { 1551 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1552 1553 /* Min high period of clock is 4us */ 1554 usec_delay(IXGBE_I2C_T_HIGH); 1555 1556 ixgbe_lower_i2c_clk(hw, &i2cctl); 1557 1558 /* Min low period of clock is 4.7us */ 1559 usec_delay(IXGBE_I2C_T_LOW); 1560 } 1561 1562 ixgbe_i2c_start(hw); 1563 1564 /* Put the i2c bus back to default state */ 1565 ixgbe_i2c_stop(hw); 1566 } 1567