1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at: 9 * http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When using or redistributing this file, you may do so under the 14 * License only. No other modification of this header is permitted. 15 * 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 29 */ 30 31 /* IntelVersion: 1.109 scm_061610_003709 */ 32 33 #include "ixgbe_api.h" 34 #include "ixgbe_common.h" 35 #include "ixgbe_phy.h" 36 37 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 38 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 39 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 40 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 41 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 42 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 43 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 44 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 45 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 46 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 47 static bool ixgbe_get_i2c_data(u32 *i2cctl); 48 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 49 50 /* 51 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 52 * @hw: pointer to the hardware structure 53 * 54 * Initialize the function pointers. 55 */ 56 s32 57 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 58 { 59 struct ixgbe_phy_info *phy = &hw->phy; 60 61 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 62 63 /* PHY */ 64 phy->ops.identify = &ixgbe_identify_phy_generic; 65 phy->ops.reset = &ixgbe_reset_phy_generic; 66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 70 phy->ops.check_link = NULL; 71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 77 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 78 phy->sfp_type = ixgbe_sfp_type_unknown; 79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 80 81 return (IXGBE_SUCCESS); 82 } 83 84 /* 85 * ixgbe_identify_phy_generic - Get physical layer module 86 * @hw: pointer to hardware structure 87 * 88 * Determines the physical layer module found on the current adapter. 89 */ 90 s32 91 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 92 { 93 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 94 u32 phy_addr; 95 u16 ext_ability = 0; 96 97 DEBUGFUNC("ixgbe_identify_phy_generic"); 98 99 if (hw->phy.type == ixgbe_phy_unknown) { 100 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 101 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 102 hw->phy.addr = phy_addr; 103 (void) ixgbe_get_phy_id(hw); 104 hw->phy.type = 105 ixgbe_get_phy_type_from_id(hw->phy.id); 106 107 if (hw->phy.type == ixgbe_phy_unknown) { 108 hw->phy.ops.read_reg(hw, 109 IXGBE_MDIO_PHY_EXT_ABILITY, 110 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 111 &ext_ability); 112 if (ext_ability & 113 IXGBE_MDIO_PHY_10GBASET_ABILITY || 114 ext_ability & 115 IXGBE_MDIO_PHY_1000BASET_ABILITY) 116 hw->phy.type = 117 ixgbe_phy_cu_unknown; 118 else 119 hw->phy.type = 120 ixgbe_phy_generic; 121 } 122 123 status = IXGBE_SUCCESS; 124 break; 125 } 126 } 127 if (status != IXGBE_SUCCESS) 128 hw->phy.addr = 0; 129 } else { 130 status = IXGBE_SUCCESS; 131 } 132 133 return (status); 134 } 135 136 /* 137 * ixgbe_validate_phy_addr - Determines phy address is valid 138 * @hw: pointer to hardware structure 139 * 140 */ 141 bool 142 ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 143 { 144 u16 phy_id = 0; 145 bool valid = false; 146 147 DEBUGFUNC("ixgbe_validate_phy_addr"); 148 149 hw->phy.addr = phy_addr; 150 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 151 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 152 153 if (phy_id != 0xFFFF && phy_id != 0x0) 154 valid = true; 155 156 return (valid); 157 } 158 159 /* 160 * ixgbe_get_phy_id - Get the phy type 161 * @hw: pointer to hardware structure 162 * 163 */ 164 s32 165 ixgbe_get_phy_id(struct ixgbe_hw *hw) 166 { 167 u32 status; 168 u16 phy_id_high = 0; 169 u16 phy_id_low = 0; 170 171 DEBUGFUNC("ixgbe_get_phy_id"); 172 173 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 174 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 175 &phy_id_high); 176 177 if (status == IXGBE_SUCCESS) { 178 hw->phy.id = (u32)(phy_id_high << 16); 179 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 180 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 181 &phy_id_low); 182 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 183 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 184 } 185 186 return (status); 187 } 188 189 /* 190 * ixgbe_get_phy_type_from_id - Get the phy type 191 * @hw: pointer to hardware structure 192 * 193 */ 194 enum ixgbe_phy_type 195 ixgbe_get_phy_type_from_id(u32 phy_id) 196 { 197 enum ixgbe_phy_type phy_type; 198 199 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 200 201 switch (phy_id) { 202 case TN1010_PHY_ID: 203 phy_type = ixgbe_phy_tn; 204 break; 205 case AQ1002_PHY_ID: 206 phy_type = ixgbe_phy_aq; 207 break; 208 case QT2022_PHY_ID: 209 phy_type = ixgbe_phy_qt; 210 break; 211 case ATH_PHY_ID: 212 phy_type = ixgbe_phy_nl; 213 break; 214 default: 215 phy_type = ixgbe_phy_unknown; 216 break; 217 } 218 219 DEBUGOUT1("phy type found is %d\n", phy_type); 220 221 return (phy_type); 222 } 223 224 /* 225 * ixgbe_reset_phy_generic - Performs a PHY reset 226 * @hw: pointer to hardware structure 227 */ 228 s32 229 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 230 { 231 u32 i; 232 u16 ctrl = 0; 233 s32 status = IXGBE_SUCCESS; 234 235 DEBUGFUNC("ixgbe_reset_phy_generic"); 236 237 if (hw->phy.type == ixgbe_phy_unknown) 238 status = ixgbe_identify_phy_generic(hw); 239 240 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 241 goto out; 242 243 if (!hw->phy.reset_if_overtemp && 244 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) { 245 /* Don't reset PHY if it's shut down due to overtemp. */ 246 goto out; 247 } 248 249 /* 250 * Perform soft PHY reset to the PHY_XS. 251 * This will cause a soft reset to the PHY 252 */ 253 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 254 IXGBE_MDIO_PHY_XS_DEV_TYPE, 255 IXGBE_MDIO_PHY_XS_RESET); 256 257 /* 258 * Poll for reset bit to self-clear indicating reset is complete. 259 * Some PHYs could take up to 3 seconds to complete and need about 260 * 1.7 usec delay after the reset is complete. 261 */ 262 for (i = 0; i < 30; i++) { 263 msec_delay(100); 264 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 265 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 266 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 267 usec_delay(2); 268 break; 269 } 270 } 271 272 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 273 status = IXGBE_ERR_RESET_FAILED; 274 DEBUGOUT("PHY reset polling failed to complete.\n"); 275 } 276 277 out: 278 return (status); 279 } 280 281 /* 282 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 283 * @hw: pointer to hardware structure 284 * @reg_addr: 32 bit address of PHY register to read 285 * @phy_data: Pointer to read data from PHY register 286 */ 287 s32 288 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 289 u32 device_type, u16 *phy_data) 290 { 291 u32 command; 292 u32 i; 293 u32 data; 294 s32 status = IXGBE_SUCCESS; 295 u16 gssr; 296 297 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 298 299 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 300 gssr = IXGBE_GSSR_PHY1_SM; 301 else 302 gssr = IXGBE_GSSR_PHY0_SM; 303 304 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 305 status = IXGBE_ERR_SWFW_SYNC; 306 307 if (status == IXGBE_SUCCESS) { 308 /* Setup and write the address cycle command */ 309 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 310 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 311 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 312 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 313 314 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 315 316 /* 317 * Check every 10 usec to see if the address cycle completed. 318 * The MDI Command bit will clear when the operation is 319 * complete 320 */ 321 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 322 usec_delay(10); 323 324 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 325 326 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 327 break; 328 } 329 } 330 331 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 332 DEBUGOUT("PHY address command did not complete.\n"); 333 status = IXGBE_ERR_PHY; 334 } 335 336 if (status == IXGBE_SUCCESS) { 337 /* 338 * Address cycle complete, setup and write the read 339 * command 340 */ 341 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 342 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 343 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 344 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 345 346 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 347 348 /* 349 * Check every 10 usec to see if the address cycle 350 * completed. The MDI Command bit will clear when the 351 * operation is complete 352 */ 353 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 354 usec_delay(10); 355 356 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 357 358 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 359 break; 360 } 361 362 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 363 DEBUGOUT("PHY read command didn't complete\n"); 364 status = IXGBE_ERR_PHY; 365 } else { 366 /* 367 * Read operation is complete. Get the data 368 * from MSRWD 369 */ 370 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 371 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 372 *phy_data = (u16)(data); 373 } 374 } 375 376 ixgbe_release_swfw_sync(hw, gssr); 377 } 378 379 return (status); 380 } 381 382 /* 383 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 384 * @hw: pointer to hardware structure 385 * @reg_addr: 32 bit PHY register to write 386 * @device_type: 5 bit device type 387 * @phy_data: Data to write to the PHY register 388 */ 389 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 390 u32 device_type, u16 phy_data) 391 { 392 u32 command; 393 u32 i; 394 s32 status = IXGBE_SUCCESS; 395 u16 gssr; 396 397 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 398 399 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 400 gssr = IXGBE_GSSR_PHY1_SM; 401 else 402 gssr = IXGBE_GSSR_PHY0_SM; 403 404 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 405 status = IXGBE_ERR_SWFW_SYNC; 406 407 if (status == IXGBE_SUCCESS) { 408 /* 409 * Put the data in the MDI single read and write data register 410 */ 411 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 412 413 /* Setup and write the address cycle command */ 414 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 415 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 416 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 417 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 418 419 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 420 421 /* 422 * Check every 10 usec to see if the address cycle completed. 423 * The MDI Command bit will clear when the operation is 424 * complete 425 */ 426 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 427 usec_delay(10); 428 429 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 430 431 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 432 break; 433 } 434 435 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 436 DEBUGOUT("PHY address cmd didn't complete\n"); 437 status = IXGBE_ERR_PHY; 438 } 439 440 if (status == IXGBE_SUCCESS) { 441 /* 442 * Address cycle complete, setup and write the write 443 * command 444 */ 445 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 446 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 447 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 448 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 449 450 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 451 452 /* 453 * Check every 10 usec to see if the address cycle 454 * completed. The MDI Command bit will clear when the 455 * operation is complete 456 */ 457 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 458 usec_delay(10); 459 460 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 461 462 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 463 break; 464 } 465 466 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 467 DEBUGOUT("PHY address cmd didn't complete\n"); 468 status = IXGBE_ERR_PHY; 469 } 470 } 471 472 ixgbe_release_swfw_sync(hw, gssr); 473 } 474 475 return (status); 476 } 477 478 /* 479 * ixgbe_setup_phy_link_generic - Set and restart autoneg 480 * @hw: pointer to hardware structure 481 * 482 * Restart autonegotiation and PHY and waits for completion. 483 */ 484 s32 485 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 486 { 487 s32 status = IXGBE_SUCCESS; 488 u32 time_out; 489 u32 max_time_out = 10; 490 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 491 bool autoneg = false; 492 ixgbe_link_speed speed; 493 494 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 495 496 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 497 498 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 499 /* Set or unset auto-negotiation 10G advertisement */ 500 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 501 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 502 &autoneg_reg); 503 504 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 505 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 506 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 507 508 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 510 autoneg_reg); 511 } 512 513 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 514 /* Set or unset auto-negotiation 1G advertisement */ 515 hw->phy.ops.read_reg(hw, 516 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 518 &autoneg_reg); 519 520 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 521 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 522 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 523 524 hw->phy.ops.write_reg(hw, 525 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 526 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 527 autoneg_reg); 528 } 529 530 if (speed & IXGBE_LINK_SPEED_100_FULL) { 531 /* Set or unset auto-negotiation 100M advertisement */ 532 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 533 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 534 &autoneg_reg); 535 536 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 537 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 538 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 539 540 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 541 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 542 autoneg_reg); 543 } 544 545 /* Restart PHY autonegotiation and wait for completion */ 546 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 547 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 548 549 autoneg_reg |= IXGBE_MII_RESTART; 550 551 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 552 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 553 554 /* Wait for autonegotiation to finish */ 555 for (time_out = 0; time_out < max_time_out; time_out++) { 556 usec_delay(10); 557 /* Restart PHY autonegotiation and wait for completion */ 558 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 559 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 560 &autoneg_reg); 561 562 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 563 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 564 break; 565 } 566 } 567 568 if (time_out == max_time_out) { 569 status = IXGBE_ERR_LINK_SETUP; 570 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 571 } 572 573 return (status); 574 } 575 576 /* 577 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 578 * @hw: pointer to hardware structure 579 * @speed: new link speed 580 * @autoneg: true if autonegotiation enabled 581 */ 582 s32 583 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 584 ixgbe_link_speed speed, 585 bool autoneg, 586 bool autoneg_wait_to_complete) 587 { 588 UNREFERENCED_PARAMETER(autoneg); 589 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 590 591 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 592 593 /* 594 * Clear autoneg_advertised and set new values based on input link 595 * speed. 596 */ 597 hw->phy.autoneg_advertised = 0; 598 599 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 600 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 601 } 602 603 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 604 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 605 } 606 607 if (speed & IXGBE_LINK_SPEED_100_FULL) 608 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 609 610 /* Setup link based on the new speed settings */ 611 hw->phy.ops.setup_link(hw); 612 613 return (IXGBE_SUCCESS); 614 } 615 616 /* 617 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 618 * @hw: pointer to hardware structure 619 * @speed: pointer to link speed 620 * @autoneg: boolean auto-negotiation value 621 * 622 * Determines the link capabilities by reading the AUTOC register. 623 */ 624 s32 625 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 626 ixgbe_link_speed *speed, bool *autoneg) 627 { 628 s32 status = IXGBE_ERR_LINK_SETUP; 629 u16 speed_ability; 630 631 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 632 633 *speed = 0; 634 *autoneg = true; 635 636 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 637 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability); 638 639 if (status == IXGBE_SUCCESS) { 640 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 641 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 642 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 643 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 644 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 645 *speed |= IXGBE_LINK_SPEED_100_FULL; 646 } 647 648 return (status); 649 } 650 651 /* 652 * ixgbe_check_phy_link_tnx - Determine link and speed status 653 * @hw: pointer to hardware structure 654 * 655 * Reads the VS1 register to determine if link is up and the current speed for 656 * the PHY. 657 */ 658 s32 659 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 660 bool *link_up) 661 { 662 s32 status = IXGBE_SUCCESS; 663 u32 time_out; 664 u32 max_time_out = 10; 665 u16 phy_link = 0; 666 u16 phy_speed = 0; 667 u16 phy_data = 0; 668 669 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 670 671 /* Initialize speed and link to default case */ 672 *link_up = false; 673 *speed = IXGBE_LINK_SPEED_10GB_FULL; 674 675 /* 676 * Check current speed and link status of the PHY register. 677 * This is a vendor specific register and may have to 678 * be changed for other copper PHYs. 679 */ 680 for (time_out = 0; time_out < max_time_out; time_out++) { 681 usec_delay(10); 682 status = hw->phy.ops.read_reg(hw, 683 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 684 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 685 &phy_data); 686 phy_link = phy_data & 687 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 688 phy_speed = phy_data & 689 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 690 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 691 *link_up = true; 692 if (phy_speed == 693 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 694 *speed = IXGBE_LINK_SPEED_1GB_FULL; 695 break; 696 } 697 } 698 699 return (status); 700 } 701 702 /* 703 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 704 * @hw: pointer to hardware structure 705 * 706 * Restart autonegotiation and PHY and waits for completion. 707 */ 708 s32 709 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 710 { 711 s32 status = IXGBE_SUCCESS; 712 u32 time_out; 713 u32 max_time_out = 10; 714 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 715 bool autoneg = false; 716 ixgbe_link_speed speed; 717 718 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 719 720 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 721 722 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 723 /* Set or unset auto-negotiation 10G advertisement */ 724 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 725 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 726 &autoneg_reg); 727 728 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 729 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 730 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 731 732 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 733 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 734 autoneg_reg); 735 } 736 737 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 738 /* Set or unset auto-negotiation 1G advertisement */ 739 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 740 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 741 &autoneg_reg); 742 743 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 744 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 745 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 746 747 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 748 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 749 autoneg_reg); 750 } 751 752 if (speed & IXGBE_LINK_SPEED_100_FULL) { 753 /* Set or unset auto-negotiation 100M advertisement */ 754 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 756 &autoneg_reg); 757 758 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 759 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 760 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 761 762 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 763 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 764 autoneg_reg); 765 } 766 767 /* Restart PHY autonegotiation and wait for completion */ 768 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 769 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 770 771 autoneg_reg |= IXGBE_MII_RESTART; 772 773 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 775 776 /* Wait for autonegotiation to finish */ 777 for (time_out = 0; time_out < max_time_out; time_out++) { 778 usec_delay(10); 779 /* Restart PHY autonegotiation and wait for completion */ 780 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 781 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 782 &autoneg_reg); 783 784 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 785 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 786 break; 787 } 788 } 789 790 if (time_out == max_time_out) { 791 status = IXGBE_ERR_LINK_SETUP; 792 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 793 } 794 795 return (status); 796 } 797 798 /* 799 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 800 * @hw: pointer to hardware structure 801 * @firmware_version: pointer to the PHY Firmware Version 802 */ 803 s32 804 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version) 805 { 806 s32 status = IXGBE_SUCCESS; 807 808 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 809 810 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 811 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 812 813 return (status); 814 } 815 816 /* 817 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 818 * @hw: pointer to hardware structure 819 * @firmware_version: pointer to the PHY Firmware Version 820 */ 821 s32 822 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 823 u16 *firmware_version) 824 { 825 s32 status = IXGBE_SUCCESS; 826 827 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 828 829 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 830 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 831 832 return (status); 833 } 834 835 /* 836 * ixgbe_reset_phy_nl - Performs a PHY reset 837 * @hw: pointer to hardware structure 838 */ 839 s32 840 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 841 { 842 u16 phy_offset, control, eword, edata, block_crc; 843 bool end_data = false; 844 u16 list_offset, data_offset; 845 u16 phy_data = 0; 846 s32 ret_val = IXGBE_SUCCESS; 847 u32 i; 848 849 DEBUGFUNC("ixgbe_reset_phy_nl"); 850 851 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 852 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 853 854 /* reset the PHY and poll for completion */ 855 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 856 IXGBE_MDIO_PHY_XS_DEV_TYPE, 857 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 858 859 for (i = 0; i < 100; i++) { 860 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 861 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 862 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 863 break; 864 msec_delay(10); 865 } 866 867 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 868 DEBUGOUT("PHY reset did not complete.\n"); 869 ret_val = IXGBE_ERR_PHY; 870 goto out; 871 } 872 873 /* Get init offsets */ 874 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 875 &data_offset); 876 if (ret_val != IXGBE_SUCCESS) 877 goto out; 878 879 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 880 data_offset++; 881 while (!end_data) { 882 /* 883 * Read control word from PHY init contents offset 884 */ 885 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 886 control = (eword & IXGBE_CONTROL_MASK_NL) >> 887 IXGBE_CONTROL_SHIFT_NL; 888 edata = eword & IXGBE_DATA_MASK_NL; 889 switch (control) { 890 case IXGBE_DELAY_NL: 891 data_offset++; 892 DEBUGOUT1("DELAY: %d MS\n", edata); 893 msec_delay(edata); 894 break; 895 case IXGBE_DATA_NL: 896 DEBUGOUT("DATA: \n"); 897 data_offset++; 898 hw->eeprom.ops.read(hw, data_offset++, &phy_offset); 899 for (i = 0; i < edata; i++) { 900 hw->eeprom.ops.read(hw, data_offset, &eword); 901 hw->phy.ops.write_reg(hw, phy_offset, 902 IXGBE_TWINAX_DEV, eword); 903 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 904 phy_offset); 905 data_offset++; 906 phy_offset++; 907 } 908 break; 909 case IXGBE_CONTROL_NL: 910 data_offset++; 911 DEBUGOUT("CONTROL: \n"); 912 if (edata == IXGBE_CONTROL_EOL_NL) { 913 DEBUGOUT("EOL\n"); 914 end_data = true; 915 } else if (edata == IXGBE_CONTROL_SOL_NL) { 916 DEBUGOUT("SOL\n"); 917 } else { 918 DEBUGOUT("Bad control value\n"); 919 ret_val = IXGBE_ERR_PHY; 920 goto out; 921 } 922 break; 923 default: 924 DEBUGOUT("Bad control type\n"); 925 ret_val = IXGBE_ERR_PHY; 926 goto out; 927 } 928 } 929 930 out: 931 return (ret_val); 932 } 933 934 /* 935 * ixgbe_identify_sfp_module_generic - Identifies SFP module 936 * @hw: pointer to hardware structure 937 * 938 * Searches for and identifies the SFP module and assigns appropriate PHY type. 939 */ 940 s32 941 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 942 { 943 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 944 u32 vendor_oui = 0; 945 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 946 u8 identifier = 0; 947 u8 comp_codes_1g = 0; 948 u8 comp_codes_10g = 0; 949 u8 oui_bytes[3] = {0, 0, 0}; 950 u8 cable_tech = 0; 951 u8 cable_spec = 0; 952 u16 enforce_sfp = 0; 953 954 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 955 956 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 957 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 958 status = IXGBE_ERR_SFP_NOT_PRESENT; 959 goto out; 960 } 961 962 status = hw->phy.ops.read_i2c_eeprom(hw, 963 IXGBE_SFF_IDENTIFIER, &identifier); 964 965 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 966 status = IXGBE_ERR_SFP_NOT_PRESENT; 967 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 968 if (hw->phy.type != ixgbe_phy_nl) { 969 hw->phy.id = 0; 970 hw->phy.type = ixgbe_phy_unknown; 971 } 972 goto out; 973 } 974 975 /* LAN ID is needed for sfp_type determination */ 976 hw->mac.ops.set_lan_id(hw); 977 978 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 979 hw->phy.type = ixgbe_phy_sfp_unsupported; 980 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 981 } else { 982 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 983 &comp_codes_1g); 984 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 985 &comp_codes_10g); 986 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 987 &cable_tech); 988 989 /* 990 * ID Module 991 * ============ 992 * 0 SFP_DA_CU 993 * 1 SFP_SR 994 * 2 SFP_LR 995 * 3 SFP_DA_CORE0 - 82599-specific 996 * 4 SFP_DA_CORE1 - 82599-specific 997 * 5 SFP_SR/LR_CORE0 - 82599-specific 998 * 6 SFP_SR/LR_CORE1 - 82599-specific 999 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1000 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1001 * 9 SFP_1g_cu_CORE0 - 82599-specific 1002 * 10 SFP_1g_cu_CORE1 - 82599-specific 1003 */ 1004 if (hw->mac.type == ixgbe_mac_82598EB) { 1005 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1006 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1007 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1008 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1009 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1010 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1011 else 1012 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1013 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1014 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1015 if (hw->bus.lan_id == 0) 1016 hw->phy.sfp_type = 1017 ixgbe_sfp_type_da_cu_core0; 1018 else 1019 hw->phy.sfp_type = 1020 ixgbe_sfp_type_da_cu_core1; 1021 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1022 hw->phy.ops.read_i2c_eeprom( 1023 hw, IXGBE_SFF_CABLE_SPEC_COMP, &cable_spec); 1024 if (cable_spec & 1025 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1026 if (hw->bus.lan_id == 0) 1027 hw->phy.sfp_type = 1028 ixgbe_sfp_type_da_act_lmt_core0; 1029 else 1030 hw->phy.sfp_type = 1031 ixgbe_sfp_type_da_act_lmt_core1; 1032 } else 1033 hw->phy.sfp_type = 1034 ixgbe_sfp_type_unknown; 1035 } else if (comp_codes_10g & 1036 (IXGBE_SFF_10GBASESR_CAPABLE | 1037 IXGBE_SFF_10GBASELR_CAPABLE)) { 1038 if (hw->bus.lan_id == 0) 1039 hw->phy.sfp_type = 1040 ixgbe_sfp_type_srlr_core0; 1041 else 1042 hw->phy.sfp_type = 1043 ixgbe_sfp_type_srlr_core1; 1044 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1045 if (hw->bus.lan_id == 0) 1046 hw->phy.sfp_type = 1047 ixgbe_sfp_type_1g_cu_core0; 1048 else 1049 hw->phy.sfp_type = 1050 ixgbe_sfp_type_1g_cu_core1; 1051 } else { 1052 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1053 } 1054 } 1055 1056 if (hw->phy.sfp_type != stored_sfp_type) 1057 hw->phy.sfp_setup_needed = true; 1058 1059 /* Determine if the SFP+ PHY is dual speed or not. */ 1060 hw->phy.multispeed_fiber = false; 1061 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1062 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1063 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1064 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1065 hw->phy.multispeed_fiber = true; 1066 1067 /* Determine PHY vendor */ 1068 if (hw->phy.type != ixgbe_phy_nl) { 1069 hw->phy.id = identifier; 1070 hw->phy.ops.read_i2c_eeprom(hw, 1071 IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 1072 hw->phy.ops.read_i2c_eeprom(hw, 1073 IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 1074 hw->phy.ops.read_i2c_eeprom(hw, 1075 IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 1076 1077 vendor_oui = 1078 ((oui_bytes[0] << 1079 IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1080 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1081 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1082 1083 switch (vendor_oui) { 1084 case IXGBE_SFF_VENDOR_OUI_TYCO: 1085 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1086 hw->phy.type = 1087 ixgbe_phy_sfp_passive_tyco; 1088 break; 1089 case IXGBE_SFF_VENDOR_OUI_FTL: 1090 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1091 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1092 else 1093 hw->phy.type = ixgbe_phy_sfp_ftl; 1094 break; 1095 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1096 hw->phy.type = ixgbe_phy_sfp_avago; 1097 break; 1098 case IXGBE_SFF_VENDOR_OUI_INTEL: 1099 hw->phy.type = ixgbe_phy_sfp_intel; 1100 break; 1101 default: 1102 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1103 hw->phy.type = 1104 ixgbe_phy_sfp_passive_unknown; 1105 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1106 hw->phy.type = 1107 ixgbe_phy_sfp_active_unknown; 1108 else 1109 hw->phy.type = ixgbe_phy_sfp_unknown; 1110 break; 1111 } 1112 } 1113 1114 /* Allow any DA cable vendor */ 1115 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1116 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1117 status = IXGBE_SUCCESS; 1118 goto out; 1119 } 1120 1121 /* Verify supporteed 1G SFP modules */ 1122 if (comp_codes_10g == 0 && 1123 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1124 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) { 1125 hw->phy.type = ixgbe_phy_sfp_unsupported; 1126 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1127 goto out; 1128 } 1129 1130 /* Anything else 82598-based is supported */ 1131 if (hw->mac.type == ixgbe_mac_82598EB) { 1132 status = IXGBE_SUCCESS; 1133 goto out; 1134 } 1135 1136 (void) ixgbe_get_device_caps(hw, &enforce_sfp); 1137 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1138 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1139 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) { 1140 /* Make sure we're a supported PHY type */ 1141 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1142 status = IXGBE_SUCCESS; 1143 } else { 1144 DEBUGOUT("SFP+ module not supported\n"); 1145 hw->phy.type = ixgbe_phy_sfp_unsupported; 1146 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1147 } 1148 } else { 1149 status = IXGBE_SUCCESS; 1150 } 1151 } 1152 1153 out: 1154 return (status); 1155 } 1156 1157 1158 /* 1159 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1160 * @hw: pointer to hardware structure 1161 * @list_offset: offset to the SFP ID list 1162 * @data_offset: offset to the SFP data block 1163 * 1164 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1165 * so it returns the offsets to the phy init sequence block. 1166 */ 1167 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1168 u16 *list_offset, u16 *data_offset) 1169 { 1170 u16 sfp_id; 1171 u16 sfp_type = hw->phy.sfp_type; 1172 1173 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1174 1175 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1176 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1177 1178 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1179 return (IXGBE_ERR_SFP_NOT_PRESENT); 1180 1181 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1182 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1183 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1184 1185 /* 1186 * Limiting active cables and 1G Phys must be initialized as 1187 * SR modules 1188 */ 1189 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1190 sfp_type == ixgbe_sfp_type_1g_cu_core0) 1191 sfp_type = ixgbe_sfp_type_srlr_core0; 1192 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1193 sfp_type == ixgbe_sfp_type_1g_cu_core1) 1194 sfp_type = ixgbe_sfp_type_srlr_core1; 1195 1196 /* Read offset to PHY init contents */ 1197 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1198 1199 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1200 return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT); 1201 1202 /* Shift offset to first ID word */ 1203 (*list_offset)++; 1204 1205 /* 1206 * Find the matching SFP ID in the EEPROM 1207 * and program the init sequence 1208 */ 1209 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1210 1211 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1212 if (sfp_id == sfp_type) { 1213 (*list_offset)++; 1214 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1215 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1216 DEBUGOUT("SFP+ module not supported\n"); 1217 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1218 } else { 1219 break; 1220 } 1221 } else { 1222 (*list_offset) += 2; 1223 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1224 return (IXGBE_ERR_PHY); 1225 } 1226 } 1227 1228 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1229 DEBUGOUT("No matching SFP+ module found\n"); 1230 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1231 } 1232 1233 return (IXGBE_SUCCESS); 1234 } 1235 1236 /* 1237 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1238 * @hw: pointer to hardware structure 1239 * @byte_offset: EEPROM byte offset to read 1240 * @eeprom_data: value read 1241 * 1242 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1243 */ 1244 s32 1245 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1246 u8 *eeprom_data) 1247 { 1248 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1249 1250 return (hw->phy.ops.read_i2c_byte(hw, byte_offset, 1251 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1252 } 1253 1254 /* 1255 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1256 * @hw: pointer to hardware structure 1257 * @byte_offset: EEPROM byte offset to write 1258 * @eeprom_data: value to write 1259 * 1260 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1261 */ 1262 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1263 u8 eeprom_data) 1264 { 1265 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1266 1267 return (hw->phy.ops.write_i2c_byte(hw, byte_offset, 1268 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1269 } 1270 1271 /* 1272 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1273 * @hw: pointer to hardware structure 1274 * @byte_offset: byte offset to read 1275 * @data: value read 1276 * 1277 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1278 * a specified deivce address. 1279 */ 1280 s32 1281 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1282 u8 dev_addr, u8 *data) 1283 { 1284 s32 status = IXGBE_SUCCESS; 1285 u32 max_retry = 10; 1286 u32 retry = 0; 1287 u16 swfw_mask = 0; 1288 bool nack = 1; 1289 1290 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1291 1292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1293 swfw_mask = IXGBE_GSSR_PHY1_SM; 1294 else 1295 swfw_mask = IXGBE_GSSR_PHY0_SM; 1296 1297 do { 1298 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1299 status = IXGBE_ERR_SWFW_SYNC; 1300 goto read_byte_out; 1301 } 1302 1303 ixgbe_i2c_start(hw); 1304 1305 /* Device Address and write indication */ 1306 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1307 if (status != IXGBE_SUCCESS) 1308 goto fail; 1309 1310 status = ixgbe_get_i2c_ack(hw); 1311 if (status != IXGBE_SUCCESS) 1312 goto fail; 1313 1314 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1315 if (status != IXGBE_SUCCESS) 1316 goto fail; 1317 1318 status = ixgbe_get_i2c_ack(hw); 1319 if (status != IXGBE_SUCCESS) 1320 goto fail; 1321 1322 ixgbe_i2c_start(hw); 1323 1324 /* Device Address and read indication */ 1325 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1326 if (status != IXGBE_SUCCESS) 1327 goto fail; 1328 1329 status = ixgbe_get_i2c_ack(hw); 1330 if (status != IXGBE_SUCCESS) 1331 goto fail; 1332 1333 status = ixgbe_clock_in_i2c_byte(hw, data); 1334 if (status != IXGBE_SUCCESS) 1335 goto fail; 1336 1337 status = ixgbe_clock_out_i2c_bit(hw, nack); 1338 if (status != IXGBE_SUCCESS) 1339 goto fail; 1340 1341 ixgbe_i2c_stop(hw); 1342 break; 1343 1344 fail: 1345 ixgbe_release_swfw_sync(hw, swfw_mask); 1346 msec_delay(100); 1347 ixgbe_i2c_bus_clear(hw); 1348 retry++; 1349 if (retry < max_retry) 1350 DEBUGOUT("I2C byte read error - Retrying.\n"); 1351 else 1352 DEBUGOUT("I2C byte read error.\n"); 1353 } while (retry < max_retry); 1354 1355 ixgbe_release_swfw_sync(hw, swfw_mask); 1356 1357 read_byte_out: 1358 return (status); 1359 } 1360 1361 /* 1362 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1363 * @hw: pointer to hardware structure 1364 * @byte_offset: byte offset to write 1365 * @data: value to write 1366 * 1367 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1368 * a specified device address. 1369 */ 1370 s32 1371 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1372 u8 dev_addr, u8 data) 1373 { 1374 s32 status = IXGBE_SUCCESS; 1375 u32 max_retry = 1; 1376 u32 retry = 0; 1377 u16 swfw_mask = 0; 1378 1379 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1380 1381 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1382 swfw_mask = IXGBE_GSSR_PHY1_SM; 1383 else 1384 swfw_mask = IXGBE_GSSR_PHY0_SM; 1385 1386 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1387 status = IXGBE_ERR_SWFW_SYNC; 1388 goto write_byte_out; 1389 } 1390 1391 do { 1392 ixgbe_i2c_start(hw); 1393 1394 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1395 if (status != IXGBE_SUCCESS) 1396 goto fail; 1397 1398 status = ixgbe_get_i2c_ack(hw); 1399 if (status != IXGBE_SUCCESS) 1400 goto fail; 1401 1402 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1403 if (status != IXGBE_SUCCESS) 1404 goto fail; 1405 1406 status = ixgbe_get_i2c_ack(hw); 1407 if (status != IXGBE_SUCCESS) 1408 goto fail; 1409 1410 status = ixgbe_clock_out_i2c_byte(hw, data); 1411 if (status != IXGBE_SUCCESS) 1412 goto fail; 1413 1414 status = ixgbe_get_i2c_ack(hw); 1415 if (status != IXGBE_SUCCESS) 1416 goto fail; 1417 1418 ixgbe_i2c_stop(hw); 1419 break; 1420 1421 fail: 1422 ixgbe_i2c_bus_clear(hw); 1423 retry++; 1424 if (retry < max_retry) 1425 DEBUGOUT("I2C byte write error - Retrying.\n"); 1426 else 1427 DEBUGOUT("I2C byte write error.\n"); 1428 } while (retry < max_retry); 1429 1430 ixgbe_release_swfw_sync(hw, swfw_mask); 1431 1432 write_byte_out: 1433 return (status); 1434 } 1435 1436 /* 1437 * ixgbe_i2c_start - Sets I2C start condition 1438 * @hw: pointer to hardware structure 1439 * 1440 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1441 */ 1442 static void 1443 ixgbe_i2c_start(struct ixgbe_hw *hw) 1444 { 1445 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1446 1447 DEBUGFUNC("ixgbe_i2c_start"); 1448 1449 /* Start condition must begin with data and clock high */ 1450 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1451 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1452 1453 /* Setup time for start condition (4.7us) */ 1454 usec_delay(IXGBE_I2C_T_SU_STA); 1455 1456 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1457 1458 /* Hold time for start condition (4us) */ 1459 usec_delay(IXGBE_I2C_T_HD_STA); 1460 1461 ixgbe_lower_i2c_clk(hw, &i2cctl); 1462 1463 /* Minimum low period of clock is 4.7 us */ 1464 usec_delay(IXGBE_I2C_T_LOW); 1465 } 1466 1467 /* 1468 * ixgbe_i2c_stop - Sets I2C stop condition 1469 * @hw: pointer to hardware structure 1470 * 1471 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1472 */ 1473 static void 1474 ixgbe_i2c_stop(struct ixgbe_hw *hw) 1475 { 1476 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1477 1478 DEBUGFUNC("ixgbe_i2c_stop"); 1479 1480 /* Stop condition must begin with data low and clock high */ 1481 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1482 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1483 1484 /* Setup time for stop condition (4us) */ 1485 usec_delay(IXGBE_I2C_T_SU_STO); 1486 1487 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1488 1489 /* bus free time between stop and start (4.7us) */ 1490 usec_delay(IXGBE_I2C_T_BUF); 1491 } 1492 1493 /* 1494 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1495 * @hw: pointer to hardware structure 1496 * @data: data byte to clock in 1497 * 1498 * Clocks in one byte data via I2C data/clock 1499 */ 1500 static s32 1501 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1502 { 1503 s32 status = IXGBE_SUCCESS; 1504 s32 i; 1505 bool bit = 0; 1506 1507 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1508 1509 for (i = 7; i >= 0; i--) { 1510 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1511 *data |= bit<<i; 1512 1513 if (status != IXGBE_SUCCESS) 1514 break; 1515 } 1516 1517 return (status); 1518 } 1519 1520 /* 1521 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1522 * @hw: pointer to hardware structure 1523 * @data: data byte clocked out 1524 * 1525 * Clocks out one byte data via I2C data/clock 1526 */ 1527 static s32 1528 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1529 { 1530 s32 status = IXGBE_SUCCESS; 1531 s32 i; 1532 u32 i2cctl; 1533 bool bit = 0; 1534 1535 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1536 1537 for (i = 7; i >= 0; i--) { 1538 bit = (data >> i) & 0x1; 1539 status = ixgbe_clock_out_i2c_bit(hw, bit); 1540 1541 if (status != IXGBE_SUCCESS) 1542 break; 1543 } 1544 1545 /* Release SDA line (set high) */ 1546 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1547 i2cctl |= IXGBE_I2C_DATA_OUT; 1548 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1549 1550 return (status); 1551 } 1552 1553 /* 1554 * ixgbe_get_i2c_ack - Polls for I2C ACK 1555 * @hw: pointer to hardware structure 1556 * 1557 * Clocks in/out one bit via I2C data/clock 1558 */ 1559 static s32 1560 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1561 { 1562 s32 status; 1563 u32 i = 0; 1564 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1565 u32 timeout = 10; 1566 bool ack = 1; 1567 1568 DEBUGFUNC("ixgbe_get_i2c_ack"); 1569 1570 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1571 1572 if (status != IXGBE_SUCCESS) 1573 goto out; 1574 1575 /* Minimum high period of clock is 4us */ 1576 usec_delay(IXGBE_I2C_T_HIGH); 1577 1578 /* 1579 * Poll for ACK. Note that ACK in I2C spec is 1580 * transition from 1 to 0 1581 */ 1582 for (i = 0; i < timeout; i++) { 1583 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1584 ack = ixgbe_get_i2c_data(&i2cctl); 1585 1586 usec_delay(1); 1587 if (ack == 0) 1588 break; 1589 } 1590 1591 if (ack == 1) { 1592 DEBUGOUT("I2C ack was not received.\n"); 1593 status = IXGBE_ERR_I2C; 1594 } 1595 1596 ixgbe_lower_i2c_clk(hw, &i2cctl); 1597 1598 /* Minimum low period of clock is 4.7 us */ 1599 usec_delay(IXGBE_I2C_T_LOW); 1600 1601 out: 1602 return (status); 1603 } 1604 1605 /* 1606 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1607 * @hw: pointer to hardware structure 1608 * @data: read data value 1609 * 1610 * Clocks in one bit via I2C data/clock 1611 */ 1612 static s32 1613 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1614 { 1615 s32 status; 1616 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1617 1618 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1619 1620 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1621 1622 /* Minimum high period of clock is 4us */ 1623 usec_delay(IXGBE_I2C_T_HIGH); 1624 1625 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1626 *data = ixgbe_get_i2c_data(&i2cctl); 1627 1628 ixgbe_lower_i2c_clk(hw, &i2cctl); 1629 1630 /* Minimum low period of clock is 4.7 us */ 1631 usec_delay(IXGBE_I2C_T_LOW); 1632 1633 return (status); 1634 } 1635 1636 /* 1637 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1638 * @hw: pointer to hardware structure 1639 * @data: data value to write 1640 * 1641 * Clocks out one bit via I2C data/clock 1642 */ 1643 static s32 1644 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1645 { 1646 s32 status; 1647 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1648 1649 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1650 1651 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1652 if (status == IXGBE_SUCCESS) { 1653 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1654 1655 /* Minimum high period of clock is 4us */ 1656 usec_delay(IXGBE_I2C_T_HIGH); 1657 1658 ixgbe_lower_i2c_clk(hw, &i2cctl); 1659 1660 /* 1661 * Minimum low period of clock is 4.7 us. 1662 * This also takes care of the data hold time. 1663 */ 1664 usec_delay(IXGBE_I2C_T_LOW); 1665 } else { 1666 status = IXGBE_ERR_I2C; 1667 DEBUGOUT1("I2C data was not set to %X\n", data); 1668 } 1669 1670 return (status); 1671 } 1672 1673 /* 1674 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1675 * @hw: pointer to hardware structure 1676 * @i2cctl: Current value of I2CCTL register 1677 * 1678 * Raises the I2C clock line '0'->'1' 1679 */ 1680 static s32 1681 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1682 { 1683 s32 status = IXGBE_SUCCESS; 1684 1685 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1686 1687 *i2cctl |= IXGBE_I2C_CLK_OUT; 1688 1689 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1690 1691 /* SCL rise time (1000ns) */ 1692 usec_delay(IXGBE_I2C_T_RISE); 1693 1694 return (status); 1695 } 1696 1697 /* 1698 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1699 * @hw: pointer to hardware structure 1700 * @i2cctl: Current value of I2CCTL register 1701 * 1702 * Lowers the I2C clock line '1'->'0' 1703 */ 1704 static void 1705 ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1706 { 1707 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1708 1709 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1710 1711 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1712 1713 /* SCL fall time (300ns) */ 1714 usec_delay(IXGBE_I2C_T_FALL); 1715 } 1716 1717 /* 1718 * ixgbe_set_i2c_data - Sets the I2C data bit 1719 * @hw: pointer to hardware structure 1720 * @i2cctl: Current value of I2CCTL register 1721 * @data: I2C data value (0 or 1) to set 1722 * 1723 * Sets the I2C data bit 1724 */ 1725 static s32 1726 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1727 { 1728 s32 status = IXGBE_SUCCESS; 1729 1730 DEBUGFUNC("ixgbe_set_i2c_data"); 1731 1732 if (data) 1733 *i2cctl |= IXGBE_I2C_DATA_OUT; 1734 else 1735 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1736 1737 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1738 1739 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1740 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1741 1742 /* Verify data was set correctly */ 1743 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1744 if (data != ixgbe_get_i2c_data(i2cctl)) { 1745 status = IXGBE_ERR_I2C; 1746 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1747 } 1748 1749 return (status); 1750 } 1751 1752 /* 1753 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1754 * @hw: pointer to hardware structure 1755 * @i2cctl: Current value of I2CCTL register 1756 * 1757 * Returns the I2C data bit value 1758 */ 1759 static bool 1760 ixgbe_get_i2c_data(u32 *i2cctl) 1761 { 1762 bool data; 1763 1764 DEBUGFUNC("ixgbe_get_i2c_data"); 1765 1766 if (*i2cctl & IXGBE_I2C_DATA_IN) 1767 data = 1; 1768 else 1769 data = 0; 1770 1771 return (data); 1772 } 1773 1774 /* 1775 * ixgbe_i2c_bus_clear - Clears the I2C bus 1776 * @hw: pointer to hardware structure 1777 * 1778 * Clears the I2C bus by sending nine clock pulses. 1779 * Used when data line is stuck low. 1780 */ 1781 void 1782 ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1783 { 1784 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1785 u32 i; 1786 1787 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1788 1789 ixgbe_i2c_start(hw); 1790 1791 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1792 1793 for (i = 0; i < 9; i++) { 1794 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1795 1796 /* Min high period of clock is 4us */ 1797 usec_delay(IXGBE_I2C_T_HIGH); 1798 1799 ixgbe_lower_i2c_clk(hw, &i2cctl); 1800 1801 /* Min low period of clock is 4.7us */ 1802 usec_delay(IXGBE_I2C_T_LOW); 1803 } 1804 1805 ixgbe_i2c_start(hw); 1806 1807 /* Put the i2c bus back to default state */ 1808 ixgbe_i2c_stop(hw); 1809 } 1810 1811 /* 1812 * ixgbe_tn_check_overtemp - Checks if an overtemp occured. 1813 * @hw: pointer to hardware structure 1814 * 1815 * Checks if the LASI temp alarm status was triggered due to overtemp 1816 */ 1817 s32 1818 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1819 { 1820 s32 status = IXGBE_SUCCESS; 1821 u16 phy_data = 0; 1822 1823 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1824 1825 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1826 goto out; 1827 1828 /* Check that the LASI temp alarm status was triggered */ 1829 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1830 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1831 1832 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1833 goto out; 1834 1835 status = IXGBE_ERR_OVERTEMP; 1836 out: 1837 return (status); 1838 } 1839