1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IXGBE_OSDEP_H 30 #define _IXGBE_OSDEP_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/ddi.h> 48 #include <sys/dditypes.h> 49 #include <sys/sunddi.h> 50 #include <sys/pci.h> 51 #include <sys/atomic.h> 52 #include <sys/note.h> 53 #include "ixgbe_debug.h" 54 55 /* function declarations */ 56 struct ixgbe_hw; 57 uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t); 58 59 60 #define usec_delay(x) drv_usecwait(x) 61 #define msec_delay(x) drv_usecwait(x * 1000) 62 63 #ifdef IXGBE_DEBUG 64 #define DEBUGOUT(S) IXGBE_DEBUGLOG_0(NULL, S) 65 #define DEBUGOUT1(S, A) IXGBE_DEBUGLOG_1(NULL, S, A) 66 #define DEBUGOUT2(S, A, B) IXGBE_DEBUGLOG_2(NULL, S, A, B) 67 #define DEBUGOUT3(S, A, B, C) IXGBE_DEBUGLOG_3(NULL, S, A, B, C) 68 #define DEBUGOUT6(S, A, B, C, D, E, F) \ 69 IXGBE_DEBUGLOG_6(NULL, S, A, B, C, D, E, F) 70 #define DEBUGFUNC(F) IXGBE_DEBUGLOG_1(NULL, "Entering %s", F) 71 #else 72 #define DEBUGOUT(S) 73 #define DEBUGOUT1(S, A) 74 #define DEBUGOUT2(S, A, B) 75 #define DEBUGOUT3(S, A, B, C) 76 #define DEBUGOUT6(S, A, B, C, D, E, F) 77 #define DEBUGFUNC(F) 78 #endif 79 80 #define OS_DEP(hw) ((struct ixgbe_osdep *)((hw)->back)) 81 82 #define false B_FALSE 83 #define true B_TRUE 84 85 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg 86 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 87 #define PCI_COMMAND_REGISTER 0x04 88 #define PCI_EX_CONF_CAP 0xE0 89 #define MAX_NUM_UNICAST_ADDRESSES 0x10 90 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 91 #define SPEED_10GB 10000 92 #define SPEED_1GB 1000 93 #define SPEED_100 100 94 #define FULL_DUPLEX 2 95 96 #define IXGBE_WRITE_FLUSH(a) (void) IXGBE_READ_REG(a, IXGBE_STATUS) 97 98 #define IXGBE_WRITE_REG(a, reg, value) \ 99 ddi_put32((OS_DEP(a))->reg_handle, \ 100 (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value)) 101 102 #define IXGBE_READ_REG(a, reg) \ 103 ddi_get32((OS_DEP(a))->reg_handle, \ 104 (uint32_t *)((uintptr_t)(a)->hw_addr + reg)) 105 106 #define msec_delay_irq msec_delay 107 108 #define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x)) 109 110 typedef int8_t s8; 111 typedef int16_t s16; 112 typedef int32_t s32; 113 typedef int64_t s64; 114 typedef uint8_t u8; 115 typedef uint16_t u16; 116 typedef uint32_t u32; 117 typedef uint64_t u64; 118 typedef boolean_t bool; 119 120 struct ixgbe_osdep { 121 ddi_acc_handle_t reg_handle; 122 ddi_acc_handle_t cfg_handle; 123 struct ixgbe *ixgbe; 124 }; 125 126 #ifdef __cplusplus 127 } 128 #endif 129 130 #endif /* _IXGBE_OSDEP_H */ 131