xref: /titanic_41/usr/src/uts/common/io/ixgbe/ixgbe_common.h (revision e4f5a11d4a234623168c1558fcdf4341e11769e1)
1 /*
2  * CDDL HEADER START
3  *
4  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
5  * The contents of this file are subject to the terms of the
6  * Common Development and Distribution License (the "License").
7  * You may not use this file except in compliance with the License.
8  *
9  * You can obtain a copy of the license at:
10  *      http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When using or redistributing this file, you may do so under the
15  * License only. No other modification of this header is permitted.
16  *
17  * If applicable, add the following below this CDDL HEADER, with the
18  * fields enclosed by brackets "[]" replaced with your own identifying
19  * information: Portions Copyright [yyyy] [name of copyright owner]
20  *
21  * CDDL HEADER END
22  */
23 
24 /*
25  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
26  * Use is subject to license terms.
27  */
28 
29 /* IntelVersion: 1.94 sol_ixgbe_shared_339b */
30 
31 #ifndef _IXGBE_COMMON_H
32 #define	_IXGBE_COMMON_H
33 
34 #include "ixgbe_type.h"
35 #ifndef IXGBE_WRITE_REG64
36 #define	IXGBE_WRITE_REG64(hw, reg, value) \
37 	do { \
38 		IXGBE_WRITE_REG(hw, reg, (u32) value); \
39 		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
40 	} while (0)
41 #endif /* IXGBE_WRITE_REG64 */
42 
43 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
44 
45 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
46 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
47 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
48 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
49 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
50 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
51 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
52 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
53 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
54 
55 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
56 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
57 
58 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
59 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
60 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
61 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
62     u16 *data);
63 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
64 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
65     u16 *checksum_val);
66 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
67 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68 
69 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
70     u32 enable_addr);
71 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
72 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
73 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
74     u32 mc_addr_count,
75     ixgbe_mc_addr_itr func);
76 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
77     u32 addr_count, ixgbe_mc_addr_itr func);
78 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
79 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
80 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
81 
82 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
83 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
84 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
85 
86 s32 ixgbe_validate_mac_addr(u8 *mac_addr);
87 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
88 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
89 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
90 
91 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
92 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
93 
94 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
95 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
96 
97 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
98 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
99 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
100 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
101 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
102     u32 vind, bool vlan_on);
103 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
104 
105 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
106     ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete);
107 
108 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
109     u16 *wwpn_prefix);
110 
111 #endif /* _IXGBE_COMMON_H */
112