1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.90 v2-7-8_2009-4-7 */ 30 31 #ifndef _IXGBE_COMMON_H 32 #define _IXGBE_COMMON_H 33 34 #include "ixgbe_type.h" 35 36 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); 37 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); 38 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); 39 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); 40 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num); 41 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); 42 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); 43 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw); 44 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); 45 46 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); 47 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); 48 49 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 50 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 51 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 52 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 53 u16 *data); 54 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 55 u16 *checksum_val); 56 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); 57 58 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 59 u32 enable_addr); 60 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index); 61 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); 62 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 63 u32 mc_addr_count, 64 ixgbe_mc_addr_itr func); 65 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 66 u32 addr_count, ixgbe_mc_addr_itr func); 67 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 68 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); 69 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); 70 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); 71 72 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num); 73 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num); 74 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw); 75 76 s32 ixgbe_validate_mac_addr(u8 *mac_addr); 77 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask); 78 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask); 79 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 80 81 s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val); 82 s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val); 83 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); 84 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); 85 86 #endif /* _IXGBE_COMMON_H */ 87