1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 /* IntelVersion: 1.199 v2-7-8_2009-4-7 */ 29 30 #include "ixgbe_common.h" 31 #include "ixgbe_api.h" 32 33 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 34 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 35 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 36 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 37 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 38 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 39 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 40 u16 count); 41 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 42 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 43 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 44 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 45 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 46 47 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 48 49 /* 50 * ixgbe_init_ops_generic - Inits function ptrs 51 * @hw: pointer to the hardware structure 52 * 53 * Initialize the function pointers. 54 */ 55 s32 56 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 57 { 58 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 59 struct ixgbe_mac_info *mac = &hw->mac; 60 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 61 62 /* EEPROM */ 63 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 64 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 65 if (eec & (1 << 8)) 66 eeprom->ops.read = &ixgbe_read_eeprom_generic; 67 else 68 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 69 eeprom->ops.write = &ixgbe_write_eeprom_generic; 70 eeprom->ops.validate_checksum = 71 &ixgbe_validate_eeprom_checksum_generic; 72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 73 74 /* MAC */ 75 mac->ops.init_hw = &ixgbe_init_hw_generic; 76 mac->ops.reset_hw = NULL; 77 mac->ops.start_hw = &ixgbe_start_hw_generic; 78 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 79 mac->ops.get_media_type = NULL; 80 mac->ops.get_supported_physical_layer = NULL; 81 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 82 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 83 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 84 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 85 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 86 87 /* LEDs */ 88 mac->ops.led_on = &ixgbe_led_on_generic; 89 mac->ops.led_off = &ixgbe_led_off_generic; 90 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 91 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 92 93 /* RAR, Multicast, VLAN */ 94 mac->ops.set_rar = &ixgbe_set_rar_generic; 95 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 96 mac->ops.insert_mac_addr = NULL; 97 mac->ops.set_vmdq = NULL; 98 mac->ops.clear_vmdq = NULL; 99 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 100 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 101 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 102 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 103 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 104 mac->ops.clear_vfta = NULL; 105 mac->ops.set_vfta = NULL; 106 mac->ops.init_uta_tables = NULL; 107 108 /* Flow Control */ 109 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 110 111 /* Link */ 112 mac->ops.get_link_capabilities = NULL; 113 mac->ops.setup_link = NULL; 114 mac->ops.setup_link_speed = NULL; 115 mac->ops.check_link = NULL; 116 117 return (IXGBE_SUCCESS); 118 } 119 120 /* 121 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 122 * @hw: pointer to hardware structure 123 * 124 * Starts the hardware by filling the bus info structure and media type, clears 125 * all on chip counters, initializes receive address registers, multicast 126 * table, VLAN filter table, calls routine to set up link and flow control 127 * settings, and leaves transmit and receive units disabled and uninitialized 128 */ 129 s32 130 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 131 { 132 u32 ctrl_ext; 133 134 /* Set the media type */ 135 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 136 137 /* PHY ops initialization must be done in reset_hw() */ 138 139 /* Identify the PHY */ 140 hw->phy.ops.identify(hw); 141 142 /* Clear the VLAN filter table */ 143 hw->mac.ops.clear_vfta(hw); 144 145 /* Clear statistics registers */ 146 hw->mac.ops.clear_hw_cntrs(hw); 147 148 /* Set No Snoop Disable */ 149 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 150 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 151 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 152 IXGBE_WRITE_FLUSH(hw); 153 154 /* Setup flow control */ 155 (void) ixgbe_setup_fc(hw, 0); 156 157 /* Clear adapter stopped flag */ 158 hw->adapter_stopped = false; 159 160 return (IXGBE_SUCCESS); 161 } 162 163 /* 164 * ixgbe_init_hw_generic - Generic hardware initialization 165 * @hw: pointer to hardware structure 166 * 167 * Initialize the hardware by resetting the hardware, filling the bus info 168 * structure and media type, clears all on chip counters, initializes receive 169 * address registers, multicast table, VLAN filter table, calls routine to set 170 * up link and flow control settings, and leaves transmit and receive units 171 * disabled and uninitialized 172 */ 173 s32 174 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 175 { 176 s32 status = IXGBE_SUCCESS; 177 178 /* Reset the hardware */ 179 status = hw->mac.ops.reset_hw(hw); 180 181 if (status == IXGBE_SUCCESS) { 182 /* Start the HW */ 183 status = hw->mac.ops.start_hw(hw); 184 } 185 186 return (status); 187 } 188 189 /* 190 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 191 * @hw: pointer to hardware structure 192 * 193 * Clears all hardware statistics counters by reading them from the hardware 194 * Statistics counters are clear on read. 195 */ 196 s32 197 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 198 { 199 u16 i = 0; 200 201 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 202 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 203 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 204 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 205 for (i = 0; i < 8; i++) 206 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 207 208 (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 209 (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 210 (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 211 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 212 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 213 if (hw->mac.type >= ixgbe_mac_82599EB) { 214 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 215 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 216 } else { 217 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 218 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 219 } 220 221 for (i = 0; i < 8; i++) { 222 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 223 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 224 if (hw->mac.type >= ixgbe_mac_82599EB) { 225 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 226 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 227 } else { 228 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 229 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 230 } 231 } 232 if (hw->mac.type >= ixgbe_mac_82599EB) 233 for (i = 0; i < 8; i++) 234 (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 235 236 (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 237 (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 238 (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 239 (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 240 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 241 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 242 (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 243 (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 244 (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 245 (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 246 (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 247 (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 248 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 249 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 250 for (i = 0; i < 8; i++) 251 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 252 (void) IXGBE_READ_REG(hw, IXGBE_RUC); 253 (void) IXGBE_READ_REG(hw, IXGBE_RFC); 254 (void) IXGBE_READ_REG(hw, IXGBE_ROC); 255 (void) IXGBE_READ_REG(hw, IXGBE_RJC); 256 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 257 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 258 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 259 (void) IXGBE_READ_REG(hw, IXGBE_TORL); 260 (void) IXGBE_READ_REG(hw, IXGBE_TORH); 261 (void) IXGBE_READ_REG(hw, IXGBE_TPR); 262 (void) IXGBE_READ_REG(hw, IXGBE_TPT); 263 (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 264 (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 265 (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 266 (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 267 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 268 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 269 (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 270 (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 271 for (i = 0; i < 16; i++) { 272 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 273 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 274 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 275 if (hw->mac.type >= ixgbe_mac_82599EB) { 276 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 277 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 278 } else { 279 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 280 } 281 } 282 283 return (IXGBE_SUCCESS); 284 } 285 286 /* 287 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 288 * @hw: pointer to hardware structure 289 * @pba_num: stores the part number from the EEPROM 290 * 291 * Reads the part number from the EEPROM. 292 */ 293 s32 294 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 295 { 296 s32 ret_val; 297 u16 data; 298 299 DEBUGFUNC("ixgbe_read_pba_num_generic"); 300 301 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 302 if (ret_val) { 303 DEBUGOUT("NVM Read Error\n"); 304 return (ret_val); 305 } 306 *pba_num = (u32)(data << 16); 307 308 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 309 if (ret_val) { 310 DEBUGOUT("NVM Read Error\n"); 311 return (ret_val); 312 } 313 *pba_num |= data; 314 315 return (IXGBE_SUCCESS); 316 } 317 318 /* 319 * ixgbe_get_mac_addr_generic - Generic get MAC address 320 * @hw: pointer to hardware structure 321 * @mac_addr: Adapter MAC address 322 * 323 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 324 * A reset of the adapter must be performed prior to calling this function 325 * in order for the MAC address to have been loaded from the EEPROM into RAR0 326 */ 327 s32 328 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 329 { 330 u32 rar_high; 331 u32 rar_low; 332 u16 i; 333 334 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 335 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 336 337 for (i = 0; i < 4; i++) 338 mac_addr[i] = (u8)(rar_low >> (i*8)); 339 340 for (i = 0; i < 2; i++) 341 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 342 343 return (IXGBE_SUCCESS); 344 } 345 346 /* 347 * ixgbe_get_bus_info_generic - Generic set PCI bus info 348 * @hw: pointer to hardware structure 349 * 350 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 351 */ 352 s32 353 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 354 { 355 struct ixgbe_mac_info *mac = &hw->mac; 356 u16 link_status; 357 358 hw->bus.type = ixgbe_bus_type_pci_express; 359 360 /* Get the negotiated link width and speed from PCI config space */ 361 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 362 363 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 364 case IXGBE_PCI_LINK_WIDTH_1: 365 hw->bus.width = ixgbe_bus_width_pcie_x1; 366 break; 367 case IXGBE_PCI_LINK_WIDTH_2: 368 hw->bus.width = ixgbe_bus_width_pcie_x2; 369 break; 370 case IXGBE_PCI_LINK_WIDTH_4: 371 hw->bus.width = ixgbe_bus_width_pcie_x4; 372 break; 373 case IXGBE_PCI_LINK_WIDTH_8: 374 hw->bus.width = ixgbe_bus_width_pcie_x8; 375 break; 376 default: 377 hw->bus.width = ixgbe_bus_width_unknown; 378 break; 379 } 380 381 switch (link_status & IXGBE_PCI_LINK_SPEED) { 382 case IXGBE_PCI_LINK_SPEED_2500: 383 hw->bus.speed = ixgbe_bus_speed_2500; 384 break; 385 case IXGBE_PCI_LINK_SPEED_5000: 386 hw->bus.speed = ixgbe_bus_speed_5000; 387 break; 388 default: 389 hw->bus.speed = ixgbe_bus_speed_unknown; 390 break; 391 } 392 393 mac->ops.set_lan_id(hw); 394 395 return (IXGBE_SUCCESS); 396 } 397 398 399 /* 400 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 401 * @hw: pointer to the HW structure 402 * 403 * Determines the LAN function id by reading memory-mapped registers 404 * and swaps the port value if requested. 405 */ 406 void 407 ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 408 { 409 struct ixgbe_bus_info *bus = &hw->bus; 410 u32 reg; 411 412 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 413 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 414 bus->lan_id = bus->func; 415 416 /* check for a port swap */ 417 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 418 if (reg & IXGBE_FACTPS_LFS) 419 bus->func ^= 0x1; 420 } 421 422 /* 423 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 424 * @hw: pointer to hardware structure 425 * 426 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 427 * disables transmit and receive units. The adapter_stopped flag is used by 428 * the shared code and drivers to determine if the adapter is in a stopped 429 * state and should not touch the hardware. 430 */ 431 s32 432 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 433 { 434 u32 number_of_queues; 435 u32 reg_val; 436 u16 i; 437 438 /* 439 * Set the adapter_stopped flag so other driver functions stop touching 440 * the hardware 441 */ 442 hw->adapter_stopped = true; 443 444 /* Disable the receive unit */ 445 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 446 reg_val &= ~(IXGBE_RXCTRL_RXEN); 447 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 448 IXGBE_WRITE_FLUSH(hw); 449 msec_delay(2); 450 451 /* Clear interrupt mask to stop from interrupts being generated */ 452 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 453 454 /* Clear any pending interrupts */ 455 (void) IXGBE_READ_REG(hw, IXGBE_EICR); 456 457 /* Disable the transmit unit. Each queue must be disabled. */ 458 number_of_queues = hw->mac.max_tx_queues; 459 for (i = 0; i < number_of_queues; i++) { 460 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 461 if (reg_val & IXGBE_TXDCTL_ENABLE) { 462 reg_val &= ~IXGBE_TXDCTL_ENABLE; 463 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 464 } 465 } 466 467 /* 468 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 469 * access and verify no pending requests 470 */ 471 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 472 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 473 } 474 475 return (IXGBE_SUCCESS); 476 } 477 478 /* 479 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 480 * @hw: pointer to hardware structure 481 * @index: led number to turn on 482 */ 483 s32 484 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 485 { 486 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 487 488 /* To turn on the LED, set mode to ON. */ 489 led_reg &= ~IXGBE_LED_MODE_MASK(index); 490 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 491 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 492 IXGBE_WRITE_FLUSH(hw); 493 494 return (IXGBE_SUCCESS); 495 } 496 497 /* 498 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 499 * @hw: pointer to hardware structure 500 * @index: led number to turn off 501 */ 502 s32 503 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 504 { 505 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 506 507 /* To turn off the LED, set mode to OFF. */ 508 led_reg &= ~IXGBE_LED_MODE_MASK(index); 509 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 510 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 511 IXGBE_WRITE_FLUSH(hw); 512 513 return (IXGBE_SUCCESS); 514 } 515 516 /* 517 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 518 * @hw: pointer to hardware structure 519 * 520 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 521 * ixgbe_hw struct in order to set up EEPROM access. 522 */ 523 s32 524 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 525 { 526 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 527 u32 eec; 528 u16 eeprom_size; 529 530 if (eeprom->type == ixgbe_eeprom_uninitialized) { 531 eeprom->type = ixgbe_eeprom_none; 532 /* 533 * Set default semaphore delay to 10ms which is a well 534 * tested value 535 */ 536 eeprom->semaphore_delay = 10; 537 538 /* 539 * Check for EEPROM present first. 540 * If not present leave as none 541 */ 542 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 543 if (eec & IXGBE_EEC_PRES) { 544 eeprom->type = ixgbe_eeprom_spi; 545 546 /* 547 * SPI EEPROM is assumed here. This code would need to 548 * change if a future EEPROM is not SPI. 549 */ 550 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 551 IXGBE_EEC_SIZE_SHIFT); 552 eeprom->word_size = 1 << (eeprom_size + 553 IXGBE_EEPROM_WORD_SIZE_SHIFT); 554 } 555 556 if (eec & IXGBE_EEC_ADDR_SIZE) 557 eeprom->address_bits = 16; 558 else 559 eeprom->address_bits = 8; 560 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 561 "%d\n", eeprom->type, eeprom->word_size, 562 eeprom->address_bits); 563 } 564 565 return (IXGBE_SUCCESS); 566 } 567 568 /* 569 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 570 * @hw: pointer to hardware structure 571 * @offset: offset within the EEPROM to be written to 572 * @data: 16 bit word to be written to the EEPROM 573 * 574 * If ixgbe_eeprom_update_checksum is not called after this function, the 575 * EEPROM will most likely contain an invalid checksum. 576 */ 577 s32 578 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 579 { 580 s32 status; 581 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 582 583 hw->eeprom.ops.init_params(hw); 584 585 if (offset >= hw->eeprom.word_size) { 586 status = IXGBE_ERR_EEPROM; 587 goto out; 588 } 589 590 /* Prepare the EEPROM for writing */ 591 status = ixgbe_acquire_eeprom(hw); 592 593 if (status == IXGBE_SUCCESS) { 594 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 595 ixgbe_release_eeprom(hw); 596 status = IXGBE_ERR_EEPROM; 597 } 598 } 599 600 if (status == IXGBE_SUCCESS) { 601 ixgbe_standby_eeprom(hw); 602 603 /* Send the WRITE ENABLE command (8 bit opcode ) */ 604 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 605 IXGBE_EEPROM_OPCODE_BITS); 606 607 ixgbe_standby_eeprom(hw); 608 609 /* 610 * Some SPI eeproms use the 8th address bit embedded in the 611 * opcode 612 */ 613 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 614 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 615 616 /* Send the Write command (8-bit opcode + addr) */ 617 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 618 IXGBE_EEPROM_OPCODE_BITS); 619 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 620 hw->eeprom.address_bits); 621 622 /* Send the data */ 623 data = (data >> 8) | (data << 8); 624 ixgbe_shift_out_eeprom_bits(hw, data, 16); 625 ixgbe_standby_eeprom(hw); 626 627 msec_delay(hw->eeprom.semaphore_delay); 628 629 /* Done with writing - release the EEPROM */ 630 ixgbe_release_eeprom(hw); 631 } 632 633 out: 634 return (status); 635 } 636 637 /* 638 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 639 * @hw: pointer to hardware structure 640 * @offset: offset within the EEPROM to be read 641 * @data: read 16 bit value from EEPROM 642 * 643 * Reads 16 bit value from EEPROM through bit-bang method 644 */ 645 s32 646 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 647 u16 *data) 648 { 649 s32 status; 650 u16 word_in; 651 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 652 653 hw->eeprom.ops.init_params(hw); 654 655 if (offset >= hw->eeprom.word_size) { 656 status = IXGBE_ERR_EEPROM; 657 goto out; 658 } 659 660 /* Prepare the EEPROM for reading */ 661 status = ixgbe_acquire_eeprom(hw); 662 663 if (status == IXGBE_SUCCESS) { 664 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 665 ixgbe_release_eeprom(hw); 666 status = IXGBE_ERR_EEPROM; 667 } 668 } 669 670 if (status == IXGBE_SUCCESS) { 671 ixgbe_standby_eeprom(hw); 672 673 /* 674 * Some SPI eeproms use the 8th address bit embedded in the 675 * opcode 676 */ 677 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 678 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 679 680 /* Send the READ command (opcode + addr) */ 681 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 682 IXGBE_EEPROM_OPCODE_BITS); 683 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 684 hw->eeprom.address_bits); 685 686 /* Read the data. */ 687 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 688 *data = (word_in >> 8) | (word_in << 8); 689 690 /* End this read operation */ 691 ixgbe_release_eeprom(hw); 692 } 693 694 out: 695 return (status); 696 } 697 698 /* 699 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 700 * @hw: pointer to hardware structure 701 * @offset: offset of word in the EEPROM to read 702 * @data: word read from the EEPROM 703 * 704 * Reads a 16 bit word from the EEPROM using the EERD register. 705 */ 706 s32 707 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 708 { 709 u32 eerd; 710 s32 status; 711 712 hw->eeprom.ops.init_params(hw); 713 714 if (offset >= hw->eeprom.word_size) { 715 status = IXGBE_ERR_EEPROM; 716 goto out; 717 } 718 719 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 720 IXGBE_EEPROM_READ_REG_START; 721 722 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 723 status = ixgbe_poll_eeprom_eerd_done(hw); 724 725 if (status == IXGBE_SUCCESS) { 726 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 727 IXGBE_EEPROM_READ_REG_DATA); 728 } else { 729 DEBUGOUT("Eeprom read timed out\n"); 730 } 731 732 out: 733 return (status); 734 } 735 736 /* 737 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 738 * @hw: pointer to hardware structure 739 * 740 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 741 */ 742 static s32 743 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 744 { 745 u32 i; 746 u32 reg; 747 s32 status = IXGBE_ERR_EEPROM; 748 749 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 750 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 751 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 752 status = IXGBE_SUCCESS; 753 break; 754 } 755 usec_delay(5); 756 } 757 return (status); 758 } 759 760 /* 761 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 762 * @hw: pointer to hardware structure 763 * 764 * Prepares EEPROM for access using bit-bang method. This function should 765 * be called before issuing a command to the EEPROM. 766 */ 767 static s32 768 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 769 { 770 s32 status = IXGBE_SUCCESS; 771 u32 eec; 772 u32 i; 773 774 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 775 status = IXGBE_ERR_SWFW_SYNC; 776 777 if (status == IXGBE_SUCCESS) { 778 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 779 780 /* Request EEPROM Access */ 781 eec |= IXGBE_EEC_REQ; 782 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 783 784 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 785 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 786 if (eec & IXGBE_EEC_GNT) 787 break; 788 usec_delay(5); 789 } 790 791 /* Release if grant not acquired */ 792 if (!(eec & IXGBE_EEC_GNT)) { 793 eec &= ~IXGBE_EEC_REQ; 794 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 795 DEBUGOUT("Could not acquire EEPROM grant\n"); 796 797 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 798 status = IXGBE_ERR_EEPROM; 799 } 800 } 801 802 /* Setup EEPROM for Read/Write */ 803 if (status == IXGBE_SUCCESS) { 804 /* Clear CS and SK */ 805 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 806 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 807 IXGBE_WRITE_FLUSH(hw); 808 usec_delay(1); 809 } 810 return (status); 811 } 812 813 /* 814 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 815 * @hw: pointer to hardware structure 816 * 817 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 818 */ 819 static s32 820 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 821 { 822 s32 status = IXGBE_ERR_EEPROM; 823 u32 timeout; 824 u32 i; 825 u32 swsm; 826 827 /* Set timeout value based on size of EEPROM */ 828 timeout = hw->eeprom.word_size + 1; 829 830 /* Get SMBI software semaphore between device drivers first */ 831 for (i = 0; i < timeout; i++) { 832 /* 833 * If the SMBI bit is 0 when we read it, then the bit will be 834 * set and we have the semaphore 835 */ 836 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 837 if (!(swsm & IXGBE_SWSM_SMBI)) { 838 status = IXGBE_SUCCESS; 839 break; 840 } 841 msec_delay(1); 842 } 843 844 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 845 if (status == IXGBE_SUCCESS) { 846 for (i = 0; i < timeout; i++) { 847 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 848 849 /* Set the SW EEPROM semaphore bit to request access */ 850 swsm |= IXGBE_SWSM_SWESMBI; 851 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 852 853 /* 854 * If we set the bit successfully then we got the 855 * semaphore. 856 */ 857 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 858 if (swsm & IXGBE_SWSM_SWESMBI) 859 break; 860 861 usec_delay(50); 862 } 863 864 /* 865 * Release semaphores and return error if SW EEPROM semaphore 866 * was not granted because we don't have access to the EEPROM 867 */ 868 if (i >= timeout) { 869 DEBUGOUT("SWESMBI Software EEPROM semaphore " 870 "not granted.\n"); 871 ixgbe_release_eeprom_semaphore(hw); 872 status = IXGBE_ERR_EEPROM; 873 } 874 } else { 875 DEBUGOUT("Software semaphore SMBI between device drivers " 876 "not granted.\n"); 877 } 878 879 return (status); 880 } 881 882 /* 883 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 884 * @hw: pointer to hardware structure 885 * 886 * This function clears hardware semaphore bits. 887 */ 888 static void 889 ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 890 { 891 u32 swsm; 892 893 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 894 895 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 896 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 897 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 898 IXGBE_WRITE_FLUSH(hw); 899 } 900 901 /* 902 * ixgbe_ready_eeprom - Polls for EEPROM ready 903 * @hw: pointer to hardware structure 904 */ 905 static s32 906 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 907 { 908 s32 status = IXGBE_SUCCESS; 909 u16 i; 910 u8 spi_stat_reg; 911 912 /* 913 * Read "Status Register" repeatedly until the LSB is cleared. The 914 * EEPROM will signal that the command has been completed by clearing 915 * bit 0 of the internal status register. If it's not cleared within 916 * 5 milliseconds, then error out. 917 */ 918 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 919 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 920 IXGBE_EEPROM_OPCODE_BITS); 921 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 922 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 923 break; 924 925 usec_delay(5); 926 ixgbe_standby_eeprom(hw); 927 }; 928 929 /* 930 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 931 * devices (and only 0-5mSec on 5V devices) 932 */ 933 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 934 DEBUGOUT("SPI EEPROM Status error\n"); 935 status = IXGBE_ERR_EEPROM; 936 } 937 938 return (status); 939 } 940 941 /* 942 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 943 * @hw: pointer to hardware structure 944 */ 945 static void 946 ixgbe_standby_eeprom(struct ixgbe_hw *hw) 947 { 948 u32 eec; 949 950 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 951 952 /* Toggle CS to flush commands */ 953 eec |= IXGBE_EEC_CS; 954 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 955 IXGBE_WRITE_FLUSH(hw); 956 usec_delay(1); 957 eec &= ~IXGBE_EEC_CS; 958 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 959 IXGBE_WRITE_FLUSH(hw); 960 usec_delay(1); 961 } 962 963 /* 964 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 965 * @hw: pointer to hardware structure 966 * @data: data to send to the EEPROM 967 * @count: number of bits to shift out 968 */ 969 static void 970 ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 971 u16 count) 972 { 973 u32 eec; 974 u32 mask; 975 u32 i; 976 977 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 978 979 /* 980 * Mask is used to shift "count" bits of "data" out to the EEPROM 981 * one bit at a time. Determine the starting bit based on count 982 */ 983 mask = 0x01 << (count - 1); 984 985 for (i = 0; i < count; i++) { 986 /* 987 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 988 * "1", and then raising and then lowering the clock (the SK 989 * bit controls the clock input to the EEPROM). A "0" is 990 * shifted out to the EEPROM by setting "DI" to "0" and then 991 * raising and then lowering the clock. 992 */ 993 if (data & mask) 994 eec |= IXGBE_EEC_DI; 995 else 996 eec &= ~IXGBE_EEC_DI; 997 998 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 999 IXGBE_WRITE_FLUSH(hw); 1000 1001 usec_delay(1); 1002 1003 ixgbe_raise_eeprom_clk(hw, &eec); 1004 ixgbe_lower_eeprom_clk(hw, &eec); 1005 1006 /* 1007 * Shift mask to signify next bit of data to shift in to the 1008 * EEPROM 1009 */ 1010 mask = mask >> 1; 1011 }; 1012 1013 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1014 eec &= ~IXGBE_EEC_DI; 1015 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1016 IXGBE_WRITE_FLUSH(hw); 1017 } 1018 1019 /* 1020 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1021 * @hw: pointer to hardware structure 1022 */ 1023 static u16 1024 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1025 { 1026 u32 eec; 1027 u32 i; 1028 u16 data = 0; 1029 1030 /* 1031 * In order to read a register from the EEPROM, we need to shift 1032 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1033 * the clock input to the EEPROM (setting the SK bit), and then reading 1034 * the value of the "DO" bit. During this "shifting in" process the 1035 * "DI" bit should always be clear. 1036 */ 1037 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1038 1039 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1040 1041 for (i = 0; i < count; i++) { 1042 data = data << 1; 1043 ixgbe_raise_eeprom_clk(hw, &eec); 1044 1045 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1046 1047 eec &= ~(IXGBE_EEC_DI); 1048 if (eec & IXGBE_EEC_DO) 1049 data |= 1; 1050 1051 ixgbe_lower_eeprom_clk(hw, &eec); 1052 } 1053 1054 return (data); 1055 } 1056 1057 /* 1058 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1059 * @hw: pointer to hardware structure 1060 * @eec: EEC register's current value 1061 */ 1062 static void 1063 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1064 { 1065 /* 1066 * Raise the clock input to the EEPROM 1067 * (setting the SK bit), then delay 1068 */ 1069 *eec = *eec | IXGBE_EEC_SK; 1070 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1071 IXGBE_WRITE_FLUSH(hw); 1072 usec_delay(1); 1073 } 1074 1075 /* 1076 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1077 * @hw: pointer to hardware structure 1078 * @eecd: EECD's current value 1079 */ 1080 static void 1081 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1082 { 1083 /* 1084 * Lower the clock input to the EEPROM (clearing the SK bit), then 1085 * delay 1086 */ 1087 *eec = *eec & ~IXGBE_EEC_SK; 1088 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1089 IXGBE_WRITE_FLUSH(hw); 1090 usec_delay(1); 1091 } 1092 1093 /* 1094 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1095 * @hw: pointer to hardware structure 1096 */ 1097 static void 1098 ixgbe_release_eeprom(struct ixgbe_hw *hw) 1099 { 1100 u32 eec; 1101 1102 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1103 1104 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1105 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1106 1107 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1108 IXGBE_WRITE_FLUSH(hw); 1109 1110 usec_delay(1); 1111 1112 /* Stop requesting EEPROM access */ 1113 eec &= ~IXGBE_EEC_REQ; 1114 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1115 1116 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1117 } 1118 1119 /* 1120 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1121 * @hw: pointer to hardware structure 1122 */ 1123 static u16 1124 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1125 { 1126 u16 i; 1127 u16 j; 1128 u16 checksum = 0; 1129 u16 length = 0; 1130 u16 pointer = 0; 1131 u16 word = 0; 1132 1133 /* Include 0x0-0x3F in the checksum */ 1134 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1135 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1136 DEBUGOUT("EEPROM read failed\n"); 1137 break; 1138 } 1139 checksum += word; 1140 } 1141 1142 /* Include all data from pointers except for the fw pointer */ 1143 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1144 hw->eeprom.ops.read(hw, i, &pointer); 1145 1146 /* Make sure the pointer seems valid */ 1147 if (pointer != 0xFFFF && pointer != 0) { 1148 hw->eeprom.ops.read(hw, pointer, &length); 1149 1150 if (length != 0xFFFF && length != 0) { 1151 for (j = pointer+1; j <= pointer+length; j++) { 1152 hw->eeprom.ops.read(hw, j, &word); 1153 checksum += word; 1154 } 1155 } 1156 } 1157 } 1158 1159 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1160 1161 return (checksum); 1162 } 1163 1164 /* 1165 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1166 * @hw: pointer to hardware structure 1167 * @checksum_val: calculated checksum 1168 * 1169 * Performs checksum calculation and validates the EEPROM checksum. If the 1170 * caller does not need checksum_val, the value can be NULL. 1171 */ 1172 s32 1173 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1174 u16 *checksum_val) 1175 { 1176 s32 status; 1177 u16 checksum; 1178 u16 read_checksum = 0; 1179 1180 /* 1181 * Read the first word from the EEPROM. If this times out or fails, do 1182 * not continue or we could be in for a very long wait while every 1183 * EEPROM read fails 1184 */ 1185 status = hw->eeprom.ops.read(hw, 0, &checksum); 1186 1187 if (status == IXGBE_SUCCESS) { 1188 checksum = ixgbe_calc_eeprom_checksum(hw); 1189 1190 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1191 1192 /* 1193 * Verify read checksum from EEPROM is the same as 1194 * calculated checksum 1195 */ 1196 if (read_checksum != checksum) 1197 status = IXGBE_ERR_EEPROM_CHECKSUM; 1198 1199 /* If the user cares, return the calculated checksum */ 1200 if (checksum_val) 1201 *checksum_val = checksum; 1202 } else { 1203 DEBUGOUT("EEPROM read failed\n"); 1204 } 1205 1206 return (status); 1207 } 1208 1209 /* 1210 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1211 * @hw: pointer to hardware structure 1212 */ 1213 s32 1214 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1215 { 1216 s32 status; 1217 u16 checksum; 1218 1219 /* 1220 * Read the first word from the EEPROM. If this times out or fails, do 1221 * not continue or we could be in for a very long wait while every 1222 * EEPROM read fails 1223 */ 1224 status = hw->eeprom.ops.read(hw, 0, &checksum); 1225 1226 if (status == IXGBE_SUCCESS) { 1227 checksum = ixgbe_calc_eeprom_checksum(hw); 1228 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1229 checksum); 1230 } else { 1231 DEBUGOUT("EEPROM read failed\n"); 1232 } 1233 1234 return (status); 1235 } 1236 1237 /* 1238 * ixgbe_validate_mac_addr - Validate MAC address 1239 * @mac_addr: pointer to MAC address. 1240 * 1241 * Tests a MAC address to ensure it is a valid Individual Address 1242 */ 1243 s32 1244 ixgbe_validate_mac_addr(u8 *mac_addr) 1245 { 1246 s32 status = IXGBE_SUCCESS; 1247 1248 /* Make sure it is not a multicast address */ 1249 if (IXGBE_IS_MULTICAST(mac_addr)) { 1250 DEBUGOUT("MAC address is multicast\n"); 1251 status = IXGBE_ERR_INVALID_MAC_ADDR; 1252 /* Not a broadcast address */ 1253 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1254 DEBUGOUT("MAC address is broadcast\n"); 1255 status = IXGBE_ERR_INVALID_MAC_ADDR; 1256 /* Reject the zero address */ 1257 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1258 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1259 DEBUGOUT("MAC address is all zeros\n"); 1260 status = IXGBE_ERR_INVALID_MAC_ADDR; 1261 } 1262 return (status); 1263 } 1264 1265 /* 1266 * ixgbe_set_rar_generic - Set Rx address register 1267 * @hw: pointer to hardware structure 1268 * @index: Receive address register to write 1269 * @addr: Address to put into receive address register 1270 * @vmdq: VMDq "set" or "pool" index 1271 * @enable_addr: set flag that address is active 1272 * 1273 * Puts an ethernet address into a receive address register. 1274 */ 1275 s32 1276 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1277 u32 enable_addr) 1278 { 1279 u32 rar_low, rar_high; 1280 u32 rar_entries = hw->mac.num_rar_entries; 1281 1282 /* setup VMDq pool selection before this RAR gets enabled */ 1283 hw->mac.ops.set_vmdq(hw, index, vmdq); 1284 1285 /* Make sure we are using a valid rar index range */ 1286 if (index < rar_entries) { 1287 /* 1288 * HW expects these in little endian so we reverse the byte 1289 * order from network order (big endian) to little endian 1290 */ 1291 rar_low = ((u32)addr[0] | 1292 ((u32)addr[1] << 8) | 1293 ((u32)addr[2] << 16) | 1294 ((u32)addr[3] << 24)); 1295 /* 1296 * Some parts put the VMDq setting in the extra RAH bits, 1297 * so save everything except the lower 16 bits that hold part 1298 * of the address and the address valid bit. 1299 */ 1300 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1301 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1302 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1303 1304 if (enable_addr != 0) 1305 rar_high |= IXGBE_RAH_AV; 1306 1307 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1308 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1309 } else { 1310 DEBUGOUT1("RAR index %d is out of range.\n", index); 1311 } 1312 1313 return (IXGBE_SUCCESS); 1314 } 1315 1316 /* 1317 * ixgbe_clear_rar_generic - Remove Rx address register 1318 * @hw: pointer to hardware structure 1319 * @index: Receive address register to write 1320 * 1321 * Clears an ethernet address from a receive address register. 1322 */ 1323 s32 1324 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1325 { 1326 u32 rar_high; 1327 u32 rar_entries = hw->mac.num_rar_entries; 1328 1329 /* Make sure we are using a valid rar index range */ 1330 if (index < rar_entries) { 1331 /* 1332 * Some parts put the VMDq setting in the extra RAH bits, 1333 * so save everything except the lower 16 bits that hold part 1334 * of the address and the address valid bit. 1335 */ 1336 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1337 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1338 1339 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1340 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1341 } else { 1342 DEBUGOUT1("RAR index %d is out of range.\n", index); 1343 } 1344 1345 /* clear VMDq pool/queue selection for this RAR */ 1346 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1347 1348 return (IXGBE_SUCCESS); 1349 } 1350 1351 /* 1352 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1353 * @hw: pointer to hardware structure 1354 * 1355 * Places the MAC address in receive address register 0 and clears the rest 1356 * of the receive address registers. Clears the multicast table. Assumes 1357 * the receiver is in reset when the routine is called. 1358 */ 1359 s32 1360 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1361 { 1362 u32 i; 1363 u32 rar_entries = hw->mac.num_rar_entries; 1364 1365 /* 1366 * If the current mac address is valid, assume it is a software override 1367 * to the permanent address. 1368 * Otherwise, use the permanent address from the eeprom. 1369 */ 1370 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1371 IXGBE_ERR_INVALID_MAC_ADDR) { 1372 /* Get the MAC address from the RAR0 for later reference */ 1373 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1374 1375 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1376 hw->mac.addr[0], hw->mac.addr[1], 1377 hw->mac.addr[2]); 1378 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1379 hw->mac.addr[4], hw->mac.addr[5]); 1380 } else { 1381 /* Setup the receive address. */ 1382 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1383 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1384 hw->mac.addr[0], hw->mac.addr[1], 1385 hw->mac.addr[2]); 1386 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1387 hw->mac.addr[4], hw->mac.addr[5]); 1388 1389 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1390 } 1391 hw->addr_ctrl.overflow_promisc = 0; 1392 1393 hw->addr_ctrl.rar_used_count = 1; 1394 1395 /* Zero out the other receive addresses. */ 1396 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1397 for (i = 1; i < rar_entries; i++) { 1398 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1399 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1400 } 1401 1402 /* Clear the MTA */ 1403 hw->addr_ctrl.mta_in_use = 0; 1404 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1405 1406 DEBUGOUT(" Clearing MTA\n"); 1407 for (i = 0; i < hw->mac.mcft_size; i++) 1408 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1409 1410 (void) ixgbe_init_uta_tables(hw); 1411 1412 return (IXGBE_SUCCESS); 1413 } 1414 1415 1416 /* 1417 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1418 * @hw: pointer to hardware structure 1419 * @addr: new address 1420 * 1421 * Adds it to unused receive address register or goes into promiscuous mode. 1422 */ 1423 void 1424 ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1425 { 1426 u32 rar_entries = hw->mac.num_rar_entries; 1427 u32 rar; 1428 1429 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1430 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1431 1432 /* 1433 * Place this address in the RAR if there is room, 1434 * else put the controller into promiscuous mode 1435 */ 1436 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1437 rar = hw->addr_ctrl.rar_used_count; 1438 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1439 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1440 hw->addr_ctrl.rar_used_count++; 1441 } else { 1442 hw->addr_ctrl.overflow_promisc++; 1443 } 1444 1445 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1446 } 1447 1448 /* 1449 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1450 * @hw: pointer to hardware structure 1451 * @addr_list: the list of new addresses 1452 * @addr_count: number of addresses 1453 * @next: iterator function to walk the address list 1454 * 1455 * The given list replaces any existing list. Clears the secondary addrs from 1456 * receive address registers. Uses unused receive address registers for the 1457 * first secondary addresses, and falls back to promiscuous mode as needed. 1458 * 1459 * Drivers using secondary unicast addresses must set user_set_promisc when 1460 * manually putting the device into promiscuous mode. 1461 */ 1462 s32 1463 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1464 u32 addr_count, ixgbe_mc_addr_itr next) 1465 { 1466 u8 *addr; 1467 u32 i; 1468 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1469 u32 uc_addr_in_use; 1470 u32 fctrl; 1471 u32 vmdq; 1472 1473 /* 1474 * Clear accounting of old secondary address list, 1475 * don't count RAR[0] 1476 */ 1477 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1478 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1479 hw->addr_ctrl.overflow_promisc = 0; 1480 1481 /* Zero out the other receive addresses */ 1482 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1483 for (i = 1; i <= uc_addr_in_use; i++) { 1484 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1485 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1486 } 1487 1488 /* Add the new addresses */ 1489 for (i = 0; i < addr_count; i++) { 1490 DEBUGOUT(" Adding the secondary addresses:\n"); 1491 addr = next(hw, &addr_list, &vmdq); 1492 ixgbe_add_uc_addr(hw, addr, vmdq); 1493 } 1494 1495 if (hw->addr_ctrl.overflow_promisc) { 1496 /* enable promisc if not already in overflow or set by user */ 1497 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1498 DEBUGOUT(" Entering address overflow promisc mode\n"); 1499 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1500 fctrl |= IXGBE_FCTRL_UPE; 1501 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1502 } 1503 } else { 1504 /* only disable if set by overflow, not by user */ 1505 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1506 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1507 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1508 fctrl &= ~IXGBE_FCTRL_UPE; 1509 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1510 } 1511 } 1512 1513 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1514 return (IXGBE_SUCCESS); 1515 } 1516 1517 /* 1518 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1519 * @hw: pointer to hardware structure 1520 * @mc_addr: the multicast address 1521 * 1522 * Extracts the 12 bits, from a multicast address, to determine which 1523 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1524 * incoming rx multicast addresses, to determine the bit-vector to check in 1525 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1526 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1527 * to mc_filter_type. 1528 */ 1529 static s32 1530 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1531 { 1532 u32 vector = 0; 1533 1534 switch (hw->mac.mc_filter_type) { 1535 case 0: /* use bits [47:36] of the address */ 1536 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1537 break; 1538 case 1: /* use bits [46:35] of the address */ 1539 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1540 break; 1541 case 2: /* use bits [45:34] of the address */ 1542 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1543 break; 1544 case 3: /* use bits [43:32] of the address */ 1545 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1546 break; 1547 default: /* Invalid mc_filter_type */ 1548 DEBUGOUT("MC filter type param set incorrectly\n"); 1549 ASSERT(0); 1550 break; 1551 } 1552 1553 /* vector can only be 12-bits or boundary will be exceeded */ 1554 vector &= 0xFFF; 1555 return (vector); 1556 } 1557 1558 /* 1559 * ixgbe_set_mta - Set bit-vector in multicast table 1560 * @hw: pointer to hardware structure 1561 * @hash_value: Multicast address hash value 1562 * 1563 * Sets the bit-vector in the multicast table. 1564 */ 1565 void 1566 ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1567 { 1568 u32 vector; 1569 u32 vector_bit; 1570 u32 vector_reg; 1571 u32 mta_reg; 1572 1573 hw->addr_ctrl.mta_in_use++; 1574 1575 vector = ixgbe_mta_vector(hw, mc_addr); 1576 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1577 1578 /* 1579 * The MTA is a register array of 128 32-bit registers. It is treated 1580 * like an array of 4096 bits. We want to set bit 1581 * BitArray[vector_value]. So we figure out what register the bit is 1582 * in, read it, OR in the new bit, then write back the new value. The 1583 * register is determined by the upper 7 bits of the vector value and 1584 * the bit within that register are determined by the lower 5 bits of 1585 * the value. 1586 */ 1587 vector_reg = (vector >> 5) & 0x7F; 1588 vector_bit = vector & 0x1F; 1589 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1590 mta_reg |= (1 << vector_bit); 1591 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1592 } 1593 1594 /* 1595 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1596 * @hw: pointer to hardware structure 1597 * @mc_addr_list: the list of new multicast addresses 1598 * @mc_addr_count: number of addresses 1599 * @next: iterator function to walk the multicast address list 1600 * 1601 * The given list replaces any existing list. Clears the MC addrs from receive 1602 * address registers and the multicast table. Uses unused receive address 1603 * registers for the first multicast addresses, and hashes the rest into the 1604 * multicast table. 1605 */ 1606 s32 1607 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1608 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1609 { 1610 u32 i; 1611 u32 vmdq; 1612 1613 /* 1614 * Set the new number of MC addresses that we are being requested to 1615 * use. 1616 */ 1617 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1618 hw->addr_ctrl.mta_in_use = 0; 1619 1620 /* Clear the MTA */ 1621 DEBUGOUT(" Clearing MTA\n"); 1622 for (i = 0; i < hw->mac.mcft_size; i++) 1623 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1624 1625 /* Add the new addresses */ 1626 for (i = 0; i < mc_addr_count; i++) { 1627 DEBUGOUT(" Adding the multicast addresses:\n"); 1628 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1629 } 1630 1631 /* Enable mta */ 1632 if (hw->addr_ctrl.mta_in_use > 0) 1633 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1634 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1635 1636 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1637 return (IXGBE_SUCCESS); 1638 } 1639 1640 /* 1641 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1642 * @hw: pointer to hardware structure 1643 * 1644 * Enables multicast address in RAR and the use of the multicast hash table. 1645 */ 1646 s32 1647 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1648 { 1649 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1650 1651 if (a->mta_in_use > 0) 1652 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1653 hw->mac.mc_filter_type); 1654 1655 return (IXGBE_SUCCESS); 1656 } 1657 1658 /* 1659 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1660 * @hw: pointer to hardware structure 1661 * 1662 * Disables multicast address in RAR and the use of the multicast hash table. 1663 */ 1664 s32 1665 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1666 { 1667 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1668 1669 if (a->mta_in_use > 0) 1670 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1671 1672 return (IXGBE_SUCCESS); 1673 } 1674 1675 /* 1676 * ixgbe_fc_enable_generic - Enable flow control 1677 * @hw: pointer to hardware structure 1678 * @packetbuf_num: packet buffer number (0-7) 1679 * 1680 * Enable flow control according to the current settings. 1681 */ 1682 s32 1683 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1684 { 1685 s32 ret_val = IXGBE_SUCCESS; 1686 u32 mflcn_reg, fccfg_reg; 1687 u32 reg; 1688 1689 DEBUGFUNC("ixgbe_fc_enable_generic"); 1690 1691 /* Negotiate the fc mode to use */ 1692 ret_val = ixgbe_fc_autoneg(hw); 1693 if (ret_val) 1694 goto out; 1695 1696 /* Disable any previous flow control settings */ 1697 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1698 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1699 1700 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1701 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1702 1703 /* 1704 * The possible values of fc.current_mode are: 1705 * 0: Flow control is completely disabled 1706 * 1: Rx flow control is enabled (we can receive pause frames, 1707 * but not send pause frames). 1708 * 2: Tx flow control is enabled (we can send pause frames but 1709 * we do not support receiving pause frames). 1710 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1711 * other: Invalid. 1712 */ 1713 switch (hw->fc.current_mode) { 1714 case ixgbe_fc_none: 1715 /* 1716 * Flow control is disabled by software override or autoneg. 1717 * The code below will actually disable it in the HW. 1718 */ 1719 break; 1720 case ixgbe_fc_rx_pause: 1721 /* 1722 * Rx Flow control is enabled and Tx Flow control is 1723 * disabled by software override. Since there really 1724 * isn't a way to advertise that we are capable of RX 1725 * Pause ONLY, we will advertise that we support both 1726 * symmetric and asymmetric Rx PAUSE. Later, we will 1727 * disable the adapter's ability to send PAUSE frames. 1728 */ 1729 mflcn_reg |= IXGBE_MFLCN_RFCE; 1730 break; 1731 case ixgbe_fc_tx_pause: 1732 /* 1733 * Tx Flow control is enabled, and Rx Flow control is 1734 * disabled by software override. 1735 */ 1736 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1737 break; 1738 case ixgbe_fc_full: 1739 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1740 mflcn_reg |= IXGBE_MFLCN_RFCE; 1741 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1742 break; 1743 default: 1744 DEBUGOUT("Flow control param set incorrectly\n"); 1745 ret_val = -IXGBE_ERR_CONFIG; 1746 goto out; 1747 } 1748 1749 /* Set 802.3x based flow control settings. */ 1750 mflcn_reg |= IXGBE_MFLCN_DPF; 1751 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1752 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1753 1754 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 1755 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1756 if (hw->fc.send_xon) { 1757 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), 1758 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 1759 } else { 1760 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), 1761 hw->fc.low_water); 1762 } 1763 1764 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1765 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1766 } 1767 1768 /* Configure pause time (2 TCs per register) */ 1769 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num)); 1770 if ((packetbuf_num & 1) == 0) 1771 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1772 else 1773 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1774 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1775 1776 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1777 1778 out: 1779 return (ret_val); 1780 } 1781 1782 /* 1783 * ixgbe_fc_autoneg - Configure flow control 1784 * @hw: pointer to hardware structure 1785 * 1786 * Compares our advertised flow control capabilities to those advertised by 1787 * our link partner, and determines the proper flow control mode to use. 1788 */ 1789 s32 1790 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1791 { 1792 s32 ret_val = IXGBE_SUCCESS; 1793 ixgbe_link_speed speed; 1794 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1795 bool link_up; 1796 1797 DEBUGFUNC("ixgbe_fc_autoneg"); 1798 1799 /* 1800 * AN should have completed when the cable was plugged in. 1801 * Look for reasons to bail out. Bail out if: 1802 * - FC autoneg is disabled, or if 1803 * - we don't have multispeed fiber, or if 1804 * - we're not running at 1G, or if 1805 * - link is not up, or if 1806 * - link is up but AN did not complete, or if 1807 * - link is up and AN completed but timed out 1808 * 1809 * Since we're being called from an LSC, link is already know to be up. 1810 * So use link_up_wait_to_complete=false. 1811 */ 1812 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1813 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1814 1815 if (hw->fc.disable_fc_autoneg || 1816 !hw->phy.multispeed_fiber || 1817 (speed != IXGBE_LINK_SPEED_1GB_FULL) || 1818 !link_up || 1819 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1820 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1821 hw->fc.fc_was_autonegged = false; 1822 hw->fc.current_mode = hw->fc.requested_mode; 1823 DEBUGOUT("Autoneg FC was skipped.\n"); 1824 goto out; 1825 } 1826 1827 /* 1828 * Read the AN advertisement and LP ability registers and resolve 1829 * local flow control settings accordingly 1830 */ 1831 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1832 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1833 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1834 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1835 /* 1836 * Now we need to check if the user selected Rx ONLY 1837 * of pause frames. In this case, we had to advertise 1838 * FULL flow control because we could not advertise RX 1839 * ONLY. Hence, we must now check to see if we need to 1840 * turn OFF the TRANSMISSION of PAUSE frames. 1841 */ 1842 if (hw->fc.requested_mode == ixgbe_fc_full) { 1843 hw->fc.current_mode = ixgbe_fc_full; 1844 DEBUGOUT("Flow Control = FULL.\n"); 1845 } else { 1846 hw->fc.current_mode = ixgbe_fc_rx_pause; 1847 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1848 } 1849 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1850 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1851 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1852 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1853 hw->fc.current_mode = ixgbe_fc_tx_pause; 1854 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1855 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1856 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1857 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1858 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1859 hw->fc.current_mode = ixgbe_fc_rx_pause; 1860 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1861 } else { 1862 hw->fc.current_mode = ixgbe_fc_none; 1863 DEBUGOUT("Flow Control = NONE.\n"); 1864 } 1865 1866 /* Record that current_mode is the result of a successful autoneg */ 1867 hw->fc.fc_was_autonegged = true; 1868 1869 out: 1870 return (ret_val); 1871 } 1872 1873 /* 1874 * ixgbe_setup_fc - Set up flow control 1875 * @hw: pointer to hardware structure 1876 * 1877 * Called at init time to set up flow control. 1878 */ 1879 s32 1880 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 1881 { 1882 s32 ret_val = IXGBE_SUCCESS; 1883 u32 reg; 1884 1885 /* Validate the packetbuf configuration */ 1886 if (packetbuf_num < 0 || packetbuf_num > 7) { 1887 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 1888 " 0-7\n", packetbuf_num); 1889 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1890 goto out; 1891 } 1892 1893 /* 1894 * Validate the water mark configuration. Zero water marks are invalid 1895 * because it causes the controller to just blast out fc packets. 1896 */ 1897 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 1898 DEBUGOUT("Invalid water mark configuration\n"); 1899 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1900 goto out; 1901 } 1902 1903 /* 1904 * Validate the requested mode. Strict IEEE mode does not allow 1905 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 1906 */ 1907 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 1908 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 1909 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1910 goto out; 1911 } 1912 1913 /* 1914 * 10gig parts do not have a word in the EEPROM to determine the 1915 * default flow control setting, so we explicitly set it to full. 1916 */ 1917 if (hw->fc.requested_mode == ixgbe_fc_default) 1918 hw->fc.requested_mode = ixgbe_fc_full; 1919 1920 /* 1921 * Set up the 1G flow control advertisement registers so the HW will be 1922 * able to do fc autoneg once the cable is plugged in. If we end up 1923 * using 10g instead, this is harmless. 1924 */ 1925 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1926 1927 /* 1928 * The possible values of fc.requested_mode are: 1929 * 0: Flow control is completely disabled 1930 * 1: Rx flow control is enabled (we can receive pause frames, 1931 * but not send pause frames). 1932 * 2: Tx flow control is enabled (we can send pause frames but 1933 * we do not support receiving pause frames). 1934 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1935 * other: Invalid. 1936 */ 1937 switch (hw->fc.requested_mode) { 1938 case ixgbe_fc_none: 1939 /* Flow control completely disabled by software override. */ 1940 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1941 break; 1942 case ixgbe_fc_rx_pause: 1943 /* 1944 * Rx Flow control is enabled and Tx Flow control is 1945 * disabled by software override. Since there really 1946 * isn't a way to advertise that we are capable of RX 1947 * Pause ONLY, we will advertise that we support both 1948 * symmetric and asymmetric Rx PAUSE. Later, we will 1949 * disable the adapter's ability to send PAUSE frames. 1950 */ 1951 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1952 break; 1953 case ixgbe_fc_tx_pause: 1954 /* 1955 * Tx Flow control is enabled, and Rx Flow control is 1956 * disabled by software override. 1957 */ 1958 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 1959 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 1960 break; 1961 case ixgbe_fc_full: 1962 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1963 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1964 break; 1965 default: 1966 DEBUGOUT("Flow control param set incorrectly\n"); 1967 ret_val = -IXGBE_ERR_CONFIG; 1968 goto out; 1969 } 1970 1971 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 1972 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 1973 1974 /* Enable and restart autoneg to inform the link partner */ 1975 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 1976 1977 /* Disable AN timeout */ 1978 if (hw->fc.strict_ieee) 1979 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 1980 1981 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 1982 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 1983 1984 out: 1985 return (ret_val); 1986 } 1987 1988 /* 1989 * ixgbe_disable_pcie_master - Disable PCI-express master access 1990 * @hw: pointer to hardware structure 1991 * 1992 * Disables PCI-Express master access and verifies there are no pending 1993 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1994 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1995 * is returned signifying master requests disabled. 1996 */ 1997 s32 1998 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1999 { 2000 u32 i; 2001 u32 reg_val; 2002 u32 number_of_queues; 2003 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2004 2005 /* Disable the receive unit by stopping each queue */ 2006 number_of_queues = hw->mac.max_rx_queues; 2007 for (i = 0; i < number_of_queues; i++) { 2008 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2009 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2010 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2011 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2012 } 2013 } 2014 2015 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2016 reg_val |= IXGBE_CTRL_GIO_DIS; 2017 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2018 2019 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2020 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 2021 status = IXGBE_SUCCESS; 2022 break; 2023 } 2024 usec_delay(100); 2025 } 2026 2027 return (status); 2028 } 2029 2030 /* 2031 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2032 * @hw: pointer to hardware structure 2033 * @mask: Mask to specify which semaphore to acquire 2034 * 2035 * Acquires the SWFW semaphore thought the GSSR register for the specified 2036 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2037 */ 2038 s32 2039 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2040 { 2041 u32 gssr; 2042 u32 swmask = mask; 2043 u32 fwmask = mask << 5; 2044 s32 timeout = 200; 2045 2046 while (timeout) { 2047 /* 2048 * SW EEPROM semaphore bit is used for access to all 2049 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2050 */ 2051 if (ixgbe_get_eeprom_semaphore(hw)) 2052 return (-IXGBE_ERR_SWFW_SYNC); 2053 2054 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2055 if (!(gssr & (fwmask | swmask))) 2056 break; 2057 2058 /* 2059 * Firmware currently using resource (fwmask) or other software 2060 * thread currently using resource (swmask) 2061 */ 2062 ixgbe_release_eeprom_semaphore(hw); 2063 msec_delay(5); 2064 timeout--; 2065 } 2066 2067 if (!timeout) { 2068 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2069 return (-IXGBE_ERR_SWFW_SYNC); 2070 } 2071 2072 gssr |= swmask; 2073 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2074 2075 ixgbe_release_eeprom_semaphore(hw); 2076 return (IXGBE_SUCCESS); 2077 } 2078 2079 /* 2080 * ixgbe_release_swfw_sync - Release SWFW semaphore 2081 * @hw: pointer to hardware structure 2082 * @mask: Mask to specify which semaphore to release 2083 * 2084 * Releases the SWFW semaphore thought the GSSR register for the specified 2085 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2086 */ 2087 void 2088 ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2089 { 2090 u32 gssr; 2091 u32 swmask = mask; 2092 2093 (void) ixgbe_get_eeprom_semaphore(hw); 2094 2095 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2096 gssr &= ~swmask; 2097 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2098 2099 ixgbe_release_eeprom_semaphore(hw); 2100 } 2101 2102 /* 2103 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2104 * @hw: pointer to hardware structure 2105 * @regval: register value to write to RXCTRL 2106 * 2107 * Enables the Rx DMA unit 2108 */ 2109 s32 2110 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2111 { 2112 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2113 2114 return (IXGBE_SUCCESS); 2115 } 2116 2117 /* 2118 * ixgbe_blink_led_start_generic - Blink LED based on index. 2119 * @hw: pointer to hardware structure 2120 * @index: led number to blink 2121 */ 2122 s32 2123 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2124 { 2125 ixgbe_link_speed speed = 0; 2126 bool link_up = 0; 2127 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2128 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2129 2130 /* 2131 * Link must be up to auto-blink the LEDs; 2132 * Force it if link is down. 2133 */ 2134 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2135 2136 if (!link_up) { 2137 autoc_reg |= IXGBE_AUTOC_FLU; 2138 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2139 msec_delay(10); 2140 } 2141 2142 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2143 led_reg |= IXGBE_LED_BLINK(index); 2144 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2145 IXGBE_WRITE_FLUSH(hw); 2146 2147 return (IXGBE_SUCCESS); 2148 } 2149 2150 /* 2151 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2152 * @hw: pointer to hardware structure 2153 * @index: led number to stop blinking 2154 */ 2155 s32 2156 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2157 { 2158 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2159 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2160 2161 autoc_reg &= ~IXGBE_AUTOC_FLU; 2162 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2163 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2164 2165 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2166 led_reg &= ~IXGBE_LED_BLINK(index); 2167 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2168 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2169 IXGBE_WRITE_FLUSH(hw); 2170 2171 return (IXGBE_SUCCESS); 2172 } 2173