1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 /* IntelVersion: 1.227 sol_ixgbe_shared_339b */ 29 30 #include "ixgbe_common.h" 31 #include "ixgbe_api.h" 32 33 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 34 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 35 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 36 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 37 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 38 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 39 u16 count); 40 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 41 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 42 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 43 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 44 45 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 46 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 47 u16 *san_mac_offset); 48 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 49 50 /* 51 * ixgbe_init_ops_generic - Inits function ptrs 52 * @hw: pointer to the hardware structure 53 * 54 * Initialize the function pointers. 55 */ 56 s32 57 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 58 { 59 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 60 struct ixgbe_mac_info *mac = &hw->mac; 61 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 62 63 DEBUGFUNC("ixgbe_init_ops_generic"); 64 65 /* EEPROM */ 66 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 67 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 68 if (eec & (1 << 8)) 69 eeprom->ops.read = &ixgbe_read_eerd_generic; 70 else 71 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 72 eeprom->ops.write = &ixgbe_write_eeprom_generic; 73 eeprom->ops.validate_checksum = 74 &ixgbe_validate_eeprom_checksum_generic; 75 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 76 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 77 78 /* MAC */ 79 mac->ops.init_hw = &ixgbe_init_hw_generic; 80 mac->ops.reset_hw = NULL; 81 mac->ops.start_hw = &ixgbe_start_hw_generic; 82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 83 mac->ops.get_media_type = NULL; 84 mac->ops.get_supported_physical_layer = NULL; 85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 90 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 91 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 92 93 /* LEDs */ 94 mac->ops.led_on = &ixgbe_led_on_generic; 95 mac->ops.led_off = &ixgbe_led_off_generic; 96 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 97 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 98 99 /* RAR, Multicast, VLAN */ 100 mac->ops.set_rar = &ixgbe_set_rar_generic; 101 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 102 mac->ops.insert_mac_addr = NULL; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.clear_vmdq = NULL; 105 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 108 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 109 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 110 mac->ops.clear_vfta = NULL; 111 mac->ops.set_vfta = NULL; 112 mac->ops.init_uta_tables = NULL; 113 114 /* Flow Control */ 115 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 116 117 /* Link */ 118 mac->ops.get_link_capabilities = NULL; 119 mac->ops.setup_link = NULL; 120 mac->ops.check_link = NULL; 121 122 return (IXGBE_SUCCESS); 123 } 124 125 /* 126 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 127 * @hw: pointer to hardware structure 128 * 129 * Starts the hardware by filling the bus info structure and media type, clears 130 * all on chip counters, initializes receive address registers, multicast 131 * table, VLAN filter table, calls routine to set up link and flow control 132 * settings, and leaves transmit and receive units disabled and uninitialized 133 */ 134 s32 135 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 136 { 137 u32 ctrl_ext; 138 139 DEBUGFUNC("ixgbe_start_hw_generic"); 140 141 /* Set the media type */ 142 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 143 144 /* PHY ops initialization must be done in reset_hw() */ 145 146 /* Clear the VLAN filter table */ 147 hw->mac.ops.clear_vfta(hw); 148 149 /* Clear statistics registers */ 150 hw->mac.ops.clear_hw_cntrs(hw); 151 152 /* Set No Snoop Disable */ 153 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 154 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 155 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 156 IXGBE_WRITE_FLUSH(hw); 157 158 /* Setup flow control */ 159 (void) ixgbe_setup_fc(hw, 0); 160 161 /* Clear adapter stopped flag */ 162 hw->adapter_stopped = false; 163 164 return (IXGBE_SUCCESS); 165 } 166 167 /* 168 * ixgbe_init_hw_generic - Generic hardware initialization 169 * @hw: pointer to hardware structure 170 * 171 * Initialize the hardware by resetting the hardware, filling the bus info 172 * structure and media type, clears all on chip counters, initializes receive 173 * address registers, multicast table, VLAN filter table, calls routine to set 174 * up link and flow control settings, and leaves transmit and receive units 175 * disabled and uninitialized 176 */ 177 s32 178 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 179 { 180 s32 status = IXGBE_SUCCESS; 181 182 DEBUGFUNC("ixgbe_init_hw_generic"); 183 184 /* Reset the hardware */ 185 status = hw->mac.ops.reset_hw(hw); 186 187 if (status == IXGBE_SUCCESS) { 188 /* Start the HW */ 189 status = hw->mac.ops.start_hw(hw); 190 } 191 192 return (status); 193 } 194 195 /* 196 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 197 * @hw: pointer to hardware structure 198 * 199 * Clears all hardware statistics counters by reading them from the hardware 200 * Statistics counters are clear on read. 201 */ 202 s32 203 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 204 { 205 u16 i = 0; 206 207 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 208 209 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 210 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 211 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 212 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 213 for (i = 0; i < 8; i++) 214 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 215 216 (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 217 (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 218 (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 219 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 220 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 221 if (hw->mac.type >= ixgbe_mac_82599EB) { 222 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 223 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 224 } else { 225 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 226 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 227 } 228 229 for (i = 0; i < 8; i++) { 230 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 231 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 232 if (hw->mac.type >= ixgbe_mac_82599EB) { 233 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 234 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 235 } else { 236 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 237 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 238 } 239 } 240 if (hw->mac.type >= ixgbe_mac_82599EB) 241 for (i = 0; i < 8; i++) 242 (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 243 244 (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 245 (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 246 (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 247 (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 248 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 249 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 250 (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 251 (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 252 (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 253 (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 254 (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 255 (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 256 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 257 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 258 for (i = 0; i < 8; i++) 259 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 260 (void) IXGBE_READ_REG(hw, IXGBE_RUC); 261 (void) IXGBE_READ_REG(hw, IXGBE_RFC); 262 (void) IXGBE_READ_REG(hw, IXGBE_ROC); 263 (void) IXGBE_READ_REG(hw, IXGBE_RJC); 264 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 265 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 266 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 267 (void) IXGBE_READ_REG(hw, IXGBE_TORL); 268 (void) IXGBE_READ_REG(hw, IXGBE_TORH); 269 (void) IXGBE_READ_REG(hw, IXGBE_TPR); 270 (void) IXGBE_READ_REG(hw, IXGBE_TPT); 271 (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 272 (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 273 (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 274 (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 275 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 276 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 277 (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 278 (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 279 for (i = 0; i < 16; i++) { 280 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 281 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 282 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 283 if (hw->mac.type >= ixgbe_mac_82599EB) { 284 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 285 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 286 } else { 287 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 288 } 289 } 290 291 return (IXGBE_SUCCESS); 292 } 293 294 /* 295 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 296 * @hw: pointer to hardware structure 297 * @pba_num: stores the part number from the EEPROM 298 * 299 * Reads the part number from the EEPROM. 300 */ 301 s32 302 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 303 { 304 s32 ret_val; 305 u16 data; 306 307 DEBUGFUNC("ixgbe_read_pba_num_generic"); 308 309 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 310 if (ret_val) { 311 DEBUGOUT("NVM Read Error\n"); 312 return (ret_val); 313 } 314 *pba_num = (u32)(data << 16); 315 316 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 317 if (ret_val) { 318 DEBUGOUT("NVM Read Error\n"); 319 return (ret_val); 320 } 321 *pba_num |= data; 322 323 return (IXGBE_SUCCESS); 324 } 325 326 /* 327 * ixgbe_get_mac_addr_generic - Generic get MAC address 328 * @hw: pointer to hardware structure 329 * @mac_addr: Adapter MAC address 330 * 331 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 332 * A reset of the adapter must be performed prior to calling this function 333 * in order for the MAC address to have been loaded from the EEPROM into RAR0 334 */ 335 s32 336 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 337 { 338 u32 rar_high; 339 u32 rar_low; 340 u16 i; 341 342 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 343 344 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 345 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 346 347 for (i = 0; i < 4; i++) 348 mac_addr[i] = (u8)(rar_low >> (i*8)); 349 350 for (i = 0; i < 2; i++) 351 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 352 353 return (IXGBE_SUCCESS); 354 } 355 356 /* 357 * ixgbe_get_bus_info_generic - Generic set PCI bus info 358 * @hw: pointer to hardware structure 359 * 360 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 361 */ 362 s32 363 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 364 { 365 struct ixgbe_mac_info *mac = &hw->mac; 366 u16 link_status; 367 368 DEBUGFUNC("ixgbe_get_bus_info_generic"); 369 370 hw->bus.type = ixgbe_bus_type_pci_express; 371 372 /* Get the negotiated link width and speed from PCI config space */ 373 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 374 375 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 376 case IXGBE_PCI_LINK_WIDTH_1: 377 hw->bus.width = ixgbe_bus_width_pcie_x1; 378 break; 379 case IXGBE_PCI_LINK_WIDTH_2: 380 hw->bus.width = ixgbe_bus_width_pcie_x2; 381 break; 382 case IXGBE_PCI_LINK_WIDTH_4: 383 hw->bus.width = ixgbe_bus_width_pcie_x4; 384 break; 385 case IXGBE_PCI_LINK_WIDTH_8: 386 hw->bus.width = ixgbe_bus_width_pcie_x8; 387 break; 388 default: 389 hw->bus.width = ixgbe_bus_width_unknown; 390 break; 391 } 392 393 switch (link_status & IXGBE_PCI_LINK_SPEED) { 394 case IXGBE_PCI_LINK_SPEED_2500: 395 hw->bus.speed = ixgbe_bus_speed_2500; 396 break; 397 case IXGBE_PCI_LINK_SPEED_5000: 398 hw->bus.speed = ixgbe_bus_speed_5000; 399 break; 400 default: 401 hw->bus.speed = ixgbe_bus_speed_unknown; 402 break; 403 } 404 405 mac->ops.set_lan_id(hw); 406 407 return (IXGBE_SUCCESS); 408 } 409 410 411 /* 412 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 413 * @hw: pointer to the HW structure 414 * 415 * Determines the LAN function id by reading memory-mapped registers 416 * and swaps the port value if requested. 417 */ 418 void 419 ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 420 { 421 struct ixgbe_bus_info *bus = &hw->bus; 422 u32 reg; 423 424 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 425 426 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 427 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 428 bus->lan_id = bus->func; 429 430 /* check for a port swap */ 431 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 432 if (reg & IXGBE_FACTPS_LFS) 433 bus->func ^= 0x1; 434 } 435 436 /* 437 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 438 * @hw: pointer to hardware structure 439 * 440 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 441 * disables transmit and receive units. The adapter_stopped flag is used by 442 * the shared code and drivers to determine if the adapter is in a stopped 443 * state and should not touch the hardware. 444 */ 445 s32 446 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 447 { 448 u32 number_of_queues; 449 u32 reg_val; 450 u16 i; 451 452 DEBUGFUNC("ixgbe_stop_adapter_generic"); 453 454 /* 455 * Set the adapter_stopped flag so other driver functions stop touching 456 * the hardware 457 */ 458 hw->adapter_stopped = true; 459 460 /* Disable the receive unit */ 461 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 462 reg_val &= ~(IXGBE_RXCTRL_RXEN); 463 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 464 IXGBE_WRITE_FLUSH(hw); 465 msec_delay(2); 466 467 /* Clear interrupt mask to stop from interrupts being generated */ 468 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 469 470 /* Clear any pending interrupts */ 471 (void) IXGBE_READ_REG(hw, IXGBE_EICR); 472 473 /* Disable the transmit unit. Each queue must be disabled. */ 474 number_of_queues = hw->mac.max_tx_queues; 475 for (i = 0; i < number_of_queues; i++) { 476 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 477 if (reg_val & IXGBE_TXDCTL_ENABLE) { 478 reg_val &= ~IXGBE_TXDCTL_ENABLE; 479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 480 } 481 } 482 483 /* 484 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 485 * access and verify no pending requests 486 */ 487 (void) ixgbe_disable_pcie_master(hw); 488 489 return (IXGBE_SUCCESS); 490 } 491 492 /* 493 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 494 * @hw: pointer to hardware structure 495 * @index: led number to turn on 496 */ 497 s32 498 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 499 { 500 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 501 502 DEBUGFUNC("ixgbe_led_on_generic"); 503 504 /* To turn on the LED, set mode to ON. */ 505 led_reg &= ~IXGBE_LED_MODE_MASK(index); 506 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 507 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 508 IXGBE_WRITE_FLUSH(hw); 509 510 return (IXGBE_SUCCESS); 511 } 512 513 /* 514 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 515 * @hw: pointer to hardware structure 516 * @index: led number to turn off 517 */ 518 s32 519 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 520 { 521 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 522 523 DEBUGFUNC("ixgbe_led_off_generic"); 524 525 /* To turn off the LED, set mode to OFF. */ 526 led_reg &= ~IXGBE_LED_MODE_MASK(index); 527 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 528 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 529 IXGBE_WRITE_FLUSH(hw); 530 531 return (IXGBE_SUCCESS); 532 } 533 534 /* 535 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 536 * @hw: pointer to hardware structure 537 * 538 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 539 * ixgbe_hw struct in order to set up EEPROM access. 540 */ 541 s32 542 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 543 { 544 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 545 u32 eec; 546 u16 eeprom_size; 547 548 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 549 550 if (eeprom->type == ixgbe_eeprom_uninitialized) { 551 eeprom->type = ixgbe_eeprom_none; 552 /* 553 * Set default semaphore delay to 10ms which is a well 554 * tested value 555 */ 556 eeprom->semaphore_delay = 10; 557 558 /* 559 * Check for EEPROM present first. 560 * If not present leave as none 561 */ 562 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 563 if (eec & IXGBE_EEC_PRES) { 564 eeprom->type = ixgbe_eeprom_spi; 565 566 /* 567 * SPI EEPROM is assumed here. This code would need to 568 * change if a future EEPROM is not SPI. 569 */ 570 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 571 IXGBE_EEC_SIZE_SHIFT); 572 eeprom->word_size = 1 << (eeprom_size + 573 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); 574 } 575 576 if (eec & IXGBE_EEC_ADDR_SIZE) 577 eeprom->address_bits = 16; 578 else 579 eeprom->address_bits = 8; 580 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 581 "%d\n", eeprom->type, eeprom->word_size, 582 eeprom->address_bits); 583 } 584 585 return (IXGBE_SUCCESS); 586 } 587 588 /* 589 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 590 * @hw: pointer to hardware structure 591 * @offset: offset within the EEPROM to be written to 592 * @data: 16 bit word to be written to the EEPROM 593 * 594 * If ixgbe_eeprom_update_checksum is not called after this function, the 595 * EEPROM will most likely contain an invalid checksum. 596 */ 597 s32 598 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 599 { 600 s32 status; 601 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 602 603 DEBUGFUNC("ixgbe_write_eeprom_generic"); 604 605 hw->eeprom.ops.init_params(hw); 606 607 if (offset >= hw->eeprom.word_size) { 608 status = IXGBE_ERR_EEPROM; 609 goto out; 610 } 611 612 /* Prepare the EEPROM for writing */ 613 status = ixgbe_acquire_eeprom(hw); 614 615 if (status == IXGBE_SUCCESS) { 616 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 617 ixgbe_release_eeprom(hw); 618 status = IXGBE_ERR_EEPROM; 619 } 620 } 621 622 if (status == IXGBE_SUCCESS) { 623 ixgbe_standby_eeprom(hw); 624 625 /* Send the WRITE ENABLE command (8 bit opcode ) */ 626 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 627 IXGBE_EEPROM_OPCODE_BITS); 628 629 ixgbe_standby_eeprom(hw); 630 631 /* 632 * Some SPI eeproms use the 8th address bit embedded in the 633 * opcode 634 */ 635 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 636 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 637 638 /* Send the Write command (8-bit opcode + addr) */ 639 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 640 IXGBE_EEPROM_OPCODE_BITS); 641 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 642 hw->eeprom.address_bits); 643 644 /* Send the data */ 645 data = (data >> 8) | (data << 8); 646 ixgbe_shift_out_eeprom_bits(hw, data, 16); 647 ixgbe_standby_eeprom(hw); 648 649 /* Done with writing - release the EEPROM */ 650 ixgbe_release_eeprom(hw); 651 } 652 653 out: 654 return (status); 655 } 656 657 /* 658 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 659 * @hw: pointer to hardware structure 660 * @offset: offset within the EEPROM to be read 661 * @data: read 16 bit value from EEPROM 662 * 663 * Reads 16 bit value from EEPROM through bit-bang method 664 */ 665 s32 666 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 667 u16 *data) 668 { 669 s32 status; 670 u16 word_in; 671 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 672 673 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 674 675 hw->eeprom.ops.init_params(hw); 676 677 if (offset >= hw->eeprom.word_size) { 678 status = IXGBE_ERR_EEPROM; 679 goto out; 680 } 681 682 /* Prepare the EEPROM for reading */ 683 status = ixgbe_acquire_eeprom(hw); 684 685 if (status == IXGBE_SUCCESS) { 686 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 687 ixgbe_release_eeprom(hw); 688 status = IXGBE_ERR_EEPROM; 689 } 690 } 691 692 if (status == IXGBE_SUCCESS) { 693 ixgbe_standby_eeprom(hw); 694 695 /* 696 * Some SPI eeproms use the 8th address bit embedded in the 697 * opcode 698 */ 699 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 700 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 701 702 /* Send the READ command (opcode + addr) */ 703 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 704 IXGBE_EEPROM_OPCODE_BITS); 705 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 706 hw->eeprom.address_bits); 707 708 /* Read the data. */ 709 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 710 *data = (word_in >> 8) | (word_in << 8); 711 712 /* End this read operation */ 713 ixgbe_release_eeprom(hw); 714 } 715 716 out: 717 return (status); 718 } 719 720 /* 721 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 722 * @hw: pointer to hardware structure 723 * @offset: offset of word in the EEPROM to read 724 * @data: word read from the EEPROM 725 * 726 * Reads a 16 bit word from the EEPROM using the EERD register. 727 */ 728 s32 729 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 730 { 731 u32 eerd; 732 s32 status; 733 734 DEBUGFUNC("ixgbe_read_eerd_generic"); 735 736 hw->eeprom.ops.init_params(hw); 737 738 if (offset >= hw->eeprom.word_size) { 739 status = IXGBE_ERR_EEPROM; 740 goto out; 741 } 742 743 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 744 IXGBE_EEPROM_RW_REG_START; 745 746 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 747 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 748 749 if (status == IXGBE_SUCCESS) 750 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 751 IXGBE_EEPROM_RW_REG_DATA); 752 else 753 DEBUGOUT("Eeprom read timed out\n"); 754 755 out: 756 return (status); 757 } 758 759 /* 760 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 761 * @hw: pointer to hardware structure 762 * @ee_reg: EEPROM flag for polling 763 * 764 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 765 * read or write is done respectively. 766 */ 767 s32 768 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 769 { 770 u32 i; 771 u32 reg; 772 s32 status = IXGBE_ERR_EEPROM; 773 774 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 775 776 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 777 if (ee_reg == IXGBE_NVM_POLL_READ) 778 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 779 else 780 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 781 782 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 783 status = IXGBE_SUCCESS; 784 break; 785 } 786 usec_delay(5); 787 } 788 return (status); 789 } 790 791 /* 792 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 793 * @hw: pointer to hardware structure 794 * 795 * Prepares EEPROM for access using bit-bang method. This function should 796 * be called before issuing a command to the EEPROM. 797 */ 798 static s32 799 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 800 { 801 s32 status = IXGBE_SUCCESS; 802 u32 eec; 803 u32 i; 804 805 DEBUGFUNC("ixgbe_acquire_eeprom"); 806 807 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 808 status = IXGBE_ERR_SWFW_SYNC; 809 810 if (status == IXGBE_SUCCESS) { 811 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 812 813 /* Request EEPROM Access */ 814 eec |= IXGBE_EEC_REQ; 815 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 816 817 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 818 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 819 if (eec & IXGBE_EEC_GNT) 820 break; 821 usec_delay(5); 822 } 823 824 /* Release if grant not acquired */ 825 if (!(eec & IXGBE_EEC_GNT)) { 826 eec &= ~IXGBE_EEC_REQ; 827 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 828 DEBUGOUT("Could not acquire EEPROM grant\n"); 829 830 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 831 status = IXGBE_ERR_EEPROM; 832 } 833 } 834 835 /* Setup EEPROM for Read/Write */ 836 if (status == IXGBE_SUCCESS) { 837 /* Clear CS and SK */ 838 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 839 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 840 IXGBE_WRITE_FLUSH(hw); 841 usec_delay(1); 842 } 843 return (status); 844 } 845 846 /* 847 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 848 * @hw: pointer to hardware structure 849 * 850 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 851 */ 852 static s32 853 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 854 { 855 s32 status = IXGBE_ERR_EEPROM; 856 u32 timeout = 2000; 857 u32 i; 858 u32 swsm; 859 860 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 861 862 /* Get SMBI software semaphore between device drivers first */ 863 for (i = 0; i < timeout; i++) { 864 /* 865 * If the SMBI bit is 0 when we read it, then the bit will be 866 * set and we have the semaphore 867 */ 868 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 869 if (!(swsm & IXGBE_SWSM_SMBI)) { 870 status = IXGBE_SUCCESS; 871 break; 872 } 873 usec_delay(50); 874 } 875 876 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 877 if (status == IXGBE_SUCCESS) { 878 for (i = 0; i < timeout; i++) { 879 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 880 881 /* Set the SW EEPROM semaphore bit to request access */ 882 swsm |= IXGBE_SWSM_SWESMBI; 883 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 884 885 /* 886 * If we set the bit successfully then we got the 887 * semaphore. 888 */ 889 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 890 if (swsm & IXGBE_SWSM_SWESMBI) 891 break; 892 893 usec_delay(50); 894 } 895 896 /* 897 * Release semaphores and return error if SW EEPROM semaphore 898 * was not granted because we don't have access to the EEPROM 899 */ 900 if (i >= timeout) { 901 DEBUGOUT("SWESMBI Software EEPROM semaphore " 902 "not granted.\n"); 903 ixgbe_release_eeprom_semaphore(hw); 904 status = IXGBE_ERR_EEPROM; 905 } 906 } else { 907 DEBUGOUT("Software semaphore SMBI between device drivers " 908 "not granted.\n"); 909 } 910 911 return (status); 912 } 913 914 /* 915 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 916 * @hw: pointer to hardware structure 917 * 918 * This function clears hardware semaphore bits. 919 */ 920 static void 921 ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 922 { 923 u32 swsm; 924 925 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 926 927 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 928 929 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 930 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 931 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 932 IXGBE_WRITE_FLUSH(hw); 933 } 934 935 /* 936 * ixgbe_ready_eeprom - Polls for EEPROM ready 937 * @hw: pointer to hardware structure 938 */ 939 static s32 940 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 941 { 942 s32 status = IXGBE_SUCCESS; 943 u16 i; 944 u8 spi_stat_reg; 945 946 DEBUGFUNC("ixgbe_ready_eeprom"); 947 948 /* 949 * Read "Status Register" repeatedly until the LSB is cleared. The 950 * EEPROM will signal that the command has been completed by clearing 951 * bit 0 of the internal status register. If it's not cleared within 952 * 5 milliseconds, then error out. 953 */ 954 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 955 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 956 IXGBE_EEPROM_OPCODE_BITS); 957 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 958 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 959 break; 960 961 usec_delay(5); 962 ixgbe_standby_eeprom(hw); 963 }; 964 965 /* 966 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 967 * devices (and only 0-5mSec on 5V devices) 968 */ 969 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 970 DEBUGOUT("SPI EEPROM Status error\n"); 971 status = IXGBE_ERR_EEPROM; 972 } 973 974 return (status); 975 } 976 977 /* 978 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 979 * @hw: pointer to hardware structure 980 */ 981 static void 982 ixgbe_standby_eeprom(struct ixgbe_hw *hw) 983 { 984 u32 eec; 985 986 DEBUGFUNC("ixgbe_standby_eeprom"); 987 988 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 989 990 /* Toggle CS to flush commands */ 991 eec |= IXGBE_EEC_CS; 992 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 993 IXGBE_WRITE_FLUSH(hw); 994 usec_delay(1); 995 eec &= ~IXGBE_EEC_CS; 996 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 997 IXGBE_WRITE_FLUSH(hw); 998 usec_delay(1); 999 } 1000 1001 /* 1002 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1003 * @hw: pointer to hardware structure 1004 * @data: data to send to the EEPROM 1005 * @count: number of bits to shift out 1006 */ 1007 static void 1008 ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1009 u16 count) 1010 { 1011 u32 eec; 1012 u32 mask; 1013 u32 i; 1014 1015 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1016 1017 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1018 1019 /* 1020 * Mask is used to shift "count" bits of "data" out to the EEPROM 1021 * one bit at a time. Determine the starting bit based on count 1022 */ 1023 mask = 0x01 << (count - 1); 1024 1025 for (i = 0; i < count; i++) { 1026 /* 1027 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1028 * "1", and then raising and then lowering the clock (the SK 1029 * bit controls the clock input to the EEPROM). A "0" is 1030 * shifted out to the EEPROM by setting "DI" to "0" and then 1031 * raising and then lowering the clock. 1032 */ 1033 if (data & mask) 1034 eec |= IXGBE_EEC_DI; 1035 else 1036 eec &= ~IXGBE_EEC_DI; 1037 1038 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1039 IXGBE_WRITE_FLUSH(hw); 1040 1041 usec_delay(1); 1042 1043 ixgbe_raise_eeprom_clk(hw, &eec); 1044 ixgbe_lower_eeprom_clk(hw, &eec); 1045 1046 /* 1047 * Shift mask to signify next bit of data to shift in to the 1048 * EEPROM 1049 */ 1050 mask = mask >> 1; 1051 }; 1052 1053 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1054 eec &= ~IXGBE_EEC_DI; 1055 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1056 IXGBE_WRITE_FLUSH(hw); 1057 } 1058 1059 /* 1060 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1061 * @hw: pointer to hardware structure 1062 */ 1063 static u16 1064 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1065 { 1066 u32 eec; 1067 u32 i; 1068 u16 data = 0; 1069 1070 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1071 1072 /* 1073 * In order to read a register from the EEPROM, we need to shift 1074 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1075 * the clock input to the EEPROM (setting the SK bit), and then reading 1076 * the value of the "DO" bit. During this "shifting in" process the 1077 * "DI" bit should always be clear. 1078 */ 1079 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1080 1081 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1082 1083 for (i = 0; i < count; i++) { 1084 data = data << 1; 1085 ixgbe_raise_eeprom_clk(hw, &eec); 1086 1087 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1088 1089 eec &= ~(IXGBE_EEC_DI); 1090 if (eec & IXGBE_EEC_DO) 1091 data |= 1; 1092 1093 ixgbe_lower_eeprom_clk(hw, &eec); 1094 } 1095 1096 return (data); 1097 } 1098 1099 /* 1100 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1101 * @hw: pointer to hardware structure 1102 * @eec: EEC register's current value 1103 */ 1104 static void 1105 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1106 { 1107 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1108 1109 /* 1110 * Raise the clock input to the EEPROM 1111 * (setting the SK bit), then delay 1112 */ 1113 *eec = *eec | IXGBE_EEC_SK; 1114 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1115 IXGBE_WRITE_FLUSH(hw); 1116 usec_delay(1); 1117 } 1118 1119 /* 1120 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1121 * @hw: pointer to hardware structure 1122 * @eecd: EECD's current value 1123 */ 1124 static void 1125 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1126 { 1127 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1128 1129 /* 1130 * Lower the clock input to the EEPROM (clearing the SK bit), then 1131 * delay 1132 */ 1133 *eec = *eec & ~IXGBE_EEC_SK; 1134 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1135 IXGBE_WRITE_FLUSH(hw); 1136 usec_delay(1); 1137 } 1138 1139 /* 1140 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1141 * @hw: pointer to hardware structure 1142 */ 1143 static void 1144 ixgbe_release_eeprom(struct ixgbe_hw *hw) 1145 { 1146 u32 eec; 1147 1148 DEBUGFUNC("ixgbe_release_eeprom"); 1149 1150 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1151 1152 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1153 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1154 1155 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1156 IXGBE_WRITE_FLUSH(hw); 1157 1158 usec_delay(1); 1159 1160 /* Stop requesting EEPROM access */ 1161 eec &= ~IXGBE_EEC_REQ; 1162 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1163 1164 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1165 1166 /* Delay before attempt to obtain semaphore again to allow FW access */ 1167 msec_delay(hw->eeprom.semaphore_delay); 1168 } 1169 1170 /* 1171 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1172 * @hw: pointer to hardware structure 1173 */ 1174 u16 1175 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1176 { 1177 u16 i; 1178 u16 j; 1179 u16 checksum = 0; 1180 u16 length = 0; 1181 u16 pointer = 0; 1182 u16 word = 0; 1183 1184 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 1185 1186 /* Include 0x0-0x3F in the checksum */ 1187 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1188 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1189 DEBUGOUT("EEPROM read failed\n"); 1190 break; 1191 } 1192 checksum += word; 1193 } 1194 1195 /* Include all data from pointers except for the fw pointer */ 1196 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1197 hw->eeprom.ops.read(hw, i, &pointer); 1198 1199 /* Make sure the pointer seems valid */ 1200 if (pointer != 0xFFFF && pointer != 0) { 1201 hw->eeprom.ops.read(hw, pointer, &length); 1202 1203 if (length != 0xFFFF && length != 0) { 1204 for (j = pointer+1; j <= pointer+length; j++) { 1205 hw->eeprom.ops.read(hw, j, &word); 1206 checksum += word; 1207 } 1208 } 1209 } 1210 } 1211 1212 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1213 1214 return (checksum); 1215 } 1216 1217 /* 1218 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1219 * @hw: pointer to hardware structure 1220 * @checksum_val: calculated checksum 1221 * 1222 * Performs checksum calculation and validates the EEPROM checksum. If the 1223 * caller does not need checksum_val, the value can be NULL. 1224 */ 1225 s32 1226 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1227 u16 *checksum_val) 1228 { 1229 s32 status; 1230 u16 checksum; 1231 u16 read_checksum = 0; 1232 1233 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1234 1235 /* 1236 * Read the first word from the EEPROM. If this times out or fails, do 1237 * not continue or we could be in for a very long wait while every 1238 * EEPROM read fails 1239 */ 1240 status = hw->eeprom.ops.read(hw, 0, &checksum); 1241 1242 if (status == IXGBE_SUCCESS) { 1243 checksum = hw->eeprom.ops.calc_checksum(hw); 1244 1245 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1246 1247 /* 1248 * Verify read checksum from EEPROM is the same as 1249 * calculated checksum 1250 */ 1251 if (read_checksum != checksum) 1252 status = IXGBE_ERR_EEPROM_CHECKSUM; 1253 1254 /* If the user cares, return the calculated checksum */ 1255 if (checksum_val) 1256 *checksum_val = checksum; 1257 } else { 1258 DEBUGOUT("EEPROM read failed\n"); 1259 } 1260 1261 return (status); 1262 } 1263 1264 /* 1265 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1266 * @hw: pointer to hardware structure 1267 */ 1268 s32 1269 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1270 { 1271 s32 status; 1272 u16 checksum; 1273 1274 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1275 1276 /* 1277 * Read the first word from the EEPROM. If this times out or fails, do 1278 * not continue or we could be in for a very long wait while every 1279 * EEPROM read fails 1280 */ 1281 status = hw->eeprom.ops.read(hw, 0, &checksum); 1282 1283 if (status == IXGBE_SUCCESS) { 1284 checksum = hw->eeprom.ops.calc_checksum(hw); 1285 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1286 checksum); 1287 } else { 1288 DEBUGOUT("EEPROM read failed\n"); 1289 } 1290 1291 return (status); 1292 } 1293 1294 /* 1295 * ixgbe_validate_mac_addr - Validate MAC address 1296 * @mac_addr: pointer to MAC address. 1297 * 1298 * Tests a MAC address to ensure it is a valid Individual Address 1299 */ 1300 s32 1301 ixgbe_validate_mac_addr(u8 *mac_addr) 1302 { 1303 s32 status = IXGBE_SUCCESS; 1304 1305 DEBUGFUNC("ixgbe_validate_mac_addr"); 1306 1307 /* Make sure it is not a multicast address */ 1308 if (IXGBE_IS_MULTICAST(mac_addr)) { 1309 DEBUGOUT("MAC address is multicast\n"); 1310 status = IXGBE_ERR_INVALID_MAC_ADDR; 1311 /* Not a broadcast address */ 1312 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1313 DEBUGOUT("MAC address is broadcast\n"); 1314 status = IXGBE_ERR_INVALID_MAC_ADDR; 1315 /* Reject the zero address */ 1316 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1317 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1318 DEBUGOUT("MAC address is all zeros\n"); 1319 status = IXGBE_ERR_INVALID_MAC_ADDR; 1320 } 1321 return (status); 1322 } 1323 1324 /* 1325 * ixgbe_set_rar_generic - Set Rx address register 1326 * @hw: pointer to hardware structure 1327 * @index: Receive address register to write 1328 * @addr: Address to put into receive address register 1329 * @vmdq: VMDq "set" or "pool" index 1330 * @enable_addr: set flag that address is active 1331 * 1332 * Puts an ethernet address into a receive address register. 1333 */ 1334 s32 1335 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1336 u32 enable_addr) 1337 { 1338 u32 rar_low, rar_high; 1339 u32 rar_entries = hw->mac.num_rar_entries; 1340 1341 DEBUGFUNC("ixgbe_set_rar_generic"); 1342 1343 /* setup VMDq pool selection before this RAR gets enabled */ 1344 hw->mac.ops.set_vmdq(hw, index, vmdq); 1345 1346 /* Make sure we are using a valid rar index range */ 1347 if (index < rar_entries) { 1348 /* 1349 * HW expects these in little endian so we reverse the byte 1350 * order from network order (big endian) to little endian 1351 */ 1352 rar_low = ((u32)addr[0] | 1353 ((u32)addr[1] << 8) | 1354 ((u32)addr[2] << 16) | 1355 ((u32)addr[3] << 24)); 1356 /* 1357 * Some parts put the VMDq setting in the extra RAH bits, 1358 * so save everything except the lower 16 bits that hold part 1359 * of the address and the address valid bit. 1360 */ 1361 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1362 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1363 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1364 1365 if (enable_addr != 0) 1366 rar_high |= IXGBE_RAH_AV; 1367 1368 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1369 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1370 } else { 1371 DEBUGOUT1("RAR index %d is out of range.\n", index); 1372 } 1373 1374 return (IXGBE_SUCCESS); 1375 } 1376 1377 /* 1378 * ixgbe_clear_rar_generic - Remove Rx address register 1379 * @hw: pointer to hardware structure 1380 * @index: Receive address register to write 1381 * 1382 * Clears an ethernet address from a receive address register. 1383 */ 1384 s32 1385 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1386 { 1387 u32 rar_high; 1388 u32 rar_entries = hw->mac.num_rar_entries; 1389 1390 DEBUGFUNC("ixgbe_clear_rar_generic"); 1391 1392 /* Make sure we are using a valid rar index range */ 1393 if (index < rar_entries) { 1394 /* 1395 * Some parts put the VMDq setting in the extra RAH bits, 1396 * so save everything except the lower 16 bits that hold part 1397 * of the address and the address valid bit. 1398 */ 1399 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1400 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1401 1402 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1403 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1404 } else { 1405 DEBUGOUT1("RAR index %d is out of range.\n", index); 1406 } 1407 1408 /* clear VMDq pool/queue selection for this RAR */ 1409 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1410 1411 return (IXGBE_SUCCESS); 1412 } 1413 1414 /* 1415 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1416 * @hw: pointer to hardware structure 1417 * 1418 * Places the MAC address in receive address register 0 and clears the rest 1419 * of the receive address registers. Clears the multicast table. Assumes 1420 * the receiver is in reset when the routine is called. 1421 */ 1422 s32 1423 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1424 { 1425 u32 i; 1426 u32 rar_entries = hw->mac.num_rar_entries; 1427 1428 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 1429 1430 /* 1431 * If the current mac address is valid, assume it is a software override 1432 * to the permanent address. 1433 * Otherwise, use the permanent address from the eeprom. 1434 */ 1435 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1436 IXGBE_ERR_INVALID_MAC_ADDR) { 1437 /* Get the MAC address from the RAR0 for later reference */ 1438 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1439 1440 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1441 hw->mac.addr[0], hw->mac.addr[1], 1442 hw->mac.addr[2]); 1443 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1444 hw->mac.addr[4], hw->mac.addr[5]); 1445 } else { 1446 /* Setup the receive address. */ 1447 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1448 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1449 hw->mac.addr[0], hw->mac.addr[1], 1450 hw->mac.addr[2]); 1451 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1452 hw->mac.addr[4], hw->mac.addr[5]); 1453 1454 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1455 } 1456 hw->addr_ctrl.overflow_promisc = 0; 1457 1458 hw->addr_ctrl.rar_used_count = 1; 1459 1460 /* Zero out the other receive addresses. */ 1461 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1462 for (i = 1; i < rar_entries; i++) { 1463 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1464 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1465 } 1466 1467 /* Clear the MTA */ 1468 hw->addr_ctrl.mta_in_use = 0; 1469 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1470 1471 DEBUGOUT(" Clearing MTA\n"); 1472 for (i = 0; i < hw->mac.mcft_size; i++) 1473 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1474 1475 (void) ixgbe_init_uta_tables(hw); 1476 1477 return (IXGBE_SUCCESS); 1478 } 1479 1480 1481 /* 1482 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1483 * @hw: pointer to hardware structure 1484 * @addr: new address 1485 * 1486 * Adds it to unused receive address register or goes into promiscuous mode. 1487 */ 1488 void 1489 ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1490 { 1491 u32 rar_entries = hw->mac.num_rar_entries; 1492 u32 rar; 1493 1494 DEBUGFUNC("ixgbe_add_uc_addr"); 1495 1496 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1497 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1498 1499 /* 1500 * Place this address in the RAR if there is room, 1501 * else put the controller into promiscuous mode 1502 */ 1503 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1504 rar = hw->addr_ctrl.rar_used_count; 1505 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1506 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1507 hw->addr_ctrl.rar_used_count++; 1508 } else { 1509 hw->addr_ctrl.overflow_promisc++; 1510 } 1511 1512 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1513 } 1514 1515 /* 1516 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1517 * @hw: pointer to hardware structure 1518 * @addr_list: the list of new addresses 1519 * @addr_count: number of addresses 1520 * @next: iterator function to walk the address list 1521 * 1522 * The given list replaces any existing list. Clears the secondary addrs from 1523 * receive address registers. Uses unused receive address registers for the 1524 * first secondary addresses, and falls back to promiscuous mode as needed. 1525 * 1526 * Drivers using secondary unicast addresses must set user_set_promisc when 1527 * manually putting the device into promiscuous mode. 1528 */ 1529 s32 1530 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1531 u32 addr_count, ixgbe_mc_addr_itr next) 1532 { 1533 u8 *addr; 1534 u32 i; 1535 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1536 u32 uc_addr_in_use; 1537 u32 fctrl; 1538 u32 vmdq; 1539 1540 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 1541 1542 /* 1543 * Clear accounting of old secondary address list, 1544 * don't count RAR[0] 1545 */ 1546 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1547 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1548 hw->addr_ctrl.overflow_promisc = 0; 1549 1550 /* Zero out the other receive addresses */ 1551 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use + 1); 1552 for (i = 0; i < uc_addr_in_use; i++) { 1553 IXGBE_WRITE_REG(hw, IXGBE_RAL(i + 1), 0); 1554 IXGBE_WRITE_REG(hw, IXGBE_RAH(i + 1), 0); 1555 } 1556 1557 /* Add the new addresses */ 1558 for (i = 0; i < addr_count; i++) { 1559 DEBUGOUT(" Adding the secondary addresses:\n"); 1560 addr = next(hw, &addr_list, &vmdq); 1561 ixgbe_add_uc_addr(hw, addr, vmdq); 1562 } 1563 1564 if (hw->addr_ctrl.overflow_promisc) { 1565 /* enable promisc if not already in overflow or set by user */ 1566 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1567 DEBUGOUT(" Entering address overflow promisc mode\n"); 1568 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1569 fctrl |= IXGBE_FCTRL_UPE; 1570 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1571 } 1572 } else { 1573 /* only disable if set by overflow, not by user */ 1574 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1575 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1576 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1577 fctrl &= ~IXGBE_FCTRL_UPE; 1578 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1579 } 1580 } 1581 1582 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1583 return (IXGBE_SUCCESS); 1584 } 1585 1586 /* 1587 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1588 * @hw: pointer to hardware structure 1589 * @mc_addr: the multicast address 1590 * 1591 * Extracts the 12 bits, from a multicast address, to determine which 1592 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1593 * incoming rx multicast addresses, to determine the bit-vector to check in 1594 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1595 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1596 * to mc_filter_type. 1597 */ 1598 static s32 1599 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1600 { 1601 u32 vector = 0; 1602 1603 DEBUGFUNC("ixgbe_mta_vector"); 1604 1605 switch (hw->mac.mc_filter_type) { 1606 case 0: /* use bits [47:36] of the address */ 1607 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1608 break; 1609 case 1: /* use bits [46:35] of the address */ 1610 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1611 break; 1612 case 2: /* use bits [45:34] of the address */ 1613 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1614 break; 1615 case 3: /* use bits [43:32] of the address */ 1616 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1617 break; 1618 default: /* Invalid mc_filter_type */ 1619 DEBUGOUT("MC filter type param set incorrectly\n"); 1620 ASSERT(0); 1621 break; 1622 } 1623 1624 /* vector can only be 12-bits or boundary will be exceeded */ 1625 vector &= 0xFFF; 1626 return (vector); 1627 } 1628 1629 /* 1630 * ixgbe_set_mta - Set bit-vector in multicast table 1631 * @hw: pointer to hardware structure 1632 * @hash_value: Multicast address hash value 1633 * 1634 * Sets the bit-vector in the multicast table. 1635 */ 1636 void 1637 ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1638 { 1639 u32 vector; 1640 u32 vector_bit; 1641 u32 vector_reg; 1642 u32 mta_reg; 1643 1644 DEBUGFUNC("ixgbe_set_mta"); 1645 1646 hw->addr_ctrl.mta_in_use++; 1647 1648 vector = ixgbe_mta_vector(hw, mc_addr); 1649 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1650 1651 /* 1652 * The MTA is a register array of 128 32-bit registers. It is treated 1653 * like an array of 4096 bits. We want to set bit 1654 * BitArray[vector_value]. So we figure out what register the bit is 1655 * in, read it, OR in the new bit, then write back the new value. The 1656 * register is determined by the upper 7 bits of the vector value and 1657 * the bit within that register are determined by the lower 5 bits of 1658 * the value. 1659 */ 1660 vector_reg = (vector >> 5) & 0x7F; 1661 vector_bit = vector & 0x1F; 1662 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1663 mta_reg |= (1 << vector_bit); 1664 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1665 } 1666 1667 /* 1668 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1669 * @hw: pointer to hardware structure 1670 * @mc_addr_list: the list of new multicast addresses 1671 * @mc_addr_count: number of addresses 1672 * @next: iterator function to walk the multicast address list 1673 * 1674 * The given list replaces any existing list. Clears the MC addrs from receive 1675 * address registers and the multicast table. Uses unused receive address 1676 * registers for the first multicast addresses, and hashes the rest into the 1677 * multicast table. 1678 */ 1679 s32 1680 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1681 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1682 { 1683 u32 i; 1684 u32 vmdq; 1685 1686 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 1687 1688 /* 1689 * Set the new number of MC addresses that we are being requested to 1690 * use. 1691 */ 1692 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1693 hw->addr_ctrl.mta_in_use = 0; 1694 1695 /* Clear the MTA */ 1696 DEBUGOUT(" Clearing MTA\n"); 1697 for (i = 0; i < hw->mac.mcft_size; i++) 1698 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1699 1700 /* Add the new addresses */ 1701 for (i = 0; i < mc_addr_count; i++) { 1702 DEBUGOUT(" Adding the multicast addresses:\n"); 1703 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1704 } 1705 1706 /* Enable mta */ 1707 if (hw->addr_ctrl.mta_in_use > 0) 1708 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1709 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1710 1711 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1712 return (IXGBE_SUCCESS); 1713 } 1714 1715 /* 1716 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1717 * @hw: pointer to hardware structure 1718 * 1719 * Enables multicast address in RAR and the use of the multicast hash table. 1720 */ 1721 s32 1722 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1723 { 1724 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1725 1726 DEBUGFUNC("ixgbe_enable_mc_generic"); 1727 1728 if (a->mta_in_use > 0) 1729 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1730 hw->mac.mc_filter_type); 1731 1732 return (IXGBE_SUCCESS); 1733 } 1734 1735 /* 1736 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1737 * @hw: pointer to hardware structure 1738 * 1739 * Disables multicast address in RAR and the use of the multicast hash table. 1740 */ 1741 s32 1742 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1743 { 1744 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1745 1746 DEBUGFUNC("ixgbe_disable_mc_generic"); 1747 1748 if (a->mta_in_use > 0) 1749 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1750 1751 return (IXGBE_SUCCESS); 1752 } 1753 1754 /* 1755 * ixgbe_fc_enable_generic - Enable flow control 1756 * @hw: pointer to hardware structure 1757 * @packetbuf_num: packet buffer number (0-7) 1758 * 1759 * Enable flow control according to the current settings. 1760 */ 1761 s32 1762 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1763 { 1764 s32 ret_val = IXGBE_SUCCESS; 1765 u32 mflcn_reg, fccfg_reg; 1766 u32 reg; 1767 u32 rx_pba_size; 1768 1769 DEBUGFUNC("ixgbe_fc_enable_generic"); 1770 1771 /* Negotiate the fc mode to use */ 1772 ret_val = ixgbe_fc_autoneg(hw); 1773 if (ret_val) 1774 goto out; 1775 1776 /* Disable any previous flow control settings */ 1777 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1778 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1779 1780 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1781 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1782 1783 /* 1784 * The possible values of fc.current_mode are: 1785 * 0: Flow control is completely disabled 1786 * 1: Rx flow control is enabled (we can receive pause frames, 1787 * but not send pause frames). 1788 * 2: Tx flow control is enabled (we can send pause frames but 1789 * we do not support receiving pause frames). 1790 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1791 * other: Invalid. 1792 */ 1793 switch (hw->fc.current_mode) { 1794 case ixgbe_fc_none: 1795 /* 1796 * Flow control is disabled by software override or autoneg. 1797 * The code below will actually disable it in the HW. 1798 */ 1799 break; 1800 case ixgbe_fc_rx_pause: 1801 /* 1802 * Rx Flow control is enabled and Tx Flow control is 1803 * disabled by software override. Since there really 1804 * isn't a way to advertise that we are capable of RX 1805 * Pause ONLY, we will advertise that we support both 1806 * symmetric and asymmetric Rx PAUSE. Later, we will 1807 * disable the adapter's ability to send PAUSE frames. 1808 */ 1809 mflcn_reg |= IXGBE_MFLCN_RFCE; 1810 break; 1811 case ixgbe_fc_tx_pause: 1812 /* 1813 * Tx Flow control is enabled, and Rx Flow control is 1814 * disabled by software override. 1815 */ 1816 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1817 break; 1818 case ixgbe_fc_full: 1819 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1820 mflcn_reg |= IXGBE_MFLCN_RFCE; 1821 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1822 break; 1823 default: 1824 DEBUGOUT("Flow control param set incorrectly\n"); 1825 ret_val = IXGBE_ERR_CONFIG; 1826 goto out; 1827 } 1828 1829 /* Set 802.3x based flow control settings. */ 1830 mflcn_reg |= IXGBE_MFLCN_DPF; 1831 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1832 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1833 1834 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1835 /* Thresholds are different for link flow control when in DCB mode */ 1836 if (reg & IXGBE_MTQC_RT_ENA) { 1837 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1838 1839 /* Always disable XON for LFC when in DCB mode */ 1840 reg = (rx_pba_size >> 5) & 0xFFE0; 1841 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1842 1843 reg = (rx_pba_size >> 2) & 0xFFE0; 1844 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1845 reg |= IXGBE_FCRTH_FCEN; 1846 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1847 } else { 1848 /* 1849 * Set up and enable Rx high/low water mark thresholds, 1850 * enable XON. 1851 */ 1852 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1853 if (hw->fc.send_xon) { 1854 IXGBE_WRITE_REG(hw, 1855 IXGBE_FCRTL_82599(packetbuf_num), 1856 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 1857 } else { 1858 IXGBE_WRITE_REG(hw, 1859 IXGBE_FCRTL_82599(packetbuf_num), 1860 hw->fc.low_water); 1861 } 1862 1863 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1864 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1865 } 1866 } 1867 1868 /* Configure pause time (2 TCs per register) */ 1869 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1870 if ((packetbuf_num & 1) == 0) 1871 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1872 else 1873 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1874 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1875 1876 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1877 1878 out: 1879 return (ret_val); 1880 } 1881 1882 /* 1883 * ixgbe_fc_autoneg - Configure flow control 1884 * @hw: pointer to hardware structure 1885 * 1886 * Compares our advertised flow control capabilities to those advertised by 1887 * our link partner, and determines the proper flow control mode to use. 1888 */ 1889 s32 1890 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1891 { 1892 s32 ret_val = IXGBE_SUCCESS; 1893 ixgbe_link_speed speed; 1894 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1895 u32 links2, anlp1_reg, autoc_reg, links; 1896 bool link_up; 1897 1898 DEBUGFUNC("ixgbe_fc_autoneg"); 1899 1900 /* 1901 * AN should have completed when the cable was plugged in. 1902 * Look for reasons to bail out. Bail out if: 1903 * - FC autoneg is disabled, or if 1904 * - link is not up. 1905 * 1906 * Since we're being called from an LSC, link is already known to be up. 1907 * So use link_up_wait_to_complete=false. 1908 */ 1909 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1910 1911 if (hw->fc.disable_fc_autoneg || (!link_up)) { 1912 hw->fc.fc_was_autonegged = false; 1913 hw->fc.current_mode = hw->fc.requested_mode; 1914 goto out; 1915 } 1916 1917 /* 1918 * On backplane, bail out if 1919 * - backplane autoneg was not completed, or if 1920 * - we are 82599 and link partner is not AN enabled 1921 */ 1922 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1923 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 1924 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 1925 hw->fc.fc_was_autonegged = false; 1926 hw->fc.current_mode = hw->fc.requested_mode; 1927 goto out; 1928 } 1929 1930 if (hw->mac.type == ixgbe_mac_82599EB) { 1931 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 1932 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 1933 hw->fc.fc_was_autonegged = false; 1934 hw->fc.current_mode = hw->fc.requested_mode; 1935 goto out; 1936 } 1937 } 1938 } 1939 1940 /* 1941 * On multispeed fiber at 1g, bail out if 1942 * - link is up but AN did not complete, or if 1943 * - link is up and AN completed but timed out 1944 */ 1945 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { 1946 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1947 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1948 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1949 hw->fc.fc_was_autonegged = false; 1950 hw->fc.current_mode = hw->fc.requested_mode; 1951 goto out; 1952 } 1953 } 1954 1955 /* 1956 * Bail out on 1957 * - copper or CX4 adapters 1958 * - fiber adapters running at 10gig 1959 */ 1960 if ((hw->phy.media_type == ixgbe_media_type_copper) || 1961 (hw->phy.media_type == ixgbe_media_type_cx4) || 1962 ((hw->phy.media_type == ixgbe_media_type_fiber) && 1963 (speed == IXGBE_LINK_SPEED_10GB_FULL))) { 1964 hw->fc.fc_was_autonegged = false; 1965 hw->fc.current_mode = hw->fc.requested_mode; 1966 goto out; 1967 } 1968 1969 /* 1970 * Read the AN advertisement and LP ability registers and resolve 1971 * local flow control settings accordingly 1972 */ 1973 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1974 (hw->phy.media_type != ixgbe_media_type_backplane)) { 1975 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1976 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1977 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1978 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1979 /* 1980 * Now we need to check if the user selected Rx ONLY 1981 * of pause frames. In this case, we had to advertise 1982 * FULL flow control because we could not advertise RX 1983 * ONLY. Hence, we must now check to see if we need to 1984 * turn OFF the TRANSMISSION of PAUSE frames. 1985 */ 1986 if (hw->fc.requested_mode == ixgbe_fc_full) { 1987 hw->fc.current_mode = ixgbe_fc_full; 1988 DEBUGOUT("Flow Control = FULL.\n"); 1989 } else { 1990 hw->fc.current_mode = ixgbe_fc_rx_pause; 1991 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1992 } 1993 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1994 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1995 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1996 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1997 hw->fc.current_mode = ixgbe_fc_tx_pause; 1998 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1999 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 2000 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 2001 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 2002 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 2003 hw->fc.current_mode = ixgbe_fc_rx_pause; 2004 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2005 } else { 2006 hw->fc.current_mode = ixgbe_fc_none; 2007 DEBUGOUT("Flow Control = NONE.\n"); 2008 } 2009 } 2010 2011 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2012 /* 2013 * Read the 10g AN autoc and LP ability registers and resolve 2014 * local flow control settings accordingly 2015 */ 2016 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2017 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2018 2019 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2020 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { 2021 /* 2022 * Now we need to check if the user selected Rx ONLY 2023 * of pause frames. In this case, we had to advertise 2024 * FULL flow control because we could not advertise RX 2025 * ONLY. Hence, we must now check to see if we need to 2026 * turn OFF the TRANSMISSION of PAUSE frames. 2027 */ 2028 if (hw->fc.requested_mode == ixgbe_fc_full) { 2029 hw->fc.current_mode = ixgbe_fc_full; 2030 DEBUGOUT("Flow Control = FULL.\n"); 2031 } else { 2032 hw->fc.current_mode = ixgbe_fc_rx_pause; 2033 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2034 } 2035 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2036 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 2037 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 2038 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 2039 hw->fc.current_mode = ixgbe_fc_tx_pause; 2040 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2041 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2042 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 2043 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 2044 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 2045 hw->fc.current_mode = ixgbe_fc_rx_pause; 2046 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2047 } else { 2048 hw->fc.current_mode = ixgbe_fc_none; 2049 DEBUGOUT("Flow Control = NONE.\n"); 2050 } 2051 } 2052 /* Record that current_mode is the result of a successful autoneg */ 2053 hw->fc.fc_was_autonegged = true; 2054 2055 out: 2056 return (ret_val); 2057 } 2058 2059 /* 2060 * ixgbe_setup_fc - Set up flow control 2061 * @hw: pointer to hardware structure 2062 * 2063 * Called at init time to set up flow control. 2064 */ 2065 s32 2066 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2067 { 2068 s32 ret_val = IXGBE_SUCCESS; 2069 u32 reg; 2070 2071 DEBUGFUNC("ixgbe_setup_fc"); 2072 2073 /* Validate the packetbuf configuration */ 2074 if (packetbuf_num < 0 || packetbuf_num > 7) { 2075 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 2076 " 0-7\n", packetbuf_num); 2077 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2078 goto out; 2079 } 2080 2081 /* 2082 * Validate the water mark configuration. Zero water marks are invalid 2083 * because it causes the controller to just blast out fc packets. 2084 */ 2085 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 2086 DEBUGOUT("Invalid water mark configuration\n"); 2087 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2088 goto out; 2089 } 2090 2091 /* 2092 * Validate the requested mode. Strict IEEE mode does not allow 2093 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2094 */ 2095 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2096 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2097 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2098 goto out; 2099 } 2100 2101 /* 2102 * 10gig parts do not have a word in the EEPROM to determine the 2103 * default flow control setting, so we explicitly set it to full. 2104 */ 2105 if (hw->fc.requested_mode == ixgbe_fc_default) 2106 hw->fc.requested_mode = ixgbe_fc_full; 2107 2108 /* 2109 * Set up the 1G flow control advertisement registers so the HW will be 2110 * able to do fc autoneg once the cable is plugged in. If we end up 2111 * using 10g instead, this is harmless. 2112 */ 2113 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2114 2115 /* 2116 * The possible values of fc.requested_mode are: 2117 * 0: Flow control is completely disabled 2118 * 1: Rx flow control is enabled (we can receive pause frames, 2119 * but not send pause frames). 2120 * 2: Tx flow control is enabled (we can send pause frames but 2121 * we do not support receiving pause frames). 2122 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2123 * other: Invalid. 2124 */ 2125 switch (hw->fc.requested_mode) { 2126 case ixgbe_fc_none: 2127 /* Flow control completely disabled by software override. */ 2128 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2129 break; 2130 case ixgbe_fc_rx_pause: 2131 /* 2132 * Rx Flow control is enabled and Tx Flow control is 2133 * disabled by software override. Since there really 2134 * isn't a way to advertise that we are capable of RX 2135 * Pause ONLY, we will advertise that we support both 2136 * symmetric and asymmetric Rx PAUSE. Later, we will 2137 * disable the adapter's ability to send PAUSE frames. 2138 */ 2139 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2140 break; 2141 case ixgbe_fc_tx_pause: 2142 /* 2143 * Tx Flow control is enabled, and Rx Flow control is 2144 * disabled by software override. 2145 */ 2146 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2147 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2148 break; 2149 case ixgbe_fc_full: 2150 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2151 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2152 break; 2153 default: 2154 DEBUGOUT("Flow control param set incorrectly\n"); 2155 ret_val = IXGBE_ERR_CONFIG; 2156 goto out; 2157 } 2158 2159 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2160 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2161 2162 /* Disable AN timeout */ 2163 if (hw->fc.strict_ieee) 2164 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2165 2166 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2167 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2168 2169 /* 2170 * Set up the 10G flow control advertisement registers so the HW 2171 * can do fc autoneg once the cable is plugged in. If we end up 2172 * using 1g instead, this is harmless. 2173 */ 2174 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2175 2176 /* 2177 * The possible values of fc.requested_mode are: 2178 * 0: Flow control is completely disabled 2179 * 1: Rx flow control is enabled (we can receive pause frames, 2180 * but not send pause frames). 2181 * 2: Tx flow control is enabled (we can send pause frames but 2182 * we do not support receiving pause frames). 2183 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2184 * other: Invalid. 2185 */ 2186 switch (hw->fc.requested_mode) { 2187 case ixgbe_fc_none: 2188 /* Flow control completely disabled by software override. */ 2189 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2190 break; 2191 case ixgbe_fc_rx_pause: 2192 /* 2193 * Rx Flow control is enabled and Tx Flow control is 2194 * disabled by software override. Since there really 2195 * isn't a way to advertise that we are capable of RX 2196 * Pause ONLY, we will advertise that we support both 2197 * symmetric and asymmetric Rx PAUSE. Later, we will 2198 * disable the adapter's ability to send PAUSE frames. 2199 */ 2200 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2201 break; 2202 case ixgbe_fc_tx_pause: 2203 /* 2204 * Tx Flow control is enabled, and Rx Flow control is 2205 * disabled by software override. 2206 */ 2207 reg |= (IXGBE_AUTOC_ASM_PAUSE); 2208 reg &= ~(IXGBE_AUTOC_SYM_PAUSE); 2209 break; 2210 case ixgbe_fc_full: 2211 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2212 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2213 break; 2214 default: 2215 DEBUGOUT("Flow control param set incorrectly\n"); 2216 ret_val = IXGBE_ERR_CONFIG; 2217 goto out; 2218 } 2219 /* 2220 * AUTOC restart handles negotiation of 1G and 10G. There is 2221 * no need to set the PCS1GCTL register. 2222 */ 2223 reg |= IXGBE_AUTOC_AN_RESTART; 2224 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); 2225 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2226 2227 out: 2228 return (ret_val); 2229 } 2230 2231 /* 2232 * ixgbe_disable_pcie_master - Disable PCI-express master access 2233 * @hw: pointer to hardware structure 2234 * 2235 * Disables PCI-Express master access and verifies there are no pending 2236 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2237 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2238 * is returned signifying master requests disabled. 2239 */ 2240 s32 2241 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2242 { 2243 u32 i; 2244 u32 reg_val; 2245 u32 number_of_queues; 2246 s32 status = IXGBE_SUCCESS; 2247 2248 DEBUGFUNC("ixgbe_disable_pcie_master"); 2249 2250 /* Just jump out if bus mastering is already disabled */ 2251 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2252 goto out; 2253 2254 /* Disable the receive unit by stopping each queue */ 2255 number_of_queues = hw->mac.max_rx_queues; 2256 for (i = 0; i < number_of_queues; i++) { 2257 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2258 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2259 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2260 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2261 } 2262 } 2263 2264 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2265 reg_val |= IXGBE_CTRL_GIO_DIS; 2266 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2267 2268 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2269 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2270 goto out; 2271 usec_delay(100); 2272 } 2273 2274 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2275 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2276 2277 /* 2278 * The GIO Master Disable bit didn't clear. There are multiple reasons 2279 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they 2280 * all require a double reset to recover from. Before proceeding, we 2281 * first wait a little more to try to ensure that, at a minimum, the 2282 * PCIe block has no transactions pending. 2283 */ 2284 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2285 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2286 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2287 break; 2288 usec_delay(100); 2289 } 2290 2291 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT) 2292 DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); 2293 2294 /* 2295 * Two consecutive resets are required via CTRL.RST per datasheet 2296 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2297 * of this need. The first reset prevents new master requests from 2298 * being issued by our device. We then must wait 1usec for any 2299 * remaining completions from the PCIe bus to trickle in, and then reset 2300 * again to clear out any effects they may have had on our device. 2301 */ 2302 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2303 2304 out: 2305 return (status); 2306 } 2307 2308 /* 2309 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2310 * @hw: pointer to hardware structure 2311 * @mask: Mask to specify which semaphore to acquire 2312 * 2313 * Acquires the SWFW semaphore thought the GSSR register for the specified 2314 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2315 */ 2316 s32 2317 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2318 { 2319 u32 gssr; 2320 u32 swmask = mask; 2321 u32 fwmask = mask << 5; 2322 s32 timeout = 200; 2323 2324 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2325 2326 while (timeout) { 2327 /* 2328 * SW EEPROM semaphore bit is used for access to all 2329 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2330 */ 2331 if (ixgbe_get_eeprom_semaphore(hw)) 2332 return (IXGBE_ERR_SWFW_SYNC); 2333 2334 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2335 if (!(gssr & (fwmask | swmask))) 2336 break; 2337 2338 /* 2339 * Firmware currently using resource (fwmask) or other software 2340 * thread currently using resource (swmask) 2341 */ 2342 ixgbe_release_eeprom_semaphore(hw); 2343 msec_delay(5); 2344 timeout--; 2345 } 2346 2347 if (!timeout) { 2348 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2349 return (IXGBE_ERR_SWFW_SYNC); 2350 } 2351 2352 gssr |= swmask; 2353 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2354 2355 ixgbe_release_eeprom_semaphore(hw); 2356 return (IXGBE_SUCCESS); 2357 } 2358 2359 /* 2360 * ixgbe_release_swfw_sync - Release SWFW semaphore 2361 * @hw: pointer to hardware structure 2362 * @mask: Mask to specify which semaphore to release 2363 * 2364 * Releases the SWFW semaphore thought the GSSR register for the specified 2365 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2366 */ 2367 void 2368 ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2369 { 2370 u32 gssr; 2371 u32 swmask = mask; 2372 2373 DEBUGFUNC("ixgbe_release_swfw_sync"); 2374 2375 (void) ixgbe_get_eeprom_semaphore(hw); 2376 2377 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2378 gssr &= ~swmask; 2379 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2380 2381 ixgbe_release_eeprom_semaphore(hw); 2382 } 2383 2384 /* 2385 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2386 * @hw: pointer to hardware structure 2387 * @regval: register value to write to RXCTRL 2388 * 2389 * Enables the Rx DMA unit 2390 */ 2391 s32 2392 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2393 { 2394 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2395 2396 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2397 2398 return (IXGBE_SUCCESS); 2399 } 2400 2401 /* 2402 * ixgbe_blink_led_start_generic - Blink LED based on index. 2403 * @hw: pointer to hardware structure 2404 * @index: led number to blink 2405 */ 2406 s32 2407 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2408 { 2409 ixgbe_link_speed speed = 0; 2410 bool link_up = 0; 2411 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2412 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2413 2414 DEBUGFUNC("ixgbe_blink_led_start_generic"); 2415 2416 /* 2417 * Link must be up to auto-blink the LEDs; 2418 * Force it if link is down. 2419 */ 2420 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2421 2422 if (!link_up) { 2423 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2424 autoc_reg |= IXGBE_AUTOC_FLU; 2425 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2426 msec_delay(10); 2427 } 2428 2429 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2430 led_reg |= IXGBE_LED_BLINK(index); 2431 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2432 IXGBE_WRITE_FLUSH(hw); 2433 2434 return (IXGBE_SUCCESS); 2435 } 2436 2437 /* 2438 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2439 * @hw: pointer to hardware structure 2440 * @index: led number to stop blinking 2441 */ 2442 s32 2443 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2444 { 2445 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2446 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2447 2448 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 2449 2450 autoc_reg &= ~IXGBE_AUTOC_FLU; 2451 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2452 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2453 2454 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2455 led_reg &= ~IXGBE_LED_BLINK(index); 2456 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2457 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2458 IXGBE_WRITE_FLUSH(hw); 2459 2460 return (IXGBE_SUCCESS); 2461 } 2462 2463 /* 2464 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2465 * @hw: pointer to hardware structure 2466 * @san_mac_offset: SAN MAC address offset 2467 * 2468 * This function will read the EEPROM location for the SAN MAC address 2469 * pointer, and returns the value at that location. This is used in both 2470 * get and set mac_addr routines. 2471 */ 2472 static s32 2473 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset) 2474 { 2475 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 2476 2477 /* 2478 * First read the EEPROM pointer to see if the MAC addresses are 2479 * available. 2480 */ 2481 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2482 2483 return (IXGBE_SUCCESS); 2484 } 2485 2486 /* 2487 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2488 * @hw: pointer to hardware structure 2489 * @san_mac_addr: SAN MAC address 2490 * 2491 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2492 * per-port, so set_lan_id() must be called before reading the addresses. 2493 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2494 * upon for non-SFP connections, so we must call it here. 2495 */ 2496 s32 2497 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2498 { 2499 u16 san_mac_data, san_mac_offset; 2500 u8 i; 2501 2502 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 2503 2504 /* 2505 * First read the EEPROM pointer to see if the MAC addresses are 2506 * available. If they're not, no point in calling set_lan_id() here. 2507 */ 2508 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2509 2510 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2511 /* 2512 * No addresses available in this EEPROM. It's not an 2513 * error though, so just wipe the local address and return. 2514 */ 2515 for (i = 0; i < 6; i++) 2516 san_mac_addr[i] = 0xFF; 2517 2518 goto san_mac_addr_out; 2519 } 2520 2521 /* make sure we know which port we need to program */ 2522 hw->mac.ops.set_lan_id(hw); 2523 /* apply the port offset to the address offset */ 2524 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2525 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2526 for (i = 0; i < 3; i++) { 2527 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2528 san_mac_addr[i * 2] = (u8)(san_mac_data); 2529 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2530 san_mac_offset++; 2531 } 2532 2533 san_mac_addr_out: 2534 return (IXGBE_SUCCESS); 2535 } 2536 2537 /* 2538 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 2539 * @hw: pointer to hardware structure 2540 * @san_mac_addr: SAN MAC address 2541 * 2542 * Write a SAN MAC address to the EEPROM. 2543 */ 2544 s32 2545 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2546 { 2547 s32 status = IXGBE_SUCCESS; 2548 u16 san_mac_data, san_mac_offset; 2549 u8 i; 2550 2551 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 2552 2553 /* Look for SAN mac address pointer. If not defined, return */ 2554 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2555 2556 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2557 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2558 goto san_mac_addr_out; 2559 } 2560 2561 /* Make sure we know which port we need to write */ 2562 hw->mac.ops.set_lan_id(hw); 2563 /* Apply the port offset to the address offset */ 2564 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2565 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2566 2567 for (i = 0; i < 3; i++) { 2568 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2569 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2570 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2571 san_mac_offset++; 2572 } 2573 2574 san_mac_addr_out: 2575 return (status); 2576 } 2577 2578 /* 2579 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2580 * @hw: pointer to hardware structure 2581 * 2582 * Read PCIe configuration space, and get the MSI-X vector count from 2583 * the capabilities table. 2584 */ 2585 u32 2586 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2587 { 2588 u32 msix_count = 64; 2589 2590 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 2591 if (hw->mac.msix_vectors_from_pcie) { 2592 msix_count = IXGBE_READ_PCIE_WORD(hw, 2593 IXGBE_PCIE_MSIX_82599_CAPS); 2594 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2595 2596 /* 2597 * MSI-X count is zero-based in HW, so increment to give 2598 * proper value. 2599 */ 2600 msix_count++; 2601 } 2602 2603 return (msix_count); 2604 } 2605 2606 /* 2607 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 2608 * @hw: pointer to hardware structure 2609 * @addr: Address to put into receive address register 2610 * @vmdq: VMDq pool to assign 2611 * 2612 * Puts an ethernet address into a receive address register, or 2613 * finds the rar that it is aleady in; adds to the pool list 2614 */ 2615 s32 2616 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2617 { 2618 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 2619 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 2620 u32 rar; 2621 u32 rar_low, rar_high; 2622 u32 addr_low, addr_high; 2623 2624 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 2625 2626 /* swap bytes for HW little endian */ 2627 addr_low = addr[0] | (addr[1] << 8) 2628 | (addr[2] << 16) 2629 | (addr[3] << 24); 2630 addr_high = addr[4] | (addr[5] << 8); 2631 2632 /* 2633 * Either find the mac_id in rar or find the first empty space. 2634 * rar_highwater points to just after the highest currently used 2635 * rar in order to shorten the search. It grows when we add a new 2636 * rar to the top. 2637 */ 2638 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 2639 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 2640 2641 if (((IXGBE_RAH_AV & rar_high) == 0) && 2642 first_empty_rar == NO_EMPTY_RAR_FOUND) { 2643 first_empty_rar = rar; 2644 } else if ((rar_high & 0xFFFF) == addr_high) { 2645 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 2646 if (rar_low == addr_low) 2647 break; /* found it already in the rars */ 2648 } 2649 } 2650 2651 if (rar < hw->mac.rar_highwater) { 2652 /* already there so just add to the pool bits */ 2653 (void) ixgbe_set_vmdq(hw, rar, vmdq); 2654 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 2655 /* stick it into first empty RAR slot we found */ 2656 rar = first_empty_rar; 2657 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2658 } else if (rar == hw->mac.rar_highwater) { 2659 /* add it to the top of the list and inc the highwater mark */ 2660 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2661 hw->mac.rar_highwater++; 2662 } else if (rar >= hw->mac.num_rar_entries) { 2663 return (IXGBE_ERR_INVALID_MAC_ADDR); 2664 } 2665 2666 /* 2667 * If we found rar[0], make sure the default pool bit (we use pool 0) 2668 * remains cleared to be sure default pool packets will get delivered 2669 */ 2670 if (rar == 0) 2671 (void) ixgbe_clear_vmdq(hw, rar, 0); 2672 2673 return (rar); 2674 } 2675 2676 /* 2677 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2678 * @hw: pointer to hardware struct 2679 * @rar: receive address register index to disassociate 2680 * @vmdq: VMDq pool index to remove from the rar 2681 */ 2682 s32 2683 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2684 { 2685 u32 mpsar_lo, mpsar_hi; 2686 u32 rar_entries = hw->mac.num_rar_entries; 2687 2688 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 2689 2690 if (rar < rar_entries) { 2691 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2692 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2693 2694 if (!mpsar_lo && !mpsar_hi) 2695 goto done; 2696 2697 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2698 if (mpsar_lo) { 2699 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2700 mpsar_lo = 0; 2701 } 2702 if (mpsar_hi) { 2703 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2704 mpsar_hi = 0; 2705 } 2706 } else if (vmdq < 32) { 2707 mpsar_lo &= ~(1 << vmdq); 2708 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2709 } else { 2710 mpsar_hi &= ~(1 << (vmdq - 32)); 2711 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2712 } 2713 2714 /* was that the last pool using this rar? */ 2715 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2716 hw->mac.ops.clear_rar(hw, rar); 2717 } else { 2718 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2719 } 2720 2721 done: 2722 return (IXGBE_SUCCESS); 2723 } 2724 2725 /* 2726 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2727 * @hw: pointer to hardware struct 2728 * @rar: receive address register index to associate with a VMDq index 2729 * @vmdq: VMDq pool index 2730 */ 2731 s32 2732 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2733 { 2734 u32 mpsar; 2735 u32 rar_entries = hw->mac.num_rar_entries; 2736 2737 DEBUGFUNC("ixgbe_set_vmdq_generic"); 2738 2739 if (rar < rar_entries) { 2740 if (vmdq < 32) { 2741 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2742 mpsar |= 1 << vmdq; 2743 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2744 } else { 2745 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2746 mpsar |= 1 << (vmdq - 32); 2747 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2748 } 2749 } else { 2750 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2751 } 2752 return (IXGBE_SUCCESS); 2753 } 2754 2755 /* 2756 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2757 * @hw: pointer to hardware structure 2758 */ 2759 s32 2760 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2761 { 2762 int i; 2763 2764 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 2765 DEBUGOUT(" Clearing UTA\n"); 2766 2767 for (i = 0; i < 128; i++) 2768 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2769 2770 return (IXGBE_SUCCESS); 2771 } 2772 2773 /* 2774 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2775 * @hw: pointer to hardware structure 2776 * @vlan: VLAN id to write to VLAN filter 2777 * 2778 * return the VLVF index where this VLAN id should be placed 2779 * 2780 */ 2781 s32 2782 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2783 { 2784 u32 bits = 0; 2785 u32 first_empty_slot = 0; 2786 s32 regindex; 2787 2788 /* short cut the special case */ 2789 if (vlan == 0) 2790 return (0); 2791 2792 /* 2793 * Search for the vlan id in the VLVF entries. Save off the first empty 2794 * slot found along the way 2795 */ 2796 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2797 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2798 if (!bits && !(first_empty_slot)) 2799 first_empty_slot = regindex; 2800 else if ((bits & 0x0FFF) == vlan) 2801 break; 2802 } 2803 2804 /* 2805 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2806 * in the VLVF. Else use the first empty VLVF register for this 2807 * vlan id. 2808 */ 2809 if (regindex >= IXGBE_VLVF_ENTRIES) { 2810 if (first_empty_slot) 2811 regindex = first_empty_slot; 2812 else { 2813 DEBUGOUT("No space in VLVF.\n"); 2814 regindex = IXGBE_ERR_NO_SPACE; 2815 } 2816 } 2817 2818 return (regindex); 2819 } 2820 2821 /* 2822 * ixgbe_set_vfta_generic - Set VLAN filter table 2823 * @hw: pointer to hardware structure 2824 * @vlan: VLAN id to write to VLAN filter 2825 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2826 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2827 * 2828 * Turn on/off specified VLAN in the VLAN filter table. 2829 */ 2830 s32 2831 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 2832 { 2833 s32 regindex; 2834 u32 bitindex; 2835 u32 vfta; 2836 u32 bits; 2837 u32 vt; 2838 u32 targetbit; 2839 bool vfta_changed = false; 2840 2841 DEBUGFUNC("ixgbe_set_vfta_generic"); 2842 2843 if (vlan > 4095) 2844 return (IXGBE_ERR_PARAM); 2845 2846 /* 2847 * this is a 2 part operation - first the VFTA, then the 2848 * VLVF and VLVFB if VT Mode is set 2849 * We don't write the VFTA until we know the VLVF part succeeded. 2850 */ 2851 2852 /* 2853 * Part 1 2854 * The VFTA is a bitstring made up of 128 32-bit registers 2855 * that enable the particular VLAN id, much like the MTA: 2856 * bits[11-5]: which register 2857 * bits[4-0]: which bit in the register 2858 */ 2859 regindex = (vlan >> 5) & 0x7F; 2860 bitindex = vlan & 0x1F; 2861 targetbit = (1 << bitindex); 2862 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2863 2864 if (vlan_on) { 2865 if (!(vfta & targetbit)) { 2866 vfta |= targetbit; 2867 vfta_changed = true; 2868 } 2869 } else { 2870 if ((vfta & targetbit)) { 2871 vfta &= ~targetbit; 2872 vfta_changed = true; 2873 } 2874 } 2875 2876 2877 /* 2878 * Part 2 2879 * If VT Mode is set 2880 * Either vlan_on 2881 * make sure the vlan is in VLVF 2882 * set the vind bit in the matching VLVFB 2883 * Or !vlan_on 2884 * clear the pool bit and possibly the vind 2885 */ 2886 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2887 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2888 s32 vlvf_index; 2889 2890 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 2891 if (vlvf_index < 0) 2892 return (vlvf_index); 2893 2894 if (vlan_on) { 2895 /* set the pool bit */ 2896 if (vind < 32) { 2897 bits = IXGBE_READ_REG(hw, 2898 IXGBE_VLVFB(vlvf_index * 2)); 2899 bits |= (1 << vind); 2900 IXGBE_WRITE_REG(hw, 2901 IXGBE_VLVFB(vlvf_index * 2), 2902 bits); 2903 } else { 2904 bits = IXGBE_READ_REG(hw, 2905 IXGBE_VLVFB((vlvf_index * 2) + 1)); 2906 bits |= (1 << (vind - 32)); 2907 IXGBE_WRITE_REG(hw, 2908 IXGBE_VLVFB((vlvf_index * 2) + 1), 2909 bits); 2910 } 2911 } else { 2912 /* clear the pool bit */ 2913 if (vind < 32) { 2914 bits = IXGBE_READ_REG(hw, 2915 IXGBE_VLVFB(vlvf_index * 2)); 2916 bits &= ~(1 << vind); 2917 IXGBE_WRITE_REG(hw, 2918 IXGBE_VLVFB(vlvf_index * 2), 2919 bits); 2920 bits |= IXGBE_READ_REG(hw, 2921 IXGBE_VLVFB((vlvf_index * 2) + 1)); 2922 } else { 2923 bits = IXGBE_READ_REG(hw, 2924 IXGBE_VLVFB((vlvf_index * 2) + 1)); 2925 bits &= ~(1 << (vind - 32)); 2926 IXGBE_WRITE_REG(hw, 2927 IXGBE_VLVFB((vlvf_index * 2) + 1), 2928 bits); 2929 bits |= IXGBE_READ_REG(hw, 2930 IXGBE_VLVFB(vlvf_index * 2)); 2931 } 2932 } 2933 2934 /* 2935 * If there are still bits set in the VLVFB registers 2936 * for the VLAN ID indicated we need to see if the 2937 * caller is requesting that we clear the VFTA entry bit. 2938 * If the caller has requested that we clear the VFTA 2939 * entry bit but there are still pools/VFs using this VLAN 2940 * ID entry then ignore the request. We're not worried 2941 * about the case where we're turning the VFTA VLAN ID 2942 * entry bit on, only when requested to turn it off as 2943 * there may be multiple pools and/or VFs using the 2944 * VLAN ID entry. In that case we cannot clear the 2945 * VFTA bit until all pools/VFs using that VLAN ID have also 2946 * been cleared. This will be indicated by "bits" being 2947 * zero. 2948 */ 2949 if (bits) { 2950 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 2951 (IXGBE_VLVF_VIEN | vlan)); 2952 if (!vlan_on) { 2953 /* 2954 * someone wants to clear the vfta entry 2955 * but some pools/VFs are still using it. 2956 * Ignore it. 2957 */ 2958 vfta_changed = false; 2959 } 2960 } else { 2961 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 2962 } 2963 } 2964 2965 if (vfta_changed) 2966 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 2967 2968 return (IXGBE_SUCCESS); 2969 } 2970 2971 /* 2972 * ixgbe_clear_vfta_generic - Clear VLAN filter table 2973 * @hw: pointer to hardware structure 2974 * 2975 * Clears the VLAN filer table, and the VMDq index associated with the filter 2976 */ 2977 s32 2978 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 2979 { 2980 u32 offset; 2981 2982 DEBUGFUNC("ixgbe_clear_vfta_generic"); 2983 2984 for (offset = 0; offset < hw->mac.vft_size; offset++) 2985 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 2986 2987 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 2988 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 2989 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 2990 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 2991 } 2992 2993 return (IXGBE_SUCCESS); 2994 } 2995 2996 /* 2997 * ixgbe_check_mac_link_generic - Determine link and speed status 2998 * @hw: pointer to hardware structure 2999 * @speed: pointer to link speed 3000 * @link_up: true when link is up 3001 * @link_up_wait_to_complete: bool used to wait for link up or not 3002 * 3003 * Reads the links register to determine if link is up and the current speed 3004 */ 3005 s32 3006 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3007 bool *link_up, bool link_up_wait_to_complete) 3008 { 3009 u32 links_reg; 3010 u32 i; 3011 3012 DEBUGFUNC("ixgbe_check_mac_link_generic"); 3013 3014 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3015 if (link_up_wait_to_complete) { 3016 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3017 if (links_reg & IXGBE_LINKS_UP) { 3018 *link_up = true; 3019 break; 3020 } else { 3021 *link_up = false; 3022 } 3023 msec_delay(100); 3024 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3025 } 3026 } else { 3027 if (links_reg & IXGBE_LINKS_UP) 3028 *link_up = true; 3029 else 3030 *link_up = false; 3031 } 3032 3033 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3034 IXGBE_LINKS_SPEED_10G_82599) 3035 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3036 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3037 IXGBE_LINKS_SPEED_1G_82599) 3038 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3039 else 3040 *speed = IXGBE_LINK_SPEED_100_FULL; 3041 3042 /* if link is down, zero out the current_mode */ 3043 if (*link_up == false) { 3044 hw->fc.current_mode = ixgbe_fc_none; 3045 hw->fc.fc_was_autonegged = false; 3046 } 3047 3048 return (IXGBE_SUCCESS); 3049 } 3050 3051 /* 3052 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3053 * the EEPROM 3054 * @hw: pointer to hardware structure 3055 * @wwnn_prefix: the alternative WWNN prefix 3056 * @wwpn_prefix: the alternative WWPN prefix 3057 * 3058 * This function will read the EEPROM from the alternative SAN MAC address 3059 * block to check the support for the alternative WWNN/WWPN prefix support. 3060 */ 3061 s32 3062 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3063 u16 *wwpn_prefix) 3064 { 3065 u16 offset, caps; 3066 u16 alt_san_mac_blk_offset; 3067 3068 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 3069 3070 /* clear output first */ 3071 *wwnn_prefix = 0xFFFF; 3072 *wwpn_prefix = 0xFFFF; 3073 3074 /* check if alternative SAN MAC is supported */ 3075 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3076 &alt_san_mac_blk_offset); 3077 3078 if ((alt_san_mac_blk_offset == 0) || 3079 (alt_san_mac_blk_offset == 0xFFFF)) 3080 goto wwn_prefix_out; 3081 3082 /* check capability in alternative san mac address block */ 3083 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3084 hw->eeprom.ops.read(hw, offset, &caps); 3085 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3086 goto wwn_prefix_out; 3087 3088 /* get the corresponding prefix for WWNN/WWPN */ 3089 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3090 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3091 3092 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3093 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3094 3095 wwn_prefix_out: 3096 return (IXGBE_SUCCESS); 3097 } 3098