1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 /* IntelVersion: 1.206 v2-9-1-1_2009-6-10_NSW1 */ 29 30 #include "ixgbe_common.h" 31 #include "ixgbe_api.h" 32 33 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 34 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 35 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 36 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 37 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 38 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 39 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 40 u16 count); 41 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 42 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 43 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 44 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 45 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 46 47 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 48 49 /* 50 * ixgbe_init_ops_generic - Inits function ptrs 51 * @hw: pointer to the hardware structure 52 * 53 * Initialize the function pointers. 54 */ 55 s32 56 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 57 { 58 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 59 struct ixgbe_mac_info *mac = &hw->mac; 60 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 61 62 /* EEPROM */ 63 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 64 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 65 if (eec & (1 << 8)) 66 eeprom->ops.read = &ixgbe_read_eeprom_generic; 67 else 68 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 69 eeprom->ops.write = &ixgbe_write_eeprom_generic; 70 eeprom->ops.validate_checksum = 71 &ixgbe_validate_eeprom_checksum_generic; 72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 73 74 /* MAC */ 75 mac->ops.init_hw = &ixgbe_init_hw_generic; 76 mac->ops.reset_hw = NULL; 77 mac->ops.start_hw = &ixgbe_start_hw_generic; 78 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 79 mac->ops.get_media_type = NULL; 80 mac->ops.get_supported_physical_layer = NULL; 81 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 82 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 83 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 84 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 85 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 86 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 87 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 88 89 /* LEDs */ 90 mac->ops.led_on = &ixgbe_led_on_generic; 91 mac->ops.led_off = &ixgbe_led_off_generic; 92 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 93 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 94 95 /* RAR, Multicast, VLAN */ 96 mac->ops.set_rar = &ixgbe_set_rar_generic; 97 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 98 mac->ops.insert_mac_addr = NULL; 99 mac->ops.set_vmdq = NULL; 100 mac->ops.clear_vmdq = NULL; 101 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 102 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 103 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 104 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 105 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 106 mac->ops.clear_vfta = NULL; 107 mac->ops.set_vfta = NULL; 108 mac->ops.init_uta_tables = NULL; 109 110 /* Flow Control */ 111 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 112 113 /* Link */ 114 mac->ops.get_link_capabilities = NULL; 115 mac->ops.setup_link = NULL; 116 mac->ops.setup_link_speed = NULL; 117 mac->ops.check_link = NULL; 118 119 return (IXGBE_SUCCESS); 120 } 121 122 /* 123 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 124 * @hw: pointer to hardware structure 125 * 126 * Starts the hardware by filling the bus info structure and media type, clears 127 * all on chip counters, initializes receive address registers, multicast 128 * table, VLAN filter table, calls routine to set up link and flow control 129 * settings, and leaves transmit and receive units disabled and uninitialized 130 */ 131 s32 132 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 133 { 134 u32 ctrl_ext; 135 136 /* Set the media type */ 137 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 138 139 /* PHY ops initialization must be done in reset_hw() */ 140 141 /* Clear the VLAN filter table */ 142 hw->mac.ops.clear_vfta(hw); 143 144 /* Clear statistics registers */ 145 hw->mac.ops.clear_hw_cntrs(hw); 146 147 /* Set No Snoop Disable */ 148 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 149 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 150 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 151 IXGBE_WRITE_FLUSH(hw); 152 153 /* Setup flow control */ 154 (void) ixgbe_setup_fc(hw, 0); 155 156 /* Clear adapter stopped flag */ 157 hw->adapter_stopped = false; 158 159 return (IXGBE_SUCCESS); 160 } 161 162 /* 163 * ixgbe_init_hw_generic - Generic hardware initialization 164 * @hw: pointer to hardware structure 165 * 166 * Initialize the hardware by resetting the hardware, filling the bus info 167 * structure and media type, clears all on chip counters, initializes receive 168 * address registers, multicast table, VLAN filter table, calls routine to set 169 * up link and flow control settings, and leaves transmit and receive units 170 * disabled and uninitialized 171 */ 172 s32 173 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 174 { 175 s32 status = IXGBE_SUCCESS; 176 177 /* Reset the hardware */ 178 status = hw->mac.ops.reset_hw(hw); 179 180 if (status == IXGBE_SUCCESS) { 181 /* Start the HW */ 182 status = hw->mac.ops.start_hw(hw); 183 } 184 185 return (status); 186 } 187 188 /* 189 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 190 * @hw: pointer to hardware structure 191 * 192 * Clears all hardware statistics counters by reading them from the hardware 193 * Statistics counters are clear on read. 194 */ 195 s32 196 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 197 { 198 u16 i = 0; 199 200 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 201 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 202 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 203 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 204 for (i = 0; i < 8; i++) 205 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 206 207 (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 208 (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 209 (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 210 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 211 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 212 if (hw->mac.type >= ixgbe_mac_82599EB) { 213 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 214 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 215 } else { 216 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 217 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 218 } 219 220 for (i = 0; i < 8; i++) { 221 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 222 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 223 if (hw->mac.type >= ixgbe_mac_82599EB) { 224 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 225 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 226 } else { 227 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 228 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 229 } 230 } 231 if (hw->mac.type >= ixgbe_mac_82599EB) 232 for (i = 0; i < 8; i++) 233 (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 234 235 (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 236 (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 237 (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 238 (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 239 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 240 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 241 (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 242 (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 243 (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 244 (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 245 (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 246 (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 247 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 248 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 249 for (i = 0; i < 8; i++) 250 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 251 (void) IXGBE_READ_REG(hw, IXGBE_RUC); 252 (void) IXGBE_READ_REG(hw, IXGBE_RFC); 253 (void) IXGBE_READ_REG(hw, IXGBE_ROC); 254 (void) IXGBE_READ_REG(hw, IXGBE_RJC); 255 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 256 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 257 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 258 (void) IXGBE_READ_REG(hw, IXGBE_TORL); 259 (void) IXGBE_READ_REG(hw, IXGBE_TORH); 260 (void) IXGBE_READ_REG(hw, IXGBE_TPR); 261 (void) IXGBE_READ_REG(hw, IXGBE_TPT); 262 (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 263 (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 264 (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 265 (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 266 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 267 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 268 (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 269 (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 270 for (i = 0; i < 16; i++) { 271 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 272 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 273 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 274 if (hw->mac.type >= ixgbe_mac_82599EB) { 275 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 276 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 277 } else { 278 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 279 } 280 } 281 282 return (IXGBE_SUCCESS); 283 } 284 285 /* 286 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 287 * @hw: pointer to hardware structure 288 * @pba_num: stores the part number from the EEPROM 289 * 290 * Reads the part number from the EEPROM. 291 */ 292 s32 293 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 294 { 295 s32 ret_val; 296 u16 data; 297 298 DEBUGFUNC("ixgbe_read_pba_num_generic"); 299 300 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 301 if (ret_val) { 302 DEBUGOUT("NVM Read Error\n"); 303 return (ret_val); 304 } 305 *pba_num = (u32)(data << 16); 306 307 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 308 if (ret_val) { 309 DEBUGOUT("NVM Read Error\n"); 310 return (ret_val); 311 } 312 *pba_num |= data; 313 314 return (IXGBE_SUCCESS); 315 } 316 317 /* 318 * ixgbe_get_mac_addr_generic - Generic get MAC address 319 * @hw: pointer to hardware structure 320 * @mac_addr: Adapter MAC address 321 * 322 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 323 * A reset of the adapter must be performed prior to calling this function 324 * in order for the MAC address to have been loaded from the EEPROM into RAR0 325 */ 326 s32 327 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 328 { 329 u32 rar_high; 330 u32 rar_low; 331 u16 i; 332 333 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 334 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 335 336 for (i = 0; i < 4; i++) 337 mac_addr[i] = (u8)(rar_low >> (i*8)); 338 339 for (i = 0; i < 2; i++) 340 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 341 342 return (IXGBE_SUCCESS); 343 } 344 345 /* 346 * ixgbe_get_bus_info_generic - Generic set PCI bus info 347 * @hw: pointer to hardware structure 348 * 349 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 350 */ 351 s32 352 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 353 { 354 struct ixgbe_mac_info *mac = &hw->mac; 355 u16 link_status; 356 357 hw->bus.type = ixgbe_bus_type_pci_express; 358 359 /* Get the negotiated link width and speed from PCI config space */ 360 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 361 362 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 363 case IXGBE_PCI_LINK_WIDTH_1: 364 hw->bus.width = ixgbe_bus_width_pcie_x1; 365 break; 366 case IXGBE_PCI_LINK_WIDTH_2: 367 hw->bus.width = ixgbe_bus_width_pcie_x2; 368 break; 369 case IXGBE_PCI_LINK_WIDTH_4: 370 hw->bus.width = ixgbe_bus_width_pcie_x4; 371 break; 372 case IXGBE_PCI_LINK_WIDTH_8: 373 hw->bus.width = ixgbe_bus_width_pcie_x8; 374 break; 375 default: 376 hw->bus.width = ixgbe_bus_width_unknown; 377 break; 378 } 379 380 switch (link_status & IXGBE_PCI_LINK_SPEED) { 381 case IXGBE_PCI_LINK_SPEED_2500: 382 hw->bus.speed = ixgbe_bus_speed_2500; 383 break; 384 case IXGBE_PCI_LINK_SPEED_5000: 385 hw->bus.speed = ixgbe_bus_speed_5000; 386 break; 387 default: 388 hw->bus.speed = ixgbe_bus_speed_unknown; 389 break; 390 } 391 392 mac->ops.set_lan_id(hw); 393 394 return (IXGBE_SUCCESS); 395 } 396 397 398 /* 399 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 400 * @hw: pointer to the HW structure 401 * 402 * Determines the LAN function id by reading memory-mapped registers 403 * and swaps the port value if requested. 404 */ 405 void 406 ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 407 { 408 struct ixgbe_bus_info *bus = &hw->bus; 409 u32 reg; 410 411 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 412 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 413 bus->lan_id = bus->func; 414 415 /* check for a port swap */ 416 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 417 if (reg & IXGBE_FACTPS_LFS) 418 bus->func ^= 0x1; 419 } 420 421 /* 422 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 423 * @hw: pointer to hardware structure 424 * 425 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 426 * disables transmit and receive units. The adapter_stopped flag is used by 427 * the shared code and drivers to determine if the adapter is in a stopped 428 * state and should not touch the hardware. 429 */ 430 s32 431 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 432 { 433 u32 number_of_queues; 434 u32 reg_val; 435 u16 i; 436 437 /* 438 * Set the adapter_stopped flag so other driver functions stop touching 439 * the hardware 440 */ 441 hw->adapter_stopped = true; 442 443 /* Disable the receive unit */ 444 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 445 reg_val &= ~(IXGBE_RXCTRL_RXEN); 446 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 447 IXGBE_WRITE_FLUSH(hw); 448 msec_delay(2); 449 450 /* Clear interrupt mask to stop from interrupts being generated */ 451 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 452 453 /* Clear any pending interrupts */ 454 (void) IXGBE_READ_REG(hw, IXGBE_EICR); 455 456 /* Disable the transmit unit. Each queue must be disabled. */ 457 number_of_queues = hw->mac.max_tx_queues; 458 for (i = 0; i < number_of_queues; i++) { 459 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 460 if (reg_val & IXGBE_TXDCTL_ENABLE) { 461 reg_val &= ~IXGBE_TXDCTL_ENABLE; 462 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 463 } 464 } 465 466 /* 467 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 468 * access and verify no pending requests 469 */ 470 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 471 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 472 } 473 474 return (IXGBE_SUCCESS); 475 } 476 477 /* 478 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 479 * @hw: pointer to hardware structure 480 * @index: led number to turn on 481 */ 482 s32 483 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 484 { 485 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 486 487 /* To turn on the LED, set mode to ON. */ 488 led_reg &= ~IXGBE_LED_MODE_MASK(index); 489 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 490 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 491 IXGBE_WRITE_FLUSH(hw); 492 493 return (IXGBE_SUCCESS); 494 } 495 496 /* 497 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 498 * @hw: pointer to hardware structure 499 * @index: led number to turn off 500 */ 501 s32 502 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 503 { 504 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 505 506 /* To turn off the LED, set mode to OFF. */ 507 led_reg &= ~IXGBE_LED_MODE_MASK(index); 508 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 509 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 510 IXGBE_WRITE_FLUSH(hw); 511 512 return (IXGBE_SUCCESS); 513 } 514 515 /* 516 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 517 * @hw: pointer to hardware structure 518 * 519 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 520 * ixgbe_hw struct in order to set up EEPROM access. 521 */ 522 s32 523 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 524 { 525 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 526 u32 eec; 527 u16 eeprom_size; 528 529 if (eeprom->type == ixgbe_eeprom_uninitialized) { 530 eeprom->type = ixgbe_eeprom_none; 531 /* 532 * Set default semaphore delay to 10ms which is a well 533 * tested value 534 */ 535 eeprom->semaphore_delay = 10; 536 537 /* 538 * Check for EEPROM present first. 539 * If not present leave as none 540 */ 541 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 542 if (eec & IXGBE_EEC_PRES) { 543 eeprom->type = ixgbe_eeprom_spi; 544 545 /* 546 * SPI EEPROM is assumed here. This code would need to 547 * change if a future EEPROM is not SPI. 548 */ 549 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 550 IXGBE_EEC_SIZE_SHIFT); 551 eeprom->word_size = 1 << (eeprom_size + 552 IXGBE_EEPROM_WORD_SIZE_SHIFT); 553 } 554 555 if (eec & IXGBE_EEC_ADDR_SIZE) 556 eeprom->address_bits = 16; 557 else 558 eeprom->address_bits = 8; 559 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 560 "%d\n", eeprom->type, eeprom->word_size, 561 eeprom->address_bits); 562 } 563 564 return (IXGBE_SUCCESS); 565 } 566 567 /* 568 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 569 * @hw: pointer to hardware structure 570 * @offset: offset within the EEPROM to be written to 571 * @data: 16 bit word to be written to the EEPROM 572 * 573 * If ixgbe_eeprom_update_checksum is not called after this function, the 574 * EEPROM will most likely contain an invalid checksum. 575 */ 576 s32 577 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 578 { 579 s32 status; 580 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 581 582 hw->eeprom.ops.init_params(hw); 583 584 if (offset >= hw->eeprom.word_size) { 585 status = IXGBE_ERR_EEPROM; 586 goto out; 587 } 588 589 /* Prepare the EEPROM for writing */ 590 status = ixgbe_acquire_eeprom(hw); 591 592 if (status == IXGBE_SUCCESS) { 593 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 594 ixgbe_release_eeprom(hw); 595 status = IXGBE_ERR_EEPROM; 596 } 597 } 598 599 if (status == IXGBE_SUCCESS) { 600 ixgbe_standby_eeprom(hw); 601 602 /* Send the WRITE ENABLE command (8 bit opcode ) */ 603 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 604 IXGBE_EEPROM_OPCODE_BITS); 605 606 ixgbe_standby_eeprom(hw); 607 608 /* 609 * Some SPI eeproms use the 8th address bit embedded in the 610 * opcode 611 */ 612 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 613 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 614 615 /* Send the Write command (8-bit opcode + addr) */ 616 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 617 IXGBE_EEPROM_OPCODE_BITS); 618 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 619 hw->eeprom.address_bits); 620 621 /* Send the data */ 622 data = (data >> 8) | (data << 8); 623 ixgbe_shift_out_eeprom_bits(hw, data, 16); 624 ixgbe_standby_eeprom(hw); 625 626 /* Done with writing - release the EEPROM */ 627 ixgbe_release_eeprom(hw); 628 } 629 630 out: 631 return (status); 632 } 633 634 /* 635 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 636 * @hw: pointer to hardware structure 637 * @offset: offset within the EEPROM to be read 638 * @data: read 16 bit value from EEPROM 639 * 640 * Reads 16 bit value from EEPROM through bit-bang method 641 */ 642 s32 643 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 644 u16 *data) 645 { 646 s32 status; 647 u16 word_in; 648 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 649 650 hw->eeprom.ops.init_params(hw); 651 652 if (offset >= hw->eeprom.word_size) { 653 status = IXGBE_ERR_EEPROM; 654 goto out; 655 } 656 657 /* Prepare the EEPROM for reading */ 658 status = ixgbe_acquire_eeprom(hw); 659 660 if (status == IXGBE_SUCCESS) { 661 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 662 ixgbe_release_eeprom(hw); 663 status = IXGBE_ERR_EEPROM; 664 } 665 } 666 667 if (status == IXGBE_SUCCESS) { 668 ixgbe_standby_eeprom(hw); 669 670 /* 671 * Some SPI eeproms use the 8th address bit embedded in the 672 * opcode 673 */ 674 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 675 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 676 677 /* Send the READ command (opcode + addr) */ 678 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 679 IXGBE_EEPROM_OPCODE_BITS); 680 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 681 hw->eeprom.address_bits); 682 683 /* Read the data. */ 684 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 685 *data = (word_in >> 8) | (word_in << 8); 686 687 /* End this read operation */ 688 ixgbe_release_eeprom(hw); 689 } 690 691 out: 692 return (status); 693 } 694 695 /* 696 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 697 * @hw: pointer to hardware structure 698 * @offset: offset of word in the EEPROM to read 699 * @data: word read from the EEPROM 700 * 701 * Reads a 16 bit word from the EEPROM using the EERD register. 702 */ 703 s32 704 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 705 { 706 u32 eerd; 707 s32 status; 708 709 hw->eeprom.ops.init_params(hw); 710 711 if (offset >= hw->eeprom.word_size) { 712 status = IXGBE_ERR_EEPROM; 713 goto out; 714 } 715 716 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 717 IXGBE_EEPROM_READ_REG_START; 718 719 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 720 status = ixgbe_poll_eeprom_eerd_done(hw); 721 722 if (status == IXGBE_SUCCESS) { 723 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 724 IXGBE_EEPROM_READ_REG_DATA); 725 } else { 726 DEBUGOUT("Eeprom read timed out\n"); 727 } 728 729 out: 730 return (status); 731 } 732 733 /* 734 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 735 * @hw: pointer to hardware structure 736 * 737 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 738 */ 739 static s32 740 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 741 { 742 u32 i; 743 u32 reg; 744 s32 status = IXGBE_ERR_EEPROM; 745 746 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 747 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 748 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 749 status = IXGBE_SUCCESS; 750 break; 751 } 752 usec_delay(5); 753 } 754 return (status); 755 } 756 757 /* 758 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 759 * @hw: pointer to hardware structure 760 * 761 * Prepares EEPROM for access using bit-bang method. This function should 762 * be called before issuing a command to the EEPROM. 763 */ 764 static s32 765 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 766 { 767 s32 status = IXGBE_SUCCESS; 768 u32 eec; 769 u32 i; 770 771 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 772 status = IXGBE_ERR_SWFW_SYNC; 773 774 if (status == IXGBE_SUCCESS) { 775 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 776 777 /* Request EEPROM Access */ 778 eec |= IXGBE_EEC_REQ; 779 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 780 781 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 782 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 783 if (eec & IXGBE_EEC_GNT) 784 break; 785 usec_delay(5); 786 } 787 788 /* Release if grant not acquired */ 789 if (!(eec & IXGBE_EEC_GNT)) { 790 eec &= ~IXGBE_EEC_REQ; 791 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 792 DEBUGOUT("Could not acquire EEPROM grant\n"); 793 794 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 795 status = IXGBE_ERR_EEPROM; 796 } 797 } 798 799 /* Setup EEPROM for Read/Write */ 800 if (status == IXGBE_SUCCESS) { 801 /* Clear CS and SK */ 802 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 803 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 804 IXGBE_WRITE_FLUSH(hw); 805 usec_delay(1); 806 } 807 return (status); 808 } 809 810 /* 811 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 812 * @hw: pointer to hardware structure 813 * 814 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 815 */ 816 static s32 817 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 818 { 819 s32 status = IXGBE_ERR_EEPROM; 820 u32 timeout = 2000; 821 u32 i; 822 u32 swsm; 823 824 /* Get SMBI software semaphore between device drivers first */ 825 for (i = 0; i < timeout; i++) { 826 /* 827 * If the SMBI bit is 0 when we read it, then the bit will be 828 * set and we have the semaphore 829 */ 830 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 831 if (!(swsm & IXGBE_SWSM_SMBI)) { 832 status = IXGBE_SUCCESS; 833 break; 834 } 835 usec_delay(50); 836 } 837 838 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 839 if (status == IXGBE_SUCCESS) { 840 for (i = 0; i < timeout; i++) { 841 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 842 843 /* Set the SW EEPROM semaphore bit to request access */ 844 swsm |= IXGBE_SWSM_SWESMBI; 845 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 846 847 /* 848 * If we set the bit successfully then we got the 849 * semaphore. 850 */ 851 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 852 if (swsm & IXGBE_SWSM_SWESMBI) 853 break; 854 855 usec_delay(50); 856 } 857 858 /* 859 * Release semaphores and return error if SW EEPROM semaphore 860 * was not granted because we don't have access to the EEPROM 861 */ 862 if (i >= timeout) { 863 DEBUGOUT("SWESMBI Software EEPROM semaphore " 864 "not granted.\n"); 865 ixgbe_release_eeprom_semaphore(hw); 866 status = IXGBE_ERR_EEPROM; 867 } 868 } else { 869 DEBUGOUT("Software semaphore SMBI between device drivers " 870 "not granted.\n"); 871 } 872 873 return (status); 874 } 875 876 /* 877 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 878 * @hw: pointer to hardware structure 879 * 880 * This function clears hardware semaphore bits. 881 */ 882 static void 883 ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 884 { 885 u32 swsm; 886 887 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 888 889 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 890 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 891 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 892 IXGBE_WRITE_FLUSH(hw); 893 } 894 895 /* 896 * ixgbe_ready_eeprom - Polls for EEPROM ready 897 * @hw: pointer to hardware structure 898 */ 899 static s32 900 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 901 { 902 s32 status = IXGBE_SUCCESS; 903 u16 i; 904 u8 spi_stat_reg; 905 906 /* 907 * Read "Status Register" repeatedly until the LSB is cleared. The 908 * EEPROM will signal that the command has been completed by clearing 909 * bit 0 of the internal status register. If it's not cleared within 910 * 5 milliseconds, then error out. 911 */ 912 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 913 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 914 IXGBE_EEPROM_OPCODE_BITS); 915 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 916 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 917 break; 918 919 usec_delay(5); 920 ixgbe_standby_eeprom(hw); 921 }; 922 923 /* 924 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 925 * devices (and only 0-5mSec on 5V devices) 926 */ 927 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 928 DEBUGOUT("SPI EEPROM Status error\n"); 929 status = IXGBE_ERR_EEPROM; 930 } 931 932 return (status); 933 } 934 935 /* 936 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 937 * @hw: pointer to hardware structure 938 */ 939 static void 940 ixgbe_standby_eeprom(struct ixgbe_hw *hw) 941 { 942 u32 eec; 943 944 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 945 946 /* Toggle CS to flush commands */ 947 eec |= IXGBE_EEC_CS; 948 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 949 IXGBE_WRITE_FLUSH(hw); 950 usec_delay(1); 951 eec &= ~IXGBE_EEC_CS; 952 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 953 IXGBE_WRITE_FLUSH(hw); 954 usec_delay(1); 955 } 956 957 /* 958 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 959 * @hw: pointer to hardware structure 960 * @data: data to send to the EEPROM 961 * @count: number of bits to shift out 962 */ 963 static void 964 ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 965 u16 count) 966 { 967 u32 eec; 968 u32 mask; 969 u32 i; 970 971 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 972 973 /* 974 * Mask is used to shift "count" bits of "data" out to the EEPROM 975 * one bit at a time. Determine the starting bit based on count 976 */ 977 mask = 0x01 << (count - 1); 978 979 for (i = 0; i < count; i++) { 980 /* 981 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 982 * "1", and then raising and then lowering the clock (the SK 983 * bit controls the clock input to the EEPROM). A "0" is 984 * shifted out to the EEPROM by setting "DI" to "0" and then 985 * raising and then lowering the clock. 986 */ 987 if (data & mask) 988 eec |= IXGBE_EEC_DI; 989 else 990 eec &= ~IXGBE_EEC_DI; 991 992 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 993 IXGBE_WRITE_FLUSH(hw); 994 995 usec_delay(1); 996 997 ixgbe_raise_eeprom_clk(hw, &eec); 998 ixgbe_lower_eeprom_clk(hw, &eec); 999 1000 /* 1001 * Shift mask to signify next bit of data to shift in to the 1002 * EEPROM 1003 */ 1004 mask = mask >> 1; 1005 }; 1006 1007 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1008 eec &= ~IXGBE_EEC_DI; 1009 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1010 IXGBE_WRITE_FLUSH(hw); 1011 } 1012 1013 /* 1014 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1015 * @hw: pointer to hardware structure 1016 */ 1017 static u16 1018 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1019 { 1020 u32 eec; 1021 u32 i; 1022 u16 data = 0; 1023 1024 /* 1025 * In order to read a register from the EEPROM, we need to shift 1026 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1027 * the clock input to the EEPROM (setting the SK bit), and then reading 1028 * the value of the "DO" bit. During this "shifting in" process the 1029 * "DI" bit should always be clear. 1030 */ 1031 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1032 1033 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1034 1035 for (i = 0; i < count; i++) { 1036 data = data << 1; 1037 ixgbe_raise_eeprom_clk(hw, &eec); 1038 1039 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1040 1041 eec &= ~(IXGBE_EEC_DI); 1042 if (eec & IXGBE_EEC_DO) 1043 data |= 1; 1044 1045 ixgbe_lower_eeprom_clk(hw, &eec); 1046 } 1047 1048 return (data); 1049 } 1050 1051 /* 1052 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1053 * @hw: pointer to hardware structure 1054 * @eec: EEC register's current value 1055 */ 1056 static void 1057 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1058 { 1059 /* 1060 * Raise the clock input to the EEPROM 1061 * (setting the SK bit), then delay 1062 */ 1063 *eec = *eec | IXGBE_EEC_SK; 1064 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1065 IXGBE_WRITE_FLUSH(hw); 1066 usec_delay(1); 1067 } 1068 1069 /* 1070 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1071 * @hw: pointer to hardware structure 1072 * @eecd: EECD's current value 1073 */ 1074 static void 1075 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1076 { 1077 /* 1078 * Lower the clock input to the EEPROM (clearing the SK bit), then 1079 * delay 1080 */ 1081 *eec = *eec & ~IXGBE_EEC_SK; 1082 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1083 IXGBE_WRITE_FLUSH(hw); 1084 usec_delay(1); 1085 } 1086 1087 /* 1088 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1089 * @hw: pointer to hardware structure 1090 */ 1091 static void 1092 ixgbe_release_eeprom(struct ixgbe_hw *hw) 1093 { 1094 u32 eec; 1095 1096 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1097 1098 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1099 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1100 1101 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1102 IXGBE_WRITE_FLUSH(hw); 1103 1104 usec_delay(1); 1105 1106 /* Stop requesting EEPROM access */ 1107 eec &= ~IXGBE_EEC_REQ; 1108 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1109 1110 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1111 1112 /* Delay before attempt to obtain semaphore again to allow FW access */ 1113 msec_delay(hw->eeprom.semaphore_delay); 1114 } 1115 1116 /* 1117 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1118 * @hw: pointer to hardware structure 1119 */ 1120 static u16 1121 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1122 { 1123 u16 i; 1124 u16 j; 1125 u16 checksum = 0; 1126 u16 length = 0; 1127 u16 pointer = 0; 1128 u16 word = 0; 1129 1130 /* Include 0x0-0x3F in the checksum */ 1131 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1132 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1133 DEBUGOUT("EEPROM read failed\n"); 1134 break; 1135 } 1136 checksum += word; 1137 } 1138 1139 /* Include all data from pointers except for the fw pointer */ 1140 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1141 hw->eeprom.ops.read(hw, i, &pointer); 1142 1143 /* Make sure the pointer seems valid */ 1144 if (pointer != 0xFFFF && pointer != 0) { 1145 hw->eeprom.ops.read(hw, pointer, &length); 1146 1147 if (length != 0xFFFF && length != 0) { 1148 for (j = pointer+1; j <= pointer+length; j++) { 1149 hw->eeprom.ops.read(hw, j, &word); 1150 checksum += word; 1151 } 1152 } 1153 } 1154 } 1155 1156 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1157 1158 return (checksum); 1159 } 1160 1161 /* 1162 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1163 * @hw: pointer to hardware structure 1164 * @checksum_val: calculated checksum 1165 * 1166 * Performs checksum calculation and validates the EEPROM checksum. If the 1167 * caller does not need checksum_val, the value can be NULL. 1168 */ 1169 s32 1170 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1171 u16 *checksum_val) 1172 { 1173 s32 status; 1174 u16 checksum; 1175 u16 read_checksum = 0; 1176 1177 /* 1178 * Read the first word from the EEPROM. If this times out or fails, do 1179 * not continue or we could be in for a very long wait while every 1180 * EEPROM read fails 1181 */ 1182 status = hw->eeprom.ops.read(hw, 0, &checksum); 1183 1184 if (status == IXGBE_SUCCESS) { 1185 checksum = ixgbe_calc_eeprom_checksum(hw); 1186 1187 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1188 1189 /* 1190 * Verify read checksum from EEPROM is the same as 1191 * calculated checksum 1192 */ 1193 if (read_checksum != checksum) 1194 status = IXGBE_ERR_EEPROM_CHECKSUM; 1195 1196 /* If the user cares, return the calculated checksum */ 1197 if (checksum_val) 1198 *checksum_val = checksum; 1199 } else { 1200 DEBUGOUT("EEPROM read failed\n"); 1201 } 1202 1203 return (status); 1204 } 1205 1206 /* 1207 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1208 * @hw: pointer to hardware structure 1209 */ 1210 s32 1211 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1212 { 1213 s32 status; 1214 u16 checksum; 1215 1216 /* 1217 * Read the first word from the EEPROM. If this times out or fails, do 1218 * not continue or we could be in for a very long wait while every 1219 * EEPROM read fails 1220 */ 1221 status = hw->eeprom.ops.read(hw, 0, &checksum); 1222 1223 if (status == IXGBE_SUCCESS) { 1224 checksum = ixgbe_calc_eeprom_checksum(hw); 1225 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1226 checksum); 1227 } else { 1228 DEBUGOUT("EEPROM read failed\n"); 1229 } 1230 1231 return (status); 1232 } 1233 1234 /* 1235 * ixgbe_validate_mac_addr - Validate MAC address 1236 * @mac_addr: pointer to MAC address. 1237 * 1238 * Tests a MAC address to ensure it is a valid Individual Address 1239 */ 1240 s32 1241 ixgbe_validate_mac_addr(u8 *mac_addr) 1242 { 1243 s32 status = IXGBE_SUCCESS; 1244 1245 /* Make sure it is not a multicast address */ 1246 if (IXGBE_IS_MULTICAST(mac_addr)) { 1247 DEBUGOUT("MAC address is multicast\n"); 1248 status = IXGBE_ERR_INVALID_MAC_ADDR; 1249 /* Not a broadcast address */ 1250 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1251 DEBUGOUT("MAC address is broadcast\n"); 1252 status = IXGBE_ERR_INVALID_MAC_ADDR; 1253 /* Reject the zero address */ 1254 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1255 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1256 DEBUGOUT("MAC address is all zeros\n"); 1257 status = IXGBE_ERR_INVALID_MAC_ADDR; 1258 } 1259 return (status); 1260 } 1261 1262 /* 1263 * ixgbe_set_rar_generic - Set Rx address register 1264 * @hw: pointer to hardware structure 1265 * @index: Receive address register to write 1266 * @addr: Address to put into receive address register 1267 * @vmdq: VMDq "set" or "pool" index 1268 * @enable_addr: set flag that address is active 1269 * 1270 * Puts an ethernet address into a receive address register. 1271 */ 1272 s32 1273 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1274 u32 enable_addr) 1275 { 1276 u32 rar_low, rar_high; 1277 u32 rar_entries = hw->mac.num_rar_entries; 1278 1279 /* setup VMDq pool selection before this RAR gets enabled */ 1280 hw->mac.ops.set_vmdq(hw, index, vmdq); 1281 1282 /* Make sure we are using a valid rar index range */ 1283 if (index < rar_entries) { 1284 /* 1285 * HW expects these in little endian so we reverse the byte 1286 * order from network order (big endian) to little endian 1287 */ 1288 rar_low = ((u32)addr[0] | 1289 ((u32)addr[1] << 8) | 1290 ((u32)addr[2] << 16) | 1291 ((u32)addr[3] << 24)); 1292 /* 1293 * Some parts put the VMDq setting in the extra RAH bits, 1294 * so save everything except the lower 16 bits that hold part 1295 * of the address and the address valid bit. 1296 */ 1297 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1298 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1299 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1300 1301 if (enable_addr != 0) 1302 rar_high |= IXGBE_RAH_AV; 1303 1304 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1305 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1306 } else { 1307 DEBUGOUT1("RAR index %d is out of range.\n", index); 1308 } 1309 1310 return (IXGBE_SUCCESS); 1311 } 1312 1313 /* 1314 * ixgbe_clear_rar_generic - Remove Rx address register 1315 * @hw: pointer to hardware structure 1316 * @index: Receive address register to write 1317 * 1318 * Clears an ethernet address from a receive address register. 1319 */ 1320 s32 1321 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1322 { 1323 u32 rar_high; 1324 u32 rar_entries = hw->mac.num_rar_entries; 1325 1326 /* Make sure we are using a valid rar index range */ 1327 if (index < rar_entries) { 1328 /* 1329 * Some parts put the VMDq setting in the extra RAH bits, 1330 * so save everything except the lower 16 bits that hold part 1331 * of the address and the address valid bit. 1332 */ 1333 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1334 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1335 1336 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1337 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1338 } else { 1339 DEBUGOUT1("RAR index %d is out of range.\n", index); 1340 } 1341 1342 /* clear VMDq pool/queue selection for this RAR */ 1343 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1344 1345 return (IXGBE_SUCCESS); 1346 } 1347 1348 /* 1349 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1350 * @hw: pointer to hardware structure 1351 * 1352 * Places the MAC address in receive address register 0 and clears the rest 1353 * of the receive address registers. Clears the multicast table. Assumes 1354 * the receiver is in reset when the routine is called. 1355 */ 1356 s32 1357 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1358 { 1359 u32 i; 1360 u32 rar_entries = hw->mac.num_rar_entries; 1361 1362 /* 1363 * If the current mac address is valid, assume it is a software override 1364 * to the permanent address. 1365 * Otherwise, use the permanent address from the eeprom. 1366 */ 1367 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1368 IXGBE_ERR_INVALID_MAC_ADDR) { 1369 /* Get the MAC address from the RAR0 for later reference */ 1370 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1371 1372 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1373 hw->mac.addr[0], hw->mac.addr[1], 1374 hw->mac.addr[2]); 1375 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1376 hw->mac.addr[4], hw->mac.addr[5]); 1377 } else { 1378 /* Setup the receive address. */ 1379 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1380 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1381 hw->mac.addr[0], hw->mac.addr[1], 1382 hw->mac.addr[2]); 1383 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1384 hw->mac.addr[4], hw->mac.addr[5]); 1385 1386 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1387 } 1388 hw->addr_ctrl.overflow_promisc = 0; 1389 1390 hw->addr_ctrl.rar_used_count = 1; 1391 1392 /* Zero out the other receive addresses. */ 1393 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1394 for (i = 1; i < rar_entries; i++) { 1395 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1396 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1397 } 1398 1399 /* Clear the MTA */ 1400 hw->addr_ctrl.mta_in_use = 0; 1401 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1402 1403 DEBUGOUT(" Clearing MTA\n"); 1404 for (i = 0; i < hw->mac.mcft_size; i++) 1405 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1406 1407 (void) ixgbe_init_uta_tables(hw); 1408 1409 return (IXGBE_SUCCESS); 1410 } 1411 1412 1413 /* 1414 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1415 * @hw: pointer to hardware structure 1416 * @addr: new address 1417 * 1418 * Adds it to unused receive address register or goes into promiscuous mode. 1419 */ 1420 void 1421 ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1422 { 1423 u32 rar_entries = hw->mac.num_rar_entries; 1424 u32 rar; 1425 1426 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1427 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1428 1429 /* 1430 * Place this address in the RAR if there is room, 1431 * else put the controller into promiscuous mode 1432 */ 1433 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1434 rar = hw->addr_ctrl.rar_used_count; 1435 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1436 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1437 hw->addr_ctrl.rar_used_count++; 1438 } else { 1439 hw->addr_ctrl.overflow_promisc++; 1440 } 1441 1442 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1443 } 1444 1445 /* 1446 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1447 * @hw: pointer to hardware structure 1448 * @addr_list: the list of new addresses 1449 * @addr_count: number of addresses 1450 * @next: iterator function to walk the address list 1451 * 1452 * The given list replaces any existing list. Clears the secondary addrs from 1453 * receive address registers. Uses unused receive address registers for the 1454 * first secondary addresses, and falls back to promiscuous mode as needed. 1455 * 1456 * Drivers using secondary unicast addresses must set user_set_promisc when 1457 * manually putting the device into promiscuous mode. 1458 */ 1459 s32 1460 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1461 u32 addr_count, ixgbe_mc_addr_itr next) 1462 { 1463 u8 *addr; 1464 u32 i; 1465 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1466 u32 uc_addr_in_use; 1467 u32 fctrl; 1468 u32 vmdq; 1469 1470 /* 1471 * Clear accounting of old secondary address list, 1472 * don't count RAR[0] 1473 */ 1474 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1475 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1476 hw->addr_ctrl.overflow_promisc = 0; 1477 1478 /* Zero out the other receive addresses */ 1479 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1480 for (i = 1; i <= uc_addr_in_use; i++) { 1481 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1482 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1483 } 1484 1485 /* Add the new addresses */ 1486 for (i = 0; i < addr_count; i++) { 1487 DEBUGOUT(" Adding the secondary addresses:\n"); 1488 addr = next(hw, &addr_list, &vmdq); 1489 ixgbe_add_uc_addr(hw, addr, vmdq); 1490 } 1491 1492 if (hw->addr_ctrl.overflow_promisc) { 1493 /* enable promisc if not already in overflow or set by user */ 1494 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1495 DEBUGOUT(" Entering address overflow promisc mode\n"); 1496 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1497 fctrl |= IXGBE_FCTRL_UPE; 1498 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1499 } 1500 } else { 1501 /* only disable if set by overflow, not by user */ 1502 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1503 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1504 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1505 fctrl &= ~IXGBE_FCTRL_UPE; 1506 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1507 } 1508 } 1509 1510 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1511 return (IXGBE_SUCCESS); 1512 } 1513 1514 /* 1515 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1516 * @hw: pointer to hardware structure 1517 * @mc_addr: the multicast address 1518 * 1519 * Extracts the 12 bits, from a multicast address, to determine which 1520 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1521 * incoming rx multicast addresses, to determine the bit-vector to check in 1522 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1523 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1524 * to mc_filter_type. 1525 */ 1526 static s32 1527 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1528 { 1529 u32 vector = 0; 1530 1531 switch (hw->mac.mc_filter_type) { 1532 case 0: /* use bits [47:36] of the address */ 1533 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1534 break; 1535 case 1: /* use bits [46:35] of the address */ 1536 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1537 break; 1538 case 2: /* use bits [45:34] of the address */ 1539 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1540 break; 1541 case 3: /* use bits [43:32] of the address */ 1542 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1543 break; 1544 default: /* Invalid mc_filter_type */ 1545 DEBUGOUT("MC filter type param set incorrectly\n"); 1546 ASSERT(0); 1547 break; 1548 } 1549 1550 /* vector can only be 12-bits or boundary will be exceeded */ 1551 vector &= 0xFFF; 1552 return (vector); 1553 } 1554 1555 /* 1556 * ixgbe_set_mta - Set bit-vector in multicast table 1557 * @hw: pointer to hardware structure 1558 * @hash_value: Multicast address hash value 1559 * 1560 * Sets the bit-vector in the multicast table. 1561 */ 1562 void 1563 ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1564 { 1565 u32 vector; 1566 u32 vector_bit; 1567 u32 vector_reg; 1568 u32 mta_reg; 1569 1570 hw->addr_ctrl.mta_in_use++; 1571 1572 vector = ixgbe_mta_vector(hw, mc_addr); 1573 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1574 1575 /* 1576 * The MTA is a register array of 128 32-bit registers. It is treated 1577 * like an array of 4096 bits. We want to set bit 1578 * BitArray[vector_value]. So we figure out what register the bit is 1579 * in, read it, OR in the new bit, then write back the new value. The 1580 * register is determined by the upper 7 bits of the vector value and 1581 * the bit within that register are determined by the lower 5 bits of 1582 * the value. 1583 */ 1584 vector_reg = (vector >> 5) & 0x7F; 1585 vector_bit = vector & 0x1F; 1586 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1587 mta_reg |= (1 << vector_bit); 1588 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1589 } 1590 1591 /* 1592 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1593 * @hw: pointer to hardware structure 1594 * @mc_addr_list: the list of new multicast addresses 1595 * @mc_addr_count: number of addresses 1596 * @next: iterator function to walk the multicast address list 1597 * 1598 * The given list replaces any existing list. Clears the MC addrs from receive 1599 * address registers and the multicast table. Uses unused receive address 1600 * registers for the first multicast addresses, and hashes the rest into the 1601 * multicast table. 1602 */ 1603 s32 1604 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1605 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1606 { 1607 u32 i; 1608 u32 vmdq; 1609 1610 /* 1611 * Set the new number of MC addresses that we are being requested to 1612 * use. 1613 */ 1614 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1615 hw->addr_ctrl.mta_in_use = 0; 1616 1617 /* Clear the MTA */ 1618 DEBUGOUT(" Clearing MTA\n"); 1619 for (i = 0; i < hw->mac.mcft_size; i++) 1620 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1621 1622 /* Add the new addresses */ 1623 for (i = 0; i < mc_addr_count; i++) { 1624 DEBUGOUT(" Adding the multicast addresses:\n"); 1625 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1626 } 1627 1628 /* Enable mta */ 1629 if (hw->addr_ctrl.mta_in_use > 0) 1630 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1631 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1632 1633 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1634 return (IXGBE_SUCCESS); 1635 } 1636 1637 /* 1638 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1639 * @hw: pointer to hardware structure 1640 * 1641 * Enables multicast address in RAR and the use of the multicast hash table. 1642 */ 1643 s32 1644 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1645 { 1646 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1647 1648 if (a->mta_in_use > 0) 1649 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1650 hw->mac.mc_filter_type); 1651 1652 return (IXGBE_SUCCESS); 1653 } 1654 1655 /* 1656 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1657 * @hw: pointer to hardware structure 1658 * 1659 * Disables multicast address in RAR and the use of the multicast hash table. 1660 */ 1661 s32 1662 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1663 { 1664 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1665 1666 if (a->mta_in_use > 0) 1667 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1668 1669 return (IXGBE_SUCCESS); 1670 } 1671 1672 /* 1673 * ixgbe_fc_enable_generic - Enable flow control 1674 * @hw: pointer to hardware structure 1675 * @packetbuf_num: packet buffer number (0-7) 1676 * 1677 * Enable flow control according to the current settings. 1678 */ 1679 s32 1680 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1681 { 1682 s32 ret_val = IXGBE_SUCCESS; 1683 u32 mflcn_reg, fccfg_reg; 1684 u32 reg; 1685 u32 rx_pba_size; 1686 1687 DEBUGFUNC("ixgbe_fc_enable_generic"); 1688 1689 /* Negotiate the fc mode to use */ 1690 ret_val = ixgbe_fc_autoneg(hw); 1691 if (ret_val) 1692 goto out; 1693 1694 /* Disable any previous flow control settings */ 1695 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1696 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1697 1698 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1699 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1700 1701 /* 1702 * The possible values of fc.current_mode are: 1703 * 0: Flow control is completely disabled 1704 * 1: Rx flow control is enabled (we can receive pause frames, 1705 * but not send pause frames). 1706 * 2: Tx flow control is enabled (we can send pause frames but 1707 * we do not support receiving pause frames). 1708 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1709 * other: Invalid. 1710 */ 1711 switch (hw->fc.current_mode) { 1712 case ixgbe_fc_none: 1713 /* 1714 * Flow control is disabled by software override or autoneg. 1715 * The code below will actually disable it in the HW. 1716 */ 1717 break; 1718 case ixgbe_fc_rx_pause: 1719 /* 1720 * Rx Flow control is enabled and Tx Flow control is 1721 * disabled by software override. Since there really 1722 * isn't a way to advertise that we are capable of RX 1723 * Pause ONLY, we will advertise that we support both 1724 * symmetric and asymmetric Rx PAUSE. Later, we will 1725 * disable the adapter's ability to send PAUSE frames. 1726 */ 1727 mflcn_reg |= IXGBE_MFLCN_RFCE; 1728 break; 1729 case ixgbe_fc_tx_pause: 1730 /* 1731 * Tx Flow control is enabled, and Rx Flow control is 1732 * disabled by software override. 1733 */ 1734 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1735 break; 1736 case ixgbe_fc_full: 1737 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1738 mflcn_reg |= IXGBE_MFLCN_RFCE; 1739 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1740 break; 1741 default: 1742 DEBUGOUT("Flow control param set incorrectly\n"); 1743 ret_val = -IXGBE_ERR_CONFIG; 1744 goto out; 1745 } 1746 1747 /* Set 802.3x based flow control settings. */ 1748 mflcn_reg |= IXGBE_MFLCN_DPF; 1749 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1750 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1751 1752 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1753 /* Thresholds are different for link flow control when in DCB mode */ 1754 if (reg & IXGBE_MTQC_RT_ENA) { 1755 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1756 1757 /* Always disable XON for LFC when in DCB mode */ 1758 reg = (rx_pba_size >> 5) & 0xFFE0; 1759 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1760 1761 reg = (rx_pba_size >> 2) & 0xFFE0; 1762 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1763 reg |= IXGBE_FCRTH_FCEN; 1764 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1765 } else { 1766 /* 1767 * Set up and enable Rx high/low water mark thresholds, 1768 * enable XON. 1769 */ 1770 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1771 if (hw->fc.send_xon) { 1772 IXGBE_WRITE_REG(hw, 1773 IXGBE_FCRTL_82599(packetbuf_num), 1774 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 1775 } else { 1776 IXGBE_WRITE_REG(hw, 1777 IXGBE_FCRTL_82599(packetbuf_num), 1778 hw->fc.low_water); 1779 } 1780 1781 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1782 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1783 } 1784 } 1785 1786 /* Configure pause time (2 TCs per register) */ 1787 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1788 if ((packetbuf_num & 1) == 0) 1789 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1790 else 1791 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1792 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1793 1794 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1795 1796 out: 1797 return (ret_val); 1798 } 1799 1800 /* 1801 * ixgbe_fc_autoneg - Configure flow control 1802 * @hw: pointer to hardware structure 1803 * 1804 * Compares our advertised flow control capabilities to those advertised by 1805 * our link partner, and determines the proper flow control mode to use. 1806 */ 1807 s32 1808 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1809 { 1810 s32 ret_val = IXGBE_SUCCESS; 1811 ixgbe_link_speed speed; 1812 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1813 bool link_up; 1814 1815 DEBUGFUNC("ixgbe_fc_autoneg"); 1816 1817 /* 1818 * AN should have completed when the cable was plugged in. 1819 * Look for reasons to bail out. Bail out if: 1820 * - FC autoneg is disabled, or if 1821 * - we don't have multispeed fiber, or if 1822 * - we're not running at 1G, or if 1823 * - link is not up, or if 1824 * - link is up but AN did not complete, or if 1825 * - link is up and AN completed but timed out 1826 * 1827 * Since we're being called from an LSC, link is already know to be up. 1828 * So use link_up_wait_to_complete=false. 1829 */ 1830 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1831 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1832 1833 if (hw->fc.disable_fc_autoneg || 1834 !hw->phy.multispeed_fiber || 1835 (speed != IXGBE_LINK_SPEED_1GB_FULL) || 1836 !link_up || 1837 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1838 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1839 hw->fc.fc_was_autonegged = false; 1840 hw->fc.current_mode = hw->fc.requested_mode; 1841 DEBUGOUT("Autoneg FC was skipped.\n"); 1842 goto out; 1843 } 1844 1845 /* 1846 * Read the AN advertisement and LP ability registers and resolve 1847 * local flow control settings accordingly 1848 */ 1849 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1850 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1851 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1852 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1853 /* 1854 * Now we need to check if the user selected Rx ONLY 1855 * of pause frames. In this case, we had to advertise 1856 * FULL flow control because we could not advertise RX 1857 * ONLY. Hence, we must now check to see if we need to 1858 * turn OFF the TRANSMISSION of PAUSE frames. 1859 */ 1860 if (hw->fc.requested_mode == ixgbe_fc_full) { 1861 hw->fc.current_mode = ixgbe_fc_full; 1862 DEBUGOUT("Flow Control = FULL.\n"); 1863 } else { 1864 hw->fc.current_mode = ixgbe_fc_rx_pause; 1865 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1866 } 1867 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1868 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1869 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1870 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1871 hw->fc.current_mode = ixgbe_fc_tx_pause; 1872 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1873 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1874 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1875 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1876 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1877 hw->fc.current_mode = ixgbe_fc_rx_pause; 1878 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1879 } else { 1880 hw->fc.current_mode = ixgbe_fc_none; 1881 DEBUGOUT("Flow Control = NONE.\n"); 1882 } 1883 1884 /* Record that current_mode is the result of a successful autoneg */ 1885 hw->fc.fc_was_autonegged = true; 1886 1887 out: 1888 return (ret_val); 1889 } 1890 1891 /* 1892 * ixgbe_setup_fc - Set up flow control 1893 * @hw: pointer to hardware structure 1894 * 1895 * Called at init time to set up flow control. 1896 */ 1897 s32 1898 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 1899 { 1900 s32 ret_val = IXGBE_SUCCESS; 1901 u32 reg; 1902 1903 /* Validate the packetbuf configuration */ 1904 if (packetbuf_num < 0 || packetbuf_num > 7) { 1905 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 1906 " 0-7\n", packetbuf_num); 1907 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1908 goto out; 1909 } 1910 1911 /* 1912 * Validate the water mark configuration. Zero water marks are invalid 1913 * because it causes the controller to just blast out fc packets. 1914 */ 1915 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 1916 DEBUGOUT("Invalid water mark configuration\n"); 1917 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1918 goto out; 1919 } 1920 1921 /* 1922 * Validate the requested mode. Strict IEEE mode does not allow 1923 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 1924 */ 1925 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 1926 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 1927 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1928 goto out; 1929 } 1930 1931 /* 1932 * 10gig parts do not have a word in the EEPROM to determine the 1933 * default flow control setting, so we explicitly set it to full. 1934 */ 1935 if (hw->fc.requested_mode == ixgbe_fc_default) 1936 hw->fc.requested_mode = ixgbe_fc_full; 1937 1938 /* 1939 * Set up the 1G flow control advertisement registers so the HW will be 1940 * able to do fc autoneg once the cable is plugged in. If we end up 1941 * using 10g instead, this is harmless. 1942 */ 1943 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1944 1945 /* 1946 * The possible values of fc.requested_mode are: 1947 * 0: Flow control is completely disabled 1948 * 1: Rx flow control is enabled (we can receive pause frames, 1949 * but not send pause frames). 1950 * 2: Tx flow control is enabled (we can send pause frames but 1951 * we do not support receiving pause frames). 1952 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1953 * other: Invalid. 1954 */ 1955 switch (hw->fc.requested_mode) { 1956 case ixgbe_fc_none: 1957 /* Flow control completely disabled by software override. */ 1958 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1959 break; 1960 case ixgbe_fc_rx_pause: 1961 /* 1962 * Rx Flow control is enabled and Tx Flow control is 1963 * disabled by software override. Since there really 1964 * isn't a way to advertise that we are capable of RX 1965 * Pause ONLY, we will advertise that we support both 1966 * symmetric and asymmetric Rx PAUSE. Later, we will 1967 * disable the adapter's ability to send PAUSE frames. 1968 */ 1969 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1970 break; 1971 case ixgbe_fc_tx_pause: 1972 /* 1973 * Tx Flow control is enabled, and Rx Flow control is 1974 * disabled by software override. 1975 */ 1976 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 1977 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 1978 break; 1979 case ixgbe_fc_full: 1980 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1981 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1982 break; 1983 default: 1984 DEBUGOUT("Flow control param set incorrectly\n"); 1985 ret_val = -IXGBE_ERR_CONFIG; 1986 goto out; 1987 } 1988 1989 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 1990 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 1991 1992 /* Enable and restart autoneg to inform the link partner */ 1993 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 1994 1995 /* Disable AN timeout */ 1996 if (hw->fc.strict_ieee) 1997 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 1998 1999 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2000 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2001 2002 out: 2003 return (ret_val); 2004 } 2005 2006 /* 2007 * ixgbe_disable_pcie_master - Disable PCI-express master access 2008 * @hw: pointer to hardware structure 2009 * 2010 * Disables PCI-Express master access and verifies there are no pending 2011 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2012 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2013 * is returned signifying master requests disabled. 2014 */ 2015 s32 2016 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2017 { 2018 u32 i; 2019 u32 reg_val; 2020 u32 number_of_queues; 2021 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2022 2023 /* Disable the receive unit by stopping each queue */ 2024 number_of_queues = hw->mac.max_rx_queues; 2025 for (i = 0; i < number_of_queues; i++) { 2026 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2027 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2028 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2029 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2030 } 2031 } 2032 2033 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2034 reg_val |= IXGBE_CTRL_GIO_DIS; 2035 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2036 2037 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2038 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 2039 status = IXGBE_SUCCESS; 2040 break; 2041 } 2042 usec_delay(100); 2043 } 2044 2045 return (status); 2046 } 2047 2048 /* 2049 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2050 * @hw: pointer to hardware structure 2051 * @mask: Mask to specify which semaphore to acquire 2052 * 2053 * Acquires the SWFW semaphore thought the GSSR register for the specified 2054 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2055 */ 2056 s32 2057 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2058 { 2059 u32 gssr; 2060 u32 swmask = mask; 2061 u32 fwmask = mask << 5; 2062 s32 timeout = 200; 2063 2064 while (timeout) { 2065 /* 2066 * SW EEPROM semaphore bit is used for access to all 2067 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2068 */ 2069 if (ixgbe_get_eeprom_semaphore(hw)) 2070 return (-IXGBE_ERR_SWFW_SYNC); 2071 2072 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2073 if (!(gssr & (fwmask | swmask))) 2074 break; 2075 2076 /* 2077 * Firmware currently using resource (fwmask) or other software 2078 * thread currently using resource (swmask) 2079 */ 2080 ixgbe_release_eeprom_semaphore(hw); 2081 msec_delay(5); 2082 timeout--; 2083 } 2084 2085 if (!timeout) { 2086 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2087 return (-IXGBE_ERR_SWFW_SYNC); 2088 } 2089 2090 gssr |= swmask; 2091 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2092 2093 ixgbe_release_eeprom_semaphore(hw); 2094 return (IXGBE_SUCCESS); 2095 } 2096 2097 /* 2098 * ixgbe_release_swfw_sync - Release SWFW semaphore 2099 * @hw: pointer to hardware structure 2100 * @mask: Mask to specify which semaphore to release 2101 * 2102 * Releases the SWFW semaphore thought the GSSR register for the specified 2103 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2104 */ 2105 void 2106 ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2107 { 2108 u32 gssr; 2109 u32 swmask = mask; 2110 2111 (void) ixgbe_get_eeprom_semaphore(hw); 2112 2113 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2114 gssr &= ~swmask; 2115 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2116 2117 ixgbe_release_eeprom_semaphore(hw); 2118 } 2119 2120 /* 2121 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2122 * @hw: pointer to hardware structure 2123 * @regval: register value to write to RXCTRL 2124 * 2125 * Enables the Rx DMA unit 2126 */ 2127 s32 2128 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2129 { 2130 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2131 2132 return (IXGBE_SUCCESS); 2133 } 2134 2135 /* 2136 * ixgbe_blink_led_start_generic - Blink LED based on index. 2137 * @hw: pointer to hardware structure 2138 * @index: led number to blink 2139 */ 2140 s32 2141 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2142 { 2143 ixgbe_link_speed speed = 0; 2144 bool link_up = 0; 2145 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2146 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2147 2148 /* 2149 * Link must be up to auto-blink the LEDs; 2150 * Force it if link is down. 2151 */ 2152 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2153 2154 if (!link_up) { 2155 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2156 autoc_reg |= IXGBE_AUTOC_FLU; 2157 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2158 msec_delay(10); 2159 } 2160 2161 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2162 led_reg |= IXGBE_LED_BLINK(index); 2163 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2164 IXGBE_WRITE_FLUSH(hw); 2165 2166 return (IXGBE_SUCCESS); 2167 } 2168 2169 /* 2170 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2171 * @hw: pointer to hardware structure 2172 * @index: led number to stop blinking 2173 */ 2174 s32 2175 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2176 { 2177 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2178 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2179 2180 autoc_reg &= ~IXGBE_AUTOC_FLU; 2181 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2182 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2183 2184 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2185 led_reg &= ~IXGBE_LED_BLINK(index); 2186 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2187 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2188 IXGBE_WRITE_FLUSH(hw); 2189 2190 return (IXGBE_SUCCESS); 2191 } 2192