1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 /* IntelVersion: 1.159 v2008-03-04 */ 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #include "ixgbe_common.h" 34 #include "ixgbe_api.h" 35 36 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 43 u16 count); 44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 48 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 49 50 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); 51 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); 52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 53 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); 54 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 55 56 /* 57 * ixgbe_init_ops_generic - Inits function ptrs 58 * @hw: pointer to the hardware structure 59 * 60 * Initialize the function pointers. 61 */ 62 s32 63 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 64 { 65 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 66 struct ixgbe_mac_info *mac = &hw->mac; 67 68 /* EEPROM */ 69 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 70 eeprom->ops.read = &ixgbe_read_eeprom_generic; 71 eeprom->ops.write = &ixgbe_write_eeprom_generic; 72 eeprom->ops.validate_checksum = 73 &ixgbe_validate_eeprom_checksum_generic; 74 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 75 76 /* MAC */ 77 mac->ops.init_hw = &ixgbe_init_hw_generic; 78 mac->ops.reset_hw = NULL; 79 mac->ops.start_hw = &ixgbe_start_hw_generic; 80 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 81 mac->ops.get_media_type = NULL; 82 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 83 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 84 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 85 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic; 86 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic; 87 88 /* LEDs */ 89 mac->ops.led_on = &ixgbe_led_on_generic; 90 mac->ops.led_off = &ixgbe_led_off_generic; 91 mac->ops.blink_led_start = NULL; 92 mac->ops.blink_led_stop = NULL; 93 94 /* RAR, Multicast, VLAN */ 95 mac->ops.set_rar = &ixgbe_set_rar_generic; 96 mac->ops.set_vmdq = NULL; 97 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 98 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 99 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 100 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 101 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 102 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 103 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 104 105 /* Flow Control */ 106 mac->ops.setup_fc = NULL; 107 108 /* Link */ 109 mac->ops.get_link_capabilities = NULL; 110 mac->ops.setup_link = NULL; 111 mac->ops.setup_link_speed = NULL; 112 mac->ops.check_link = NULL; 113 114 return (IXGBE_SUCCESS); 115 } 116 117 /* 118 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 119 * @hw: pointer to hardware structure 120 * 121 * Starts the hardware by filling the bus info structure and media type, clears 122 * all on chip counters, initializes receive address registers, multicast 123 * table, VLAN filter table, calls routine to set up link and flow control 124 * settings, and leaves transmit and receive units disabled and uninitialized 125 */ 126 s32 127 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 128 { 129 u32 ctrl_ext; 130 131 /* Set the media type */ 132 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 133 134 /* Set bus info */ 135 hw->mac.ops.get_bus_info(hw); 136 137 /* Identify the PHY */ 138 hw->phy.ops.identify(hw); 139 140 /* 141 * Store MAC address from RAR0, clear receive address registers, and 142 * clear the multicast table 143 */ 144 hw->mac.ops.init_rx_addrs(hw); 145 146 /* Clear the VLAN filter table */ 147 hw->mac.ops.clear_vfta(hw); 148 149 /* Set up link */ 150 hw->mac.ops.setup_link(hw); 151 152 /* Clear statistics registers */ 153 hw->mac.ops.clear_hw_cntrs(hw); 154 155 /* Set No Snoop Disable */ 156 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 157 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 158 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 159 IXGBE_WRITE_FLUSH(hw); 160 161 /* Clear adapter stopped flag */ 162 hw->adapter_stopped = FALSE; 163 164 return (IXGBE_SUCCESS); 165 } 166 167 /* 168 * ixgbe_init_hw_generic - Generic hardware initialization 169 * @hw: pointer to hardware structure 170 * 171 * Initialize the hardware by resetting the hardware, filling the bus info 172 * structure and media type, clears all on chip counters, initializes receive 173 * address registers, multicast table, VLAN filter table, calls routine to set 174 * up link and flow control settings, and leaves transmit and receive units 175 * disabled and uninitialized 176 */ 177 s32 178 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 179 { 180 /* Reset the hardware */ 181 hw->mac.ops.reset_hw(hw); 182 183 /* Start the HW */ 184 hw->mac.ops.start_hw(hw); 185 186 return (IXGBE_SUCCESS); 187 } 188 189 /* 190 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 191 * @hw: pointer to hardware structure 192 * 193 * Clears all hardware statistics counters by reading them from the hardware 194 * Statistics counters are clear on read. 195 */ 196 s32 197 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 198 { 199 u16 i = 0; 200 201 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 202 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 203 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 204 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 205 for (i = 0; i < 8; i++) 206 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 207 208 (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 209 (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 210 (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 211 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 212 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 213 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 214 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 215 216 for (i = 0; i < 8; i++) { 217 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 218 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 219 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 220 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 221 } 222 223 (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 224 (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 225 (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 226 (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 227 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 228 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 229 (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 230 (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 231 (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 232 (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 233 (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 234 (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 235 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 236 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 237 for (i = 0; i < 8; i++) 238 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 239 (void) IXGBE_READ_REG(hw, IXGBE_RUC); 240 (void) IXGBE_READ_REG(hw, IXGBE_RFC); 241 (void) IXGBE_READ_REG(hw, IXGBE_ROC); 242 (void) IXGBE_READ_REG(hw, IXGBE_RJC); 243 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 244 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 245 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 246 (void) IXGBE_READ_REG(hw, IXGBE_TORL); 247 (void) IXGBE_READ_REG(hw, IXGBE_TORH); 248 (void) IXGBE_READ_REG(hw, IXGBE_TPR); 249 (void) IXGBE_READ_REG(hw, IXGBE_TPT); 250 (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 251 (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 252 (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 253 (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 254 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 255 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 256 (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 257 (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 258 for (i = 0; i < 16; i++) { 259 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 260 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 261 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 262 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 263 } 264 265 return (IXGBE_SUCCESS); 266 } 267 268 /* 269 * ixgbe_read_pba_num - Reads part number from EEPROM 270 * @hw: pointer to hardware structure 271 * @pba_num: stores the part number from the EEPROM 272 * 273 * Reads the part number from the EEPROM. 274 */ 275 s32 276 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 277 { 278 s32 ret_val; 279 u16 data; 280 281 DEBUGFUNC("ixgbe_read_pba_num_generic"); 282 283 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 284 if (ret_val) { 285 DEBUGOUT("NVM Read Error\n"); 286 return (ret_val); 287 } 288 *pba_num = (u32)(data << 16); 289 290 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 291 if (ret_val) { 292 DEBUGOUT("NVM Read Error\n"); 293 return (ret_val); 294 } 295 *pba_num |= data; 296 297 return (IXGBE_SUCCESS); 298 } 299 300 /* 301 * ixgbe_get_mac_addr_generic - Generic get MAC address 302 * @hw: pointer to hardware structure 303 * @mac_addr: Adapter MAC address 304 * 305 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 306 * A reset of the adapter must be performed prior to calling this function 307 * in order for the MAC address to have been loaded from the EEPROM into RAR0 308 */ 309 s32 310 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 311 { 312 u32 rar_high; 313 u32 rar_low; 314 u16 i; 315 316 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 317 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 318 319 for (i = 0; i < 4; i++) 320 mac_addr[i] = (u8)(rar_low >> (i*8)); 321 322 for (i = 0; i < 2; i++) 323 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 324 325 return (IXGBE_SUCCESS); 326 } 327 328 /* 329 * ixgbe_get_bus_info_generic - Generic set PCI bus info 330 * @hw: pointer to hardware structure 331 * 332 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 333 */ 334 s32 335 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 336 { 337 u16 link_status; 338 339 hw->bus.type = ixgbe_bus_type_pci_express; 340 341 /* Get the negotiated link width and speed from PCI config space */ 342 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 343 344 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 345 case IXGBE_PCI_LINK_WIDTH_1: 346 hw->bus.width = ixgbe_bus_width_pcie_x1; 347 break; 348 case IXGBE_PCI_LINK_WIDTH_2: 349 hw->bus.width = ixgbe_bus_width_pcie_x2; 350 break; 351 case IXGBE_PCI_LINK_WIDTH_4: 352 hw->bus.width = ixgbe_bus_width_pcie_x4; 353 break; 354 case IXGBE_PCI_LINK_WIDTH_8: 355 hw->bus.width = ixgbe_bus_width_pcie_x8; 356 break; 357 default: 358 hw->bus.width = ixgbe_bus_width_unknown; 359 break; 360 } 361 362 switch (link_status & IXGBE_PCI_LINK_SPEED) { 363 case IXGBE_PCI_LINK_SPEED_2500: 364 hw->bus.speed = ixgbe_bus_speed_2500; 365 break; 366 case IXGBE_PCI_LINK_SPEED_5000: 367 hw->bus.speed = ixgbe_bus_speed_5000; 368 break; 369 default: 370 hw->bus.speed = ixgbe_bus_speed_unknown; 371 break; 372 } 373 374 return (IXGBE_SUCCESS); 375 } 376 377 /* 378 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 379 * @hw: pointer to hardware structure 380 * 381 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 382 * disables transmit and receive units. The adapter_stopped flag is used by 383 * the shared code and drivers to determine if the adapter is in a stopped 384 * state and should not touch the hardware. 385 */ 386 s32 387 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 388 { 389 u32 number_of_queues; 390 u32 reg_val; 391 u16 i; 392 393 /* 394 * Set the adapter_stopped flag so other driver functions stop touching 395 * the hardware 396 */ 397 hw->adapter_stopped = TRUE; 398 399 /* Disable the receive unit */ 400 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 401 reg_val &= ~(IXGBE_RXCTRL_RXEN); 402 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 403 IXGBE_WRITE_FLUSH(hw); 404 msec_delay(2); 405 406 /* Clear interrupt mask to stop from interrupts being generated */ 407 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 408 409 /* Clear any pending interrupts */ 410 (void) IXGBE_READ_REG(hw, IXGBE_EICR); 411 412 /* Disable the transmit unit. Each queue must be disabled. */ 413 number_of_queues = hw->mac.max_tx_queues; 414 for (i = 0; i < number_of_queues; i++) { 415 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 416 if (reg_val & IXGBE_TXDCTL_ENABLE) { 417 reg_val &= ~IXGBE_TXDCTL_ENABLE; 418 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 419 } 420 } 421 422 /* 423 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 424 * access and verify no pending requests 425 */ 426 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 427 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 428 } 429 430 return (IXGBE_SUCCESS); 431 } 432 433 /* 434 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 435 * @hw: pointer to hardware structure 436 * @index: led number to turn on 437 */ 438 s32 439 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 440 { 441 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 442 443 /* To turn on the LED, set mode to ON. */ 444 led_reg &= ~IXGBE_LED_MODE_MASK(index); 445 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 446 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 447 IXGBE_WRITE_FLUSH(hw); 448 449 return (IXGBE_SUCCESS); 450 } 451 452 /* 453 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 454 * @hw: pointer to hardware structure 455 * @index: led number to turn off 456 */ 457 s32 458 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 459 { 460 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 461 462 /* To turn off the LED, set mode to OFF. */ 463 led_reg &= ~IXGBE_LED_MODE_MASK(index); 464 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 465 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 466 IXGBE_WRITE_FLUSH(hw); 467 468 return (IXGBE_SUCCESS); 469 } 470 471 /* 472 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 473 * @hw: pointer to hardware structure 474 * 475 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 476 * ixgbe_hw struct in order to set up EEPROM access. 477 */ 478 s32 479 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 480 { 481 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 482 u32 eec; 483 u16 eeprom_size; 484 485 if (eeprom->type == ixgbe_eeprom_uninitialized) { 486 eeprom->type = ixgbe_eeprom_none; 487 488 /* 489 * Check for EEPROM present first. 490 * If not present leave as none 491 */ 492 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 493 if (eec & IXGBE_EEC_PRES) { 494 eeprom->type = ixgbe_eeprom_spi; 495 496 /* 497 * SPI EEPROM is assumed here. This code would need to 498 * change if a future EEPROM is not SPI. 499 */ 500 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 501 IXGBE_EEC_SIZE_SHIFT); 502 eeprom->word_size = 1 << (eeprom_size + 503 IXGBE_EEPROM_WORD_SIZE_SHIFT); 504 } 505 506 if (eec & IXGBE_EEC_ADDR_SIZE) 507 eeprom->address_bits = 16; 508 else 509 eeprom->address_bits = 8; 510 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 511 "%d\n", eeprom->type, eeprom->word_size, 512 eeprom->address_bits); 513 } 514 515 return (IXGBE_SUCCESS); 516 } 517 518 /* 519 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 520 * @hw: pointer to hardware structure 521 * @offset: offset within the EEPROM to be written to 522 * @data: 16 bit word to be written to the EEPROM 523 * 524 * If ixgbe_eeprom_update_checksum is not called after this function, the 525 * EEPROM will most likely contain an invalid checksum. 526 */ 527 s32 528 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 529 { 530 s32 status; 531 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 532 533 hw->eeprom.ops.init_params(hw); 534 535 if (offset >= hw->eeprom.word_size) { 536 status = IXGBE_ERR_EEPROM; 537 goto out; 538 } 539 540 /* Prepare the EEPROM for writing */ 541 status = ixgbe_acquire_eeprom(hw); 542 543 if (status == IXGBE_SUCCESS) { 544 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 545 ixgbe_release_eeprom(hw); 546 status = IXGBE_ERR_EEPROM; 547 } 548 } 549 550 if (status == IXGBE_SUCCESS) { 551 ixgbe_standby_eeprom(hw); 552 553 /* Send the WRITE ENABLE command (8 bit opcode ) */ 554 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 555 IXGBE_EEPROM_OPCODE_BITS); 556 557 ixgbe_standby_eeprom(hw); 558 559 /* 560 * Some SPI eeproms use the 8th address bit embedded in the 561 * opcode 562 */ 563 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 564 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 565 566 /* Send the Write command (8-bit opcode + addr) */ 567 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 568 IXGBE_EEPROM_OPCODE_BITS); 569 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 570 hw->eeprom.address_bits); 571 572 /* Send the data */ 573 data = (data >> 8) | (data << 8); 574 ixgbe_shift_out_eeprom_bits(hw, data, 16); 575 ixgbe_standby_eeprom(hw); 576 577 msec_delay(10); 578 579 /* Done with writing - release the EEPROM */ 580 ixgbe_release_eeprom(hw); 581 } 582 583 out: 584 return (status); 585 } 586 587 /* 588 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 589 * @hw: pointer to hardware structure 590 * @offset: offset within the EEPROM to be read 591 * @data: read 16 bit value from EEPROM 592 * 593 * Reads 16 bit value from EEPROM through bit-bang method 594 */ 595 s32 596 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 597 u16 *data) 598 { 599 s32 status; 600 u16 word_in; 601 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 602 603 hw->eeprom.ops.init_params(hw); 604 605 if (offset >= hw->eeprom.word_size) { 606 status = IXGBE_ERR_EEPROM; 607 goto out; 608 } 609 610 /* Prepare the EEPROM for reading */ 611 status = ixgbe_acquire_eeprom(hw); 612 613 if (status == IXGBE_SUCCESS) { 614 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 615 ixgbe_release_eeprom(hw); 616 status = IXGBE_ERR_EEPROM; 617 } 618 } 619 620 if (status == IXGBE_SUCCESS) { 621 ixgbe_standby_eeprom(hw); 622 623 /* 624 * Some SPI eeproms use the 8th address bit embedded in the 625 * opcode 626 */ 627 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 628 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 629 630 /* Send the READ command (opcode + addr) */ 631 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 632 IXGBE_EEPROM_OPCODE_BITS); 633 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 634 hw->eeprom.address_bits); 635 636 /* Read the data. */ 637 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 638 *data = (word_in >> 8) | (word_in << 8); 639 640 /* End this read operation */ 641 ixgbe_release_eeprom(hw); 642 } 643 644 out: 645 return (status); 646 } 647 648 /* 649 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 650 * @hw: pointer to hardware structure 651 * @offset: offset of word in the EEPROM to read 652 * @data: word read from the EEPROM 653 * 654 * Reads a 16 bit word from the EEPROM using the EERD register. 655 */ 656 s32 657 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 658 { 659 u32 eerd; 660 s32 status; 661 662 hw->eeprom.ops.init_params(hw); 663 664 if (offset >= hw->eeprom.word_size) { 665 status = IXGBE_ERR_EEPROM; 666 goto out; 667 } 668 669 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 670 IXGBE_EEPROM_READ_REG_START; 671 672 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 673 status = ixgbe_poll_eeprom_eerd_done(hw); 674 675 if (status == IXGBE_SUCCESS) 676 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 677 IXGBE_EEPROM_READ_REG_DATA); 678 else 679 DEBUGOUT("Eeprom read timed out\n"); 680 681 out: 682 return (status); 683 } 684 685 /* 686 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 687 * @hw: pointer to hardware structure 688 * 689 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 690 */ 691 static s32 692 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 693 { 694 u32 i; 695 u32 reg; 696 s32 status = IXGBE_ERR_EEPROM; 697 698 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 699 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 700 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 701 status = IXGBE_SUCCESS; 702 break; 703 } 704 usec_delay(5); 705 } 706 return (status); 707 } 708 709 /* 710 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 711 * @hw: pointer to hardware structure 712 * 713 * Prepares EEPROM for access using bit-bang method. This function should 714 * be called before issuing a command to the EEPROM. 715 */ 716 static s32 717 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 718 { 719 s32 status = IXGBE_SUCCESS; 720 u32 eec; 721 u32 i; 722 723 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 724 status = IXGBE_ERR_SWFW_SYNC; 725 726 if (status == IXGBE_SUCCESS) { 727 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 728 729 /* Request EEPROM Access */ 730 eec |= IXGBE_EEC_REQ; 731 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 732 733 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 734 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 735 if (eec & IXGBE_EEC_GNT) 736 break; 737 usec_delay(5); 738 } 739 740 /* Release if grant not acquired */ 741 if (!(eec & IXGBE_EEC_GNT)) { 742 eec &= ~IXGBE_EEC_REQ; 743 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 744 DEBUGOUT("Could not acquire EEPROM grant\n"); 745 746 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 747 status = IXGBE_ERR_EEPROM; 748 } 749 } 750 751 /* Setup EEPROM for Read/Write */ 752 if (status == IXGBE_SUCCESS) { 753 /* Clear CS and SK */ 754 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 755 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 756 IXGBE_WRITE_FLUSH(hw); 757 usec_delay(1); 758 } 759 return (status); 760 } 761 762 /* 763 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 764 * @hw: pointer to hardware structure 765 * 766 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 767 */ 768 static s32 769 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 770 { 771 s32 status = IXGBE_ERR_EEPROM; 772 u32 timeout; 773 u32 i; 774 u32 swsm; 775 776 /* Set timeout value based on size of EEPROM */ 777 timeout = hw->eeprom.word_size + 1; 778 779 /* Get SMBI software semaphore between device drivers first */ 780 for (i = 0; i < timeout; i++) { 781 /* 782 * If the SMBI bit is 0 when we read it, then the bit will be 783 * set and we have the semaphore 784 */ 785 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 786 if (!(swsm & IXGBE_SWSM_SMBI)) { 787 status = IXGBE_SUCCESS; 788 break; 789 } 790 msec_delay(1); 791 } 792 793 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 794 if (status == IXGBE_SUCCESS) { 795 for (i = 0; i < timeout; i++) { 796 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 797 798 /* Set the SW EEPROM semaphore bit to request access */ 799 swsm |= IXGBE_SWSM_SWESMBI; 800 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 801 802 /* 803 * If we set the bit successfully then we got the 804 * semaphore. 805 */ 806 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 807 if (swsm & IXGBE_SWSM_SWESMBI) 808 break; 809 810 usec_delay(50); 811 } 812 813 /* 814 * Release semaphores and return error if SW EEPROM semaphore 815 * was not granted because we don't have access to the EEPROM 816 */ 817 if (i >= timeout) { 818 DEBUGOUT("Driver can't access the Eeprom - Semaphore " 819 "not granted.\n"); 820 ixgbe_release_eeprom_semaphore(hw); 821 status = IXGBE_ERR_EEPROM; 822 } 823 } 824 825 return (status); 826 } 827 828 /* 829 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 830 * @hw: pointer to hardware structure 831 * 832 * This function clears hardware semaphore bits. 833 */ 834 static void 835 ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 836 { 837 u32 swsm; 838 839 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 840 841 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 842 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 843 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 844 IXGBE_WRITE_FLUSH(hw); 845 } 846 847 /* 848 * ixgbe_ready_eeprom - Polls for EEPROM ready 849 * @hw: pointer to hardware structure 850 */ 851 static s32 852 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 853 { 854 s32 status = IXGBE_SUCCESS; 855 u16 i; 856 u8 spi_stat_reg; 857 858 /* 859 * Read "Status Register" repeatedly until the LSB is cleared. The 860 * EEPROM will signal that the command has been completed by clearing 861 * bit 0 of the internal status register. If it's not cleared within 862 * 5 milliseconds, then error out. 863 */ 864 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 865 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 866 IXGBE_EEPROM_OPCODE_BITS); 867 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 868 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 869 break; 870 871 usec_delay(5); 872 ixgbe_standby_eeprom(hw); 873 }; 874 875 /* 876 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 877 * devices (and only 0-5mSec on 5V devices) 878 */ 879 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 880 DEBUGOUT("SPI EEPROM Status error\n"); 881 status = IXGBE_ERR_EEPROM; 882 } 883 884 return (status); 885 } 886 887 /* 888 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 889 * @hw: pointer to hardware structure 890 */ 891 static void 892 ixgbe_standby_eeprom(struct ixgbe_hw *hw) 893 { 894 u32 eec; 895 896 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 897 898 /* Toggle CS to flush commands */ 899 eec |= IXGBE_EEC_CS; 900 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 901 IXGBE_WRITE_FLUSH(hw); 902 usec_delay(1); 903 eec &= ~IXGBE_EEC_CS; 904 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 905 IXGBE_WRITE_FLUSH(hw); 906 usec_delay(1); 907 } 908 909 /* 910 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 911 * @hw: pointer to hardware structure 912 * @data: data to send to the EEPROM 913 * @count: number of bits to shift out 914 */ 915 static void 916 ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 917 u16 count) 918 { 919 u32 eec; 920 u32 mask; 921 u32 i; 922 923 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 924 925 /* 926 * Mask is used to shift "count" bits of "data" out to the EEPROM 927 * one bit at a time. Determine the starting bit based on count 928 */ 929 mask = 0x01 << (count - 1); 930 931 for (i = 0; i < count; i++) { 932 /* 933 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 934 * "1", and then raising and then lowering the clock (the SK 935 * bit controls the clock input to the EEPROM). A "0" is 936 * shifted out to the EEPROM by setting "DI" to "0" and then 937 * raising and then lowering the clock. 938 */ 939 if (data & mask) 940 eec |= IXGBE_EEC_DI; 941 else 942 eec &= ~IXGBE_EEC_DI; 943 944 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 945 IXGBE_WRITE_FLUSH(hw); 946 947 usec_delay(1); 948 949 ixgbe_raise_eeprom_clk(hw, &eec); 950 ixgbe_lower_eeprom_clk(hw, &eec); 951 952 /* 953 * Shift mask to signify next bit of data to shift in to the 954 * EEPROM 955 */ 956 mask = mask >> 1; 957 }; 958 959 /* We leave the "DI" bit set to "0" when we leave this routine. */ 960 eec &= ~IXGBE_EEC_DI; 961 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 962 IXGBE_WRITE_FLUSH(hw); 963 } 964 965 /* 966 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 967 * @hw: pointer to hardware structure 968 */ 969 static u16 970 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 971 { 972 u32 eec; 973 u32 i; 974 u16 data = 0; 975 976 /* 977 * In order to read a register from the EEPROM, we need to shift 978 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 979 * the clock input to the EEPROM (setting the SK bit), and then reading 980 * the value of the "DO" bit. During this "shifting in" process the 981 * "DI" bit should always be clear. 982 */ 983 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 984 985 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 986 987 for (i = 0; i < count; i++) { 988 data = data << 1; 989 ixgbe_raise_eeprom_clk(hw, &eec); 990 991 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 992 993 eec &= ~(IXGBE_EEC_DI); 994 if (eec & IXGBE_EEC_DO) 995 data |= 1; 996 997 ixgbe_lower_eeprom_clk(hw, &eec); 998 } 999 1000 return (data); 1001 } 1002 1003 /* 1004 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1005 * @hw: pointer to hardware structure 1006 * @eec: EEC register's current value 1007 */ 1008 static void 1009 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1010 { 1011 /* 1012 * Raise the clock input to the EEPROM 1013 * (setting the SK bit), then delay 1014 */ 1015 *eec = *eec | IXGBE_EEC_SK; 1016 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1017 IXGBE_WRITE_FLUSH(hw); 1018 usec_delay(1); 1019 } 1020 1021 /* 1022 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1023 * @hw: pointer to hardware structure 1024 * @eecd: EECD's current value 1025 */ 1026 static void 1027 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1028 { 1029 /* 1030 * Lower the clock input to the EEPROM (clearing the SK bit), then 1031 * delay 1032 */ 1033 *eec = *eec & ~IXGBE_EEC_SK; 1034 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1035 IXGBE_WRITE_FLUSH(hw); 1036 usec_delay(1); 1037 } 1038 1039 /* 1040 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1041 * @hw: pointer to hardware structure 1042 */ 1043 static void 1044 ixgbe_release_eeprom(struct ixgbe_hw *hw) 1045 { 1046 u32 eec; 1047 1048 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1049 1050 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1051 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1052 1053 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1054 IXGBE_WRITE_FLUSH(hw); 1055 1056 usec_delay(1); 1057 1058 /* Stop requesting EEPROM access */ 1059 eec &= ~IXGBE_EEC_REQ; 1060 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1061 1062 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1063 } 1064 1065 /* 1066 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1067 * @hw: pointer to hardware structure 1068 */ 1069 static u16 1070 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1071 { 1072 u16 i; 1073 u16 j; 1074 u16 checksum = 0; 1075 u16 length = 0; 1076 u16 pointer = 0; 1077 u16 word = 0; 1078 1079 /* Include 0x0-0x3F in the checksum */ 1080 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1081 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1082 DEBUGOUT("EEPROM read failed\n"); 1083 break; 1084 } 1085 checksum += word; 1086 } 1087 1088 /* Include all data from pointers except for the fw pointer */ 1089 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1090 hw->eeprom.ops.read(hw, i, &pointer); 1091 1092 /* Make sure the pointer seems valid */ 1093 if (pointer != 0xFFFF && pointer != 0) { 1094 hw->eeprom.ops.read(hw, pointer, &length); 1095 1096 if (length != 0xFFFF && length != 0) { 1097 for (j = pointer+1; j <= pointer+length; j++) { 1098 hw->eeprom.ops.read(hw, j, &word); 1099 checksum += word; 1100 } 1101 } 1102 } 1103 } 1104 1105 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1106 1107 return (checksum); 1108 } 1109 1110 /* 1111 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1112 * @hw: pointer to hardware structure 1113 * @checksum_val: calculated checksum 1114 * 1115 * Performs checksum calculation and validates the EEPROM checksum. If the 1116 * caller does not need checksum_val, the value can be NULL. 1117 */ 1118 s32 1119 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1120 u16 *checksum_val) 1121 { 1122 s32 status; 1123 u16 checksum; 1124 u16 read_checksum = 0; 1125 1126 /* 1127 * Read the first word from the EEPROM. If this times out or fails, do 1128 * not continue or we could be in for a very long wait while every 1129 * EEPROM read fails 1130 */ 1131 status = hw->eeprom.ops.read(hw, 0, &checksum); 1132 1133 if (status == IXGBE_SUCCESS) { 1134 checksum = ixgbe_calc_eeprom_checksum(hw); 1135 1136 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1137 1138 /* 1139 * Verify read checksum from EEPROM is the same as 1140 * calculated checksum 1141 */ 1142 if (read_checksum != checksum) 1143 status = IXGBE_ERR_EEPROM_CHECKSUM; 1144 1145 /* If the user cares, return the calculated checksum */ 1146 if (checksum_val) 1147 *checksum_val = checksum; 1148 } else { 1149 DEBUGOUT("EEPROM read failed\n"); 1150 } 1151 1152 return (status); 1153 } 1154 1155 /* 1156 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1157 * @hw: pointer to hardware structure 1158 */ 1159 s32 1160 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1161 { 1162 s32 status; 1163 u16 checksum; 1164 1165 /* 1166 * Read the first word from the EEPROM. If this times out or fails, do 1167 * not continue or we could be in for a very long wait while every 1168 * EEPROM read fails 1169 */ 1170 status = hw->eeprom.ops.read(hw, 0, &checksum); 1171 1172 if (status == IXGBE_SUCCESS) { 1173 checksum = ixgbe_calc_eeprom_checksum(hw); 1174 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1175 checksum); 1176 } else { 1177 DEBUGOUT("EEPROM read failed\n"); 1178 } 1179 1180 return (status); 1181 } 1182 1183 /* 1184 * ixgbe_validate_mac_addr - Validate MAC address 1185 * @mac_addr: pointer to MAC address. 1186 * 1187 * Tests a MAC address to ensure it is a valid Individual Address 1188 */ 1189 s32 1190 ixgbe_validate_mac_addr(u8 *mac_addr) 1191 { 1192 s32 status = IXGBE_SUCCESS; 1193 1194 /* Make sure it is not a multicast address */ 1195 if (IXGBE_IS_MULTICAST(mac_addr)) { 1196 DEBUGOUT("MAC address is multicast\n"); 1197 status = IXGBE_ERR_INVALID_MAC_ADDR; 1198 /* Not a broadcast address */ 1199 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1200 DEBUGOUT("MAC address is broadcast\n"); 1201 status = IXGBE_ERR_INVALID_MAC_ADDR; 1202 /* Reject the zero address */ 1203 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1204 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1205 DEBUGOUT("MAC address is all zeros\n"); 1206 status = IXGBE_ERR_INVALID_MAC_ADDR; 1207 } 1208 return (status); 1209 } 1210 1211 /* 1212 * ixgbe_set_rar_generic - Set Rx address register 1213 * @hw: pointer to hardware structure 1214 * @index: Receive address register to write 1215 * @addr: Address to put into receive address register 1216 * @vmdq: VMDq "set" or "pool" index 1217 * @enable_addr: set flag that address is active 1218 * 1219 * Puts an ethernet address into a receive address register. 1220 */ 1221 s32 1222 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1223 u32 enable_addr) 1224 { 1225 u32 rar_low, rar_high; 1226 u32 rar_entries = hw->mac.num_rar_entries; 1227 1228 /* setup VMDq pool selection before this RAR gets enabled */ 1229 hw->mac.ops.set_vmdq(hw, index, vmdq); 1230 1231 /* Make sure we are using a valid rar index range */ 1232 if (index < rar_entries) { 1233 /* 1234 * HW expects these in little endian so we reverse the byte 1235 * order from network order (big endian) to little endian 1236 */ 1237 rar_low = ((u32)addr[0] | 1238 ((u32)addr[1] << 8) | 1239 ((u32)addr[2] << 16) | 1240 ((u32)addr[3] << 24)); 1241 /* 1242 * Some parts put the VMDq setting in the extra RAH bits, 1243 * so save everything except the lower 16 bits that hold part 1244 * of the address and the address valid bit. 1245 */ 1246 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1247 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1248 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1249 1250 if (enable_addr != 0) 1251 rar_high |= IXGBE_RAH_AV; 1252 1253 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1254 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1255 } else { 1256 DEBUGOUT("Current RAR index is out of range."); 1257 } 1258 1259 return (IXGBE_SUCCESS); 1260 } 1261 1262 /* 1263 * ixgbe_enable_rar - Enable Rx address register 1264 * @hw: pointer to hardware structure 1265 * @index: index into the RAR table 1266 * 1267 * Enables the select receive address register. 1268 */ 1269 static void 1270 ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) 1271 { 1272 u32 rar_high; 1273 1274 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1275 rar_high |= IXGBE_RAH_AV; 1276 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1277 } 1278 1279 /* 1280 * ixgbe_disable_rar - Disable Rx address register 1281 * @hw: pointer to hardware structure 1282 * @index: index into the RAR table 1283 * 1284 * Disables the select receive address register. 1285 */ 1286 static void 1287 ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) 1288 { 1289 u32 rar_high; 1290 1291 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1292 rar_high &= (~IXGBE_RAH_AV); 1293 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1294 } 1295 1296 /* 1297 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1298 * @hw: pointer to hardware structure 1299 * 1300 * Places the MAC address in receive address register 0 and clears the rest 1301 * of the receive address registers. Clears the multicast table. Assumes 1302 * the receiver is in reset when the routine is called. 1303 */ 1304 s32 1305 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1306 { 1307 u32 i; 1308 u32 rar_entries = hw->mac.num_rar_entries; 1309 1310 /* 1311 * If the current mac address is valid, assume it is a software override 1312 * to the permanent address. 1313 * Otherwise, use the permanent address from the eeprom. 1314 */ 1315 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1316 IXGBE_ERR_INVALID_MAC_ADDR) { 1317 /* Get the MAC address from the RAR0 for later reference */ 1318 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1319 1320 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1321 hw->mac.addr[0], hw->mac.addr[1], 1322 hw->mac.addr[2]); 1323 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1324 hw->mac.addr[4], hw->mac.addr[5]); 1325 } else { 1326 /* Setup the receive address. */ 1327 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1328 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1329 hw->mac.addr[0], hw->mac.addr[1], 1330 hw->mac.addr[2]); 1331 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1332 hw->mac.addr[4], hw->mac.addr[5]); 1333 1334 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1335 } 1336 hw->addr_ctrl.overflow_promisc = 0; 1337 1338 hw->addr_ctrl.rar_used_count = 1; 1339 1340 /* Zero out the other receive addresses. */ 1341 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1342 for (i = 1; i < rar_entries; i++) { 1343 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1344 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1345 } 1346 1347 /* Clear the MTA */ 1348 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1349 hw->addr_ctrl.mta_in_use = 0; 1350 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1351 1352 DEBUGOUT(" Clearing MTA\n"); 1353 for (i = 0; i < hw->mac.mcft_size; i++) 1354 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1355 1356 return (IXGBE_SUCCESS); 1357 } 1358 1359 /* 1360 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1361 * @hw: pointer to hardware structure 1362 * @addr: new address 1363 * 1364 * Adds it to unused receive address register or goes into promiscuous mode. 1365 */ 1366 void 1367 ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1368 { 1369 u32 rar_entries = hw->mac.num_rar_entries; 1370 u32 rar; 1371 1372 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1373 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1374 1375 /* 1376 * Place this address in the RAR if there is room, 1377 * else put the controller into promiscuous mode 1378 */ 1379 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1380 rar = hw->addr_ctrl.rar_used_count - 1381 hw->addr_ctrl.mc_addr_in_rar_count; 1382 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1383 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1384 hw->addr_ctrl.rar_used_count++; 1385 } else { 1386 hw->addr_ctrl.overflow_promisc++; 1387 } 1388 1389 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1390 } 1391 1392 /* 1393 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1394 * @hw: pointer to hardware structure 1395 * @addr_list: the list of new addresses 1396 * @addr_count: number of addresses 1397 * @next: iterator function to walk the address list 1398 * 1399 * The given list replaces any existing list. Clears the secondary addrs from 1400 * receive address registers. Uses unused receive address registers for the 1401 * first secondary addresses, and falls back to promiscuous mode as needed. 1402 * 1403 * Drivers using secondary unicast addresses must set user_set_promisc when 1404 * manually putting the device into promiscuous mode. 1405 */ 1406 s32 1407 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1408 u32 addr_count, ixgbe_mc_addr_itr next) 1409 { 1410 u8 *addr; 1411 u32 i; 1412 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1413 u32 uc_addr_in_use; 1414 u32 fctrl; 1415 u32 vmdq; 1416 1417 /* 1418 * Clear accounting of old secondary address list, 1419 * don't count RAR[0] 1420 */ 1421 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1422 hw->addr_ctrl.mc_addr_in_rar_count - 1; 1423 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1424 hw->addr_ctrl.overflow_promisc = 0; 1425 1426 /* Zero out the other receive addresses */ 1427 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1428 for (i = 1; i <= uc_addr_in_use; i++) { 1429 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1430 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1431 } 1432 1433 /* Add the new addresses */ 1434 for (i = 0; i < addr_count; i++) { 1435 DEBUGOUT(" Adding the secondary addresses:\n"); 1436 addr = next(hw, &addr_list, &vmdq); 1437 ixgbe_add_uc_addr(hw, addr, vmdq); 1438 } 1439 1440 if (hw->addr_ctrl.overflow_promisc) { 1441 /* enable promisc if not already in overflow or set by user */ 1442 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1443 DEBUGOUT(" Entering address overflow promisc mode\n"); 1444 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1445 fctrl |= IXGBE_FCTRL_UPE; 1446 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1447 } 1448 } else { 1449 /* only disable if set by overflow, not by user */ 1450 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1451 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1452 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1453 fctrl &= ~IXGBE_FCTRL_UPE; 1454 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1455 } 1456 } 1457 1458 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1459 return (IXGBE_SUCCESS); 1460 } 1461 1462 /* 1463 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1464 * @hw: pointer to hardware structure 1465 * @mc_addr: the multicast address 1466 * 1467 * Extracts the 12 bits, from a multicast address, to determine which 1468 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1469 * incoming rx multicast addresses, to determine the bit-vector to check in 1470 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1471 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1472 * to mc_filter_type. 1473 */ 1474 static s32 1475 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1476 { 1477 u32 vector = 0; 1478 1479 switch (hw->mac.mc_filter_type) { 1480 case 0: /* use bits [47:36] of the address */ 1481 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1482 break; 1483 case 1: /* use bits [46:35] of the address */ 1484 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1485 break; 1486 case 2: /* use bits [45:34] of the address */ 1487 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1488 break; 1489 case 3: /* use bits [43:32] of the address */ 1490 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1491 break; 1492 default: /* Invalid mc_filter_type */ 1493 DEBUGOUT("MC filter type param set incorrectly\n"); 1494 ASSERT(0); 1495 break; 1496 } 1497 1498 /* vector can only be 12-bits or boundary will be exceeded */ 1499 vector &= 0xFFF; 1500 return (vector); 1501 } 1502 1503 /* 1504 * ixgbe_set_mta - Set bit-vector in multicast table 1505 * @hw: pointer to hardware structure 1506 * @hash_value: Multicast address hash value 1507 * 1508 * Sets the bit-vector in the multicast table. 1509 */ 1510 void 1511 ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1512 { 1513 u32 vector; 1514 u32 vector_bit; 1515 u32 vector_reg; 1516 u32 mta_reg; 1517 1518 hw->addr_ctrl.mta_in_use++; 1519 1520 vector = ixgbe_mta_vector(hw, mc_addr); 1521 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1522 1523 /* 1524 * The MTA is a register array of 128 32-bit registers. It is treated 1525 * like an array of 4096 bits. We want to set bit 1526 * BitArray[vector_value]. So we figure out what register the bit is 1527 * in, read it, OR in the new bit, then write back the new value. The 1528 * register is determined by the upper 7 bits of the vector value and 1529 * the bit within that register are determined by the lower 5 bits of 1530 * the value. 1531 */ 1532 vector_reg = (vector >> 5) & 0x7F; 1533 vector_bit = vector & 0x1F; 1534 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1535 mta_reg |= (1 << vector_bit); 1536 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1537 } 1538 1539 /* 1540 * ixgbe_add_mc_addr - Adds a multicast address. 1541 * @hw: pointer to hardware structure 1542 * @mc_addr: new multicast address 1543 * 1544 * Adds it to unused receive address register or to the multicast table. 1545 */ 1546 void 1547 ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) 1548 { 1549 u32 rar_entries = hw->mac.num_rar_entries; 1550 u32 rar; 1551 1552 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", 1553 mc_addr[0], mc_addr[1], mc_addr[2], 1554 mc_addr[3], mc_addr[4], mc_addr[5]); 1555 1556 /* 1557 * Place this multicast address in the RAR if there is room, 1558 * else put it in the MTA 1559 */ 1560 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1561 /* use RAR from the end up for multicast */ 1562 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; 1563 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); 1564 DEBUGOUT1("Added a multicast address to RAR[%d]\n", rar); 1565 hw->addr_ctrl.rar_used_count++; 1566 hw->addr_ctrl.mc_addr_in_rar_count++; 1567 } else { 1568 ixgbe_set_mta(hw, mc_addr); 1569 } 1570 1571 DEBUGOUT("ixgbe_add_mc_addr Complete\n"); 1572 } 1573 1574 /* 1575 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1576 * @hw: pointer to hardware structure 1577 * @mc_addr_list: the list of new multicast addresses 1578 * @mc_addr_count: number of addresses 1579 * @next: iterator function to walk the multicast address list 1580 * 1581 * The given list replaces any existing list. Clears the MC addrs from receive 1582 * address registers and the multicast table. Uses unused receive address 1583 * registers for the first multicast addresses, and hashes the rest into the 1584 * multicast table. 1585 */ 1586 s32 1587 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1588 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1589 { 1590 u32 i; 1591 u32 rar_entries = hw->mac.num_rar_entries; 1592 u32 vmdq; 1593 1594 /* 1595 * Set the new number of MC addresses that we are being requested to 1596 * use. 1597 */ 1598 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1599 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; 1600 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1601 hw->addr_ctrl.mta_in_use = 0; 1602 1603 /* Zero out the other receive addresses. */ 1604 DEBUGOUT2("Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, 1605 rar_entries - 1); 1606 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { 1607 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1608 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1609 } 1610 1611 /* Clear the MTA */ 1612 DEBUGOUT(" Clearing MTA\n"); 1613 for (i = 0; i < hw->mac.mcft_size; i++) 1614 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1615 1616 /* Add the new addresses */ 1617 for (i = 0; i < mc_addr_count; i++) { 1618 DEBUGOUT(" Adding the multicast addresses:\n"); 1619 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); 1620 } 1621 1622 /* Enable mta */ 1623 if (hw->addr_ctrl.mta_in_use > 0) 1624 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1625 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1626 1627 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1628 return (IXGBE_SUCCESS); 1629 } 1630 1631 /* 1632 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1633 * @hw: pointer to hardware structure 1634 * 1635 * Enables multicast address in RAR and the use of the multicast hash table. 1636 */ 1637 s32 1638 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1639 { 1640 u32 i; 1641 u32 rar_entries = hw->mac.num_rar_entries; 1642 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1643 1644 if (a->mc_addr_in_rar_count > 0) 1645 for (i = (rar_entries - a->mc_addr_in_rar_count); 1646 i < rar_entries; i++) 1647 ixgbe_enable_rar(hw, i); 1648 1649 if (a->mta_in_use > 0) 1650 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1651 hw->mac.mc_filter_type); 1652 1653 return (IXGBE_SUCCESS); 1654 } 1655 1656 /* 1657 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1658 * @hw: pointer to hardware structure 1659 * 1660 * Disables multicast address in RAR and the use of the multicast hash table. 1661 */ 1662 s32 1663 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1664 { 1665 u32 i; 1666 u32 rar_entries = hw->mac.num_rar_entries; 1667 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1668 1669 if (a->mc_addr_in_rar_count > 0) 1670 for (i = (rar_entries - a->mc_addr_in_rar_count); 1671 i < rar_entries; i++) 1672 ixgbe_disable_rar(hw, i); 1673 1674 if (a->mta_in_use > 0) 1675 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1676 1677 return (IXGBE_SUCCESS); 1678 } 1679 1680 /* 1681 * ixgbe_clear_vfta_generic - Clear VLAN filter table 1682 * @hw: pointer to hardware structure 1683 * 1684 * Clears the VLAN filer table, and the VMDq index associated with the filter 1685 */ 1686 s32 1687 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 1688 { 1689 u32 offset; 1690 u32 vlanbyte; 1691 1692 for (offset = 0; offset < hw->mac.vft_size; offset++) 1693 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1694 1695 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1696 for (offset = 0; offset < hw->mac.vft_size; offset++) 1697 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1698 0); 1699 1700 return (IXGBE_SUCCESS); 1701 } 1702 1703 /* 1704 * ixgbe_set_vfta_generic - Set VLAN filter table 1705 * @hw: pointer to hardware structure 1706 * @vlan: VLAN id to write to VLAN filter 1707 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1708 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1709 * 1710 * Turn on/off specified VLAN in the VLAN filter table. 1711 */ 1712 s32 1713 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1714 bool vlan_on) 1715 { 1716 u32 VftaIndex; 1717 u32 BitOffset; 1718 u32 VftaReg; 1719 u32 VftaByte; 1720 1721 /* Determine 32-bit word position in array */ 1722 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1723 1724 /* Determine the location of the (VMD) queue index */ 1725 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1726 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1727 1728 /* Set the nibble for VMD queue index */ 1729 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); 1730 VftaReg &= (~(0x0F << BitOffset)); 1731 VftaReg |= (vind << BitOffset); 1732 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); 1733 1734 /* Determine the location of the bit for this VLAN id */ 1735 BitOffset = vlan & 0x1F; /* lower five bits */ 1736 1737 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); 1738 if (vlan_on) 1739 /* Turn on this VLAN id */ 1740 VftaReg |= (1 << BitOffset); 1741 else 1742 /* Turn off this VLAN id */ 1743 VftaReg &= ~(1 << BitOffset); 1744 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); 1745 1746 return (IXGBE_SUCCESS); 1747 } 1748 1749 /* 1750 * ixgbe_disable_pcie_master - Disable PCI-express master access 1751 * @hw: pointer to hardware structure 1752 * 1753 * Disables PCI-Express master access and verifies there are no pending 1754 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1755 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1756 * is returned signifying master requests disabled. 1757 */ 1758 s32 1759 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1760 { 1761 u32 ctrl; 1762 s32 i; 1763 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1764 1765 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1766 ctrl |= IXGBE_CTRL_GIO_DIS; 1767 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1768 1769 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1770 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1771 status = IXGBE_SUCCESS; 1772 break; 1773 } 1774 usec_delay(100); 1775 } 1776 1777 return (status); 1778 } 1779 1780 1781 /* 1782 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 1783 * @hw: pointer to hardware structure 1784 * @mask: Mask to specify which semaphore to acquire 1785 * 1786 * Acquires the SWFW semaphore thought the GSSR register for the specified 1787 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1788 */ 1789 s32 1790 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1791 { 1792 u32 gssr; 1793 u32 swmask = mask; 1794 u32 fwmask = mask << 5; 1795 s32 timeout = 200; 1796 1797 while (timeout) { 1798 if (ixgbe_get_eeprom_semaphore(hw)) 1799 return (-IXGBE_ERR_SWFW_SYNC); 1800 1801 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1802 if (!(gssr & (fwmask | swmask))) 1803 break; 1804 1805 /* 1806 * Firmware currently using resource (fwmask) or other software 1807 * thread currently using resource (swmask) 1808 */ 1809 ixgbe_release_eeprom_semaphore(hw); 1810 msec_delay(5); 1811 timeout--; 1812 } 1813 1814 if (!timeout) { 1815 DEBUGOUT("Driver can't access resource, GSSR timeout.\n"); 1816 return (-IXGBE_ERR_SWFW_SYNC); 1817 } 1818 1819 gssr |= swmask; 1820 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1821 1822 ixgbe_release_eeprom_semaphore(hw); 1823 return (IXGBE_SUCCESS); 1824 } 1825 1826 /* 1827 * ixgbe_release_swfw_sync - Release SWFW semaphore 1828 * @hw: pointer to hardware structure 1829 * @mask: Mask to specify which semaphore to release 1830 * 1831 * Releases the SWFW semaphore thought the GSSR register for the specified 1832 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1833 */ 1834 void 1835 ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1836 { 1837 u32 gssr; 1838 u32 swmask = mask; 1839 1840 (void) ixgbe_get_eeprom_semaphore(hw); 1841 1842 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1843 gssr &= ~swmask; 1844 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1845 1846 ixgbe_release_eeprom_semaphore(hw); 1847 } 1848 1849 /* 1850 * ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register 1851 * @hw: pointer to hardware structure 1852 * @reg: analog register to read 1853 * @val: read value 1854 * 1855 * Performs read operation to Atlas analog register specified. 1856 */ 1857 s32 1858 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val) 1859 { 1860 u32 atlas_ctl; 1861 1862 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1863 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1864 IXGBE_WRITE_FLUSH(hw); 1865 usec_delay(10); 1866 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1867 *val = (u8)atlas_ctl; 1868 1869 return (IXGBE_SUCCESS); 1870 } 1871 1872 /* 1873 * ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register 1874 * @hw: pointer to hardware structure 1875 * @reg: atlas register to write 1876 * @val: value to write 1877 * 1878 * Performs write operation to Atlas analog register specified. 1879 */ 1880 s32 1881 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val) 1882 { 1883 u32 atlas_ctl; 1884 1885 atlas_ctl = (reg << 8) | val; 1886 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1887 IXGBE_WRITE_FLUSH(hw); 1888 usec_delay(10); 1889 1890 return (IXGBE_SUCCESS); 1891 } 1892