1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at: 9 * http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When using or redistributing this file, you may do so under the 14 * License only. No other modification of this header is permitted. 15 * 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 29 */ 30 31 /* IntelVersion: 1.140 scm_061610_003709 */ 32 33 #include "ixgbe_api.h" 34 #include "ixgbe_common.h" 35 36 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 37 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 38 39 /* 40 * ixgbe_init_shared_code - Initialize the shared code 41 * @hw: pointer to hardware structure 42 * 43 * This will assign function pointers and assign the MAC type and PHY code. 44 * Does not touch the hardware. This function must be called prior to any 45 * other function in the shared code. The ixgbe_hw structure should be 46 * memset to 0 prior to calling this function. The following fields in 47 * hw structure should be filled in prior to calling this function: 48 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 49 * subsystem_vendor_id, and revision_id 50 */ 51 s32 52 ixgbe_init_shared_code(struct ixgbe_hw *hw) 53 { 54 s32 status; 55 56 DEBUGFUNC("ixgbe_init_shared_code"); 57 58 /* 59 * Set the mac type 60 */ 61 (void) ixgbe_set_mac_type(hw); 62 63 switch (hw->mac.type) { 64 case ixgbe_mac_82598EB: 65 status = ixgbe_init_ops_82598(hw); 66 break; 67 case ixgbe_mac_82599EB: 68 status = ixgbe_init_ops_82599(hw); 69 break; 70 default: 71 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 72 break; 73 } 74 75 return (status); 76 } 77 78 /* 79 * ixgbe_set_mac_type - Sets MAC type 80 * @hw: pointer to the HW structure 81 * 82 * This function sets the mac type of the adapter based on the 83 * vendor ID and device ID stored in the hw structure. 84 */ 85 s32 86 ixgbe_set_mac_type(struct ixgbe_hw *hw) 87 { 88 s32 ret_val = IXGBE_SUCCESS; 89 90 DEBUGFUNC("ixgbe_set_mac_type\n"); 91 92 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_82598: 95 case IXGBE_DEV_ID_82598_BX: 96 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 97 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 98 case IXGBE_DEV_ID_82598AT: 99 case IXGBE_DEV_ID_82598AT2: 100 case IXGBE_DEV_ID_82598EB_CX4: 101 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 102 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 103 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 104 case IXGBE_DEV_ID_82598EB_XF_LR: 105 case IXGBE_DEV_ID_82598EB_SFP_LOM: 106 hw->mac.type = ixgbe_mac_82598EB; 107 break; 108 case IXGBE_DEV_ID_82599_KX4: 109 case IXGBE_DEV_ID_82599_KX4_MEZZ: 110 case IXGBE_DEV_ID_82599_XAUI_LOM: 111 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 112 case IXGBE_DEV_ID_82599_KR: 113 case IXGBE_DEV_ID_82599_SFP: 114 case IXGBE_DEV_ID_82599_SFP_EM: 115 case IXGBE_DEV_ID_82599_CX4: 116 case IXGBE_DEV_ID_82599_T3_LOM: 117 hw->mac.type = ixgbe_mac_82599EB; 118 break; 119 default: 120 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 121 break; 122 } 123 } else { 124 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 125 } 126 127 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 128 hw->mac.type, ret_val); 129 130 return (ret_val); 131 } 132 133 /* 134 * ixgbe_init_hw - Initialize the hardware 135 * @hw: pointer to hardware structure 136 * 137 * Initialize the hardware by resetting and then starting the hardware 138 */ 139 s32 140 ixgbe_init_hw(struct ixgbe_hw *hw) 141 { 142 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 143 IXGBE_NOT_IMPLEMENTED); 144 } 145 146 /* 147 * ixgbe_reset_hw - Performs a hardware reset 148 * @hw: pointer to hardware structure 149 * 150 * Resets the hardware by resetting the transmit and receive units, masks and 151 * clears all interrupts, performs a PHY reset, and performs a MAC reset 152 */ 153 s32 154 ixgbe_reset_hw(struct ixgbe_hw *hw) 155 { 156 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 157 IXGBE_NOT_IMPLEMENTED); 158 } 159 160 /* 161 * ixgbe_start_hw - Prepares hardware for Rx/Tx 162 * @hw: pointer to hardware structure 163 * 164 * Starts the hardware by filling the bus info structure and media type, 165 * clears all on chip counters, initializes receive address registers, 166 * multicast table, VLAN filter table, calls routine to setup link and 167 * flow control settings, and leaves transmit and receive units disabled 168 * and uninitialized. 169 */ 170 s32 171 ixgbe_start_hw(struct ixgbe_hw *hw) 172 { 173 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 174 IXGBE_NOT_IMPLEMENTED); 175 } 176 177 /* 178 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 179 * which is disabled by default in ixgbe_start_hw(); 180 * 181 * @hw: pointer to hardware structure 182 * 183 * Enable relaxed ordering; 184 */ 185 void 186 ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 187 { 188 if (hw->mac.ops.enable_relaxed_ordering) 189 hw->mac.ops.enable_relaxed_ordering(hw); 190 } 191 192 /* 193 * ixgbe_clear_hw_cntrs - Clear hardware counters 194 * @hw: pointer to hardware structure 195 * 196 * Clears all hardware statistics counters by reading them from the hardware 197 * Statistics counters are clear on read. 198 */ 199 s32 200 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 201 { 202 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 203 IXGBE_NOT_IMPLEMENTED); 204 } 205 206 /* 207 * ixgbe_get_media_type - Get media type 208 * @hw: pointer to hardware structure 209 * 210 * Returns the media type (fiber, copper, backplane) 211 */ 212 enum ixgbe_media_type 213 ixgbe_get_media_type(struct ixgbe_hw *hw) 214 { 215 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 216 ixgbe_media_type_unknown); 217 } 218 219 /* 220 * ixgbe_get_mac_addr - Get MAC address 221 * @hw: pointer to hardware structure 222 * @mac_addr: Adapter MAC address 223 * 224 * Reads the adapter's MAC address from the first Receive Address Register 225 * (RAR0) A reset of the adapter must have been performed prior to calling 226 * this function in order for the MAC address to have been loaded from the 227 * EEPROM into RAR0 228 */ 229 s32 230 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 231 { 232 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 233 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 234 } 235 236 /* 237 * ixgbe_get_san_mac_addr - Get SAN MAC address 238 * @hw: pointer to hardware structure 239 * @san_mac_addr: SAN MAC address 240 * 241 * Reads the SAN MAC address from the EEPROM, if it's available. This is 242 * per-port, so set_lan_id() must be called before reading the addresses. 243 */ 244 s32 245 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 246 { 247 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 248 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 249 } 250 251 /* 252 * ixgbe_set_san_mac_addr - Write a SAN MAC address 253 * @hw: pointer to hardware structure 254 * @san_mac_addr: SAN MAC address 255 * 256 * Writes A SAN MAC address to the EEPROM. 257 */ 258 s32 259 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 260 { 261 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 262 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 263 } 264 265 /* 266 * ixgbe_get_device_caps - Get additional device capabilities 267 * @hw: pointer to hardware structure 268 * @device_caps: the EEPROM word for device capabilities 269 * 270 * Reads the extra device capabilities from the EEPROM 271 */ 272 s32 273 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 274 { 275 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 276 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 277 } 278 279 /* 280 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 281 * @hw: pointer to hardware structure 282 * @wwnn_prefix: the alternative WWNN prefix 283 * @wwpn_prefix: the alternative WWPN prefix 284 * 285 * This function will read the EEPROM from the alternative SAN MAC address 286 * block to check the support for the alternative WWNN/WWPN prefix support. 287 */ 288 s32 289 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix) 290 { 291 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 292 (hw, wwnn_prefix, wwpn_prefix), IXGBE_NOT_IMPLEMENTED); 293 } 294 295 /* 296 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 297 * @hw: pointer to hardware structure 298 * @bs: the fcoe boot status 299 * 300 * This function will read the FCOE boot status from the iSCSI FCOE block 301 */ 302 s32 303 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 304 { 305 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 306 (hw, bs), IXGBE_NOT_IMPLEMENTED); 307 } 308 309 /* 310 * ixgbe_get_bus_info - Set PCI bus info 311 * @hw: pointer to hardware structure 312 * 313 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 314 */ 315 s32 316 ixgbe_get_bus_info(struct ixgbe_hw *hw) 317 { 318 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 319 IXGBE_NOT_IMPLEMENTED); 320 } 321 322 /* 323 * ixgbe_get_num_of_tx_queues - Get Tx queues 324 * @hw: pointer to hardware structure 325 * 326 * Returns the number of transmit queues for the given adapter. 327 */ 328 u32 329 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 330 { 331 return (hw->mac.max_tx_queues); 332 } 333 334 /* 335 * ixgbe_get_num_of_rx_queues - Get Rx queues 336 * @hw: pointer to hardware structure 337 * 338 * Returns the number of receive queues for the given adapter. 339 */ 340 u32 341 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 342 { 343 return (hw->mac.max_rx_queues); 344 } 345 346 /* 347 * ixgbe_stop_adapter - Disable Rx/Tx units 348 * @hw: pointer to hardware structure 349 * 350 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 351 * disables transmit and receive units. The adapter_stopped flag is used by 352 * the shared code and drivers to determine if the adapter is in a stopped 353 * state and should not touch the hardware. 354 */ 355 s32 356 ixgbe_stop_adapter(struct ixgbe_hw *hw) 357 { 358 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 359 IXGBE_NOT_IMPLEMENTED); 360 } 361 362 /* 363 * ixgbe_read_pba_num - Reads part number from EEPROM 364 * @hw: pointer to hardware structure 365 * @pba_num: stores the part number from the EEPROM 366 * 367 * Reads the part number from the EEPROM. 368 */ 369 s32 370 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 371 { 372 return (ixgbe_read_pba_num_generic(hw, pba_num)); 373 } 374 375 /* 376 * ixgbe_identify_phy - Get PHY type 377 * @hw: pointer to hardware structure 378 * 379 * Determines the physical layer module found on the current adapter. 380 */ 381 s32 382 ixgbe_identify_phy(struct ixgbe_hw *hw) 383 { 384 s32 status = IXGBE_SUCCESS; 385 386 if (hw->phy.type == ixgbe_phy_unknown) { 387 status = ixgbe_call_func(hw, 388 hw->phy.ops.identify, 389 (hw), 390 IXGBE_NOT_IMPLEMENTED); 391 } 392 393 return (status); 394 } 395 396 /* 397 * ixgbe_reset_phy - Perform a PHY reset 398 * @hw: pointer to hardware structure 399 */ 400 s32 401 ixgbe_reset_phy(struct ixgbe_hw *hw) 402 { 403 s32 status = IXGBE_SUCCESS; 404 405 if (hw->phy.type == ixgbe_phy_unknown) { 406 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) { 407 status = IXGBE_ERR_PHY; 408 } 409 } 410 411 if (status == IXGBE_SUCCESS) { 412 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 413 IXGBE_NOT_IMPLEMENTED); 414 } 415 return (status); 416 } 417 418 /* 419 * ixgbe_get_phy_firmware_version - 420 * @hw: pointer to hardware structure 421 * @firmware_version: pointer to firmware version 422 */ 423 s32 424 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 425 { 426 s32 status = IXGBE_SUCCESS; 427 428 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 429 (hw, firmware_version), IXGBE_NOT_IMPLEMENTED); 430 return (status); 431 } 432 433 /* 434 * ixgbe_read_phy_reg - Read PHY register 435 * @hw: pointer to hardware structure 436 * @reg_addr: 32 bit address of PHY register to read 437 * @phy_data: Pointer to read data from PHY register 438 * 439 * Reads a value from a specified PHY register 440 */ 441 s32 442 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 443 u16 *phy_data) 444 { 445 if (hw->phy.id == 0) 446 (void) ixgbe_identify_phy(hw); 447 448 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 449 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 450 } 451 452 /* 453 * ixgbe_write_phy_reg - Write PHY register 454 * @hw: pointer to hardware structure 455 * @reg_addr: 32 bit PHY register to write 456 * @phy_data: Data to write to the PHY register 457 * 458 * Writes a value to specified PHY register 459 */ 460 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 461 u16 phy_data) 462 { 463 if (hw->phy.id == 0) 464 (void) ixgbe_identify_phy(hw); 465 466 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 467 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 468 } 469 470 /* 471 * ixgbe_setup_phy_link - Restart PHY autoneg 472 * @hw: pointer to hardware structure 473 * 474 * Restart autonegotiation and PHY and waits for completion. 475 */ 476 s32 477 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 478 { 479 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 480 IXGBE_NOT_IMPLEMENTED); 481 } 482 483 /* 484 * ixgbe_check_phy_link - Determine link and speed status 485 * @hw: pointer to hardware structure 486 * 487 * Reads a PHY register to determine if link is up and the current speed for 488 * the PHY. 489 */ 490 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 491 bool *link_up) 492 { 493 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 494 link_up), IXGBE_NOT_IMPLEMENTED); 495 } 496 497 /* 498 * ixgbe_setup_phy_link_speed - Set auto advertise 499 * @hw: pointer to hardware structure 500 * @speed: new link speed 501 * @autoneg: true if autonegotiation enabled 502 * 503 * Sets the auto advertised capabilities 504 */ 505 s32 506 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 507 bool autoneg, 508 bool autoneg_wait_to_complete) 509 { 510 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 511 autoneg, autoneg_wait_to_complete), 512 IXGBE_NOT_IMPLEMENTED); 513 } 514 515 /* 516 * ixgbe_check_link - Get link and speed status 517 * @hw: pointer to hardware structure 518 * 519 * Reads the links register to determine if link is up and the current speed 520 */ 521 s32 522 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 523 bool *link_up, bool link_up_wait_to_complete) 524 { 525 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 526 link_up, link_up_wait_to_complete), IXGBE_NOT_IMPLEMENTED); 527 } 528 529 /* 530 * ixgbe_disable_tx_laser - Disable Tx laser 531 * @hw: pointer to hardware structure 532 * 533 * If the driver needs to disable the laser on SFI optics. 534 */ 535 void 536 ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 537 { 538 if (hw->mac.ops.disable_tx_laser) 539 hw->mac.ops.disable_tx_laser(hw); 540 } 541 542 /* 543 * ixgbe_enable_tx_laser - Enable Tx laser 544 * @hw: pointer to hardware structure 545 * 546 * If the driver needs to enable the laser on SFI optics. 547 */ 548 void 549 ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 550 { 551 if (hw->mac.ops.enable_tx_laser) 552 hw->mac.ops.enable_tx_laser(hw); 553 } 554 555 /* 556 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 557 * @hw: pointer to hardware structure 558 * 559 * When the driver changes the link speeds that it can support then 560 * flap the tx laser to alert the link partner to start autotry 561 * process on its end. 562 */ 563 void 564 ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 565 { 566 if (hw->mac.ops.flap_tx_laser) 567 hw->mac.ops.flap_tx_laser(hw); 568 } 569 570 /* 571 * ixgbe_setup_link - Set link speed 572 * @hw: pointer to hardware structure 573 * @speed: new link speed 574 * @autoneg: true if autonegotiation enabled 575 * 576 * Configures link settings. Restarts the link. 577 * Performs autonegotiation if needed. 578 */ 579 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 580 bool autoneg, 581 bool autoneg_wait_to_complete) 582 { 583 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 584 autoneg, autoneg_wait_to_complete), 585 IXGBE_NOT_IMPLEMENTED); 586 } 587 588 /* 589 * ixgbe_get_link_capabilities - Returns link capabilities 590 * @hw: pointer to hardware structure 591 * 592 * Determines the link capabilities of the current configuration. 593 */ 594 s32 595 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 596 bool *autoneg) 597 { 598 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 599 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 600 } 601 602 /* 603 * ixgbe_led_on - Turn on LEDs 604 * @hw: pointer to hardware structure 605 * @index: led number to turn on 606 * 607 * Turns on the software controllable LEDs. 608 */ 609 s32 610 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 611 { 612 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 613 IXGBE_NOT_IMPLEMENTED); 614 } 615 616 /* 617 * ixgbe_led_off - Turn off LEDs 618 * @hw: pointer to hardware structure 619 * @index: led number to turn off 620 * 621 * Turns off the software controllable LEDs. 622 */ 623 s32 624 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 625 { 626 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 627 IXGBE_NOT_IMPLEMENTED); 628 } 629 630 /* 631 * ixgbe_blink_led_start - Blink LEDs 632 * @hw: pointer to hardware structure 633 * @index: led number to blink 634 * 635 * Blink LED based on index. 636 */ 637 s32 638 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 639 { 640 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 641 IXGBE_NOT_IMPLEMENTED); 642 } 643 644 /* 645 * ixgbe_blink_led_stop - Stop blinking LEDs 646 * @hw: pointer to hardware structure 647 * 648 * Stop blinking LED based on index. 649 */ 650 s32 651 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 652 { 653 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 654 IXGBE_NOT_IMPLEMENTED); 655 } 656 657 /* 658 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 659 * @hw: pointer to hardware structure 660 * 661 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 662 * ixgbe_hw struct in order to set up EEPROM access. 663 */ 664 s32 665 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 666 { 667 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 668 IXGBE_NOT_IMPLEMENTED); 669 } 670 671 672 /* 673 * ixgbe_write_eeprom - Write word to EEPROM 674 * @hw: pointer to hardware structure 675 * @offset: offset within the EEPROM to be written to 676 * @data: 16 bit word to be written to the EEPROM 677 * 678 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 679 * called after this function, the EEPROM will most likely contain an 680 * invalid checksum. 681 */ 682 s32 683 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 684 { 685 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 686 IXGBE_NOT_IMPLEMENTED); 687 } 688 689 /* 690 * ixgbe_read_eeprom - Read word from EEPROM 691 * @hw: pointer to hardware structure 692 * @offset: offset within the EEPROM to be read 693 * @data: read 16 bit value from EEPROM 694 * 695 * Reads 16 bit value from EEPROM 696 */ 697 s32 698 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 699 { 700 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 701 IXGBE_NOT_IMPLEMENTED); 702 } 703 704 /* 705 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 706 * @hw: pointer to hardware structure 707 * @checksum_val: calculated checksum 708 * 709 * Performs checksum calculation and validates the EEPROM checksum 710 */ 711 s32 712 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 713 { 714 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 715 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 716 } 717 718 /* 719 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 720 * @hw: pointer to hardware structure 721 */ 722 s32 723 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 724 { 725 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 726 IXGBE_NOT_IMPLEMENTED); 727 } 728 729 /* 730 * ixgbe_insert_mac_addr - Find a RAR for this mac address 731 * @hw: pointer to hardware structure 732 * @addr: Address to put into receive address register 733 * @vmdq: VMDq pool to assign 734 * 735 * Puts an ethernet address into a receive address register, or 736 * finds the rar that it is aleady in; adds to the pool list 737 */ 738 s32 739 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 740 { 741 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 742 (hw, addr, vmdq), IXGBE_NOT_IMPLEMENTED); 743 } 744 745 /* 746 * ixgbe_set_rar - Set Rx address register 747 * @hw: pointer to hardware structure 748 * @index: Receive address register to write 749 * @addr: Address to put into receive address register 750 * @vmdq: VMDq "set" 751 * @enable_addr: set flag that address is active 752 * 753 * Puts an ethernet address into a receive address register. 754 */ 755 s32 756 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 757 u32 enable_addr) 758 { 759 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 760 enable_addr), IXGBE_NOT_IMPLEMENTED); 761 } 762 763 /* 764 * ixgbe_clear_rar - Clear Rx address register 765 * @hw: pointer to hardware structure 766 * @index: Receive address register to write 767 * 768 * Puts an ethernet address into a receive address register. 769 */ 770 s32 771 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 772 { 773 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 774 IXGBE_NOT_IMPLEMENTED); 775 } 776 777 /* 778 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 779 * @hw: pointer to hardware structure 780 * @rar: receive address register index to associate with VMDq index 781 * @vmdq: VMDq set or pool index 782 */ 783 s32 784 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 785 { 786 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 787 IXGBE_NOT_IMPLEMENTED); 788 } 789 790 /* 791 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 792 * @hw: pointer to hardware structure 793 * @rar: receive address register index to disassociate with VMDq index 794 * @vmdq: VMDq set or pool index 795 */ 796 s32 797 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 798 { 799 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 800 IXGBE_NOT_IMPLEMENTED); 801 } 802 803 /* 804 * ixgbe_init_rx_addrs - Initializes receive address filters. 805 * @hw: pointer to hardware structure 806 * 807 * Places the MAC address in receive address register 0 and clears the rest 808 * of the receive address registers. Clears the multicast table. Assumes 809 * the receiver is in reset when the routine is called. 810 */ 811 s32 812 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 813 { 814 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 815 IXGBE_NOT_IMPLEMENTED); 816 } 817 818 /* 819 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 820 * @hw: pointer to hardware structure 821 */ 822 u32 823 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 824 { 825 return (hw->mac.num_rar_entries); 826 } 827 828 /* 829 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 830 * @hw: pointer to hardware structure 831 * @addr_list: the list of new multicast addresses 832 * @addr_count: number of addresses 833 * @func: iterator function to walk the multicast address list 834 * 835 * The given list replaces any existing list. Clears the secondary addrs from 836 * receive address registers. Uses unused receive address registers for the 837 * first secondary addresses, and falls back to promiscuous mode as needed. 838 */ 839 s32 840 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 841 u32 addr_count, ixgbe_mc_addr_itr func) 842 { 843 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 844 addr_list, addr_count, func), 845 IXGBE_NOT_IMPLEMENTED); 846 } 847 848 /* 849 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 850 * @hw: pointer to hardware structure 851 * @mc_addr_list: the list of new multicast addresses 852 * @mc_addr_count: number of addresses 853 * @func: iterator function to walk the multicast address list 854 * 855 * The given list replaces any existing list. Clears the MC addrs from receive 856 * address registers and the multicast table. Uses unused receive address 857 * registers for the first multicast addresses, and hashes the rest into the 858 * multicast table. 859 */ 860 s32 861 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 862 u32 mc_addr_count, ixgbe_mc_addr_itr func) 863 { 864 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 865 mc_addr_list, mc_addr_count, func), 866 IXGBE_NOT_IMPLEMENTED); 867 } 868 869 /* 870 * ixgbe_enable_mc - Enable multicast address in RAR 871 * @hw: pointer to hardware structure 872 * 873 * Enables multicast address in RAR and the use of the multicast hash table. 874 */ 875 s32 876 ixgbe_enable_mc(struct ixgbe_hw *hw) 877 { 878 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 879 IXGBE_NOT_IMPLEMENTED); 880 } 881 882 /* 883 * ixgbe_disable_mc - Disable multicast address in RAR 884 * @hw: pointer to hardware structure 885 * 886 * Disables multicast address in RAR and the use of the multicast hash table. 887 */ 888 s32 889 ixgbe_disable_mc(struct ixgbe_hw *hw) 890 { 891 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 892 IXGBE_NOT_IMPLEMENTED); 893 } 894 895 /* 896 * ixgbe_clear_vfta - Clear VLAN filter table 897 * @hw: pointer to hardware structure 898 * 899 * Clears the VLAN filer table, and the VMDq index associated with the filter 900 */ 901 s32 902 ixgbe_clear_vfta(struct ixgbe_hw *hw) 903 { 904 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 905 IXGBE_NOT_IMPLEMENTED); 906 } 907 908 /* 909 * ixgbe_set_vfta - Set VLAN filter table 910 * @hw: pointer to hardware structure 911 * @vlan: VLAN id to write to VLAN filter 912 * @vind: VMDq output index that maps queue to VLAN id in VFTA 913 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 914 * 915 * Turn on/off specified VLAN in the VLAN filter table. 916 */ 917 s32 918 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 919 { 920 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 921 vlan_on), IXGBE_NOT_IMPLEMENTED); 922 } 923 924 /* 925 * ixgbe_fc_enable - Enable flow control 926 * @hw: pointer to hardware structure 927 * @packetbuf_num: packet buffer number (0-7) 928 * 929 * Configures the flow control settings based on SW configuration. 930 */ 931 s32 932 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 933 { 934 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 935 IXGBE_NOT_IMPLEMENTED); 936 } 937 938 /* 939 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 940 * @hw: pointer to hardware structure 941 * @reg: analog register to read 942 * @val: read value 943 * 944 * Performs write operation to analog register specified. 945 */ 946 s32 947 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 948 { 949 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 950 val), IXGBE_NOT_IMPLEMENTED); 951 } 952 953 /* 954 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 955 * @hw: pointer to hardware structure 956 * @reg: analog register to write 957 * @val: value to write 958 * 959 * Performs write operation to Atlas analog register specified. 960 */ 961 s32 962 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 963 { 964 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 965 val), IXGBE_NOT_IMPLEMENTED); 966 } 967 968 /* 969 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 970 * @hw: pointer to hardware structure 971 * 972 * Initializes the Unicast Table Arrays to zero on device load. This 973 * is part of the Rx init addr execution path. 974 */ 975 s32 976 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 977 { 978 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 979 IXGBE_NOT_IMPLEMENTED); 980 } 981 982 /* 983 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 984 * @hw: pointer to hardware structure 985 * @byte_offset: byte offset to read 986 * @data: value read 987 * 988 * Performs byte read operation to SFP module's EEPROM over I2C interface. 989 */ 990 s32 991 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 992 u8 *data) 993 { 994 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 995 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 996 } 997 998 /* 999 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1000 * @hw: pointer to hardware structure 1001 * @byte_offset: byte offset to write 1002 * @data: value to write 1003 * 1004 * Performs byte write operation to SFP module's EEPROM over I2C interface 1005 * at a specified device address. 1006 */ 1007 s32 1008 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1009 u8 data) 1010 { 1011 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, 1012 (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1013 } 1014 1015 /* 1016 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1017 * @hw: pointer to hardware structure 1018 * @byte_offset: EEPROM byte offset to write 1019 * @eeprom_data: value to write 1020 * 1021 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1022 */ 1023 s32 1024 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data) 1025 { 1026 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1027 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /* 1031 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1032 * @hw: pointer to hardware structure 1033 * @byte_offset: EEPROM byte offset to read 1034 * @eeprom_data: value read 1035 * 1036 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1037 */ 1038 s32 1039 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1040 { 1041 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1042 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /* 1046 * ixgbe_get_supported_physical_layer - Returns physical layer type 1047 * @hw: pointer to hardware structure 1048 * 1049 * Determines physical layer capabilities of the current configuration. 1050 */ 1051 u32 1052 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1053 { 1054 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1055 (hw), IXGBE_NOT_IMPLEMENTED); 1056 } 1057 1058 /* 1059 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 1060 * @hw: pointer to hardware structure 1061 * @regval: bitfield to write to the Rx DMA register 1062 * 1063 * Enables the Rx DMA unit of the device. 1064 */ 1065 s32 1066 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1067 { 1068 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1069 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1070 } 1071 1072 /* 1073 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1074 * @hw: pointer to hardware structure 1075 * @mask: Mask to specify which semaphore to acquire 1076 * 1077 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1078 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1079 */ 1080 s32 1081 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1082 { 1083 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1084 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1085 } 1086 1087 /* 1088 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1089 * @hw: pointer to hardware structure 1090 * @mask: Mask to specify which semaphore to release 1091 * 1092 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1093 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1094 */ 1095 void 1096 ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1097 { 1098 if (hw->mac.ops.release_swfw_sync) 1099 hw->mac.ops.release_swfw_sync(hw, mask); 1100 } 1101