1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.120 v2-9-1-1_2009-6-10_NSW1 */ 30 31 #include "ixgbe_api.h" 32 #include "ixgbe_common.h" 33 34 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 35 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 36 37 /* 38 * ixgbe_init_shared_code - Initialize the shared code 39 * @hw: pointer to hardware structure 40 * 41 * This will assign function pointers and assign the MAC type and PHY code. 42 * Does not touch the hardware. This function must be called prior to any 43 * other function in the shared code. The ixgbe_hw structure should be 44 * memset to 0 prior to calling this function. The following fields in 45 * hw structure should be filled in prior to calling this function: 46 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 47 * subsystem_vendor_id, and revision_id 48 */ 49 s32 50 ixgbe_init_shared_code(struct ixgbe_hw *hw) 51 { 52 s32 status; 53 54 /* 55 * Set the mac type 56 */ 57 (void) ixgbe_set_mac_type(hw); 58 59 switch (hw->mac.type) { 60 case ixgbe_mac_82598EB: 61 status = ixgbe_init_ops_82598(hw); 62 break; 63 case ixgbe_mac_82599EB: 64 status = ixgbe_init_ops_82599(hw); 65 break; 66 default: 67 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 68 break; 69 } 70 71 return (status); 72 } 73 74 /* 75 * ixgbe_set_mac_type - Sets MAC type 76 * @hw: pointer to the HW structure 77 * 78 * This function sets the mac type of the adapter based on the 79 * vendor ID and device ID stored in the hw structure. 80 */ 81 s32 82 ixgbe_set_mac_type(struct ixgbe_hw *hw) 83 { 84 s32 ret_val = IXGBE_SUCCESS; 85 86 DEBUGFUNC("ixgbe_set_mac_type\n"); 87 88 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 89 switch (hw->device_id) { 90 case IXGBE_DEV_ID_82598: 91 case IXGBE_DEV_ID_82598_BX: 92 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 93 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 94 case IXGBE_DEV_ID_82598AT: 95 case IXGBE_DEV_ID_82598EB_CX4: 96 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 97 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 98 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 99 case IXGBE_DEV_ID_82598EB_XF_LR: 100 case IXGBE_DEV_ID_82598EB_SFP_LOM: 101 hw->mac.type = ixgbe_mac_82598EB; 102 break; 103 case IXGBE_DEV_ID_82599_KX4: 104 case IXGBE_DEV_ID_82599_KX4_SIK: 105 case IXGBE_DEV_ID_82599_XAUI_LOM: 106 case IXGBE_DEV_ID_82599_SFP: 107 case IXGBE_DEV_ID_82599_SPW: 108 case IXGBE_DEV_ID_82599_CX4: 109 hw->mac.type = ixgbe_mac_82599EB; 110 break; 111 default: 112 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 113 break; 114 } 115 } else { 116 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 117 } 118 119 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 120 hw->mac.type, ret_val); 121 122 return (ret_val); 123 } 124 125 /* 126 * ixgbe_init_hw - Initialize the hardware 127 * @hw: pointer to hardware structure 128 * 129 * Initialize the hardware by resetting and then starting the hardware 130 */ 131 s32 132 ixgbe_init_hw(struct ixgbe_hw *hw) 133 { 134 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 135 IXGBE_NOT_IMPLEMENTED); 136 } 137 138 /* 139 * ixgbe_reset_hw - Performs a hardware reset 140 * @hw: pointer to hardware structure 141 * 142 * Resets the hardware by resetting the transmit and receive units, masks and 143 * clears all interrupts, performs a PHY reset, and performs a MAC reset 144 */ 145 s32 146 ixgbe_reset_hw(struct ixgbe_hw *hw) 147 { 148 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 149 IXGBE_NOT_IMPLEMENTED); 150 } 151 152 /* 153 * ixgbe_start_hw - Prepares hardware for Rx/Tx 154 * @hw: pointer to hardware structure 155 * 156 * Starts the hardware by filling the bus info structure and media type, 157 * clears all on chip counters, initializes receive address registers, 158 * multicast table, VLAN filter table, calls routine to setup link and 159 * flow control settings, and leaves transmit and receive units disabled 160 * and uninitialized. 161 */ 162 s32 163 ixgbe_start_hw(struct ixgbe_hw *hw) 164 { 165 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 166 IXGBE_NOT_IMPLEMENTED); 167 } 168 169 /* 170 * ixgbe_clear_hw_cntrs - Clear hardware counters 171 * @hw: pointer to hardware structure 172 * 173 * Clears all hardware statistics counters by reading them from the hardware 174 * Statistics counters are clear on read. 175 */ 176 s32 177 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 178 { 179 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 180 IXGBE_NOT_IMPLEMENTED); 181 } 182 183 /* 184 * ixgbe_get_media_type - Get media type 185 * @hw: pointer to hardware structure 186 * 187 * Returns the media type (fiber, copper, backplane) 188 */ 189 enum ixgbe_media_type 190 ixgbe_get_media_type(struct ixgbe_hw *hw) 191 { 192 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 193 ixgbe_media_type_unknown); 194 } 195 196 /* 197 * ixgbe_get_mac_addr - Get MAC address 198 * @hw: pointer to hardware structure 199 * @mac_addr: Adapter MAC address 200 * 201 * Reads the adapter's MAC address from the first Receive Address Register 202 * (RAR0) A reset of the adapter must have been performed prior to calling 203 * this function in order for the MAC address to have been loaded from the 204 * EEPROM into RAR0 205 */ 206 s32 207 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 208 { 209 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 210 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 211 } 212 213 /* 214 * ixgbe_get_san_mac_addr - Get SAN MAC address 215 * @hw: pointer to hardware structure 216 * @san_mac_addr: SAN MAC address 217 * 218 * Reads the SAN MAC address from the EEPROM, if it's available. This is 219 * per-port, so set_lan_id() must be called before reading the addresses. 220 */ 221 s32 222 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 223 { 224 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 225 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 226 } 227 228 /* 229 * ixgbe_set_san_mac_addr - Write a SAN MAC address 230 * @hw: pointer to hardware structure 231 * @san_mac_addr: SAN MAC address 232 * 233 * Writes A SAN MAC address to the EEPROM. 234 */ 235 s32 236 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 237 { 238 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 239 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 240 } 241 242 /* 243 * ixgbe_get_device_caps - Get additional device capabilities 244 * @hw: pointer to hardware structure 245 * @device_caps: the EEPROM word for device capabilities 246 * 247 * Reads the extra device capabilities from the EEPROM 248 */ 249 s32 250 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 251 { 252 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 253 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 254 } 255 256 /* 257 * ixgbe_get_bus_info - Set PCI bus info 258 * @hw: pointer to hardware structure 259 * 260 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 261 */ 262 s32 263 ixgbe_get_bus_info(struct ixgbe_hw *hw) 264 { 265 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 266 IXGBE_NOT_IMPLEMENTED); 267 } 268 269 /* 270 * ixgbe_get_num_of_tx_queues - Get Tx queues 271 * @hw: pointer to hardware structure 272 * 273 * Returns the number of transmit queues for the given adapter. 274 */ 275 u32 276 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 277 { 278 return (hw->mac.max_tx_queues); 279 } 280 281 /* 282 * ixgbe_get_num_of_rx_queues - Get Rx queues 283 * @hw: pointer to hardware structure 284 * 285 * Returns the number of receive queues for the given adapter. 286 */ 287 u32 288 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 289 { 290 return (hw->mac.max_rx_queues); 291 } 292 293 /* 294 * ixgbe_stop_adapter - Disable Rx/Tx units 295 * @hw: pointer to hardware structure 296 * 297 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 298 * disables transmit and receive units. The adapter_stopped flag is used by 299 * the shared code and drivers to determine if the adapter is in a stopped 300 * state and should not touch the hardware. 301 */ 302 s32 303 ixgbe_stop_adapter(struct ixgbe_hw *hw) 304 { 305 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 306 IXGBE_NOT_IMPLEMENTED); 307 } 308 309 /* 310 * ixgbe_read_pba_num - Reads part number from EEPROM 311 * @hw: pointer to hardware structure 312 * @pba_num: stores the part number from the EEPROM 313 * 314 * Reads the part number from the EEPROM. 315 */ 316 s32 317 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 318 { 319 return (ixgbe_read_pba_num_generic(hw, pba_num)); 320 } 321 322 /* 323 * ixgbe_identify_phy - Get PHY type 324 * @hw: pointer to hardware structure 325 * 326 * Determines the physical layer module found on the current adapter. 327 */ 328 s32 329 ixgbe_identify_phy(struct ixgbe_hw *hw) 330 { 331 s32 status = IXGBE_SUCCESS; 332 333 if (hw->phy.type == ixgbe_phy_unknown) { 334 status = ixgbe_call_func(hw, 335 hw->phy.ops.identify, 336 (hw), 337 IXGBE_NOT_IMPLEMENTED); 338 } 339 340 return (status); 341 } 342 343 /* 344 * ixgbe_reset_phy - Perform a PHY reset 345 * @hw: pointer to hardware structure 346 */ 347 s32 348 ixgbe_reset_phy(struct ixgbe_hw *hw) 349 { 350 s32 status = IXGBE_SUCCESS; 351 352 if (hw->phy.type == ixgbe_phy_unknown) { 353 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) { 354 status = IXGBE_ERR_PHY; 355 } 356 } 357 358 if (status == IXGBE_SUCCESS) { 359 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 360 IXGBE_NOT_IMPLEMENTED); 361 } 362 return (status); 363 } 364 365 /* 366 * ixgbe_get_phy_firmware_version - 367 * @hw: pointer to hardware structure 368 * @firmware_version: pointer to firmware version 369 */ 370 s32 371 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 372 { 373 s32 status = IXGBE_SUCCESS; 374 375 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 376 (hw, firmware_version), IXGBE_NOT_IMPLEMENTED); 377 return (status); 378 } 379 380 /* 381 * ixgbe_read_phy_reg - Read PHY register 382 * @hw: pointer to hardware structure 383 * @reg_addr: 32 bit address of PHY register to read 384 * @phy_data: Pointer to read data from PHY register 385 * 386 * Reads a value from a specified PHY register 387 */ 388 s32 389 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 390 u16 *phy_data) 391 { 392 if (hw->phy.id == 0) 393 (void) ixgbe_identify_phy(hw); 394 395 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 396 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 397 } 398 399 /* 400 * ixgbe_write_phy_reg - Write PHY register 401 * @hw: pointer to hardware structure 402 * @reg_addr: 32 bit PHY register to write 403 * @phy_data: Data to write to the PHY register 404 * 405 * Writes a value to specified PHY register 406 */ 407 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 408 u16 phy_data) 409 { 410 if (hw->phy.id == 0) 411 (void) ixgbe_identify_phy(hw); 412 413 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 414 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 415 } 416 417 /* 418 * ixgbe_setup_phy_link - Restart PHY autoneg 419 * @hw: pointer to hardware structure 420 * 421 * Restart autonegotiation and PHY and waits for completion. 422 */ 423 s32 424 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 425 { 426 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 427 IXGBE_NOT_IMPLEMENTED); 428 } 429 430 /* 431 * ixgbe_check_phy_link - Determine link and speed status 432 * @hw: pointer to hardware structure 433 * 434 * Reads a PHY register to determine if link is up and the current speed for 435 * the PHY. 436 */ 437 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 438 bool *link_up) 439 { 440 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 441 link_up), IXGBE_NOT_IMPLEMENTED); 442 } 443 444 /* 445 * ixgbe_setup_phy_link_speed - Set auto advertise 446 * @hw: pointer to hardware structure 447 * @speed: new link speed 448 * @autoneg: true if autonegotiation enabled 449 * 450 * Sets the auto advertised capabilities 451 */ 452 s32 453 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 454 bool autoneg, 455 bool autoneg_wait_to_complete) 456 { 457 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 458 autoneg, autoneg_wait_to_complete), 459 IXGBE_NOT_IMPLEMENTED); 460 } 461 462 /* 463 * ixgbe_setup_link - Configure link settings 464 * @hw: pointer to hardware structure 465 * 466 * Configures link settings based on values in the ixgbe_hw struct. 467 * Restarts the link. Performs autonegotiation if needed. 468 */ 469 s32 470 ixgbe_setup_link(struct ixgbe_hw *hw) 471 { 472 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw), 473 IXGBE_NOT_IMPLEMENTED); 474 } 475 476 /* 477 * ixgbe_check_link - Get link and speed status 478 * @hw: pointer to hardware structure 479 * 480 * Reads the links register to determine if link is up and the current speed 481 */ 482 s32 483 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 484 bool *link_up, bool link_up_wait_to_complete) 485 { 486 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 487 link_up, link_up_wait_to_complete), IXGBE_NOT_IMPLEMENTED); 488 } 489 490 /* 491 * ixgbe_setup_link_speed - Set link speed 492 * @hw: pointer to hardware structure 493 * @speed: new link speed 494 * @autoneg: true if autonegotiation enabled 495 * 496 * Set the link speed and restarts the link. 497 */ 498 s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 499 bool autoneg, 500 bool autoneg_wait_to_complete) 501 { 502 return ixgbe_call_func(hw, hw->mac.ops.setup_link_speed, (hw, speed, 503 autoneg, autoneg_wait_to_complete), 504 IXGBE_NOT_IMPLEMENTED); 505 } 506 507 /* 508 * ixgbe_get_link_capabilities - Returns link capabilities 509 * @hw: pointer to hardware structure 510 * 511 * Determines the link capabilities of the current configuration. 512 */ 513 s32 514 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 515 bool *autoneg) 516 { 517 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 518 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 519 } 520 521 /* 522 * ixgbe_led_on - Turn on LEDs 523 * @hw: pointer to hardware structure 524 * @index: led number to turn on 525 * 526 * Turns on the software controllable LEDs. 527 */ 528 s32 529 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 530 { 531 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 532 IXGBE_NOT_IMPLEMENTED); 533 } 534 535 /* 536 * ixgbe_led_off - Turn off LEDs 537 * @hw: pointer to hardware structure 538 * @index: led number to turn off 539 * 540 * Turns off the software controllable LEDs. 541 */ 542 s32 543 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 544 { 545 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 546 IXGBE_NOT_IMPLEMENTED); 547 } 548 549 /* 550 * ixgbe_blink_led_start - Blink LEDs 551 * @hw: pointer to hardware structure 552 * @index: led number to blink 553 * 554 * Blink LED based on index. 555 */ 556 s32 557 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 558 { 559 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 560 IXGBE_NOT_IMPLEMENTED); 561 } 562 563 /* 564 * ixgbe_blink_led_stop - Stop blinking LEDs 565 * @hw: pointer to hardware structure 566 * 567 * Stop blinking LED based on index. 568 */ 569 s32 570 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 571 { 572 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 573 IXGBE_NOT_IMPLEMENTED); 574 } 575 576 /* 577 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 578 * @hw: pointer to hardware structure 579 * 580 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 581 * ixgbe_hw struct in order to set up EEPROM access. 582 */ 583 s32 584 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 585 { 586 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 587 IXGBE_NOT_IMPLEMENTED); 588 } 589 590 591 /* 592 * ixgbe_write_eeprom - Write word to EEPROM 593 * @hw: pointer to hardware structure 594 * @offset: offset within the EEPROM to be written to 595 * @data: 16 bit word to be written to the EEPROM 596 * 597 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 598 * called after this function, the EEPROM will most likely contain an 599 * invalid checksum. 600 */ 601 s32 602 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 603 { 604 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 605 IXGBE_NOT_IMPLEMENTED); 606 } 607 608 /* 609 * ixgbe_read_eeprom - Read word from EEPROM 610 * @hw: pointer to hardware structure 611 * @offset: offset within the EEPROM to be read 612 * @data: read 16 bit value from EEPROM 613 * 614 * Reads 16 bit value from EEPROM 615 */ 616 s32 617 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 618 { 619 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 620 IXGBE_NOT_IMPLEMENTED); 621 } 622 623 /* 624 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 625 * @hw: pointer to hardware structure 626 * @checksum_val: calculated checksum 627 * 628 * Performs checksum calculation and validates the EEPROM checksum 629 */ 630 s32 631 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 632 { 633 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 634 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 635 } 636 637 /* 638 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 639 * @hw: pointer to hardware structure 640 */ 641 s32 642 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 643 { 644 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 645 IXGBE_NOT_IMPLEMENTED); 646 } 647 648 /* 649 * ixgbe_insert_mac_addr - Find a RAR for this mac address 650 * @hw: pointer to hardware structure 651 * @addr: Address to put into receive address register 652 * @vmdq: VMDq pool to assign 653 * 654 * Puts an ethernet address into a receive address register, or 655 * finds the rar that it is aleady in; adds to the pool list 656 */ 657 s32 658 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 659 { 660 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 661 (hw, addr, vmdq), IXGBE_NOT_IMPLEMENTED); 662 } 663 664 /* 665 * ixgbe_set_rar - Set Rx address register 666 * @hw: pointer to hardware structure 667 * @index: Receive address register to write 668 * @addr: Address to put into receive address register 669 * @vmdq: VMDq "set" 670 * @enable_addr: set flag that address is active 671 * 672 * Puts an ethernet address into a receive address register. 673 */ 674 s32 675 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 676 u32 enable_addr) 677 { 678 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 679 enable_addr), IXGBE_NOT_IMPLEMENTED); 680 } 681 682 /* 683 * ixgbe_clear_rar - Clear Rx address register 684 * @hw: pointer to hardware structure 685 * @index: Receive address register to write 686 * 687 * Puts an ethernet address into a receive address register. 688 */ 689 s32 690 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 691 { 692 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 693 IXGBE_NOT_IMPLEMENTED); 694 } 695 696 /* 697 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 698 * @hw: pointer to hardware structure 699 * @rar: receive address register index to associate with VMDq index 700 * @vmdq: VMDq set or pool index 701 */ 702 s32 703 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 704 { 705 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 706 IXGBE_NOT_IMPLEMENTED); 707 } 708 709 /* 710 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 711 * @hw: pointer to hardware structure 712 * @rar: receive address register index to disassociate with VMDq index 713 * @vmdq: VMDq set or pool index 714 */ 715 s32 716 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 717 { 718 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 719 IXGBE_NOT_IMPLEMENTED); 720 } 721 722 /* 723 * ixgbe_init_rx_addrs - Initializes receive address filters. 724 * @hw: pointer to hardware structure 725 * 726 * Places the MAC address in receive address register 0 and clears the rest 727 * of the receive address registers. Clears the multicast table. Assumes 728 * the receiver is in reset when the routine is called. 729 */ 730 s32 731 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 732 { 733 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 734 IXGBE_NOT_IMPLEMENTED); 735 } 736 737 /* 738 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 739 * @hw: pointer to hardware structure 740 */ 741 u32 742 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 743 { 744 return (hw->mac.num_rar_entries); 745 } 746 747 /* 748 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 749 * @hw: pointer to hardware structure 750 * @addr_list: the list of new multicast addresses 751 * @addr_count: number of addresses 752 * @func: iterator function to walk the multicast address list 753 * 754 * The given list replaces any existing list. Clears the secondary addrs from 755 * receive address registers. Uses unused receive address registers for the 756 * first secondary addresses, and falls back to promiscuous mode as needed. 757 */ 758 s32 759 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 760 u32 addr_count, ixgbe_mc_addr_itr func) 761 { 762 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 763 addr_list, addr_count, func), 764 IXGBE_NOT_IMPLEMENTED); 765 } 766 767 /* 768 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 769 * @hw: pointer to hardware structure 770 * @mc_addr_list: the list of new multicast addresses 771 * @mc_addr_count: number of addresses 772 * @func: iterator function to walk the multicast address list 773 * 774 * The given list replaces any existing list. Clears the MC addrs from receive 775 * address registers and the multicast table. Uses unused receive address 776 * registers for the first multicast addresses, and hashes the rest into the 777 * multicast table. 778 */ 779 s32 780 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 781 u32 mc_addr_count, ixgbe_mc_addr_itr func) 782 { 783 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 784 mc_addr_list, mc_addr_count, func), 785 IXGBE_NOT_IMPLEMENTED); 786 } 787 788 /* 789 * ixgbe_enable_mc - Enable multicast address in RAR 790 * @hw: pointer to hardware structure 791 * 792 * Enables multicast address in RAR and the use of the multicast hash table. 793 */ 794 s32 795 ixgbe_enable_mc(struct ixgbe_hw *hw) 796 { 797 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 798 IXGBE_NOT_IMPLEMENTED); 799 } 800 801 /* 802 * ixgbe_disable_mc - Disable multicast address in RAR 803 * @hw: pointer to hardware structure 804 * 805 * Disables multicast address in RAR and the use of the multicast hash table. 806 */ 807 s32 808 ixgbe_disable_mc(struct ixgbe_hw *hw) 809 { 810 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 811 IXGBE_NOT_IMPLEMENTED); 812 } 813 814 /* 815 * ixgbe_clear_vfta - Clear VLAN filter table 816 * @hw: pointer to hardware structure 817 * 818 * Clears the VLAN filer table, and the VMDq index associated with the filter 819 */ 820 s32 821 ixgbe_clear_vfta(struct ixgbe_hw *hw) 822 { 823 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 824 IXGBE_NOT_IMPLEMENTED); 825 } 826 827 /* 828 * ixgbe_set_vfta - Set VLAN filter table 829 * @hw: pointer to hardware structure 830 * @vlan: VLAN id to write to VLAN filter 831 * @vind: VMDq output index that maps queue to VLAN id in VFTA 832 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 833 * 834 * Turn on/off specified VLAN in the VLAN filter table. 835 */ 836 s32 837 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 838 { 839 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 840 vlan_on), IXGBE_NOT_IMPLEMENTED); 841 } 842 843 /* 844 * ixgbe_fc_enable - Enable flow control 845 * @hw: pointer to hardware structure 846 * @packetbuf_num: packet buffer number (0-7) 847 * 848 * Configures the flow control settings based on SW configuration. 849 */ 850 s32 851 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 852 { 853 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 854 IXGBE_NOT_IMPLEMENTED); 855 } 856 857 /* 858 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 859 * @hw: pointer to hardware structure 860 * @reg: analog register to read 861 * @val: read value 862 * 863 * Performs write operation to analog register specified. 864 */ 865 s32 866 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 867 { 868 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 869 val), IXGBE_NOT_IMPLEMENTED); 870 } 871 872 /* 873 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 874 * @hw: pointer to hardware structure 875 * @reg: analog register to write 876 * @val: value to write 877 * 878 * Performs write operation to Atlas analog register specified. 879 */ 880 s32 881 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 882 { 883 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 884 val), IXGBE_NOT_IMPLEMENTED); 885 } 886 887 /* 888 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 889 * @hw: pointer to hardware structure 890 * 891 * Initializes the Unicast Table Arrays to zero on device load. This 892 * is part of the Rx init addr execution path. 893 */ 894 s32 895 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 896 { 897 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 898 IXGBE_NOT_IMPLEMENTED); 899 } 900 901 /* 902 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 903 * @hw: pointer to hardware structure 904 * @byte_offset: byte offset to read 905 * @data: value read 906 * 907 * Performs byte read operation to SFP module's EEPROM over I2C interface. 908 */ 909 s32 910 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 911 u8 *data) 912 { 913 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 914 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 915 } 916 917 /* 918 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 919 * @hw: pointer to hardware structure 920 * @byte_offset: byte offset to write 921 * @data: value to write 922 * 923 * Performs byte write operation to SFP module's EEPROM over I2C interface 924 * at a specified device address. 925 */ 926 s32 927 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 928 u8 data) 929 { 930 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, 931 (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED); 932 } 933 934 /* 935 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 936 * @hw: pointer to hardware structure 937 * @byte_offset: EEPROM byte offset to write 938 * @eeprom_data: value to write 939 * 940 * Performs byte write operation to SFP module's EEPROM over I2C interface. 941 */ 942 s32 943 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data) 944 { 945 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 946 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 947 } 948 949 /* 950 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 951 * @hw: pointer to hardware structure 952 * @byte_offset: EEPROM byte offset to read 953 * @eeprom_data: value read 954 * 955 * Performs byte read operation to SFP module's EEPROM over I2C interface. 956 */ 957 s32 958 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 959 { 960 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 961 (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED); 962 } 963 964 /* 965 * ixgbe_get_supported_physical_layer - Returns physical layer type 966 * @hw: pointer to hardware structure 967 * 968 * Determines physical layer capabilities of the current configuration. 969 */ 970 u32 971 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 972 { 973 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 974 (hw), IXGBE_NOT_IMPLEMENTED); 975 } 976 977 /* 978 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 979 * @hw: pointer to hardware structure 980 * @regval: bitfield to write to the Rx DMA register 981 * 982 * Enables the Rx DMA unit of the device. 983 */ 984 s32 985 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 986 { 987 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 988 (hw, regval), IXGBE_NOT_IMPLEMENTED); 989 } 990 991 /* 992 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 993 * @hw: pointer to hardware structure 994 * @mask: Mask to specify which semaphore to acquire 995 * 996 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 997 * function (CSR, PHY0, PHY1, EEPROM, Flash) 998 */ 999 s32 1000 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1001 { 1002 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1003 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1004 } 1005 1006 /* 1007 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1008 * @hw: pointer to hardware structure 1009 * @mask: Mask to specify which semaphore to release 1010 * 1011 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1012 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1013 */ 1014 void 1015 ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1016 { 1017 if (hw->mac.ops.release_swfw_sync) 1018 hw->mac.ops.release_swfw_sync(hw, mask); 1019 } 1020