1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 39 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 40 41 /** 42 * ixgbe_init_shared_code - Initialize the shared code 43 * @hw: pointer to hardware structure 44 * 45 * This will assign function pointers and assign the MAC type and PHY code. 46 * Does not touch the hardware. This function must be called prior to any 47 * other function in the shared code. The ixgbe_hw structure should be 48 * memset to 0 prior to calling this function. The following fields in 49 * hw structure should be filled in prior to calling this function: 50 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 51 * subsystem_vendor_id, and revision_id 52 **/ 53 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 54 { 55 s32 status; 56 57 DEBUGFUNC("ixgbe_init_shared_code"); 58 59 /* 60 * Set the mac type 61 */ 62 (void) ixgbe_set_mac_type(hw); 63 64 switch (hw->mac.type) { 65 case ixgbe_mac_82598EB: 66 status = ixgbe_init_ops_82598(hw); 67 break; 68 case ixgbe_mac_82599EB: 69 status = ixgbe_init_ops_82599(hw); 70 break; 71 default: 72 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 73 break; 74 } 75 76 return status; 77 } 78 79 /** 80 * ixgbe_set_mac_type - Sets MAC type 81 * @hw: pointer to the HW structure 82 * 83 * This function sets the mac type of the adapter based on the 84 * vendor ID and device ID stored in the hw structure. 85 **/ 86 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 87 { 88 s32 ret_val = IXGBE_SUCCESS; 89 90 DEBUGFUNC("ixgbe_set_mac_type\n"); 91 92 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_82598: 95 case IXGBE_DEV_ID_82598_BX: 96 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 97 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 98 case IXGBE_DEV_ID_82598AT: 99 case IXGBE_DEV_ID_82598AT2: 100 case IXGBE_DEV_ID_82598EB_CX4: 101 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 102 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 103 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 104 case IXGBE_DEV_ID_82598EB_XF_LR: 105 case IXGBE_DEV_ID_82598EB_SFP_LOM: 106 hw->mac.type = ixgbe_mac_82598EB; 107 break; 108 case IXGBE_DEV_ID_82599_KX4: 109 case IXGBE_DEV_ID_82599_KX4_MEZZ: 110 case IXGBE_DEV_ID_82599_XAUI_LOM: 111 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 112 case IXGBE_DEV_ID_82599_SFP: 113 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 114 case IXGBE_DEV_ID_82599_SFP_FCOE: 115 case IXGBE_DEV_ID_82599_CX4: 116 case IXGBE_DEV_ID_82599_T3_LOM: 117 hw->mac.type = ixgbe_mac_82599EB; 118 break; 119 default: 120 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 121 break; 122 } 123 } else { 124 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 125 } 126 127 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 128 hw->mac.type, ret_val); 129 return ret_val; 130 } 131 132 /** 133 * ixgbe_init_hw - Initialize the hardware 134 * @hw: pointer to hardware structure 135 * 136 * Initialize the hardware by resetting and then starting the hardware 137 **/ 138 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 139 { 140 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 141 IXGBE_NOT_IMPLEMENTED); 142 } 143 144 /** 145 * ixgbe_reset_hw - Performs a hardware reset 146 * @hw: pointer to hardware structure 147 * 148 * Resets the hardware by resetting the transmit and receive units, masks and 149 * clears all interrupts, performs a PHY reset, and performs a MAC reset 150 **/ 151 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 152 { 153 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 154 IXGBE_NOT_IMPLEMENTED); 155 } 156 157 /** 158 * ixgbe_start_hw - Prepares hardware for Rx/Tx 159 * @hw: pointer to hardware structure 160 * 161 * Starts the hardware by filling the bus info structure and media type, 162 * clears all on chip counters, initializes receive address registers, 163 * multicast table, VLAN filter table, calls routine to setup link and 164 * flow control settings, and leaves transmit and receive units disabled 165 * and uninitialized. 166 **/ 167 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 168 { 169 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 170 IXGBE_NOT_IMPLEMENTED); 171 } 172 173 /** 174 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 175 * which is disabled by default in ixgbe_start_hw(); 176 * 177 * @hw: pointer to hardware structure 178 * 179 * Enable relaxed ordering; 180 **/ 181 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 182 { 183 if (hw->mac.ops.enable_relaxed_ordering) 184 hw->mac.ops.enable_relaxed_ordering(hw); 185 } 186 187 /** 188 * ixgbe_clear_hw_cntrs - Clear hardware counters 189 * @hw: pointer to hardware structure 190 * 191 * Clears all hardware statistics counters by reading them from the hardware 192 * Statistics counters are clear on read. 193 **/ 194 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 195 { 196 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 197 IXGBE_NOT_IMPLEMENTED); 198 } 199 200 /** 201 * ixgbe_get_media_type - Get media type 202 * @hw: pointer to hardware structure 203 * 204 * Returns the media type (fiber, copper, backplane) 205 **/ 206 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 207 { 208 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 209 ixgbe_media_type_unknown); 210 } 211 212 /** 213 * ixgbe_get_mac_addr - Get MAC address 214 * @hw: pointer to hardware structure 215 * @mac_addr: Adapter MAC address 216 * 217 * Reads the adapter's MAC address from the first Receive Address Register 218 * (RAR0) A reset of the adapter must have been performed prior to calling 219 * this function in order for the MAC address to have been loaded from the 220 * EEPROM into RAR0 221 **/ 222 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 223 { 224 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 225 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 226 } 227 228 /** 229 * ixgbe_get_san_mac_addr - Get SAN MAC address 230 * @hw: pointer to hardware structure 231 * @san_mac_addr: SAN MAC address 232 * 233 * Reads the SAN MAC address from the EEPROM, if it's available. This is 234 * per-port, so set_lan_id() must be called before reading the addresses. 235 **/ 236 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 237 { 238 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 239 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 240 } 241 242 /** 243 * ixgbe_set_san_mac_addr - Write a SAN MAC address 244 * @hw: pointer to hardware structure 245 * @san_mac_addr: SAN MAC address 246 * 247 * Writes A SAN MAC address to the EEPROM. 248 **/ 249 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 250 { 251 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 252 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 253 } 254 255 /** 256 * ixgbe_get_device_caps - Get additional device capabilities 257 * @hw: pointer to hardware structure 258 * @device_caps: the EEPROM word for device capabilities 259 * 260 * Reads the extra device capabilities from the EEPROM 261 **/ 262 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 263 { 264 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 265 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 266 } 267 268 /** 269 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 270 * @hw: pointer to hardware structure 271 * @wwnn_prefix: the alternative WWNN prefix 272 * @wwpn_prefix: the alternative WWPN prefix 273 * 274 * This function will read the EEPROM from the alternative SAN MAC address 275 * block to check the support for the alternative WWNN/WWPN prefix support. 276 **/ 277 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 278 u16 *wwpn_prefix) 279 { 280 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 281 (hw, wwnn_prefix, wwpn_prefix), 282 IXGBE_NOT_IMPLEMENTED); 283 } 284 285 /** 286 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 287 * @hw: pointer to hardware structure 288 * @bs: the fcoe boot status 289 * 290 * This function will read the FCOE boot status from the iSCSI FCOE block 291 **/ 292 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 293 { 294 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 295 (hw, bs), 296 IXGBE_NOT_IMPLEMENTED); 297 } 298 299 /** 300 * ixgbe_get_bus_info - Set PCI bus info 301 * @hw: pointer to hardware structure 302 * 303 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 304 **/ 305 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 306 { 307 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 308 IXGBE_NOT_IMPLEMENTED); 309 } 310 311 /** 312 * ixgbe_get_num_of_tx_queues - Get Tx queues 313 * @hw: pointer to hardware structure 314 * 315 * Returns the number of transmit queues for the given adapter. 316 **/ 317 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 318 { 319 return hw->mac.max_tx_queues; 320 } 321 322 /** 323 * ixgbe_get_num_of_rx_queues - Get Rx queues 324 * @hw: pointer to hardware structure 325 * 326 * Returns the number of receive queues for the given adapter. 327 **/ 328 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 329 { 330 return hw->mac.max_rx_queues; 331 } 332 333 /** 334 * ixgbe_stop_adapter - Disable Rx/Tx units 335 * @hw: pointer to hardware structure 336 * 337 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 338 * disables transmit and receive units. The adapter_stopped flag is used by 339 * the shared code and drivers to determine if the adapter is in a stopped 340 * state and should not touch the hardware. 341 **/ 342 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 343 { 344 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 345 IXGBE_NOT_IMPLEMENTED); 346 } 347 348 /** 349 * ixgbe_read_pba_string - Reads part number string from EEPROM 350 * @hw: pointer to hardware structure 351 * @pba_num: stores the part number string from the EEPROM 352 * @pba_num_size: part number string buffer length 353 * 354 * Reads the part number string from the EEPROM. 355 **/ 356 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 357 { 358 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 359 } 360 361 /** 362 * ixgbe_read_pba_length - Reads part number string length from EEPROM 363 * @hw: pointer to hardware structure 364 * @pba_num_size: part number string buffer length 365 * 366 * Reads the part number length from the EEPROM. 367 * Returns expected buffer size in pba_num_size. 368 **/ 369 s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size) 370 { 371 return ixgbe_read_pba_length_generic(hw, pba_num_size); 372 } 373 374 /** 375 * ixgbe_read_pba_num - Reads part number from EEPROM 376 * @hw: pointer to hardware structure 377 * @pba_num: stores the part number from the EEPROM 378 * 379 * Reads the part number from the EEPROM. 380 **/ 381 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 382 { 383 return ixgbe_read_pba_num_generic(hw, pba_num); 384 } 385 386 /** 387 * ixgbe_identify_phy - Get PHY type 388 * @hw: pointer to hardware structure 389 * 390 * Determines the physical layer module found on the current adapter. 391 **/ 392 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 393 { 394 s32 status = IXGBE_SUCCESS; 395 396 if (hw->phy.type == ixgbe_phy_unknown) { 397 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 398 IXGBE_NOT_IMPLEMENTED); 399 } 400 401 return status; 402 } 403 404 /** 405 * ixgbe_reset_phy - Perform a PHY reset 406 * @hw: pointer to hardware structure 407 **/ 408 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 409 { 410 s32 status = IXGBE_SUCCESS; 411 412 if (hw->phy.type == ixgbe_phy_unknown) { 413 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 414 status = IXGBE_ERR_PHY; 415 } 416 417 if (status == IXGBE_SUCCESS) { 418 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 419 IXGBE_NOT_IMPLEMENTED); 420 } 421 return status; 422 } 423 424 /** 425 * ixgbe_get_phy_firmware_version - 426 * @hw: pointer to hardware structure 427 * @firmware_version: pointer to firmware version 428 **/ 429 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 430 { 431 s32 status = IXGBE_SUCCESS; 432 433 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 434 (hw, firmware_version), 435 IXGBE_NOT_IMPLEMENTED); 436 return status; 437 } 438 439 /** 440 * ixgbe_read_phy_reg - Read PHY register 441 * @hw: pointer to hardware structure 442 * @reg_addr: 32 bit address of PHY register to read 443 * @phy_data: Pointer to read data from PHY register 444 * 445 * Reads a value from a specified PHY register 446 **/ 447 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 448 u16 *phy_data) 449 { 450 if (hw->phy.id == 0) 451 (void) ixgbe_identify_phy(hw); 452 453 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 454 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 455 } 456 457 /** 458 * ixgbe_write_phy_reg - Write PHY register 459 * @hw: pointer to hardware structure 460 * @reg_addr: 32 bit PHY register to write 461 * @phy_data: Data to write to the PHY register 462 * 463 * Writes a value to specified PHY register 464 **/ 465 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 466 u16 phy_data) 467 { 468 if (hw->phy.id == 0) 469 (void) ixgbe_identify_phy(hw); 470 471 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 472 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 473 } 474 475 /** 476 * ixgbe_setup_phy_link - Restart PHY autoneg 477 * @hw: pointer to hardware structure 478 * 479 * Restart autonegotiation and PHY and waits for completion. 480 **/ 481 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 482 { 483 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 484 IXGBE_NOT_IMPLEMENTED); 485 } 486 487 /** 488 * ixgbe_check_phy_link - Determine link and speed status 489 * @hw: pointer to hardware structure 490 * 491 * Reads a PHY register to determine if link is up and the current speed for 492 * the PHY. 493 **/ 494 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 495 bool *link_up) 496 { 497 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 498 link_up), IXGBE_NOT_IMPLEMENTED); 499 } 500 501 /** 502 * ixgbe_setup_phy_link_speed - Set auto advertise 503 * @hw: pointer to hardware structure 504 * @speed: new link speed 505 * @autoneg: TRUE if autonegotiation enabled 506 * 507 * Sets the auto advertised capabilities 508 **/ 509 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 510 bool autoneg, 511 bool autoneg_wait_to_complete) 512 { 513 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 514 autoneg, autoneg_wait_to_complete), 515 IXGBE_NOT_IMPLEMENTED); 516 } 517 518 /** 519 * ixgbe_check_link - Get link and speed status 520 * @hw: pointer to hardware structure 521 * 522 * Reads the links register to determine if link is up and the current speed 523 **/ 524 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 525 bool *link_up, bool link_up_wait_to_complete) 526 { 527 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 528 link_up, link_up_wait_to_complete), 529 IXGBE_NOT_IMPLEMENTED); 530 } 531 532 /** 533 * ixgbe_disable_tx_laser - Disable Tx laser 534 * @hw: pointer to hardware structure 535 * 536 * If the driver needs to disable the laser on SFI optics. 537 **/ 538 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 539 { 540 if (hw->mac.ops.disable_tx_laser) 541 hw->mac.ops.disable_tx_laser(hw); 542 } 543 544 /** 545 * ixgbe_enable_tx_laser - Enable Tx laser 546 * @hw: pointer to hardware structure 547 * 548 * If the driver needs to enable the laser on SFI optics. 549 **/ 550 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 551 { 552 if (hw->mac.ops.enable_tx_laser) 553 hw->mac.ops.enable_tx_laser(hw); 554 } 555 556 /** 557 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 558 * @hw: pointer to hardware structure 559 * 560 * When the driver changes the link speeds that it can support then 561 * flap the tx laser to alert the link partner to start autotry 562 * process on its end. 563 **/ 564 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 565 { 566 if (hw->mac.ops.flap_tx_laser) 567 hw->mac.ops.flap_tx_laser(hw); 568 } 569 570 /** 571 * ixgbe_setup_link - Set link speed 572 * @hw: pointer to hardware structure 573 * @speed: new link speed 574 * @autoneg: TRUE if autonegotiation enabled 575 * 576 * Configures link settings. Restarts the link. 577 * Performs autonegotiation if needed. 578 **/ 579 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 580 bool autoneg, 581 bool autoneg_wait_to_complete) 582 { 583 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 584 autoneg, autoneg_wait_to_complete), 585 IXGBE_NOT_IMPLEMENTED); 586 } 587 588 /** 589 * ixgbe_get_link_capabilities - Returns link capabilities 590 * @hw: pointer to hardware structure 591 * 592 * Determines the link capabilities of the current configuration. 593 **/ 594 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 595 bool *autoneg) 596 { 597 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 598 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 599 } 600 601 /** 602 * ixgbe_led_on - Turn on LEDs 603 * @hw: pointer to hardware structure 604 * @index: led number to turn on 605 * 606 * Turns on the software controllable LEDs. 607 **/ 608 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 609 { 610 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 611 IXGBE_NOT_IMPLEMENTED); 612 } 613 614 /** 615 * ixgbe_led_off - Turn off LEDs 616 * @hw: pointer to hardware structure 617 * @index: led number to turn off 618 * 619 * Turns off the software controllable LEDs. 620 **/ 621 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 622 { 623 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 624 IXGBE_NOT_IMPLEMENTED); 625 } 626 627 /** 628 * ixgbe_blink_led_start - Blink LEDs 629 * @hw: pointer to hardware structure 630 * @index: led number to blink 631 * 632 * Blink LED based on index. 633 **/ 634 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 635 { 636 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 637 IXGBE_NOT_IMPLEMENTED); 638 } 639 640 /** 641 * ixgbe_blink_led_stop - Stop blinking LEDs 642 * @hw: pointer to hardware structure 643 * 644 * Stop blinking LED based on index. 645 **/ 646 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 647 { 648 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 649 IXGBE_NOT_IMPLEMENTED); 650 } 651 652 /** 653 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 654 * @hw: pointer to hardware structure 655 * 656 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 657 * ixgbe_hw struct in order to set up EEPROM access. 658 **/ 659 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 660 { 661 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 662 IXGBE_NOT_IMPLEMENTED); 663 } 664 665 666 /** 667 * ixgbe_write_eeprom - Write word to EEPROM 668 * @hw: pointer to hardware structure 669 * @offset: offset within the EEPROM to be written to 670 * @data: 16 bit word to be written to the EEPROM 671 * 672 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 673 * called after this function, the EEPROM will most likely contain an 674 * invalid checksum. 675 **/ 676 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 677 { 678 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 679 IXGBE_NOT_IMPLEMENTED); 680 } 681 682 /** 683 * ixgbe_read_eeprom - Read word from EEPROM 684 * @hw: pointer to hardware structure 685 * @offset: offset within the EEPROM to be read 686 * @data: read 16 bit value from EEPROM 687 * 688 * Reads 16 bit value from EEPROM 689 **/ 690 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 691 { 692 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 693 IXGBE_NOT_IMPLEMENTED); 694 } 695 696 /** 697 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 698 * @hw: pointer to hardware structure 699 * @checksum_val: calculated checksum 700 * 701 * Performs checksum calculation and validates the EEPROM checksum 702 **/ 703 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 704 { 705 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 706 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 707 } 708 709 /** 710 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 711 * @hw: pointer to hardware structure 712 **/ 713 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 714 { 715 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 716 IXGBE_NOT_IMPLEMENTED); 717 } 718 719 /** 720 * ixgbe_insert_mac_addr - Find a RAR for this mac address 721 * @hw: pointer to hardware structure 722 * @addr: Address to put into receive address register 723 * @vmdq: VMDq pool to assign 724 * 725 * Puts an ethernet address into a receive address register, or 726 * finds the rar that it is aleady in; adds to the pool list 727 **/ 728 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 729 { 730 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 731 (hw, addr, vmdq), 732 IXGBE_NOT_IMPLEMENTED); 733 } 734 735 /** 736 * ixgbe_set_rar - Set Rx address register 737 * @hw: pointer to hardware structure 738 * @index: Receive address register to write 739 * @addr: Address to put into receive address register 740 * @vmdq: VMDq "set" 741 * @enable_addr: set flag that address is active 742 * 743 * Puts an ethernet address into a receive address register. 744 **/ 745 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 746 u32 enable_addr) 747 { 748 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 749 enable_addr), IXGBE_NOT_IMPLEMENTED); 750 } 751 752 /** 753 * ixgbe_clear_rar - Clear Rx address register 754 * @hw: pointer to hardware structure 755 * @index: Receive address register to write 756 * 757 * Puts an ethernet address into a receive address register. 758 **/ 759 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 760 { 761 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 762 IXGBE_NOT_IMPLEMENTED); 763 } 764 765 /** 766 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 767 * @hw: pointer to hardware structure 768 * @rar: receive address register index to associate with VMDq index 769 * @vmdq: VMDq set or pool index 770 **/ 771 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 772 { 773 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 774 IXGBE_NOT_IMPLEMENTED); 775 } 776 777 /** 778 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 779 * @hw: pointer to hardware structure 780 * @rar: receive address register index to disassociate with VMDq index 781 * @vmdq: VMDq set or pool index 782 **/ 783 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 784 { 785 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 786 IXGBE_NOT_IMPLEMENTED); 787 } 788 789 /** 790 * ixgbe_init_rx_addrs - Initializes receive address filters. 791 * @hw: pointer to hardware structure 792 * 793 * Places the MAC address in receive address register 0 and clears the rest 794 * of the receive address registers. Clears the multicast table. Assumes 795 * the receiver is in reset when the routine is called. 796 **/ 797 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 798 { 799 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 800 IXGBE_NOT_IMPLEMENTED); 801 } 802 803 /** 804 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 805 * @hw: pointer to hardware structure 806 **/ 807 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 808 { 809 return hw->mac.num_rar_entries; 810 } 811 812 /** 813 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 814 * @hw: pointer to hardware structure 815 * @addr_list: the list of new multicast addresses 816 * @addr_count: number of addresses 817 * @func: iterator function to walk the multicast address list 818 * 819 * The given list replaces any existing list. Clears the secondary addrs from 820 * receive address registers. Uses unused receive address registers for the 821 * first secondary addresses, and falls back to promiscuous mode as needed. 822 **/ 823 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 824 u32 addr_count, ixgbe_mc_addr_itr func) 825 { 826 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 827 addr_list, addr_count, func), 828 IXGBE_NOT_IMPLEMENTED); 829 } 830 831 /** 832 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 833 * @hw: pointer to hardware structure 834 * @mc_addr_list: the list of new multicast addresses 835 * @mc_addr_count: number of addresses 836 * @func: iterator function to walk the multicast address list 837 * 838 * The given list replaces any existing list. Clears the MC addrs from receive 839 * address registers and the multicast table. Uses unused receive address 840 * registers for the first multicast addresses, and hashes the rest into the 841 * multicast table. 842 **/ 843 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 844 u32 mc_addr_count, ixgbe_mc_addr_itr func) 845 { 846 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 847 mc_addr_list, mc_addr_count, func), 848 IXGBE_NOT_IMPLEMENTED); 849 } 850 851 /** 852 * ixgbe_enable_mc - Enable multicast address in RAR 853 * @hw: pointer to hardware structure 854 * 855 * Enables multicast address in RAR and the use of the multicast hash table. 856 **/ 857 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 858 { 859 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 860 IXGBE_NOT_IMPLEMENTED); 861 } 862 863 /** 864 * ixgbe_disable_mc - Disable multicast address in RAR 865 * @hw: pointer to hardware structure 866 * 867 * Disables multicast address in RAR and the use of the multicast hash table. 868 **/ 869 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 870 { 871 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 872 IXGBE_NOT_IMPLEMENTED); 873 } 874 875 /** 876 * ixgbe_clear_vfta - Clear VLAN filter table 877 * @hw: pointer to hardware structure 878 * 879 * Clears the VLAN filer table, and the VMDq index associated with the filter 880 **/ 881 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 882 { 883 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 884 IXGBE_NOT_IMPLEMENTED); 885 } 886 887 /** 888 * ixgbe_set_vfta - Set VLAN filter table 889 * @hw: pointer to hardware structure 890 * @vlan: VLAN id to write to VLAN filter 891 * @vind: VMDq output index that maps queue to VLAN id in VFTA 892 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 893 * 894 * Turn on/off specified VLAN in the VLAN filter table. 895 **/ 896 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 897 { 898 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 899 vlan_on), IXGBE_NOT_IMPLEMENTED); 900 } 901 902 /** 903 * ixgbe_fc_enable - Enable flow control 904 * @hw: pointer to hardware structure 905 * @packetbuf_num: packet buffer number (0-7) 906 * 907 * Configures the flow control settings based on SW configuration. 908 **/ 909 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 910 { 911 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 912 IXGBE_NOT_IMPLEMENTED); 913 } 914 915 /** 916 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 917 * @hw: pointer to hardware structure 918 * @reg: analog register to read 919 * @val: read value 920 * 921 * Performs write operation to analog register specified. 922 **/ 923 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 924 { 925 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 926 val), IXGBE_NOT_IMPLEMENTED); 927 } 928 929 /** 930 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 931 * @hw: pointer to hardware structure 932 * @reg: analog register to write 933 * @val: value to write 934 * 935 * Performs write operation to Atlas analog register specified. 936 **/ 937 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 938 { 939 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 940 val), IXGBE_NOT_IMPLEMENTED); 941 } 942 943 /** 944 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 945 * @hw: pointer to hardware structure 946 * 947 * Initializes the Unicast Table Arrays to zero on device load. This 948 * is part of the Rx init addr execution path. 949 **/ 950 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 951 { 952 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 953 IXGBE_NOT_IMPLEMENTED); 954 } 955 956 /** 957 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 958 * @hw: pointer to hardware structure 959 * @byte_offset: byte offset to read 960 * @data: value read 961 * 962 * Performs byte read operation to SFP module's EEPROM over I2C interface. 963 **/ 964 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 965 u8 *data) 966 { 967 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 968 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 969 } 970 971 /** 972 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 973 * @hw: pointer to hardware structure 974 * @byte_offset: byte offset to write 975 * @data: value to write 976 * 977 * Performs byte write operation to SFP module's EEPROM over I2C interface 978 * at a specified device address. 979 **/ 980 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 981 u8 data) 982 { 983 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 984 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 985 } 986 987 /** 988 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 989 * @hw: pointer to hardware structure 990 * @byte_offset: EEPROM byte offset to write 991 * @eeprom_data: value to write 992 * 993 * Performs byte write operation to SFP module's EEPROM over I2C interface. 994 **/ 995 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 996 u8 byte_offset, u8 eeprom_data) 997 { 998 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 999 (hw, byte_offset, eeprom_data), 1000 IXGBE_NOT_IMPLEMENTED); 1001 } 1002 1003 /** 1004 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1005 * @hw: pointer to hardware structure 1006 * @byte_offset: EEPROM byte offset to read 1007 * @eeprom_data: value read 1008 * 1009 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1010 **/ 1011 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1012 { 1013 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1014 (hw, byte_offset, eeprom_data), 1015 IXGBE_NOT_IMPLEMENTED); 1016 } 1017 1018 /** 1019 * ixgbe_get_supported_physical_layer - Returns physical layer type 1020 * @hw: pointer to hardware structure 1021 * 1022 * Determines physical layer capabilities of the current configuration. 1023 **/ 1024 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1027 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1028 } 1029 1030 /** 1031 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 1032 * @hw: pointer to hardware structure 1033 * @regval: bitfield to write to the Rx DMA register 1034 * 1035 * Enables the Rx DMA unit of the device. 1036 **/ 1037 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1038 { 1039 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1040 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1041 } 1042 1043 /** 1044 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1045 * @hw: pointer to hardware structure 1046 * @mask: Mask to specify which semaphore to acquire 1047 * 1048 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1049 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1050 **/ 1051 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1052 { 1053 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1054 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1055 } 1056 1057 /** 1058 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1059 * @hw: pointer to hardware structure 1060 * @mask: Mask to specify which semaphore to release 1061 * 1062 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1063 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1064 **/ 1065 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1066 { 1067 if (hw->mac.ops.release_swfw_sync) 1068 hw->mac.ops.release_swfw_sync(hw, mask); 1069 } 1070 1071